K60P144M150SF3

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K60 Sub-Family Data Sheet

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K60P144M150SF3 FREESCALE | Alldatasheet

Document overview

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PDF pages: 82

Technical content

Features

Operating Characteristics – Voltage range: 1.71 to 3.6 V – Flash write voltage range: 1.71 to 3.6 V – Temperature range (ambient): -40 to 105°C
Performance – Up to 150 MHz ARM Cortex-M4 core with DSP instructions delivering 1.25 Dhrystone MIPS per MHz
Memories and memory interfaces – Up to 1024 KB program flash memory on non- FlexMemory devices – Up to 512 KB program flash memory on FlexMemory devices – Up to 512 KB FlexNVM on FlexMemory devices – 16 KB FlexRAM on FlexMemory devices – Up to 128 KB RAM – Serial programming interface (EzPort) – FlexBus external bus interface – NAND flash controller interface
Clocks – 3 to 32 MHz crystal oscillator – 32 kHz crystal oscillator – Multi-purpose clock generator
System peripherals – 10 low-power modes to provide power optimization based on application requirements – Memory protection unit with multi-master protection – 32-channel DMA controller, supporting up to 128 request sources – External watchdog monitor – Software watchdog – Low-leakage wakeup unit
Security and integrity modules – Hardware CRC module to support fast cyclic redundancy checks – Hardware random-number generator – Hardware encryption supporting DES, 3DES, AES, MD5, SHA-1, and SHA-256 algorithms – 128-bit unique identification (ID) number per chip
Human-machine interface – Low-power hardware touch sensor interface (TSI) – General-purpose input/output
Analog modules – Four 16-bit SAR ADCs – Programmable gain amplifier (PGA) (up to x64) integrated into each ADC – Two 12-bit DACs – Four analog comparators (CMP) containing a 6-bit DAC and programmable reference input – Voltage reference
Timers – Programmable delay block – Two 8-channel motor control/general purpose/PWM timers – Two 2-channel quadrature decoder/general purpose timers – IEEE 1588 timers – Periodic interrupt timers – 16-bit low-power timer – Carrier modulator transmitter – Real-time clock Freescale Semiconductor Document Number: K60P144M150SF3 Data Sheet: Advance Information Rev. 3, 2/2012 This document contains information on a new product. Specifications and information herein are subject to change without notice. © 2012 Freescale Semiconductor, Inc. Preliminary

Communication interfaces – Ethernet controller with MII and RMII interface to external PHY and hardware IEEE 1588 capability – USB high-/full-/low-speed On-the-Go controller with ULPI interface – USB full-/low-speed On-the-Go controller with on-chip transceiver – Two Controller Area Network (CAN) modules – Three SPI modules – Two I2C modules – Six UART modules – Secure Digital host controller (SDHC) – Two I2S modules K60 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. 2 Preliminary Freescale Semiconductor, Inc.

3.6 Relationship between ratings and operating

6.8.7 DSPI switching specifications (limited voltage

6.8.8 DSPI switching specifications (full voltage

K60 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. Freescale Semiconductor, Inc. Preliminary 3

K60 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. 4 Preliminary Freescale Semiconductor, Inc.

1 Ordering parts

1.1 Determining valid orderable parts

Valid orderable part numbers are provided on the web. To determine the orderable part numbers for this device, go to http://www.freescale.com and perform a part number search for the following device numbers: PK60 and MK60.

2 Part identification

2.1 Description

Part numbers for the chip have fields that identify the specific part. You can use the values of these fields to determine the specific part you have received.

2.2 Format

Part numbers for this device have the following format: Q K## A M FFF T PP CC N

2.3 Fields

This table lists the possible values for each field in the part number (not all combinations are valid): Field Description Values Q Qualification status • M = Fully qualified, general market flow

P = Prequalification K## Kinetis family • K60 A Key attribute • D = Cortex-M4 w/ DSP
F = Cortex-M4 w/ DSP and FPU M Flash memory type • N = Program flash only
X = Program flash and FlexMemory Table continues on the next page... Ordering parts K60 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. Freescale Semiconductor, Inc. Preliminary 5

FFF Program flash memory size • 32 = 32 KB

64 = 64 KB
128 = 128 KB
256 = 256 KB
512 = 512 KB
1M0 = 1 MB T Temperature range (°C) • V = –40 to 105
C = –40 to 85
MD = 144 MAPBGA (13 mm x 13 mm) CC Maximum CPU frequency (MHz) • 15 = 150 MHz N Packaging type • R = Tape and reel
(Blank) = Trays

2.4 Example

This is an example part number: MK60FN1M0VLQ15

3 Terminology and guidelines

3.1 Definition: Operating requirement

An operating requirement is a specified value or range of values for a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useful life of the chip.

3.1.1 Example

This is an example of an operating requirement, which you must meet for the accompanying operating behaviors to be guaranteed: Symbol Description Min. Max. Unit VDD 1.0 V core supply voltage 0.9 1.1 V Terminology and guidelines K60 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. 6 Preliminary Freescale Semiconductor, Inc.

3.2 Definition: Operating behavior

An operating behavior is a specified value or range of values for a technical characteristic that are guaranteed during operation if you meet the operating requirements and any other specified conditions.

3.2.1 Example

This is an example of an operating behavior, which is guaranteed if you meet the accompanying operating requirements: Symbol Description Min. Max. Unit IWP Digital I/O weak pullup/ pulldown current 10 130 µA

3.3 Definition: Attribute

An attribute is a specified value or range of values for a technical characteristic that are guaranteed, regardless of whether you meet the operating requirements.

3.3.1 Example

This is an example of an attribute: Symbol Description Min. Max. Unit CIN_D Input capacitance: digital pins — 7 pF

3.4 Definition: Rating

A rating is a minimum or maximum value of a technical characteristic that, if exceeded, may cause permanent chip failure:

Operating ratings apply during operation of the chip.
Handling ratings apply when the chip is not powered. Terminology and guidelines K60 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. Freescale Semiconductor, Inc. Preliminary 7

3.4.1 Example

This is an example of an operating rating: Symbol Description Min. Max. Unit VDD 1.0 V core supply voltage –0.3 1.2 V

3.5 Result of exceeding a rating

Failures in time (ppm) The likelihood of permanent chip failure increases rapidly as soon as a characteristic begins to exceed one of its operating ratings.

3.6 Relationship between ratings and operating requirements

No permanent failure - Correct operation Normal operating range Limited operating range - No permanent failure - Possible decreased life - Possible incorrect operation Fatal range - Probable permanent failure Limited operating range - No permanent failure - Possible decreased life - Possible incorrect operation Handling range - No permanent failure Fatal range - Probable permanent failure Operating or handling rating (max.)Operating requirement (max.)Operating requirement (min.)Operating or handling rating (min.)

3.7 Guidelines for ratings and operating requirements

Follow these guidelines for ratings and operating requirements:

Never exceed any of the chip’s ratings. Terminology and guidelines K60 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. 8 Preliminary Freescale Semiconductor, Inc.

During normal operation, don’t exceed any of the chip’s operating requirements.
If you must exceed an operating requirement at times other than during normal operation (for example, during power sequencing), limit the duration as much as possible.

3.8 Definition: Typical value

A typical value is a specified value for a technical characteristic that:

Lies within the range of values specified by the operating behavior
Given the typical manufacturing process, is representative of that characteristic during operation when you meet the typical-value conditions or other specified conditions Typical values are provided as design guidelines and are neither tested nor guaranteed.

3.8.1 Example 1

This is an example of an operating behavior that includes a typical value: Symbol Description Min. Typ. Max. Unit IWP Digital I/O weak pullup/pulldown current 10 70 130 µA

3.8.2 Example 2

This is an example of a chart that shows typical values for various voltage and temperature conditions: Terminology and guidelines K60 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. Freescale Semiconductor, Inc. Preliminary 9

150 °C 105 °C 25 °C –40 °C VDD (V) I (μA)DD_STOP TJ

3.9 Typical value conditions

Typical values assume you meet the following conditions (or other conditions as specified): Symbol Description Value Unit TA Ambient temperature 25 °C VDD 3.3 V supply voltage 3.3 V

4 Ratings

4.1 Thermal handling ratings

Symbol Description Min. Max. Unit Notes TSTG Storage temperature –55 150 °C 1 TSDR Solder temperature, lead-free — 260 °C 2 1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life. 2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. Ratings K60 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. 10 Preliminary Freescale Semiconductor, Inc.

4.2 Moisture handling ratings

Symbol Description Min. Max. Unit Notes MSL Moisture sensitivity level — 3 — 1 1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices.

4.3 ESD handling ratings

Symbol Description Min. Max. Unit Notes VHBM Electrostatic discharge voltage, human body model -2000 +2000 V 1 VCDM Electrostatic discharge voltage, charged-device model -500 +500 V 2 ILAT Latch-up current at ambient temperature of 105°C -100 +100 mA 1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM). 2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.

4.4 Voltage and current operating ratings

Symbol Description Min. Max. Unit VDD Digital supply voltage1 –0.3 3.8 V IDD Digital supply current — 300 mA VDIO Digital input voltage (except RESET, EXTAL0/XTAL0, and EXTAL1/XTAL1) 2 –0.3 5.5 V VAIO Analog3, RESET, EXTAL0/XTAL0, and EXTAL1/XTAL1 input voltage –0.3 VDD + 0.3 V ID Instantaneous maximum current single pin limit (applies to all digital pins except pins) –25 25 mA VDDA Analog supply voltage VDD – 0.3 VDD + 0.3 V VUSB_DP USB_DP input voltage –0.3 3.63 V VUSB_DM USB_DM input voltage –0.3 3.63 V VREGIN USB regulator input –0.3 6.0 V VBAT RTC battery supply voltage –0.3 3.8 V 1. It applies for all port pins. 2. It covers digital pins. 3. Analog pins are defined as pins that do not have an associated general purpose I/O port function. Ratings K60 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. Freescale Semiconductor, Inc. Preliminary 11

5 General

5.1 AC electrical characteristics

Figure 1. Input signal measurement reference

have C L=30pF loads,
are configured for fast slew rate (PORTx_PCRn[SRE]=0), and
are configured for high drive strength (PORTx_PCRn[DSE]=1) 2. input pins
have their passive filter disabled (PORTx_PCRn[PFE]=0)

5.2 Nonswitching electrical specifications

5.2.1 Voltage and current operating requirements

Table 1. Voltage and current operating requirements Table continues on the next page... K60 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. 12 Preliminary Freescale Semiconductor, Inc.

Table 1. Voltage and current operating requirements (continued)

2.7 V ≤ V DD ≤ 3.6 V
1.7 V ≤ V DD ≤ 2.7 V 0.7 × VDD 0.75 × VDD V V VIL Input low voltage (digital pins)
2.7 V ≤ V DD ≤ 3.6 V
1.7 V ≤ V DD ≤ 2.7 V 0.35 × VDD 0.3 × VDD V V VHYS Input hysteresis (digital pins) 0.06 × VDD — V IICDIO Digital pin negative DC injection current — single pin
V IN < VSS-0.3V -5 — mA IICAIO Analog2, EXTAL0/XTAL0, and EXTAL1/XTAL1 pin DC injection current — single pin
V IN < VSS-0.3V (Negative current injection)
V IN > VDD+0.3V (Positive current injection) mA IICcont Contiguous pin DC injection current —regional limit, includes sum of negative injection currents or sum of positive injection currents of 16 contiguous pins
Negative current injection
Positive current injection -25 +25 mA VRAM VDD voltage required to retain RAM 1.2 — V VRFVBAT VBAT voltage required to retain the VBAT register file VPOR_VBAT — V 1. All 5 V tolerant digital I/O pins are internally clamped to VSS through a ESD protection diode. There is no diode connection to VDD. If VIN greater than VDIO_MIN (=VSS-0.3V) is observed, then there is no need to provide current limiting resistors at the pads. If this limit cannot be observed then a current limiting resistor is required. The negative DC injection current limiting resistor is calculated as R=(VDIO_MIN-VIN)/|IIC|. 2. Analog pins are defined as pins that do not have an associated general purpose I/O port function. 3. All analog pins are internally clamped to VSS and VDD through ESD protection diodes. If VIN is greater than VAIO_MIN (=VSS-0.3V) and VIN is less than VAIO_MAX(=VDD+0.3V) is observed, then there is no need to provide current limiting resistors at the pads. If these limits cannot be observed then a current limiting resistor is required. The negative DC injection current limiting resistor is calculated as R=(VAIO_MIN-VIN)/|IIC|. The positive injection current limiting resistor is calcualted as R=(VIN-VAIO_MAX)/|IIC|. Select the larger of these two calculated resistances.

5.2.2 LVD and POR operating requirements

Table 2. LVD and POR operating requirements Table continues on the next page... K60 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.

Table 2. LVD and POR operating requirements (continued)

Level 1 falling (LVWV=00)
Level 2 falling (LVWV=01)
Level 3 falling (LVWV=10)
Level 4 falling (LVWV=11) 2.62 2.72 2.82 2.92 2.70 2.80 2.90 3.00 2.78 2.88 2.98 3.08 V V V V VHYSH Low-voltage inhibit reset/recover hysteresis — high range — ±80 — mV VLVDL Falling low-voltage detect threshold — low range (LVDV=00) 1.54 1.60 1.66 V VLVW1L VLVW2L VLVW3L VLVW4L Low-voltage warning thresholds — low range
Level 1 falling (LVWV=00)
Level 2 falling (LVWV=01)
Level 3 falling (LVWV=10)
Level 4 falling (LVWV=11) 1.74 1.84 1.94 2.04 1.80 1.90 2.00 2.10 1.86 1.96 2.06 2.16 V V V V VHYSL Low-voltage inhibit reset/recover hysteresis — low range — ±60 — mV VBG Bandgap voltage reference 0.97 1.00 1.03 V tLPO Internal low power oscillator period factory trimmed 900 1000 1100 μs 1. Rising thresholds are falling threshold + hysteresis voltage

Table 3. VBAT power operating requirements K60 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. 14 Preliminary Freescale Semiconductor, Inc.

5.2.3 Voltage and current operating behaviors

Table 4. Voltage and current operating behaviors

2.7 V ≤ V DD ≤ 3.6 V, IOH = -9mA
1.71 V ≤ V DD ≤ 2.7 V, IOH = -3mA VDD – 0.5 VDD – 0.5 V V Output high voltage — low drive strength
2.7 V ≤ V DD ≤ 3.6 V, IOH = -2mA
1.71 V ≤ V DD ≤ 2.7 V, IOH = -0.6mA VDD – 0.5 VDD – 0.5 V V IOHT Output high current total for all ports — 100 mA IOHT_io60 Output high current total for fast digital ports — 100 mA VOL Output low voltage — high drive strength
2.7 V ≤ V DD ≤ 3.6 V, IOL = 9mA
1.71 V ≤ V DD ≤ 2.7 V, IOL = 3mA 0.5 0.5 V V Output low voltage — low drive strength
2.7 V ≤ V DD ≤ 3.6 V, IOL = 2mA
1.71 V ≤ V DD ≤ 2.7 V, IOL = 0.6mA 0.5 0.5 V V IOLT Output low current total for all ports — TBD mA IOLT_io60 Output low current total for fast digital ports — TBD mA IIN Input leakage current (per pin) for full temperature range — 1 μA 1 IIN Input leakage current (per pin) at 25°C — 0.025 μA 1 IOZ Hi-Z (off-state) leakage current (per pin) — 1 μA RPU Internal pullup resistors 20 50 kΩ 2 RPD Internal pulldown resistors 20 50 kΩ 3 1. Measured at VDD=3.6V 2. Measured at VDD supply voltage = VDD min and Vinput = VSS 3. Measured at VDD supply voltage = VDD min and Vinput = VDD

5.2.4 Power mode transition operating behaviors

CPU and system clocks = 150 MHz
Bus clock = 75 MHz General K60 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. Freescale Semiconductor, Inc. Preliminary 15

FlexBus clock = 50 MHz
Flash clock = 25 MHz

Table 5. Power mode transition operating behaviors across the operating temperature range of the chip.

VLLS1 → RUN — 126 μs
VLLS2 → RUN — 82 μs
VLLS3 → RUN — 82 μs
LLS → RUN — 5.0 μs
VLPS → RUN — TBD μs
STOP → RUN — TBD μs 1. Normal boot (FTFE_FOPT[LPBOOT]=1)

5.2.5 Power consumption operating behaviors

Table 6. Power consumption operating behaviors

@ 1.8V
@ 3.0V TBD TBD mA mA IDD_RUN Run mode current — all peripheral clocks enabled, code executing from flash
@ 1.8V
@ 3.0V TBD TBD mA mA IDD_WAIT Wait mode high frequency current at 3.0 V — all peripheral clocks disabled — 37 TBD mA 2 IDD_WAIT Wait mode reduced frequency current at 3.0 V — all peripheral clocks disabled — 21 TBD mA 4 Table continues on the next page... General K60 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. 16 Preliminary Freescale Semiconductor, Inc.

Table 6. Power consumption operating behaviors (continued)

@ –40 to 25°C
@ 70°C
@ 105°C TBD TBD TBD TBD TBD TBD mA mA mA IDD_VLPR Very-low-power run mode current at 3.0 V — all peripheral clocks disabled — 2.3 TBD mA 5 IDD_VLPR Very-low-power run mode current at 3.0 V — all peripheral clocks enabled — 3.1 TBD mA 6 IDD_VLPW Very-low-power wait mode current at 3.0 V — 1.8 TBD mA 7 IDD_VLPS Very-low-power stop mode current at 3.0 V
@ –40 to 25°C
@ 70°C
@ 105°C 200 TBD TBD TBD TBD TBD μA μA μA IDD_LLS Low leakage stop mode current at 3.0 V
@ –40 to 25°C
@ 70°C
@ 105°C 200 TBD TBD TBD TBD TBD μA μA μA IDD_VLLS3 Very low-leakage stop mode 3 current at 3.0 V
@ –40 to 25°C
@ 70°C
@ 105°C 6.5 37.4 148.3 TBD TBD TBD μA μA μA #new- reference/ llsramn IDD_VLLS2 Very low-leakage stop mode 2 current at 3.0 V
@ –40 to 25°C
@ 70°C
@ 105°C 3.4 13.4 58.5 TBD TBD TBD μA μA μA IDD_VLLS1 Very low-leakage stop mode 1 current at 3.0 V
@ –40 to 25°C
@ 70°C
@ 105°C 2.9 9.8 44.7 TBD TBD TBD μA μA μA IDD_VBAT Average current when CPU is not accessing RTC registers at 3.0 V
@ –40 to 25°C
@ 70°C
@ 105°C 0.91 1.5 4.3 1.1 1.85 4.3 μA μA μA 1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See each module's specification for its supply current. General K60 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. Freescale Semiconductor, Inc. Preliminary 17

150 MHz core and system clock, 75 MHz bus, 50 MHz FlexBus clock, and 25 MHz flash clock. MCG configured for PEE mode. All peripheral clocks disabled. 3. 150 MHz core and system clock, 75 MHz bus, 50 MHz FlexBus clock, and 25 MHz flash clock. MCG configured for PEE mode. All peripheral clocks enabled, but peripherals are not in active operation. 4. 25 MHz core and system clock, 25 MHz bus clock, and 12.5 MHz FlexBus and flash clock. MCG configured for FEI mode. 5. 4 MHz core, system, 2 MHz FlexBus, and 2 MHz bus clock and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral clocks disabled. 6. 4 MHz core, system, 2 MHz FlexBus, and 2 MHz bus clock and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral clocks disabled. 7. 4 MHz core, system, 2 MHz FlexBus, and 2 MHz bus clock and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral clocks disabled. 8. Data reflects devices with 128 KB of RAM. For devices with 64 KB of RAM, power consumption is reduced by 2 μA. 9. Includes 32kHz oscillator current and RTC operation.

5.2.5.1 Diagram: Typical IDD_RUN operating behavior

The following data was measured under these conditions:

MCG in FBE mode for 50 MHz and lower frequencies. MCG in FEE mode at greater than 50 MHz frequencies. MCG in PEE mode is greater than 100 MHz frequencies.
USB regulator disabled
No GPIOs toggled
Code execution from flash with cache enabled
For the ALLOFF curve, all peripheral clocks are disabled except FTFL General K60 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. 18 Preliminary Freescale Semiconductor, Inc.

Figure 2. Run mode supply current vs. core frequency K60 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.

Figure 3. VLPR mode supply current vs. core frequency

5.2.6 EMC radiated emissions operating behaviors

Table 7. EMC radiated emissions operating behaviors for 256MAPBGA

Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions, 150

K60 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. 20 Preliminary Freescale Semiconductor, Inc.

measured orientations in each frequency range.

Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and Wideband

5.2.7 Designing with radiated emissions in mind

Go to http://www.freescale.com.
Perform a keyword search for “EMC design.”

5.2.8 Capacitance attributes

Table 8. Capacitance attributes

5.3 Switching specifications

5.3.1 Device clock specifications

Table 9. Device clock specifications

10 Mbps
100 Mbps MHz fBUS Bus clock — 75 MHz Table continues on the next page... General K60 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. Freescale Semiconductor, Inc. Preliminary 21

Table 9. Device clock specifications (continued)

The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for any

5.3.2 General switching specifications

CAN, CMT, IEEE 1588 timer, and I2C signals. Table 10. General switching specifications

Slew disabled
Slew enabled TBD TBD ns ns tio50 Port rise and fall time (low drive strength)
Slew disabled
Slew enabled TBD TBD ns ns Table continues on the next page... General K60 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. 22 Preliminary Freescale Semiconductor, Inc.

Table 10. General switching specifications (continued)

Slew disabled
Slew enabled TBD TBD ns ns tio60 Port rise and fall time (low drive strength)
Slew disabled
Slew enabled TBD TBD ns ns ttamper Port rise and fall time (high drive strength)
Slew disabled
Slew enabled TBD TBD ns ns ttamper Port rise and fall time (low drive strength)
Slew disabled
Slew enabled TBD TBD ns ns 1. The greater synchronous and asynchronous timing must be met. 2. This is the shortest pulse that is guaranteed to be recognized. 3. 25pF load 4. 15pF load 5. 75pF load 6. 15pF load 7. 75pF load 8. 15pF load

5.4 Thermal specifications

5.4.1 Thermal operating requirements

Table 11. Thermal operating requirements K60 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.

5.4.2 Thermal attributes

Board type Symbol Description 144 LQFP 144 MAPBGA Unit Notes Single-layer (1s) RθJA Thermal resistance, junction to ambient (natural convection) 45 50 °C/W 1 Four-layer (2s2p) RθJA Thermal resistance, junction to ambient (natural convection) 36 30 °C/W 1 Single-layer (1s) RθJMA Thermal resistance, junction to ambient (200 ft./ min. air speed) 36 41 °C/W 1 Four-layer (2s2p) RθJMA Thermal resistance, junction to ambient (200 ft./ min. air speed) 30 27 °C/W 1 — RθJB Thermal resistance, junction to board 24 17 °C/W 2 — RθJC Thermal resistance, junction to case 9 10 °C/W 3 — ΨJT Thermal characterization parameter, junction to package top outside center (natural convection) 2 2 °C/W 4 1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions—Natural Convection (Still Air), or EIA/JEDEC Standard JESD51-6, Integrated Circuit Thermal Test Method Environmental Conditions—Forced Convection (Moving Air). 2. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental Conditions—Junction-to-Board. 3. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate temperature used for the case temperature. The value includes the thermal resistance of the interface material between the top of the package and the cold plate. 4. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions—Natural Convection (Still Air).

6 Peripheral operating requirements and behaviors

Peripheral operating requirements and behaviors K60 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. 24 Preliminary Freescale Semiconductor, Inc.

6.1 Core modules

6.1.1 Debug trace timing specifications

Table 12. Debug trace operating behaviors Figure 4. TRACE_CLKOUT specifications Figure 5. Trace data specifications

6.1.2 JTAG electricals

Table 13. JTAG voltage range electricals Table continues on the next page... K60 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.

Table 13. JTAG voltage range electricals (continued)

JTAG
CJTAG MHz J2 TCLK cycle period 1/J1 — ns J3 TCLK clock pulse width
JTAG
CJTAG 100 200 ns ns ns J4 TCLK rise and fall times — 1 ns J5 TMS input data setup time to TCLK rise
JTAG
CJTAG 112 — ns J6 TDI input data setup time to TCLK rise 8 — ns J7 TMS input data hold time after TCLK rise
JTAG
CJTAG 3.4 3.4 — ns J8 TDI input data hold time after TCLK rise 3.4 — ns J9 TCLK low to TMS data valid
JTAG
CJTAG — 48 ns J10 TCLK low to TDO data valid — 48 ns J11 Output data hold/invalid time after clock edge1 — 3 ns 1. They are common for JTAG and CJTAG. J3 J3 J4 J4 TCLK (input)

Figure 6. Test clock input timing K60 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. 26 Preliminary Freescale Semiconductor, Inc.

Figure 9. TRST timing

6.2 System modules

There are no specifications necessary for the device's system modules.

6.3 Clock modules

6.3.1 MCG specifications

Table 14. MCG specifications

4 MHz

Table continues on the next page... K60 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. 28 Preliminary Freescale Semiconductor, Inc.

Table 14. MCG specifications (continued)

f VCO = 48 MHz
f VCO = 98 MHz 180 150 ps Jacc_fll FLL accumulated jitter of DCO output over a 1µs time window — TBD — ps tfll_acquire FLL target frequency acquisition time — — 1 ms 6 PLL0,1 fpll_ref PLL reference frequency range 8 — 16 MHz fvcoclk_2x VCO output frequency 180 — 360 MHz fvcoclk PLL output frequency 90 — 180 MHz fvcoclk_90 PLL quadrature output frequency 90 — 180 MHz Ipll PLL operating current (fast) — TBD — µA 7 Table continues on the next page... Peripheral operating requirements and behaviors K60 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. Freescale Semiconductor, Inc. Preliminary 29

This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock
These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0.
The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency deviation

(Δfdco_t) over voltage and temperature should be considered.

These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1.
The resulting clock frequency must not exceed the maximum specified clock frequency of the device.
This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed,

FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.

Excludes any oscillator currents that are also consuming power while PLL is in operation.
This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled
Accumulated jitter will depend on VCO frequency and VDIV.

6.3.2 Oscillator electrical specifications

This section provides the electrical characteristics of the module.

6.3.2.1 Oscillator DC electrical specifications

Table 15. Oscillator DC electrical specifications

32 kHz
4 MHz
8 MHz (RANGE=01)
16 MHz
24 MHz
32 MHz 500 200 300 950 1.2 1.5 nA μA μA μA mA mA Table continues on the next page... Peripheral operating requirements and behaviors K60 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. 30 Preliminary Freescale Semiconductor, Inc.

Table 15. Oscillator DC electrical specifications (continued)

32 kHz
4 MHz
8 MHz (RANGE=01)
16 MHz
24 MHz
32 MHz 400 500 2.5 μA μA μA mA mA mA Cx EXTAL load capacitance — — — 2, 3 Cy XTAL load capacitance — — — 2, 3 RF Feedback resistor — low-frequency, low-power mode (HGO=0) — — — MΩ 2, 4 Feedback resistor — low-frequency, high-gain mode (HGO=1) — 10 — MΩ Feedback resistor — high-frequency, low-power mode (HGO=0) — — — MΩ Feedback resistor — high-frequency, high-gain mode (HGO=1) — 1 — MΩ RS Series resistor — low-frequency, low-power mode (HGO=0) — — — kΩ Series resistor — low-frequency, high-gain mode (HGO=1) — 200 — kΩ Series resistor — high-frequency, low-power mode (HGO=0) — — — kΩ Series resistor — high-frequency, high-gain mode (HGO=1) kΩ Vpp5 Peak-to-peak amplitude of oscillation (oscillator mode) — low-frequency, low-power mode (HGO=0) — 0.6 — V Peak-to-peak amplitude of oscillation (oscillator mode) — low-frequency, high-gain mode (HGO=1) — VDD — V Peak-to-peak amplitude of oscillation (oscillator mode) — high-frequency, low-power mode (HGO=0) — 0.6 — V Peak-to-peak amplitude of oscillation (oscillator mode) — high-frequency, high-gain mode (HGO=1) — VDD — V 1. VDD=3.3 V, Temperature =25 °C 2. See crystal or resonator manufacturer's recommendation 3. Cx,Cy can be provided by using either the integrated capacitors or by using external components. 4. When low power mode is selected, RF is integrated and must not be attached externally. Peripheral operating requirements and behaviors K60 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. Freescale Semiconductor, Inc. Preliminary 31

The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any

6.3.2.2 Oscillator frequency specifications

Table 16. Oscillator frequency specifications

Frequencies less than 8 MHz are not in the PLL range.
Other frequency limits may apply when external clock is being used as a reference for the FLL or PLL.
When transitioning from FBE to FEI mode, restrict the frequency of the input clock so that, when it is divided by FRDIV, it

remains within the limits of the DCO input clock frequency.

Proper PC board layout procedures must be followed to achieve specifications.
Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S register

This section describes the module electrical characteristics. Table 17. 32kHz oscillator DC electrical specifications Table continues on the next page... K60 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. 32 Preliminary Freescale Semiconductor, Inc.

Table 17. 32kHz oscillator DC electrical specifications (continued)

The EXTAL32 and XTAL32 pins should only be connected to required oscillator components and must not be connected to

Table 18. 32kHz oscillator frequency specifications

Proper PC board layout procedures must be followed to achieve specifications.

6.4 Memories and memory interfaces

6.4.1 Flash (FTFE) electrical specifications

This section describes the electrical characteristics of the FTFE module.

6.4.1.1 Flash timing specifications — program and erase

active and do not include command overhead. Table 19. NVM program/erase timing specifications

Maximum time based on expectations at cycling end-of-life.

K60 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.

6.4.1.2 Flash timing specifications — commands

Table 20. Flash command timing specifications

control code 0x01
control code 0x02
control code 0x04
control code 0x08 185 TBD TBD TBD TBD μs μs μs μs tpgmpart Program Partition for EEPROM execution time — TBD TBD ms tsetram64k tsetram128k tsetram256k tsetram512k Set FlexRAM Function execution time:
64 KB EEPROM backup
128 KB EEPROM backup
256 KB EEPROM backup
512 KB EEPROM backup TBD TBD TBD TBD TBD TBD TBD TBD ms ms ms ms teewr8bers Byte-write to erased FlexRAM location execution time — 100 TBD μs 3 teewr8b64k teewr8b128k teewr8b256k teewr8b512k Byte-write to FlexRAM execution time:
64 KB EEPROM backup
128 KB EEPROM backup
256 KB EEPROM backup
512 KB EEPROM backup TBD TBD TBD TBD TBD TBD TBD TBD ms ms ms ms teewr16bers 16-bit write to erased FlexRAM location execution time — 100 TBD μs Table continues on the next page... Peripheral operating requirements and behaviors K60 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. 34 Preliminary Freescale Semiconductor, Inc.

Table 20. Flash command timing specifications (continued)

64 KB EEPROM backup
128 KB EEPROM backup
256 KB EEPROM backup
512 KB EEPROM backup TBD TBD TBD TBD TBD TBD TBD TBD ms ms ms ms teewr32bers 32-bit write to erased FlexRAM location execution time — 200 TBD μs teewr32b64k teewr32b128k teewr32b256k teewr32b512k 32-bit-write to FlexRAM execution time:
64 KB EEPROM backup
128 KB EEPROM backup
256 KB EEPROM backup
512 KB EEPROM backup TBD TBD TBD TBD TBD TBD TBD TBD ms ms ms ms 1. Assumes 25MHz flash clock frequency. 2. Maximum times for erase parameters based on expectations at cycling end-of-life. 3. For byte-writes to an erased FlexRAM location, the aligned word containing the byte must be erased.

6.4.1.3 Flash (FTFE) current and power specfications

Table 21. Flash (FTFE) current and power specfications

6.4.1.4 Reliability specifications

Table 22. NVM reliability specifications Table continues on the next page... K60 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.

Table 22. NVM reliability specifications (continued)

EEPROM backup to FlexRAM ratio = 16
EEPROM backup to FlexRAM ratio = 128
EEPROM backup to FlexRAM ratio = 512
EEPROM backup to FlexRAM ratio = 4096
EEPROM backup to FlexRAM ratio = 32,768 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD writes writes writes writes writes 1. Typical data retention values are based on measured response accelerated at high temperature and derated to a constant 25°C profile. Engineering Bulletin EB618 does not apply to this technology. 2. Data retention is based on Tjavg = 55°C (temperature profile over the lifetime of the application). 3. Cycling endurance represents number of program/erase cycles at -40°C ≤ Tj ≤ 125°C. 4. Write endurance represents the number of writes to each FlexRAM location at -40°C ≤Tj ≤ 125°C influenced by the cycling endurance of the FlexNVM (same value as data flash) and the allocated EEPROM backup per subsystem. Minimum and typical values assume all byte-writes to FlexRAM.

6.4.1.5 Write endurance to FlexRAM for EEPROM

6.4.2 EzPort Switching Specifications

Table 23. EzPort switching specifications Table continues on the next page... K60 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. 36 Preliminary Freescale Semiconductor, Inc.

Table 23. EzPort switching specifications (continued) Figure 10. EzPort Timing Diagram

6.4.3 NFC specifications

memory devices. This section describes the timing parameters of the NFC.

T H is the flash clock high time and
T L is flash clock low time, which are defined as: input clockT SCALER=NFCT = HTLT + The SCALER value is derived from the fractional divider specified in the SIM's CLKDIV4 register: SCALER = SIM_CLKDIV4[NFCFRAC] + 1 SIM_CLKDIV4[NFCDIV] + 1 Peripheral operating requirements and behaviors K60 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. Freescale Semiconductor, Inc. Preliminary 37

For example, if SCALER is 0.2, then TH = TL = TNFC/2. However, if SCALER is 0.667, then TL = 2/3 x TNFC and TH = 1/3 x TNFC. Table 24. NFC specifications Table continues on the next page... K60 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. 38 Preliminary Freescale Semiconductor, Inc.

Figure 14. Read data latch cycle timing in non-fast mode Figure 15. Read data latch cycle timing in fast mode

6.4.4 Flexbus Switching Specifications

the same as the internal system bus frequency or an integer divider of that frequency. Table 25. Flexbus limited voltage range switching specifications Table continues on the next page... K60 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. 40 Preliminary Freescale Semiconductor, Inc.

Table 25. Flexbus limited voltage range switching specifications (continued)

Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0], FB_ALE,
Specification is valid for all FB_AD[31:0] and FB_TA.

Table 26. Flexbus full voltage range switching specifications

Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0], FB_ALE,
Specification is valid for all FB_AD[31:0] and FB_TA.

K60 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.

Figure 16. FlexBus read timing diagram K60 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. 42 Preliminary Freescale Semiconductor, Inc.

Figure 17. FlexBus write timing diagram

6.5 Security and integrity modules

There are no specifications necessary for the device's security and integrity modules.

6.6 Analog

K60 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.

6.6.1 ADC electrical specifications

differential pins ADCx_DP0, ADCx_DM0. Table 27. 16-bit ADC operating conditions

1.13 VDDA VDDA V

16 bit modes
8/10/12 bit modes pF RADIN Input resistance — 2 5 kΩ RAS Analog source resistance 13/12 bit modes fADCK < 4MHz kΩ fADCK ADC conversion clock frequency ≤ 13 bit modes 1.0 18.0 MHz fADCK ADC conversion clock frequency 16 bit modes 2.0 12.0 MHz Table continues on the next page... Peripheral operating requirements and behaviors K60 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. 44 Preliminary Freescale Semiconductor, Inc.

Table 27. 16-bit ADC operating conditions (continued)

Typical values assume VDDA = 3.0 V, Temp = 25°C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for

reference only and are not tested in production.

This resistance is external to MCU. The analog source resistance should be kept as low as possible in order to achieve the

CAS time constant should be kept to <1ns.

To use the maximum ADC conversion clock frequency, the ADHSC bit should be set and the ADLPC bit should be clear.
For guidelines and examples of conversion rate calculation, download the ADC calculator tool: http://cache.freescale.com/

Figure 18. ADC input impedance equivalency diagram K60 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.

Table 28. 16-bit ADC characteristics (V REFH = VDDA, VREFL = VSSA)

ADLPC=1, ADHSC=0
ADLPC=1, ADHSC=1
ADLPC=0, ADHSC=0
ADLPC=0, ADHSC=1 1.2 3.0 2.4 4.4 2.4 4.0 5.2 6.2 3.9 7.3 6.1 9.5 MHz MHz MHz MHz tADACK = 1/ fADACK Sample Time See Reference Manual chapter for sample times TUE Total unadjusted error
12 bit modes
<12 bit modes ±1.4 ±6.8 ±2.1 LSB4 5 DNL Differential non- linearity
12 bit modes
<12 bit modes ±0.7 ±0.2 -1.1 to +1.9 -0.3 to 0.5 LSB4 5 INL Integral non- linearity
12 bit modes
<12 bit modes ±1.0 ±0.5 -2.7 to +1.9 -0.7 to +0.5 LSB4 5 EFS Full-scale error • 12 bit modes
<12 bit modes -1.4 -5.4 -1.8 LSB4 VADIN = VDDA EQ Quantization error
16 bit modes
≤13 bit modes -1 to 0 ±0.5 LSB4 ENOB Effective number of bits 16 bit differential mode
Avg=32
Avg=4 16 bit single-ended mode
Avg=32
Avg=4 12.8 11.9 12.2 11.4 14.5 13.8 13.9 13.1 bits bits bits bits SINAD Signal-to-noise plus distortion See ENOB 6.02 × ENOB + 1.76 dB THD Total harmonic distortion 16 bit differential mode
Avg=32 16 bit single-ended mode
Avg=32 –94 -85 dB dB Table continues on the next page... Peripheral operating requirements and behaviors K60 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. 46 Preliminary Freescale Semiconductor, Inc.

Table 28. 16-bit ADC characteristics (V REFH = VDDA, VREFL = VSSA) (continued)

Avg=32 16 bit single-ended mode
Avg=32 dB dB EIL Input leakage error IIn × RAS mV IIn = leakage current (refer to the MCU's voltage and current operating ratings) Temp sensor slope VTEMP25 Temp sensor voltage 25°C — 719 — mV 1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA 2. Typical values assume VDDA = 3.0 V, Temp = 25°C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and the ADLPC bit (low power). For lowest power operation the ADLPC bit should be set, the HSC bit should be clear with 1MHz ADC conversion clock speed. 4. 1 LSB = (VREFH - VREFL)/2N 5. ADC conversion clock <16MHz, Max hardware averaging (AVGE = %1, AVGS = %11) 6. Input data is 100 Hz sine wave. ADC conversion clock <12MHz. 7. Input data is 1 kHz sine wave. ADC conversion clock <12MHz. Peripheral operating requirements and behaviors K60 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. Freescale Semiconductor, Inc. Preliminary 47

Table 29. 16-bit ADC with PGA operating conditions

Typical values assume VDDA = 3.0 V, Temp = 25°C, fADCK = 6 MHz unless otherwise stated. Typical values are for

reference only and are not tested in production.

ADC must be configured to use the internal voltage reference (VREF_OUT)
PGA reference is internally connected to the VREF_OUT pin. If the user wishes to drive VREF_OUT with a voltage other

than the output of the VREF module, the VREF module must be disabled.

For single ended configurations the input impedance of the driven input is RPGAD/2
The analog source resistance (RAS), external to MCU, should be kept as minimum as possible. Increased RAS causes drop

in PGA gain without affecting other performances. This is not dependent on ADC clock frequency.

The minimum sampling time is dependent on input signal frequency and ADC mode of operation. A minimum of 1.25µs
ADC clock = 18 MHz, ADLSMP = 1, ADLST = 00, ADHSC = 1
ADC clock = 12 MHz, ADLSMP = 1, ADLST = 01, ADHSC = 1

K60 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.

Table 30. 16-bit ADC with PGA characteristics

PGAG=1
PGAG=2
PGAG=3
PGAG=4
PGAG=5
PGAG=6 0.95 1.9 3.8 7.6 15.2 30.0 58.8 31.6 63.3 1.05 2.1 4.2 8.4 16.6 33.2 67.8 RAS < 100Ω BW Input signal bandwidth
16-bit modes
< 16-bit modes kHz kHz PSRR Power supply rejection ratio Gain=1 — -84 — dB VDDA= 3V ±100mV, fVDDA= 50Hz, 60Hz CMRR Common mode rejection ratio
Gain=1
Gain=64 -84 -85 dB dB VCM= 500mVpp, fVCM= 50Hz, 100Hz VOFS Input offset voltage
Chopping disabled (ADC_PGA[PGACHPb] =1)
Chopping enabled (ADC_PGA[PGACHPb] =0) 2.4 0.2 TBD mV mV Output offset = VOFS*(Gain+1) TGSW Gain switching settling time — — 10 µs 5 dG/dT Gain drift over temperature
Gain=1
Gain=64 TBD TBD TBD TBD ppm/°C ppm/°C 0 to 50°C dVOFS/dT Offset drift over temperature Gain=1 — TBD TBD ppm/°C 0 to 50°C, ADC Averaging=32 dG/dVDDA Gain drift over supply voltage
Gain=1
Gain=64 TBD TBD TBD TBD %/V %/V VDDA from 1.71 to 3.6V Table continues on the next page... Peripheral operating requirements and behaviors K60 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. 50 Preliminary Freescale Semiconductor, Inc.

Table 30. 16-bit ADC with PGA characteristics (continued)

Gain=1
Gain=64 dB dB 16-bit differential mode, Average=32 THD Total harmonic distortion
Gain=1
Gain=64 100 dB dB 16-bit differential mode, Average=32, fin=100Hz SFDR Spurious free dynamic range
Gain=1
Gain=64 105 dB dB 16-bit differential mode, Average=32, fin=100Hz ENOB Effective number of bits
Gain=1, Average=4
Gain=1, Average=8
Gain=64, Average=4
Gain=64, Average=8
Gain=1, Average=32
Gain=2, Average=32
Gain=4, Average=32
Gain=8, Average=32
Gain=16, Average=32
Gain=32, Average=32
Gain=64, Average=32 11.6 TBD 7.2 TBD 12.8 11.0 7.9 7.3 6.8 6.8 7.5 13.4 12.7 9.6 8.7 14.5 14.3 13.8 13.1 12.5 11.5 10.6 bits bits bits bits bits bits bits bits bits bits bits 16-bit differential mode,fin=100H z SINAD Signal-to-noise plus distortion ratio See ENOB 6.02 × ENOB + 1.76 dB 1. Typical values assume VDDA =3.0V, Temp=25°C, fADCK=6MHz unless otherwise stated. 2. This current is a PGA module adder, in addition to and ADC conversion currents. 3. Between IN+ and IN-. The PGA draws a DC current from the input terminals. The magnitude of the DC current is a strong function of input common mode voltage (VCM) and the PGA gain. 4. Gain = 2PGAG 5. After changing the PGA gain setting, a minimum of 2 ADC+PGA conversions should be ignored. Peripheral operating requirements and behaviors K60 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. Freescale Semiconductor, Inc. Preliminary 51

Limit the input signal swing so that the PGA does not saturate during operation. Input signal swing is dependent on the

PGA reference voltage and gain setting.

6.6.2 CMP and 6-bit DAC electrical specifications

Table 31. Comparator and 6-bit DAC electrical specifications

CR0[HYSTCTR] = 00
CR0[HYSTCTR] = 01
CR0[HYSTCTR] = 10
CR0[HYSTCTR] = 11 mV mV mV mV VCMPOh Output high VDD – 0.5 — — V VCMPOl Output low — — 0.5 V tDHS Propagation delay, high-speed mode (EN=1, PMODE=1) 20 50 200 ns tDLS Propagation delay, low-speed mode (EN=1, PMODE=0) 80 250 600 ns Analog comparator initialization delay2 — — 40 μs IDAC6b 6-bit DAC current adder (enabled) — 7 — μA INL 6-bit DAC integral non-linearity –0.5 — 0.5 LSB3 DNL 6-bit DAC differential non-linearity –0.3 — 0.3 LSB 1. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD-0.6V. 2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to DACEN, VRSEL, PSEL, MSEL, VOSEL) and the comparator output settling to a stable level. 3. 1 LSB = Vreference/64 Peripheral operating requirements and behaviors K60 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. 52 Preliminary Freescale Semiconductor, Inc.

Figure 21. Typical hysteresis vs. Vin level (VDD=3.3V, PMODE=0) K60 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.

Figure 22. Typical hysteresis vs. Vin level (VDD=3.3V, PMODE=1) Table 32. 12-bit DAC operating requirements

The DAC reference can be selected to be VDDA or the voltage output of the VREF module (VREF_OUT)
A small load capacitance (47 pF) can improve the bandwidth performance of the DAC

K60 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. 54 Preliminary Freescale Semiconductor, Inc.

Table 33. 12-bit DAC operating behaviors

High power (SP HP)
Low power (SP LP) 1.2 0.05 1.7 0.12 V/μs CT Channel to channel cross talk — — -80 dB BW 3dB bandwidth
High power (SP HP)
Low power (SP LP) 550 kHz 1. Settling within ±1 LSB 2. The INL is measured for 0+100mV to VDACR−100 mV 3. The DNL is measured for 0+100 mV to VDACR−100 mV 4. The DNL is measured for 0+100mV to VDACR−100 mV with VDDA > 2.4V 5. Calculated by a best fit curve from VSS+100 mV to VDACR−100 mV Peripheral operating requirements and behaviors K60 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. Freescale Semiconductor, Inc. Preliminary 55

VDDA = 3.0V, reference select set for VDDA (DACx_CO:DACRFS = 1), high power mode(DACx_C0:LPEN = 0), DAC set

Figure 23. Typical INL error vs. digital code K60 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. 56 Preliminary Freescale Semiconductor, Inc.

Figure 24. Offset at half scale vs. temperature

6.6.4 Voltage reference electrical specifications

Table 34. VREF full-range operating requirements

CL must be connected to VREF_OUT if the VREF_OUT functionality is being used for either an internal or external
The load capacitance should not exceed +/-25% of the nominal specified CL value over the operating temperature range of

K60 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.

Table 35. VREF full-range operating behaviors

current = + 1.0 mA
current = - 1.0 mA mV 1, 2 Tstup Buffer startup time — — 100 µs Vvdrift Voltage drift (Vmax -Vmin across the full voltage range) — 2 — mV 1 1. See the chip's Reference Manual for the appropriate settings of the VREF Status and Control register. 2. Load regulation voltage is the difference between the VREF_OUT voltage with no load vs. voltage with defined load

Table 36. VREF limited-range operating requirements Table 37. VREF limited-range operating behaviors

6.7 Timers

See General switching specifications.

6.8 Communication interfaces

K60 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. 58 Preliminary Freescale Semiconductor, Inc.

6.8.1 Ethernet switching specifications

appropriately to arrive at timing specs/constraints for the physical interface.

6.8.1.1 MII signal switching specifications

Table 38. MII signal switching specifications Figure 25. MII transmit signal timing diagram K60 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.

Figure 26. MII receive signal timing diagram

6.8.1.2 RMII signal switching specifications

Table 39. RMII signal switching specifications

6.8.2 USB electrical specifications

standards, visit http://www.usb.org. K60 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. 60 Preliminary Freescale Semiconductor, Inc.

6.8.3 USB DCD electrical specifications

Table 40. USB DCD electrical specifications

6.8.4 USB VREG electrical specifications

Table 41. USB VREG electrical specifications

VREGIN = 5.0 V and temperature=25C
Across operating voltage and temperature 650 nA μA ILOADrun Maximum load current — Run mode — — 120 mA ILOADstby Maximum load current — Standby mode — — 1 mA VReg33out Regulator output voltage — Input supply (VREGIN) > 3.6 V
Run mode
Standby mode 2.1 3.3 2.8 3.6 3.6 V V VReg33out Regulator output voltage — Input supply (VREGIN) < 3.6 V, pass-through mode 2.1 — 3.6 V 2 COUT External output capacitor 1.76 2.2 8.16 μF ESR External output capacitor equivalent series resistance 1 — 100 mΩ ILIM Short circuit current — 290 — mA 1. Typical values assume VREGIN = 5.0 V, Temp = 25 °C unless otherwise stated. 2. Operating in pass-through mode: regulator output voltage equal to the input voltage minus a drop proportional to ILoad. Peripheral operating requirements and behaviors K60 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. Freescale Semiconductor, Inc. Preliminary 61

6.8.5 ULPI timing specifications

measured with respect to the clock as seen at the USB_CLKIN pin. Table 42. ULPI timing specifications Figure 27. ULPI timing diagram K60 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. 62 Preliminary Freescale Semiconductor, Inc.

6.8.6 CAN switching specifications

See General switching specifications.

6.8.7 DSPI switching specifications (limited voltage range)

used for communicating with slower peripheral devices. Table 43. Master mode DSPI timing (limited voltage range)

The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].

Figure 28. DSPI classic SPI timing — master mode K60 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.

Table 44. Slave mode DSPI timing (limited voltage range) Figure 29. DSPI classic SPI timing — slave mode

6.8.8 DSPI switching specifications (full voltage range)

used for communicating with slower peripheral devices. Table 45. Master mode DSPI timing (full voltage range) Table continues on the next page... K60 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. 64 Preliminary Freescale Semiconductor, Inc.

Table 45. Master mode DSPI timing (full voltage range) (continued)

The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage

range the maximum frequency of operation is reduced.

The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].

Figure 30. DSPI classic SPI timing — master mode Table 46. Slave mode DSPI timing (full voltage range) Table continues on the next page... K60 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.

Table 46. Slave mode DSPI timing (full voltage range) (continued) Figure 31. DSPI classic SPI timing — slave mode

6.8.9 I2C switching specifications

See General switching specifications.

6.8.10 UART switching specifications

See General switching specifications.

6.8.11 SDHC specifications

appropriately to arrive at timing specs/constraints for the physical interface. Table 47. SDHC switching specifications Table continues on the next page... K60 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. 66 Preliminary Freescale Semiconductor, Inc.

Figure 32. SDHC timing

6.8.12 I2S/SAI Switching Specifications

K60 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.

frame sync (FS) signal shown in the following figures. Table 48. I2S/SAI master mode timing

This parameter is limited in VLPx modes.
Applies to first bit in each frame and only if the TCR4[FSE] bit is clear

Figure 33. I2S/SAI timing — master modes K60 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. 68 Preliminary Freescale Semiconductor, Inc.

Table 49. I2S/SAI slave mode timing

Applies to first bit in each frame and only if the TCR4[FSE] bit is clear

Figure 34. I2S/SAI timing — slave modes

6.9 Human-machine interfaces (HMI)

K60 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.

6.9.1 TSI electrical specifications

Table 50. TSI electrical specifications

1uA setting (REFCHRG=0)
32uA setting (REFCHRG=31) 1.133 1.5 μA 2, 3 IELE Electrode oscillator current source base current
1uA setting (EXTCHRG=0)
32uA setting (EXTCHRG=31) 1.133 1.5 μA 2, 4 Pres5 Electrode capacitance measurement precision — 8.3333 38.4 pF/count 5 Pres20 Electrode capacitance measurement precision — 8.3333 38.4 pF/count 6 Pres100 Electrode capacitance measurement precision — 8.3333 38.4 pF/count 7 MaxSens Maximum sensitivity 0.003 12.5 — fF/count 8 Res Resolution — — 16 bits TCon20 Response time @ 20 pF 8 15 25 μs 9 ITSI_RUN Current added in run mode — 55 — μA ITSI_LP Low power mode current adder — 1.3 TBD μA 10 1. The TSI module is functional with capacitance values outside this range. However, optimal performance is not guaranteed. 2. Fixed external capacitance of 20 pF. 3. The programmable current source value is generated by multiplying the SCANC[REFCHRG] value and the base current. 4. The programmable current source value is generated by multiplying the SCANC[EXTCHRG] value and the base current. 5. Measured with a 5 pF electrode, reference oscillator frequency of 10 MHz, PS = 128, NSCN = 8; Iext = 16. 6. Measured with a 20 pF electrode, reference oscillator frequency of 10 MHz, PS = 128, NSCN = 2; Iext = 16. 7. Measured with a 20 pF electrode, reference oscillator frequency of 10 MHz, PS = 16, NSCN = 3; Iext = 16. 8. Sensitivity defines the minimum capacitance change when a single count from the TSI module changes, it is equal to (Cref * Iext)/( Iref * PS * NSCN). Sensitivity depends on the configuration used. The typical value listed is based on the following configuration: Iext = 5 μA, EXTCHRG = 4, PS = 128, NSCN = 2, Iref = 16 μA, REFCHRG = 15, Cref = 1.0 pF. The minimum sensitivity describes the smallest possible capacitance that can be measured by a single count (this is the best sensitivity but is described as a minimum because it’s the smallest number). The minimum sensitivity parameter is based on the following configuration: Iext = 1 μA, EXTCHRG = 0, PS = 128, NSCN = 32, Iref = 32 μA, REFCHRG = 31, Cref= 0.5 pF 9. Time to do one complete measurement of the electrode. Sensitivity resolution of 0.0133 pF, PS = 0, NSCN = 0, 1 electrode, EXTCHRG = 15. 10. REFCHRG=0, EXTCHRG=4, PS=7, NSCN=0F, LPSCNITV=F, LPO is selected (1 kHz), and fixed external capacitance of 20 pF. Data is captured with an average of 7 periods window.

7 Dimensions

K60 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. 70 Preliminary Freescale Semiconductor, Inc.

7.1 Obtaining package dimensions

Package dimensions are provided in package drawings. To find a package drawing, go to http://www.freescale.com and perform a keyword search for the drawing’s document number: If you want the drawing for this package Then use this document number 144-pin LQFP 98ASS23177W 144-pin MAPBGA 98ASA00222D

8 Pinout

8.1 K60 Signal Multiplexing and Pin Assignments

The following table shows the signals available on each pin and the locations of these pins on the devices supported by this document. The Port Control Module is responsible for selecting which ALT functionality is available on each pin. 144 LQF P 144 MAP BGA Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort — L5 RTC_WAKE UP_B RTC_WAKE UP_B RTC_WAKE UP_B — M5 NC NC NC — A10 NC NC NC — B10 NC NC NC — C10 NC NC NC

1 D3 PTE0 ADC1_SE4

a ADC1_SE4 a PTE0 SPI1_PCS1UART1_TXSDHC0_D1 I2C1_SDARTC_CLKO UT

2 D2 PTE1/

LLWU_P0 ADC1_SE5 a ADC1_SE5 a PTE1/ LLWU_P0 SPI1_SOUTUART1_RXSDHC0_D0 I2C1_SCLSPI1_SIN

3 D1 PTE2/

LLWU_P1 ADC1_SE6 a ADC1_SE6 a PTE2/ LLWU_P1 SPI1_SCKUART1_CT S_b SDHC0_DC LK

4 E4 PTE3 ADC1_SE7

a ADC1_SE7 a PTE3 SPI1_SIN UART1_RT S_b SDHC0_CM D SPI1_SOUT

5 E5 VDD VDD VDD

6 F6 VSS VSS VSS

7 E3 PTE4/

LLWU_P2 DISABLED PTE4/ LLWU_P2 SPI1_PCS0UART3_TXSDHC0_D3

8 E2 PTE5 DISABLED PTE5 SPI1_PCS2UART3_RXSDHC0_D2 FTM3_CH0

K60 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. Freescale Semiconductor, Inc. Preliminary 71

P 144 MAP BGA Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort

9 E1 PTE6 DISABLED PTE6 SPI1_PCS3UART3_CT

S_b I2S0_MCLK FTM3_CH1USB_SOF_ OUT

10 F4 PTE7 DISABLED PTE7 UART3_RT

S_b I2S0_RXD0 FTM3_CH2

11 F3 PTE8 ADC2_SE1

ADC2_SE1 PTE8 I2S0_RXD1UART5_TXI2S0_RX_F S FTM3_CH3

12 F2 PTE9 ADC2_SE1

ADC2_SE1 PTE9 I2S0_TXD1UART5_RXI2S0_RX_B CLK FTM3_CH4

13 F1 PTE10 DISABLED PTE10 UART5_CT

S_b I2S0_TXD0 FTM3_CH5

14 G4 PTE11 ADC3_SE1

ADC3_SE1 PTE11 UART5_RT S_b I2S0_TX_F S FTM3_CH6

15 G3 PTE12 ADC3_SE1

ADC3_SE1 PTE12 I2S0_TX_B CLK FTM3_CH7

16 E6 VDD VDD VDD

17 F7 VSS VSS VSS

18 H3 VSS VSS VSS

19 H1 USB0_DPUSB0_DPUSB0_DP

20 H2 USB0_DMUSB0_DMUSB0_DM

21 G1 VOUT33 VOUT33 VOUT33

22 G2 VREGIN VREGIN VREGIN

23 J1 PGA2_DP/

ADC2_DP0/ ADC3_DP3/ ADC0_DP1 PGA2_DP/ ADC2_DP0/ ADC3_DP3/ ADC0_DP1 PGA2_DP/ ADC2_DP0/ ADC3_DP3/ ADC0_DP1

24 J2 PGA2_DM/

ADC2_DM0/ ADC3_DM3/ ADC0_DM1 PGA2_DM/ ADC2_DM0/ ADC3_DM3/ ADC0_DM1 PGA2_DM/ ADC2_DM0/ ADC3_DM3/ ADC0_DM1

25 K1 PGA3_DP/

ADC3_DP0/ ADC2_DP3/ ADC1_DP1 PGA3_DP/ ADC3_DP0/ ADC2_DP3/ ADC1_DP1 PGA3_DP/ ADC3_DP0/ ADC2_DP3/ ADC1_DP1

26 K2 PGA3_DM/

ADC3_DM0/ ADC2_DM3/ ADC1_DM1 PGA3_DM/ ADC3_DM0/ ADC2_DM3/ ADC1_DM1 PGA3_DM/ ADC3_DM0/ ADC2_DM3/ ADC1_DM1

27 L1 PGA0_DP/

ADC0_DP0/ ADC1_DP3 PGA0_DP/ ADC0_DP0/ ADC1_DP3 PGA0_DP/ ADC0_DP0/ ADC1_DP3

28 L2 PGA0_DM/

ADC0_DM0/ ADC1_DM3 PGA0_DM/ ADC0_DM0/ ADC1_DM3 PGA0_DM/ ADC0_DM0/ ADC1_DM3

29 M1 PGA1_DP/

ADC1_DP0/ ADC0_DP3 PGA1_DP/ ADC1_DP0/ ADC0_DP3 PGA1_DP/ ADC1_DP0/ ADC0_DP3 Pinout K60 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. 72 Preliminary Freescale Semiconductor, Inc.

P 144 MAP BGA Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort

30 M2 PGA1_DM/

ADC1_DM0/ ADC0_DM3 PGA1_DM/ ADC1_DM0/ ADC0_DM3 PGA1_DM/ ADC1_DM0/ ADC0_DM3

31 H5 VDDA VDDA VDDA

32 G5 VREFH VREFH VREFH

33 G6 VREFL VREFL VREFL

34 H6 VSSA VSSA VSSA

35 K3 ADC1_SE1

CMP2_IN2/ ADC0_SE2 ADC1_SE1 CMP2_IN2/ ADC0_SE2 ADC1_SE1 CMP2_IN2/ ADC0_SE2

36 J3 ADC0_SE1

CMP1_IN2/ ADC0_SE2 ADC0_SE1 CMP1_IN2/ ADC0_SE2 ADC0_SE1 CMP1_IN2/ ADC0_SE2

37 M3 VREF_OUT/

CMP1_IN5/ CMP0_IN5/ ADC1_SE1 VREF_OUT/ CMP1_IN5/ CMP0_IN5/ ADC1_SE1 VREF_OUT/ CMP1_IN5/ CMP0_IN5/ ADC1_SE1

38 L3 DAC0_OUT/

CMP1_IN3/ ADC0_SE2 DAC0_OUT/ CMP1_IN3/ ADC0_SE2 DAC0_OUT/ CMP1_IN3/ ADC0_SE2

39 L4 DAC1_OUT/

CMP0_IN4/ CMP2_IN3/ ADC1_SE2 DAC1_OUT/ CMP0_IN4/ CMP2_IN3/ ADC1_SE2 DAC1_OUT/ CMP0_IN4/ CMP2_IN3/ ADC1_SE2

40 M7 XTAL32 XTAL32 XTAL32

41 M6 EXTAL32 EXTAL32 EXTAL32

42 L6 VBAT VBAT VBAT

43 — VDD VDD VDD 44 — VSS VSS VSS

45 M4 PTE24 ADC0_SE1

ADC0_SE1 7/EXTAL1 PTE24 CAN1_TX UART4_TXI2S1_TX_F S EWM_OUT I2S1_RXD1

46 K5 PTE25 ADC0_SE1

ADC0_SE1 8/XTAL1 PTE25 CAN1_RXUART4_RXI2S1_TX_B CLK EWM_IN I2S1_TXD1

47 K4 PTE26 ADC3_SE5

b ADC3_SE5 b PTE26 ENET_1588 _CLKIN UART4_CT S_b I2S1_TXD0 RTC_CLKO UT USB_CLKIN

48 J4 PTE27 ADC3_SE4

b ADC3_SE4 b PTE27 UART4_RT S_b I2S1_MCLK

49 H4 PTE28 ADC3_SE7

a ADC3_SE7 a PTE28

50 J5 PTA0 JTAG_TCL

TSI0_CH1PTA0 UART0_CT S_b/ FTM0_CH5 JTAG_TCL SWD_CLK EZP_CLK Pinout K60 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. Freescale Semiconductor, Inc. Preliminary 73

P 144 MAP BGA Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort SWD_CLK/ EZP_CLK UART0_CO L_b

51 J6 PTA1 JTAG_TDI/

EZP_DI TSI0_CH2PTA1 UART0_RXFTM0_CH6 JTAG_TDIEZP_DI

52 K6 PTA2 JTAG_TDO/

TRACE_SW O/EZP_DO TSI0_CH3PTA2 UART0_TXFTM0_CH7 JTAG_TDO/ TRACE_SW O EZP_DO

53 K7 PTA3 JTAG_TMS/

SWD_DIO TSI0_CH4PTA3 UART0_RT S_b FTM0_CH0 JTAG_TMS/ SWD_DIO

54 L7 PTA4/

LLWU_P3 NMI_b/ EZP_CS_b TSI0_CH5PTA4/ LLWU_P3 FTM0_CH1 NMI_b EZP_CS_b

55 M8 PTA5 DISABLED PTA5 USB_CLKINFTM0_CH2RMII0_RXE

MII0_RXER CMP2_OUTI2S0_TX_B CLK JTAG_TRS T_b

56 E7 VDD VDD VDD

57 G7 VSS VSS VSS

58 J7 PTA6 ADC3_SE6

a ADC3_SE6 a PTA6 ULPI_CLKFTM0_CH3I2S1_RXD0CLKOUT TRACE_CL KOUT

59 J8 PTA7 ADC0_SE1

ADC0_SE1 PTA7 ULPI_DIR FTM0_CH4I2S1_RX_B CLK TRACE_D3

60 K8 PTA8 ADC0_SE1

ADC0_SE1 PTA8 ULPI_NXTFTM1_CH0I2S1_RX_F S FTM1_QD_ PHA TRACE_D2

61 L8 PTA9 ADC3_SE5

a ADC3_SE5 a PTA9 ULPI_STPFTM1_CH1MII0_RXD3 FTM1_QD_ PHB TRACE_D1

62 M9 PTA10 ADC3_SE4

a ADC3_SE4 a PTA10 ULPI_DATA FTM2_CH0MII0_RXD2 FTM2_QD_ PHA TRACE_D0

63 L9 PTA11 ADC3_SE1

ADC3_SE1 PTA11 ULPI_DATA FTM2_CH1MII0_RXCL K FTM2_QD_ PHB

64 K9 PTA12 CMP2_IN0CMP2_IN0PTA12 CAN0_TX FTM1_CH0RMII0_RXD

MII0_RXD1 I2S0_TXD0FTM1_QD_ PHA

65 J9 PTA13/

LLWU_P4 CMP2_IN1CMP2_IN1PTA13/ LLWU_P4 CAN0_RXFTM1_CH1RMII0_RXD MII0_RXD0 I2S0_TX_F S FTM1_QD_ PHB

66 L10 PTA14 CMP3_IN0CMP3_IN0PTA14 SPI0_PCS0UART0_TXRMII0_CRS

_DV/ MII0_RXDV I2S0_RX_B CLK I2S0_TXD1

67 L11 PTA15 CMP3_IN1CMP3_IN1PTA15 SPI0_SCKUART0_RXRMII0_TXE

MII0_TXEN I2S0_RXD0

68 K10 PTA16 CMP3_IN2CMP3_IN2PTA16 SPI0_SOUTUART0_CT

S_b/ UART0_CO L_b RMII0_TXD MII0_TXD0 I2S0_RX_F S I2S0_RXD1

69 K11 PTA17 ADC1_SE1

ADC1_SE1 PTA17 SPI0_SIN UART0_RT S_b RMII0_TXD MII0_TXD1 I2S0_MCLK

70 E8 VDD VDD VDD

K60 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. 74 Preliminary Freescale Semiconductor, Inc.

P 144 MAP BGA Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort

71 G8 VSS VSS VSS

72 M12 PTA18 EXTAL0 EXTAL0 PTA18 FTM0_FLT2FTM_CLKIN

73 M11 PTA19 XTAL0 XTAL0 PTA19 FTM1_FLT0FTM_CLKIN

LPTMR0_A LT1

74 L12 RESET_b RESET_b RESET_b

75 K12 PTA24 CMP3_IN4CMP3_IN4PTA24 ULPI_DATA

MII0_TXD2 FB_A29

76 J12 PTA25 CMP3_IN5CMP3_IN5PTA25 ULPI_DATA

MII0_TXCL K FB_A28

77 J11 PTA26 ADC2_SE1

ADC2_SE1 PTA26 ULPI_DATA MII0_TXD3 FB_A27

78 J10 PTA27 ADC2_SE1

ADC2_SE1 PTA27 ULPI_DATA MII0_CRS FB_A26

79 H12 PTA28 ADC2_SE1

ADC2_SE1 PTA28 ULPI_DATA MII0_TXER FB_A25

80 H11 PTA29 ADC2_SE1

ADC2_SE1 PTA29 ULPI_DATA MII0_COL FB_A24

81 H10 PTB0/

LLWU_P5 ADC0_SE8/ ADC1_SE8/ ADC2_SE8/ ADC3_SE8/ TSI0_CH0 ADC0_SE8/ ADC1_SE8/ ADC2_SE8/ ADC3_SE8/ TSI0_CH0 PTB0/ LLWU_P5 I2C0_SCLFTM1_CH0RMII0_MDI MII0_MDIO FTM1_QD_ PHA

82 H9 PTB1 ADC0_SE9/

ADC1_SE9/ ADC2_SE9/ ADC3_SE9/ TSI0_CH6 ADC0_SE9/ ADC1_SE9/ ADC2_SE9/ ADC3_SE9/ TSI0_CH6 PTB1 I2C0_SDAFTM1_CH1RMII0_MDC /MII0_MDC FTM1_QD_ PHB

83 G12 PTB2 ADC0_SE1

2/TSI0_CH7 ADC0_SE1 2/TSI0_CH7 PTB2 I2C0_SCLUART0_RT S_b ENET0_158 8_TMR0 FTM0_FLT3

84 G11 PTB3 ADC0_SE1

3/TSI0_CH8 ADC0_SE1 3/TSI0_CH8 PTB3 I2C0_SDAUART0_CT S_b/ UART0_CO L_b ENET0_158 8_TMR1 FTM0_FLT0

85 G10 PTB4 ADC1_SE1

ADC1_SE1 PTB4 ENET0_158 8_TMR2 FTM1_FLT0

86 G9 PTB5 ADC1_SE1

ADC1_SE1 PTB5 ENET0_158 8_TMR3 FTM2_FLT0

87 F12 PTB6 ADC1_SE1

ADC1_SE1 PTB6 FB_AD23

88 F11 PTB7 ADC1_SE1

ADC1_SE1 PTB7 FB_AD22

89 F10 PTB8 DISABLED PTB8 UART3_RT

S_b FB_AD21

90 F9 PTB9 DISABLED PTB9 SPI1_PCS1UART3_CT

S_b FB_AD20

91 E12 PTB10 ADC1_SE1

ADC1_SE1 PTB10 SPI1_PCS0UART3_RXI2S1_TX_B CLK FB_AD19 FTM0_FLT1 Pinout K60 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. Freescale Semiconductor, Inc. Preliminary 75

P 144 MAP BGA Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort

92 E11 PTB11 ADC1_SE1

ADC1_SE1 PTB11 SPI1_SCKUART3_TXI2S1_TX_F S FB_AD18 FTM0_FLT2

93 H7 VSS VSS VSS

94 F5 VDD VDD VDD

95 E10 PTB16 TSI0_CH9TSI0_CH9PTB16 SPI1_SOUTUART0_RXI2S1_TXD0FB_AD17 EWM_IN

96 E9 PTB17 TSI0_CH10TSI0_CH10PTB17 SPI1_SIN UART0_TXI2S1_TXD1FB_AD16 EWM_OUT

97 D12 PTB18 TSI0_CH11TSI0_CH11PTB18 CAN0_TX FTM2_CH0I2S0_TX_B

FB_AD15 FTM2_QD_ PHA

98 D11 PTB19 TSI0_CH12TSI0_CH12PTB19 CAN0_RXFTM2_CH1I2S0_TX_F

S FB_OE_b FTM2_QD_ PHB

99 D10 PTB20 ADC2_SE4

a ADC2_SE4 a PTB20 SPI2_PCS0 FB_AD31/ NFC_DATA CMP0_OUT

100 D9 PTB21 ADC2_SE5

a ADC2_SE5 a PTB21 SPI2_SCK FB_AD30/ NFC_DATA CMP1_OUT

101 C12 PTB22 DISABLED PTB22 SPI2_SOUT FB_AD29/

NFC_DATA CMP2_OUT

102 C11 PTB23 DISABLED PTB23 SPI2_SIN SPI0_PCS5 FB_AD28/

NFC_DATA CMP3_OUT

103 B12 PTC0 ADC0_SE1

TSI0_CH13 ADC0_SE1 TSI0_CH13 PTC0 SPI0_PCS4PDB0_EXT RG FB_AD14/ NFC_DATA I2S0_TXD1

104 B11 PTC1/

LLWU_P6 ADC0_SE1 TSI0_CH14 ADC0_SE1 TSI0_CH14 PTC1/ LLWU_P6 SPI0_PCS3UART1_RT S_b FTM0_CH0FB_AD13/ NFC_DATA I2S0_TXD0

105 A12 PTC2 ADC0_SE4

CMP1_IN0/ TSI0_CH15 ADC0_SE4 CMP1_IN0/ TSI0_CH15 PTC2 SPI0_PCS2UART1_CT S_b FTM0_CH1FB_AD12/ NFC_DATA I2S0_TX_F S

106 A11 PTC3/

LLWU_P7 CMP1_IN1CMP1_IN1PTC3/ LLWU_P7 SPI0_PCS1UART1_RXFTM0_CH2CLKOUT I2S0_TX_B CLK

107 H8 VSS VSS VSS

108 — VDD VDD VDD

109 A9 PTC4/

LLWU_P8 DISABLED PTC4/ LLWU_P8 SPI0_PCS0UART1_TXFTM0_CH3FB_AD11/ NFC_DATA CMP1_OUTI2S1_TX_B CLK

110 D8 PTC5/

LLWU_P9 DISABLED PTC5/ LLWU_P9 SPI0_SCKLPTMR0_A LT2 I2S0_RXD0FB_AD10/ NFC_DATA CMP0_OUTI2S1_TX_F S

111 C8 PTC6/

LLWU_P10 CMP0_IN0CMP0_IN0PTC6/ LLWU_P10 SPI0_SOUTPDB0_EXT RG I2S0_RX_B CLK FB_AD9/ NFC_DATA I2S0_MCLK Pinout K60 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. 76 Preliminary Freescale Semiconductor, Inc.

P 144 MAP BGA Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort

112 B8 PTC7 CMP0_IN1CMP0_IN1PTC7 SPI0_SIN USB_SOF_

I2S0_RX_F S FB_AD8/ NFC_DATA

113 A8 PTC8 ADC1_SE4

CMP0_IN2 ADC1_SE4 CMP0_IN2 PTC8 FTM3_CH4I2S0_MCLKFB_AD7/ NFC_DATA

114 D7 PTC9 ADC1_SE5

CMP0_IN3 ADC1_SE5 CMP0_IN3 PTC9 FTM3_CH5I2S0_RX_B CLK FB_AD6/ NFC_DATA FTM2_FLT0

115 C7 PTC10 ADC1_SE6

b ADC1_SE6 b PTC10 I2C1_SCLFTM3_CH6I2S0_RX_F S FB_AD5/ NFC_DATA I2S1_MCLK

116 B7 PTC11/

LLWU_P11 ADC1_SE7 b ADC1_SE7 b PTC11/ LLWU_P11 I2C1_SDAFTM3_CH7I2S0_RXD1FB_RW_b/ NFC_WE

117 A7 PTC12 DISABLED PTC12 UART4_RT

S_b FB_AD27 FTM3_FLT0

118 D6 PTC13 DISABLED PTC13 UART4_CT

S_b FB_AD26

119 C6 PTC14 DISABLED PTC14 UART4_RX FB_AD25

120 B6 PTC15 DISABLED PTC15 UART4_TX FB_AD24

121 — VSS VSS VSS 122 — VDD VDD VDD

123 A6 PTC16 DISABLED PTC16 CAN1_RXUART3_RXENET0_158

8_TMR0 FB_CS5_b/ FB_TSIZ1/ FB_BE23_1 6_b NFC_RB

124 D5 PTC17 DISABLED PTC17 CAN1_TX UART3_TXENET0_158

8_TMR1 FB_CS4_b/ FB_TSIZ0/ FB_BE31_2 4_b NFC_CE0_ b

125 C5 PTC18 DISABLED PTC18 UART3_RT

S_b ENET0_158 8_TMR2 FB_TBST_b /FB_CS2_b/ FB_BE15_8 NFC_CE1_ b

126 B5 PTC19 DISABLED PTC19 UART3_CT

S_b ENET0_158 8_TMR3 FB_CS3_b/ FB_BE7_0_ b FB_TA_b

127 A5 PTD0/

LLWU_P12 DISABLED PTD0/ LLWU_P12 SPI0_PCS0UART2_RT S_b FTM3_CH0FB_ALE/ FB_CS1_b/ FB_TS_b I2S1_RXD1

128 D4 PTD1 ADC0_SE5

b ADC0_SE5 b PTD1 SPI0_SCKUART2_CT S_b FTM3_CH1FB_CS0_bI2S1_RXD0

129 C4 PTD2/

LLWU_P13 DISABLED PTD2/ LLWU_P13 SPI0_SOUTUART2_RXFTM3_CH2FB_AD4 I2S1_RX_F S

130 B4 PTD3 DISABLED PTD3 SPI0_SIN UART2_TXFTM3_CH3FB_AD3 I2S1_RX_B

131 A4 PTD4/

LLWU_P14 DISABLED PTD4/ LLWU_P14 SPI0_PCS1UART0_RT S_b FTM0_CH4FB_AD2/ NFC_DATA EWM_IN Pinout K60 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. Freescale Semiconductor, Inc. Preliminary 77

P 144 MAP BGA Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort

132 A3 PTD5 ADC0_SE6

b ADC0_SE6 b PTD5 SPI0_PCS2UART0_CT S_b/ UART0_CO L_b FTM0_CH5FB_AD1/ NFC_DATA EWM_OUT

133 A2 PTD6/

LLWU_P15 ADC0_SE7 b ADC0_SE7 b PTD6/ LLWU_P15 SPI0_PCS3UART0_RXFTM0_CH6FB_AD0 FTM0_FLT0

134 M10 VSS VSS VSS

135 F8 VDD VDD VDD

136 A1 PTD7 DISABLED PTD7 CMT_IRO UART0_TXFTM0_CH7 FTM0_FLT1

137 C9 PTD8 DISABLED PTD8 I2C0_SCLUART5_RX FB_A16/

NFC_CLE

138 B9 PTD9 DISABLED PTD9 I2C0_SDAUART5_TX FB_A17/

NFC_ALE

139 B3 PTD10 DISABLED PTD10 UART5_RT

S_b FB_A18/ NFC_RE

140 B2 PTD11 DISABLED PTD11 SPI2_PCS0UART5_CT

S_b SDHC0_CL KIN FB_A19

141 B1 PTD12 DISABLED PTD12 SPI2_SCKFTM3_FLT0SDHC0_D4 FB_A20

142 C3 PTD13 DISABLED PTD13 SPI2_SOUT SDHC0_D5 FB_A21

143 C2 PTD14 DISABLED PTD14 SPI2_SIN SDHC0_D6 FB_A22

144 C1 PTD15 DISABLED PTD15 SPI2_PCS1 SDHC0_D7 FB_A23

8.2 K60 Pinouts

The below figure shows the pinout diagram for the devices supported by this document. Many signals may be multiplexed onto a single pin. To determine what signals can be used on which pin, see the previous section. Pinout K60 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. 78 Preliminary Freescale Semiconductor, Inc.

108 VDD

116 PTC11/LLWU_P11

124 PTC17

132 PTD5

140 PTD11

Figure 35. K60 144 LQFP Pinout Diagram K60 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.

A B C D E F G H J A B C D E F G H J KK LL MM PTA18 PTC8 LLWU_P8 NC LLWU_P7 PTC2 PTA1 PTA6 PTA0 PTE27 ADC0_SE16/ ADC1_SE16/ PTE26 PTE25 PTA2 PTA3 PTA8 PTA7 VSS VSS VSSA VDDA PTE28 VSS USB0_DM PGA2_DM/ PGA3_DM/ PGA0_DM/ DAC0_OUT/ DAC1_OUT/ WAKEUP_B VBAT LLWU_P3 PTA9 PTA11 PTA12 LLWU_P4 PTB1 PTA27 LLWU_P5 PTB4 PTB5 VSS VSS VREFL VREFH PTE11 PTE12 VREGIN VOUT33 USB0_DP PGA2_DP/ PGA3_DP/ PGA0_DP/ PGA1_DP/ PGA1_DM/ VREF_OUT/ PTE24 NC EXTAL32 XTAL32 PTA5 PTA10 VSS PTA16 PTA14 PTB3 PTA29 PTA26 PTA17 PTA15 PTA19 RESET_b PTA24 PTA25 PTA28 PTB2 PTB6 PTB7 PTB8 PTB9 VDD VDD PTB17 PTB16 PTB10 PTB11 PTB19 PTB18 PTB22 PTB23 NC PTB20 PTB21LLWU_P9 PTD8LLWU_P10 PTC7 PTD9 NC LLWU_P6 PTC0 VSS VSS VDD VDD PTC13 PTC9 LLWU_P11 PTC10 PTC19 PTC15 PTC14 PTC18LLWU_P13 PTD3 PTD10 PTD13 PTE0 PTD1 PTC17 VDD VDD PTE7 PTE3LLWU_P2 PTE8 PTE9 PTE10 PTE6 PTE5 LLWU_P0 LLWU_P1 PTD15 PTD14 PTD11 PTD12 PTC12 PTC16LLWU_P12 LLWU_P14PTD5LLWU_P15PTD7 ADC1_DP0/ ADC0_DP3 ADC1_DM0/ ADC0_DM3 CMP1_IN5/ CMP0_IN5/ ADC1_SE18 PTA4/ADC0_DP0/ ADC1_DP3 ADC0_DM0/ ADC1_DM3 CMP1_IN3/ ADC0_SE23 CMP0_IN4/ CMP2_IN3/ ADC1_SE23 RTC_ ADC2_DP3/ ADC1_DP1 ADC3_DM0/ ADC2_DM3/ ADC1_DM1 CMP2_IN2/ ADC0_SE22 PTA13/ADC2_DP0/ ADC3_DP3/ ADC0_DP1 ADC2_DM0/ ADC3_DM3/ ADC0_DM1 CMP1_IN2/ ADC0_SE21 PTB0/ PTE4/ PTE2/ PTE1/ PTC5/ PTC6/ PTD2/ PTC11/ PTC1/ PTC3/ PTC4/PTD0/ PTD4/ PTD6/ Figure 36. K60 144 MAPBGA Pinout Diagram

9 Revision History

The following table provides a revision history for this document. Table 51. Revision History 1 6/2011 Initial public revision. Corrected USB conditions. Table continues on the next page...

Revision History

K60 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. 80 Preliminary Freescale Semiconductor, Inc.

Table 51. Revision History (continued) 2 11/2011 • Added AC electrical specifications.

Updated Part identification section for 120 MHz CPU frequency.
Updated Voltage and current operating ratings section.
Updated Voltage and current operating requirements section.
Updated LVD and POR operating requirements section.
Updated Voltage and current operating behaviors section.
Updated Power mode transition operating behaviors section.
Updated Power consumption operating behaviors section.
In Device clock specifications section, updated flash clock frequency and DDR clock frequency.
Updated Thermal attributes.
In MCG specifications section, updated total deviation of trimmed average DCO output Frequency, PLL reference frequency range, and lock detector detection time.
In Oscillator frequency specifications section, updated crystal startup time — 32 kHz.
Updated NFC specifications section.
In USB DCD electrical specifications section, updated data detect voltage.
In TSI electrical specifications, updated reference oscillator frequency.
Updated Pinouts.
Updated Pinouts.

K60 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. Freescale Semiconductor, Inc. Preliminary 81

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Product Information

K60P144M150SF3 specifications and overview.

Summary

K60 Sub-Family Data Sheet

Description

K60 Sub-Family Data Sheet

Source title K60P144M150SF3 Datasheet(PDF) - Freescale Semiconductor, Inc

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