K50P81M72SF1

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Document overview

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Technical content

Features

• Operating Characteristics – Voltage range: 1.71 to 3.6 V Flash write voltage range: 1.71 to 3.6 V – Temperature range (ambient): -40 to 85°C
• Clocks – 3 to 32 MHz crystal oscillator – 32 kHz crystal oscillator – Multi-purpose clock generator
• System peripherals – 10 low-power modes to provide power optimization based on application requirements – 16-channel DMA controller, supporting up to 63 request sources – External watchdog monitor – Software watchdog – Low-leakage wakeup unit
• Security and integrity modules – Hardware CRC module to support fast cyclic redundancy checks – 128-bit unique identification (ID) number per chip
• Human-machine interface – Low-power hardware touch sensor interface (TSI) – General-purpose input/output
• Analog modules – Two 16-bit SAR ADCs – Programmable gain amplifier (PGA) (up to x64) integrated into each ADC – 12-bit DAC – Two operational amplifiers – One transimpedance amplifier – Three analog comparators (CMP) containing a 6-bit DAC and programmable reference input – Voltage reference
• Timers – Programmable delay block Eight-channel motor control/general purpose/PWM timer – Two 2-channel quadrature decoder/general purpose timers – Periodic interrupt timers – 16-bit low-power timer – Carrier modulator transmitter – Real-time clock
• Communication interfaces – USB full-/low-speed On-the-Go controller with on- chip transceiver – Two SPI modules – Two I2C modules – Four UART modules – I2S module Freescale Semiconductor Document Number: K50P81M72SF1 Data Sheet: Technical Data Rev. 2, 4/2012 Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. © 2012 Freescale Semiconductor, Inc.

3.6 Relationship between ratings and operating

6.6.5 Transimpedance amplifier electrical

6.6.6 Transimpedance amplifier electrical

6.8.4 DSPI switching specifications (limited voltage

6.8.5 DSPI switching specifications (full voltage range).62 K50 Sub-Family Data Sheet, Rev. 2, 4/2012. 2 Freescale Semiconductor, Inc.

K50 Sub-Family Data Sheet, Rev. 2, 4/2012. Freescale Semiconductor, Inc. 3

1 Ordering parts

1.1 Determining valid orderable parts

Valid orderable part numbers are provided on the web. To determine the orderable part numbers for this device, go to http://www.freescale.com and perform a part number search for the following device numbers: PK50 and MK50.

2 Part identification

2.1 Description

Part numbers for the chip have fields that identify the specific part. You can use the values of these fields to determine the specific part you have received.

2.2 Format

Part numbers for this device have the following format: Q K## A M FFF R T PP CC N

2.3 Fields

This table lists the possible values for each field in the part number (not all combinations are valid): Field Description Values Q Qualification status • M = Fully qualified, general market flow

• P = Prequalification K## Kinetis family • K50 A Key attribute • D = Cortex-M4 w/ DSP
• F = Cortex-M4 w/ DSP and FPU M Flash memory type • N = Program flash only
• X = Program flash and FlexMemory Table continues on the next page... Ordering parts K50 Sub-Family Data Sheet, Rev. 2, 4/2012. 4 Freescale Semiconductor, Inc.

FFF Program flash memory size • 32 = 32 KB

• 64 = 64 KB
• 128 = 128 KB
• 256 = 256 KB
• 512 = 512 KB
• 1M0 = 1 MB R Silicon revision • Z = Initial
• (Blank) = Main
• A = Revision after main T Temperature range (°C) • V = –40 to 105
• C = –40 to 85
• FT = 48 QFN (7 mm x 7 mm)
• LF = 48 LQFP (7 mm x 7 mm)
• LH = 64 LQFP (10 mm x 10 mm)
• MP = 64 MAPBGA (5 mm x 5 mm)
• LK = 80 LQFP (12 mm x 12 mm)
• MB = 81 MAPBGA (8 mm x 8 mm)
• LL = 100 LQFP (14 mm x 14 mm)
• ML = 104 MAPBGA (8 mm x 8 mm)
• MC = 121 MAPBGA (8 mm x 8 mm)
• LQ = 144 LQFP (20 mm x 20 mm)
• MD = 144 MAPBGA (13 mm x 13 mm)
• MJ = 256 MAPBGA (17 mm x 17 mm) CC Maximum CPU frequency (MHz) • 5 = 50 MHz
• 7 = 72 MHz
• 10 = 100 MHz
• 12 = 120 MHz
• 15 = 150 MHz N Packaging type • R = Tape and reel
• (Blank) = Trays

2.4 Example

This is an example part number: MK50DN512ZVMD10

3 Terminology and guidelines

Terminology and guidelines K50 Sub-Family Data Sheet, Rev. 2, 4/2012. Freescale Semiconductor, Inc. 5

3.1 Definition: Operating requirement

An operating requirement is a specified value or range of values for a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useful life of the chip.

3.1.1 Example

This is an example of an operating requirement, which you must meet for the accompanying operating behaviors to be guaranteed: Symbol Description Min. Max. Unit VDD 1.0 V core supply voltage 0.9 1.1 V

3.2 Definition: Operating behavior

An operating behavior is a specified value or range of values for a technical characteristic that are guaranteed during operation if you meet the operating requirements and any other specified conditions.

3.2.1 Example

This is an example of an operating behavior, which is guaranteed if you meet the accompanying operating requirements: Symbol Description Min. Max. Unit IWP Digital I/O weak pullup/ pulldown current 10 130 µA

3.3 Definition: Attribute

An attribute is a specified value or range of values for a technical characteristic that are guaranteed, regardless of whether you meet the operating requirements. Terminology and guidelines K50 Sub-Family Data Sheet, Rev. 2, 4/2012. 6 Freescale Semiconductor, Inc.

3.3.1 Example

This is an example of an attribute: Symbol Description Min. Max. Unit CIN_D Input capacitance: digital pins — 7 pF

3.4 Definition: Rating

A rating is a minimum or maximum value of a technical characteristic that, if exceeded, may cause permanent chip failure:

• Operating ratings apply during operation of the chip.
• Handling ratings apply when the chip is not powered.

3.4.1 Example

This is an example of an operating rating: Symbol Description Min. Max. Unit VDD 1.0 V core supply voltage –0.3 1.2 V

3.5 Result of exceeding a rating

Failures in time (ppm) The likelihood of permanent chip failure increases rapidly as soon as a characteristic begins to exceed one of its operating ratings. Terminology and guidelines K50 Sub-Family Data Sheet, Rev. 2, 4/2012. Freescale Semiconductor, Inc. 7

3.6 Relationship between ratings and operating requirements

• No permanent failure - Correct operation Normal operating rangeFatal range Expected permanent failure Fatal range Expected permanent failure Operating rating (max.)Operating requirement (max.)Operating requirement (min.)Operating rating (min.) Operating (power on) Degraded operating range Degraded operating range No permanent failure Handling rangeFatal range Expected permanent failure Fatal range Expected permanent failure Handling rating (max.)Handling rating (min.) Handling (power off) - No permanent failure - Possible decreased life - Possible incorrect operation - No permanent failure - Possible decreased life - Possible incorrect operation

3.7 Guidelines for ratings and operating requirements

Follow these guidelines for ratings and operating requirements:

• Never exceed any of the chip’s ratings.
• During normal operation, don’t exceed any of the chip’s operating requirements.
• If you must exceed an operating requirement at times other than during normal operation (for example, during power sequencing), limit the duration as much as possible.

3.8 Definition: Typical value

A typical value is a specified value for a technical characteristic that:

• Lies within the range of values specified by the operating behavior
• Given the typical manufacturing process, is representative of that characteristic during operation when you meet the typical-value conditions or other specified conditions Typical values are provided as design guidelines and are neither tested nor guaranteed. Terminology and guidelines K50 Sub-Family Data Sheet, Rev. 2, 4/2012. 8 Freescale Semiconductor, Inc.

3.8.1 Example 1

This is an example of an operating behavior that includes a typical value: Symbol Description Min. Typ. Max. Unit IWP Digital I/O weak pullup/pulldown current 10 70 130 µA

3.8.2 Example 2

This is an example of a chart that shows typical values for various voltage and temperature conditions: 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 150 °C 105 °C 25 °C –40 °C VDD (V) I (μA)DD_STOP TJ

3.9 Typical value conditions

Typical values assume you meet the following conditions (or other conditions as specified): Symbol Description Value Unit TA Ambient temperature 25 °C VDD 3.3 V supply voltage 3.3 V Terminology and guidelines K50 Sub-Family Data Sheet, Rev. 2, 4/2012. Freescale Semiconductor, Inc. 9

4 Ratings

4.1 Thermal handling ratings

Symbol Description Min. Max. Unit Notes TSTG Storage temperature –55 150 °C 1 TSDR Solder temperature, lead-free — 260 °C 2 1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life. 2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices.

4.2 Moisture handling ratings

Symbol Description Min. Max. Unit Notes MSL Moisture sensitivity level — 3 — 1 1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices.

4.3 ESD handling ratings

Symbol Description Min. Max. Unit Notes VHBM Electrostatic discharge voltage, human body model -2000 +2000 V 1 VCDM Electrostatic discharge voltage, charged-device model -500 +500 V 2 ILAT Latch-up current at ambient temperature of 105°C -100 +100 mA 1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM). 2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.

4.4 Voltage and current operating ratings

Symbol Description Min. Max. Unit VDD Digital supply voltage –0.3 3.8 V Table continues on the next page... Ratings K50 Sub-Family Data Sheet, Rev. 2, 4/2012. 10 Freescale Semiconductor, Inc.

1. Analog pins are defined as pins that do not have an associated general purpose I/O port function.

5 General

5.1 AC electrical characteristics

Figure 1. Input signal measurement reference

• have C L=30pF loads,
• are configured for fast slew rate (PORTx_PCRn[SRE]=0), and
• are configured for high drive strength (PORTx_PCRn[DSE]=1) 2. input pins
• have their passive filter disabled (PORTx_PCRn[PFE]=0) General K50 Sub-Family Data Sheet, Rev. 2, 4/2012. Freescale Semiconductor, Inc. 11

5.2 Nonswitching electrical specifications

5.2.1 Voltage and current operating requirements

Table 1. Voltage and current operating requirements

• 2.7 V ≤ V DD ≤ 3.6 V
• 1.7 V ≤ V DD ≤ 2.7 V 0.7 × VDD 0.75 × VDD V V VIL Input low voltage
• 2.7 V ≤ V DD ≤ 3.6 V
• 1.7 V ≤ V DD ≤ 2.7 V 0.35 × VDD 0.3 × VDD V V VHYS Input hysteresis 0.06 × VDD — V IICDIO Digital pin negative DC injection current — single pin
• V IN < VSS-0.3V -5 — mA IICAIO Analog2, EXTAL, and XTAL pin DC injection current — single pin
• V IN < VSS-0.3V (Negative current injection)
• V IN > VDD+0.3V (Positive current injection) mA IICcont Contiguous pin DC injection current —regional limit, includes sum of negative injection currents or sum of positive injection currents of 16 contiguous pins
• Negative current injection
• Positive current injection -25 +25 mA VRAM VDD voltage required to retain RAM 1.2 — V VRFVBAT VBAT voltage required to retain the VBAT register file VPOR_VBAT — V 1. All 5 V tolerant digital I/O pins are internally clamped to VSS through a ESD protection diode. There is no diode connection to VDD. If VIN greater than VDIO_MIN (=VSS-0.3V) is observed, then there is no need to provide current limiting resistors at the pads. If this limit cannot be observed then a current limiting resistor is required. The negative DC injection current limiting resistor is calculated as R=(VDIO_MIN-VIN)/|IIC|. 2. Analog pins are defined as pins that do not have an associated general purpose I/O port function. General K50 Sub-Family Data Sheet, Rev. 2, 4/2012. 12 Freescale Semiconductor, Inc.

1. All analog pins are internally clamped to VSS and VDD through ESD protection diodes. If VIN is greater than VAIO_MIN

calcualted as R=(VIN-VAIO_MAX)/|IIC|. Select the larger of these two calculated resistances.

5.2.2 LVD and POR operating requirements

Table 2. V DD supply LVD and POR operating requirements

• Level 1 falling (LVWV=00)
• Level 2 falling (LVWV=01)
• Level 3 falling (LVWV=10)
• Level 4 falling (LVWV=11) 2.62 2.72 2.82 2.92 2.70 2.80 2.90 3.00 2.78 2.88 2.98 3.08 V V V V VHYSH Low-voltage inhibit reset/recover hysteresis — high range — ±80 — mV VLVDL Falling low-voltage detect threshold — low range (LVDV=00) 1.54 1.60 1.66 V VLVW1L VLVW2L VLVW3L VLVW4L Low-voltage warning thresholds — low range
• Level 1 falling (LVWV=00)
• Level 2 falling (LVWV=01)
• Level 3 falling (LVWV=10)
• Level 4 falling (LVWV=11) 1.74 1.84 1.94 2.04 1.80 1.90 2.00 2.10 1.86 1.96 2.06 2.16 V V V V VHYSL Low-voltage inhibit reset/recover hysteresis — low range — ±60 — mV VBG Bandgap voltage reference 0.97 1.00 1.03 V tLPO Internal low power oscillator period — factory trimmed 900 1000 1100 μs 1. Rising thresholds are falling threshold + hysteresis voltage

Table 3. VBAT power operating requirements K50 Sub-Family Data Sheet, Rev. 2, 4/2012.

5.2.3 Voltage and current operating behaviors

Table 4. Voltage and current operating behaviors

• 2.7 V ≤ V DD ≤ 3.6 V, IOH = -9mA
• 1.71 V ≤ V DD ≤ 2.7 V, IOH = -3mA VDD – 0.5 VDD – 0.5 V V Output high voltage — low drive strength
• 2.7 V ≤ V DD ≤ 3.6 V, IOH = -2mA
• 1.71 V ≤ V DD ≤ 2.7 V, IOH = -0.6mA VDD – 0.5 VDD – 0.5 V V IOHT Output high current total for all ports — 100 mA VOL Output low voltage — high drive strength
• 2.7 V ≤ V DD ≤ 3.6 V, IOL = 9mA
• 1.71 V ≤ V DD ≤ 2.7 V, IOL = 3mA 0.5 0.5 V V Output low voltage — low drive strength
• 2.7 V ≤ V DD ≤ 3.6 V, IOL = 2mA
• 1.71 V ≤ V DD ≤ 2.7 V, IOL = 0.6mA 0.5 0.5 V V IOLT Output low current total for all ports — 100 mA IIN Input leakage current (per pin) for full temperature range except TRI0_DM, TRI0_DP, TRI1_DM, TRI1_DP — 1 μA 1 IIN Input leakage current (per pin) at 25°C except TRI0_DM, TRI0_DP, TRI1_DM, TRI1_DP — 0.025 μA 1 IILKG_A Input leakage current (per pin) for TRI0_DM, TRI0_DP, TRI1_DM, TRI1_DP — 5 nA 1 IOZ Hi-Z (off-state) leakage current (per pin) — 1 μA RPU Internal pullup resistors 20 50 kΩ 2 RPD Internal pulldown resistors 20 50 kΩ 3 1. Measured at VDD=3.6V 2. Measured at VDD supply voltage = VDD min and Vinput = VSS 3. Measured at VDD supply voltage = VDD min and Vinput = VDD

5.2.4 Power mode transition operating behaviors

• CPU and system clocks = 72 MHz
• Bus clock = 36 MHz General K50 Sub-Family Data Sheet, Rev. 2, 4/2012. 14 Freescale Semiconductor, Inc.

• FlexBus clock = 36 MHz
• Flash clock = 24 MHz

Table 5. Power mode transition operating behaviors across the operating temperature range of the chip.

• VLLS1 → RUN — 112 μs
• VLLS2 → RUN — 74 μs
• VLLS3 → RUN — 73 μs
• LLS → RUN — 5.9 μs
• VLPS → RUN — 5.8 μs
• STOP → RUN — 4.2 μs 1. Normal boot (FTFL_OPT[LPBOOT]=1)

5.2.5 Power consumption operating behaviors

Table 6. Power consumption operating behaviors

• @ 1.8V
• @ 3.0V 21.5 21.5 mA mA IDD_RUN Run mode current — all peripheral clocks enabled, code executing from flash
• @ 1.8V
• @ 3.0V
• @ 25°C
• @ 125°C mA mA mA 3, 4 IDD_WAIT Wait mode high frequency current at 3.0 V — all peripheral clocks disabled — 12.5 — mA 2 IDD_WAIT Wait mode reduced frequency current at 3.0 V — all peripheral clocks disabled — 7.2 — mA 5 Table continues on the next page... General K50 Sub-Family Data Sheet, Rev. 2, 4/2012. Freescale Semiconductor, Inc. 15

Table 6. Power consumption operating behaviors (continued)

• @ –40 to 25°C
• @ 70°C
• @ 105°C 0.35 0.384 0.628 0.567 0.793 1.2 mA mA mA IDD_VLPS Very-low-power stop mode current at 3.0 V
• @ –40 to 25°C
• @ 70°C
• @ 105°C 5.9 26.1 98.1 32.7 59.8 188 μA μA μA IDD_LLS Low leakage stop mode current at 3.0 V
• @ –40 to 25°C
• @ 70°C
• @ 105°C 2.6 10.3 42.5 8.6 29.1 92.5 μA μA μA IDD_VLLS3 Very low-leakage stop mode 3 current at 3.0 V
• @ –40 to 25°C
• @ 70°C
• @ 105°C 1.9 6.9 28.1 5.8 12.1 41.9 μA μA μA IDD_VLLS2 Very low-leakage stop mode 2 current at 3.0 V
• @ –40 to 25°C
• @ 70°C
• @ 105°C 1.59 4.3 17.5 5.5 9.5 μA μA μA IDD_VLLS1 Very low-leakage stop mode 1 current at 3.0 V
• @ –40 to 25°C
• @ 70°C
• @ 105°C 1.47 2.97 12.41 5.4 8.1 μA μA μA IDD_VBAT Average current with RTC and 32kHz disabled at 3.0 V
• @ –40 to 25°C
• @ 70°C
• @ 105°C 0.19 0.49 2.2 0.22 0.64 3.2 μA μA μA Table continues on the next page... General K50 Sub-Family Data Sheet, Rev. 2, 4/2012. 16 Freescale Semiconductor, Inc.

• @ 1.8V
• @ –40 to 25°C
• @ 70°C
• @ 105°C
• @ 3.0V
• @ –40 to 25°C
• @ 70°C
• @ 105°C 0.57 0.90 2.4 0.67 1.0 2.7 0.67 1.2 3.5 0.94 1.4 3.9 μA μA μA μA μA μA 1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See each module's specification for its supply current. 2. 72MHz core and system clock, 36MHz bus and FlexBus clock, and 24MHz flash clock. MCG configured for FEE mode. All peripheral clocks disabled. 3. 72MHz core and system clock, 36MHz bus and FlexBus clock, and 24MHz flash clock. MCG configured for FEE mode. All peripheral clocks enabled. 4. Max values are measured with CPU executing DSP instructions. 5. 25MHz core, system, bus, FlexBus and flash clock. MCG configured for FEI mode. 6. 4 MHz core and system clock, 4 MHz FlexBus and bus clock, and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral clocks disabled. Code executing from flash. 7. 4 MHz core and system clock, 4 MHz FlexBus and bus clock, and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral clocks enabled but peripherals are not in active operation. Code executing from flash. 8. 4 MHz core and system clock, 4 MHz FlexBus and bus clock, and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral clocks disabled. 9. Data reflects devices with 128 KB of RAM. For devices with 64 KB of RAM, power consumption is reduced by 2 μA. 10. Includes 32kHz oscillator current and RTC operation.

5.2.5.1 Diagram: Typical IDD_RUN operating behavior

• MCG in FBE mode for 50 MHz and lower frequencies. MCG in FEE mode at greater than 50 MHz frequencies.
• USB regulator disabled
• No GPIOs toggled
• Code execution from flash with cache enabled
• For the ALLOFF curve, all peripheral clocks are disabled except FTFL General K50 Sub-Family Data Sheet, Rev. 2, 4/2012. Freescale Semiconductor, Inc. 17

Figure 2. Run mode supply current vs. core frequency K50 Sub-Family Data Sheet, Rev. 2, 4/2012. 18 Freescale Semiconductor, Inc.

Figure 3. VLPR mode supply current vs. core frequency

5.2.6 Designing with radiated emissions in mind

1. Go to http://www.freescale.com.
2. Perform a keyword search for “EMC design.”

5.2.7 Capacitance attributes

Table 7. Capacitance attributes Table continues on the next page... K50 Sub-Family Data Sheet, Rev. 2, 4/2012.

Table 7. Capacitance attributes (continued)

5.3 Switching specifications

5.3.1 Device clock specifications

Table 8. Device clock specifications

1. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for any

K50 Sub-Family Data Sheet, Rev. 2, 4/2012. 20 Freescale Semiconductor, Inc.

5.3.2 General switching specifications

Table 9. General switching specifications

• Slew disabled
• 1.71 ≤ V DD ≤ 2.7V
• Slew enabled
• 1.71 ≤ V DD ≤ 2.7V ns ns ns ns Port rise and fall time (low drive strength)
• Slew disabled
• 1.71 ≤ V DD ≤ 2.7V
• Slew enabled
• 1.71 ≤ V DD ≤ 2.7V ns ns ns ns 1. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or may not be recognized. In Stop, VLPS, LLS, and VLLSx modes, the synchronizer is bypassed so shorter pulses can be recognized in that case. 2. The greater synchronous and asynchronous timing must be met. 3. This is the minimum pulse width that is guaranteed to be recognized as a pin interrupt request in Stop, VLPS, LLS, and VLLSx modes. 4. 75pF load 5. 15pF load

5.4 Thermal specifications

K50 Sub-Family Data Sheet, Rev. 2, 4/2012.

5.4.1 Thermal operating requirements

Table 10. Thermal operating requirements

5.4.2 Thermal attributes

1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site

K50 Sub-Family Data Sheet, Rev. 2, 4/2012. 22 Freescale Semiconductor, Inc.

1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental

JESD51-3 specification. For the MAPBGA, the board meets the JESD51-9 specification.

1. Determined according to JEDEC Standard JESD51-6, Integrated Circuits Thermal Test Method Environmental
2. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental

Conditions—Junction-to-Board. Board temperature is measured on the top surface of the board near the package.

1. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate

between the top of the package and the cold plate.

1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental

Conditions—Natural Convection (Still Air).

6 Peripheral operating requirements and behaviors

6.1 Core modules

6.1.1 Debug trace timing specifications

Table 11. Debug trace operating behaviors Figure 4. TRACE_CLKOUT specifications K50 Sub-Family Data Sheet, Rev. 2, 4/2012.

Figure 5. Trace data specifications

6.1.2 JTAG electricals

Table 12. JTAG voltage range electricals

• JTAG
• CJTAG MHz J2 TCLK cycle period 1/J1 — ns J3 TCLK clock pulse width
• JTAG
• CJTAG 100 200 ns ns ns J4 TCLK rise and fall times — 1 ns J5 TMS input data setup time to TCLK rise
• JTAG
• CJTAG 112 ns J6 TDI input data setup time to TCLK rise 8 — ns J7 TMS input data hold time after TCLK rise
• JTAG
• CJTAG 3.4 3.4 ns J8 TDI input data hold time after TCLK rise 3.4 — ns J9 TCLK low to TMS data valid
• JTAG
• CJTAG ns J10 TCLK low to TDO data valid — 48 ns J11 Output data hold/invalid time after clock edge1 — 3 ns 1. They are common for JTAG and CJTAG. Input transition = 1 ns and Output load = 50pf Peripheral operating requirements and behaviors K50 Sub-Family Data Sheet, Rev. 2, 4/2012. 24 Freescale Semiconductor, Inc.

Figure 8. Test Access Port timing Figure 9. TRST timing

6.2 System modules

There are no specifications necessary for the device's system modules.

6.3 Clock modules

K50 Sub-Family Data Sheet, Rev. 2, 4/2012. 26 Freescale Semiconductor, Inc.

6.3.1 MCG specifications

Table 13. MCG specifications Table continues on the next page... K50 Sub-Family Data Sheet, Rev. 2, 4/2012.

Table 13. MCG specifications (continued)

• f VCO = 48 MHz
• f VCO = 98 MHz 180 150 ps tfll_acquire FLL target frequency acquisition time — — 1 ms 6 PLL fvco VCO operating frequency 48.0 — 100 MHz Ipll PLL operating current
• PLL @ 96 MHz (f osc_hi_1 = 8 MHz, fpll_ref =

2 MHz, VDIV multiplier = 48)

• PLL @ 48 MHz (f osc_hi_1 = 8 MHz, fpll_ref =

2 MHz, VDIV multiplier = 24)

• f vco = 48 MHz
• f vco = 100 MHz 120 ps ps Jacc_pll PLL accumulated jitter over 1µs (RMS)
• f vco = 48 MHz
• f vco = 100 MHz 1350 600 ps ps Dlock Lock entry frequency tolerance ± 1.49 — ± 2.98 % Dunl Lock exit frequency tolerance ± 4.47 — ± 5.97 % tpll_lock Lock detector detection time — — 150 × 10-6 + 1075(1/ fpll_ref) s 9 1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock mode). 2. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0. 3. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency deviation (Δfdco_t) over voltage and temperature should be considered. 4. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1. 5. The resulting clock frequency must not exceed the maximum specified clock frequency of the device. Peripheral operating requirements and behaviors K50 Sub-Family Data Sheet, Rev. 2, 4/2012. 28 Freescale Semiconductor, Inc.

1. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed,

FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.

1. Excludes any oscillator currents that are also consuming power while PLL is in operation.
2. This specification was obtained using a Freescale developed PCB. PLL jitter is dependent on the noise characteristics of

each PCB and results will vary.

1. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled

6.3.2 Oscillator electrical specifications

This section provides the electrical characteristics of the module.

6.3.2.1 Oscillator DC electrical specifications

Table 14. Oscillator DC electrical specifications

• 32 kHz
• 4 MHz
• 8 MHz (RANGE=01)
• 16 MHz
• 24 MHz
• 32 MHz 500 200 300 950 1.2 1.5 nA μA μA μA mA mA IDDOSC Supply current — high gain mode (HGO=1)
• 32 kHz
• 4 MHz
• 8 MHz (RANGE=01)
• 16 MHz
• 24 MHz
• 32 MHz 400 500 2.5 μA μA μA mA mA mA Cx EXTAL load capacitance — — — 2, 3 Cy XTAL load capacitance — — — 2, 3 Table continues on the next page... Peripheral operating requirements and behaviors K50 Sub-Family Data Sheet, Rev. 2, 4/2012. Freescale Semiconductor, Inc. 29

Table 14. Oscillator DC electrical specifications (continued)

1. VDD=3.3 V, Temperature =25 °C
2. See crystal or resonator manufacturer's recommendation
3. Cx,Cy can be provided by using either the integrated capacitors or by using external components.
4. When low power mode is selected, RF is integrated and must not be attached externally.
5. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any

6.3.2.2 Oscillator frequency specifications

Table 15. Oscillator frequency specifications Table continues on the next page... K50 Sub-Family Data Sheet, Rev. 2, 4/2012. 30 Freescale Semiconductor, Inc.

Table 15. Oscillator frequency specifications (continued)

1. Other frequency limits may apply when external clock is being used as a reference for the FLL or PLL.
2. When transitioning from FBE to FEI mode, restrict the frequency of the input clock so that, when it is divided by FRDIV, it

remains within the limits of the DCO input clock frequency.

1. Proper PC board layout procedures must be followed to achieve specifications.
2. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S register

This section describes the module electrical characteristics. Table 16. 32kHz oscillator DC electrical specifications

1. The EXTAL32 and XTAL32 pins should only be connected to required oscillator components and must not be connected to

K50 Sub-Family Data Sheet, Rev. 2, 4/2012.

Table 17. 32kHz oscillator frequency specifications

1. Proper PC board layout procedures must be followed to achieve specifications.

6.4 Memories and memory interfaces

6.4.1 Flash electrical specifications

This section describes the electrical characteristics of the flash memory module.

6.4.1.1 Flash timing specifications — program and erase

active and do not include command overhead. Table 18. NVM program/erase timing specifications

1. Maximum time based on expectations at cycling end-of-life.

6.4.1.2 Flash timing specifications — commands

Table 19. Flash command timing specifications

• 32 KB data flash
• 256 KB program flash 0.5 1.7 ms ms trd1sec1k Read 1s Section execution time (data flash sector) — — 60 μs 1 trd1sec2k Read 1s Section execution time (program flash sector) — — 60 μs 1 Table continues on the next page... Peripheral operating requirements and behaviors K50 Sub-Family Data Sheet, Rev. 2, 4/2012. 32 Freescale Semiconductor, Inc.

Table 19. Flash command timing specifications (continued)

• 32 KB data flash
• 256 KB program flash 122 465 985 ms ms tersscr Erase Flash Sector execution time — 14 114 ms 2 tpgmsec512p tpgmsec512d tpgmsec1kp tpgmsec1kd Program Section execution time
• 512 B program flash
• 512 B data flash
• 1 KB program flash
• 1 KB data flash 2.4 4.7 4.7 9.3 ms ms ms ms trd1all Read 1s All Blocks execution time — — 1.8 ms trdonce Read Once execution time — — 25 μs 1 tpgmonce Program Once execution time — 65 — μs tersall Erase All Blocks execution time — 175 1500 ms 2 tvfykey Verify Backdoor Access Key execution time — — 30 μs 1 tswapx01 tswapx02 tswapx04 tswapx08 Swap Control execution time
• control code 0x01
• control code 0x02
• control code 0x04
• control code 0x08 200 150 150 μs μs μs μs tpgmpart32k Program Partition for EEPROM execution time
• 32 KB FlexNVM ms tsetramff tsetram8k tsetram32k Set FlexRAM Function execution time:
• Control Code 0xFF
• 8 KB EEPROM backup
• 32 KB EEPROM backup 0.3 0.7 0.5 1.0 μs ms ms Byte-write to FlexRAM for EEPROM operation teewr8bers Byte-write to erased FlexRAM location execution time — 175 260 μs 3 Table continues on the next page... Peripheral operating requirements and behaviors K50 Sub-Family Data Sheet, Rev. 2, 4/2012. Freescale Semiconductor, Inc. 33

• 8 KB EEPROM backup
• 16 KB EEPROM backup
• 32 KB EEPROM backup 340 385 475 1700 1800 2000 μs μs μs Word-write to FlexRAM for EEPROM operation teewr16bers Word-write to erased FlexRAM location execution time — 175 260 μs teewr16b8k teewr16b16k teewr16b32k Word-write to FlexRAM execution time:
• 8 KB EEPROM backup
• 16 KB EEPROM backup
• 32 KB EEPROM backup 340 385 475 1700 1800 2000 μs μs μs Longword-write to FlexRAM for EEPROM operation teewr32bers Longword-write to erased FlexRAM location execution time — 360 540 μs teewr32b8k teewr32b16k teewr32b32k Longword-write to FlexRAM execution time:
• 8 KB EEPROM backup
• 16 KB EEPROM backup
• 32 KB EEPROM backup 545 630 810 1950 2050 2250 μs μs μs 1. Assumes 25MHz flash clock frequency. 2. Maximum times for erase parameters based on expectations at cycling end-of-life. 3. For byte-writes to an erased FlexRAM location, the aligned word containing the byte must be erased.

6.4.1.3 Flash current and power specfications

Table 20. Flash current and power specfications

6.4.1.4 Reliability specifications

Table 21. NVM reliability specifications Table continues on the next page... K50 Sub-Family Data Sheet, Rev. 2, 4/2012. 34 Freescale Semiconductor, Inc.

Table 21. NVM reliability specifications (continued)

• EEPROM backup to FlexRAM ratio = 16
• EEPROM backup to FlexRAM ratio = 128
• EEPROM backup to FlexRAM ratio = 512
• EEPROM backup to FlexRAM ratio = 4096
• EEPROM backup to FlexRAM ratio = 8192 35 K 315 K 1.27 M 10 M 20 M 175 K 1.6 M 6.4 M 50 M 100 M writes writes writes writes writes 1. Typical data retention values are based on measured response accelerated at high temperature and derated to a constant 25°C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in Engineering Bulletin EB619. 2. Cycling endurance represents number of program/erase cycles at -40°C ≤ Tj ≤ 125°C. 3. Write endurance represents the number of writes to each FlexRAM location at -40°C ≤Tj ≤ 125°C influenced by the cycling endurance of the FlexNVM (same value as data flash) and the allocated EEPROM backup per subsystem. Minimum and typical values assume all byte-writes to FlexRAM.

6.4.1.5 Write endurance to FlexRAM for EEPROM

can be set to any of several non-zero values. shown below assume that only one configuration is ever used. K50 Sub-Family Data Sheet, Rev. 2, 4/2012.

• Writes_subsystem — minimum number of writes to each FlexRAM location for subsystem (each subsystem can have different endurance)
• EEPROM — allocated FlexNVM for each EEPROM subsystem based on DEPART; entered with Program Partition command
• EEESPLIT — FlexRAM split factor for subsystem; entered with the Program Partition command
• EEESIZE — allocated FlexRAM based on DEPART; entered with Program Partition command
• Write_efficiency —
• 0.25 for 8-bit writes to FlexRAM
• 0.50 for 16-bit or 32-bit writes to FlexRAM
• n nvmcycd — data flash cycling endurance

Figure 10. EEPROM backup writes to FlexRAM K50 Sub-Family Data Sheet, Rev. 2, 4/2012. 36 Freescale Semiconductor, Inc.

6.4.2 EzPort Switching Specifications

Table 22. EzPort switching specifications Figure 11. EzPort Timing Diagram

6.4.3 Flexbus Switching Specifications

the same as the internal system bus frequency or an integer divider of that frequency. K50 Sub-Family Data Sheet, Rev. 2, 4/2012.

Table 23. Flexbus limited voltage range switching specifications

1. Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0], FB_ALE,
2. Specification is valid for all FB_AD[31:0] and FB_TA.

Table 24. Flexbus full voltage range switching specifications

1. Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0], FB_ALE,
2. Specification is valid for all FB_AD[31:0] and FB_TA.

K50 Sub-Family Data Sheet, Rev. 2, 4/2012. 38 Freescale Semiconductor, Inc.

Figure 12. FlexBus read timing diagram K50 Sub-Family Data Sheet, Rev. 2, 4/2012.

Figure 13. FlexBus write timing diagram

6.5 Security and integrity modules

There are no specifications necessary for the device's security and integrity modules.

6.6 Analog

K50 Sub-Family Data Sheet, Rev. 2, 4/2012. 40 Freescale Semiconductor, Inc.

6.6.1 ADC electrical specifications

differential pins ADCx_DP0, ADCx_DM0. Table 25. 16-bit ADC operating conditions

1.13 VDDA VDDA V

• 16 bit modes
• 8/10/12 bit modes pF RADIN Input resistance — 2 5 kΩ RAS Analog source resistance 13/12 bit modes fADCK < 4MHz kΩ fADCK ADC conversion clock frequency ≤ 13 bit modes 1.0 18.0 MHz fADCK ADC conversion clock frequency 16 bit modes 2.0 12.0 MHz Table continues on the next page... Peripheral operating requirements and behaviors K50 Sub-Family Data Sheet, Rev. 2, 4/2012. Freescale Semiconductor, Inc. 41

Table 25. 16-bit ADC operating conditions (continued)

1. Typical values assume VDDA = 3.0 V, Temp = 25°C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for

reference only and are not tested in production.

1. This resistance is external to MCU. The analog source resistance should be kept as low as possible in order to achieve the

CAS time constant should be kept to <1ns.

1. To use the maximum ADC conversion clock frequency, the ADHSC bit should be set and the ADLPC bit should be clear.
2. For guidelines and examples of conversion rate calculation, download the ADC calculator tool: http://cache.freescale.com/

Figure 14. ADC input impedance equivalency diagram K50 Sub-Family Data Sheet, Rev. 2, 4/2012. 42 Freescale Semiconductor, Inc.

Table 26. 16-bit ADC characteristics (V REFH = VDDA, VREFL = VSSA)

• ADLPC=1, ADHSC=0
• ADLPC=1, ADHSC=1
• ADLPC=0, ADHSC=0
• ADLPC=0, ADHSC=1 1.2 3.0 2.4 4.4 2.4 4.0 5.2 6.2 3.9 7.3 6.1 9.5 MHz MHz MHz MHz tADACK = 1/ fADACK Sample Time See Reference Manual chapter for sample times TUE Total unadjusted error
• 12 bit modes
• <12 bit modes ±1.4 ±6.8 ±2.1 LSB4 5 DNL Differential non- linearity
• 12 bit modes
• <12 bit modes ±0.7 ±0.2 -1.1 to +1.9 -0.3 to 0.5 LSB4 5 INL Integral non- linearity
• 12 bit modes
• <12 bit modes ±1.0 ±0.5 -2.7 to +1.9 -0.7 to +0.5 LSB4 5 EFS Full-scale error • 12 bit modes
• <12 bit modes -1.4 -5.4 -1.8 LSB4 VADIN = VDDA EQ Quantization error
• 16 bit modes
• ≤13 bit modes -1 to 0 ±0.5 LSB4 ENOB Effective number of bits 16 bit differential mode
• Avg=32
• Avg=4 16 bit single-ended mode
• Avg=32
• Avg=4 12.8 11.9 12.2 11.4 14.5 13.8 13.9 13.1 bits bits bits bits SINAD Signal-to-noise plus distortion See ENOB 6.02 × ENOB + 1.76 dB THD Total harmonic distortion 16 bit differential mode
• Avg=32 16 bit single-ended mode
• Avg=32 –94 -85 dB dB Table continues on the next page... Peripheral operating requirements and behaviors K50 Sub-Family Data Sheet, Rev. 2, 4/2012. Freescale Semiconductor, Inc. 43

Table 26. 16-bit ADC characteristics (V REFH = VDDA, VREFL = VSSA) (continued)

• Avg=32 16 bit single-ended mode
• Avg=32 dB dB EIL Input leakage error IIn × RAS mV IIn = leakage current (refer to the MCU's voltage and current operating ratings) Temp sensor slope VTEMP25 Temp sensor voltage 25°C — 719 — mV 1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA 2. Typical values assume VDDA = 3.0 V, Temp = 25°C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and the ADLPC bit (low power). For lowest power operation the ADLPC bit should be set, the HSC bit should be clear with 1MHz ADC conversion clock speed. 4. 1 LSB = (VREFH - VREFL)/2N 5. ADC conversion clock <16MHz, Max hardware averaging (AVGE = %1, AVGS = %11) 6. Input data is 100 Hz sine wave. ADC conversion clock <12MHz. 7. Input data is 1 kHz sine wave. ADC conversion clock <12MHz. Peripheral operating requirements and behaviors K50 Sub-Family Data Sheet, Rev. 2, 4/2012. 44 Freescale Semiconductor, Inc.

Table 27. 16-bit ADC with PGA operating conditions

1. Typical values assume VDDA = 3.0 V, Temp = 25°C, fADCK = 6 MHz unless otherwise stated. Typical values are for

reference only and are not tested in production.

1. ADC must be configured to use the internal voltage reference (VREF_OUT)
2. PGA reference is internally connected to the VREF_OUT pin. If the user wishes to drive VREF_OUT with a voltage other

than the output of the VREF module, the VREF module must be disabled.

1. For single ended configurations the input impedance of the driven input is RPGAD/2
2. The analog source resistance (RAS), external to MCU, should be kept as minimum as possible. Increased RAS causes drop

in PGA gain without affecting other performances. This is not dependent on ADC clock frequency.

1. The minimum sampling time is dependent on input signal frequency and ADC mode of operation. A minimum of 1.25µs
2. ADC clock = 18 MHz, ADLSMP = 1, ADLST = 00, ADHSC = 1
3. ADC clock = 12 MHz, ADLSMP = 1, ADLST = 01, ADHSC = 1

K50 Sub-Family Data Sheet, Rev. 2, 4/2012. 46 Freescale Semiconductor, Inc.

Table 28. 16-bit ADC with PGA characteristics

• PGAG=1
• PGAG=2
• PGAG=3
• PGAG=4
• PGAG=5
• PGAG=6 0.95 1.9 3.8 7.6 15.2 30.0 58.8 31.6 63.3 1.05 2.1 4.2 8.4 16.6 33.2 67.8 RAS < 100Ω BW Input signal bandwidth
• 16-bit modes
• < 16-bit modes kHz kHz PSRR Power supply rejection ratio Gain=1 — -84 — dB VDDA= 3V ±100mV, fVDDA= 50Hz, 60Hz CMRR Common mode rejection ratio
• Gain=1
• Gain=64 -84 -85 dB dB VCM= 500mVpp, fVCM= 50Hz, 100Hz VOFS Input offset voltage — 0.2 — mV Output offset = VOFS*(Gain+1) TGSW Gain switching settling time — — 10 µs 5 dG/dT Gain drift over full temperature range
• Gain=1
• Gain=64 ppm/°C ppm/°C dG/dVDDA Gain drift over supply voltage
• Gain=1
• Gain=64 0.07 0.14 0.21 0.31 %/V %/V VDDA from 1.71 to 3.6V Table continues on the next page... Peripheral operating requirements and behaviors K50 Sub-Family Data Sheet, Rev. 2, 4/2012. Freescale Semiconductor, Inc. 47

Table 28. 16-bit ADC with PGA characteristics (continued)

• Gain=1
• Gain=64 dB dB 16-bit differential mode, Average=32 THD Total harmonic distortion
• Gain=1
• Gain=64 100 dB dB 16-bit differential mode, Average=32, fin=100Hz SFDR Spurious free dynamic range
• Gain=1
• Gain=64 105 dB dB 16-bit differential mode, Average=32, fin=100Hz ENOB Effective number of bits
• Gain=1, Average=4
• Gain=64, Average=4
• Gain=1, Average=32
• Gain=2, Average=32
• Gain=4, Average=32
• Gain=8, Average=32
• Gain=16, Average=32
• Gain=32, Average=32
• Gain=64, Average=32 11.6 7.2 12.8 11.0 7.9 7.3 6.8 6.8 7.5 13.4 9.6 14.5 14.3 13.8 13.1 12.5 11.5 10.6 bits bits bits bits bits bits bits bits bits 16-bit differential mode,fin=100H z SINAD Signal-to-noise plus distortion ratio See ENOB 6.02 × ENOB + 1.76 dB 1. Typical values assume VDDA =3.0V, Temp=25°C, fADCK=6MHz unless otherwise stated. 2. This current is a PGA module adder, in addition to ADC conversion currents. 3. Between IN+ and IN-. The PGA draws a DC current from the input terminals. The magnitude of the DC current is a strong function of input common mode voltage (VCM) and the PGA gain. 4. Gain = 2PGAG 5. After changing the PGA gain setting, a minimum of 2 ADC+PGA conversions should be ignored. 6. Limit the input signal swing so that the PGA does not saturate during operation. Input signal swing is dependent on the PGA reference voltage and gain setting. Peripheral operating requirements and behaviors K50 Sub-Family Data Sheet, Rev. 2, 4/2012. 48 Freescale Semiconductor, Inc.

6.6.2 CMP and 6-bit DAC electrical specifications

Table 29. Comparator and 6-bit DAC electrical specifications

• CR0[HYSTCTR] = 00
• CR0[HYSTCTR] = 01
• CR0[HYSTCTR] = 10
• CR0[HYSTCTR] = 11 mV mV mV mV VCMPOh Output high VDD – 0.5 — — V VCMPOl Output low — — 0.5 V tDHS Propagation delay, high-speed mode (EN=1, PMODE=1) 20 50 200 ns tDLS Propagation delay, low-speed mode (EN=1, PMODE=0) 80 250 600 ns Analog comparator initialization delay2 — — 40 μs IDAC6b 6-bit DAC current adder (enabled) — 7 — μA INL 6-bit DAC integral non-linearity –0.5 — 0.5 LSB3 DNL 6-bit DAC differential non-linearity –0.3 — 0.3 LSB 1. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD-0.6V. 2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to DACEN, VRSEL, PSEL, MSEL, VOSEL) and the comparator output settling to a stable level. 3. 1 LSB = Vreference/64 Peripheral operating requirements and behaviors K50 Sub-Family Data Sheet, Rev. 2, 4/2012. Freescale Semiconductor, Inc. 49

Figure 17. Typical hysteresis vs. Vin level (VDD=3.3V, PMODE=0) K50 Sub-Family Data Sheet, Rev. 2, 4/2012. 50 Freescale Semiconductor, Inc.

Figure 18. Typical hysteresis vs. Vin level (VDD=3.3V, PMODE=1) Table 30. 12-bit DAC operating requirements

1. The DAC reference can be selected to be VDDA or the voltage output of the VREF module (VREF_OUT)
2. A small load capacitance (47 pF) can improve the bandwidth performance of the DAC

K50 Sub-Family Data Sheet, Rev. 2, 4/2012.

Table 31. 12-bit DAC operating behaviors

• High power (SP HP)
• Low power (SP LP) 1.2 0.05 1.7 0.12 V/μs CT Channel to channel cross talk — — -80 dB BW 3dB bandwidth
• High power (SP HP)
• Low power (SP LP) 550 kHz 1. Settling within ±1 LSB 2. The INL is measured for 0+100mV to VDACR−100 mV 3. The DNL is measured for 0+100 mV to VDACR−100 mV 4. The DNL is measured for 0+100mV to VDACR−100 mV with VDDA > 2.4V 5. Calculated by a best fit curve from VSS+100 mV to VDACR−100 mV Peripheral operating requirements and behaviors K50 Sub-Family Data Sheet, Rev. 2, 4/2012. 52 Freescale Semiconductor, Inc.

1. VDDA = 3.0V, reference select set for VDDA (DACx_CO:DACRFS = 1), high power mode(DACx_C0:LPEN = 0), DAC set

Figure 19. Typical INL error vs. digital code K50 Sub-Family Data Sheet, Rev. 2, 4/2012.

Figure 20. Offset at half scale vs. temperature

6.6.4 Op-amp electrical specifications

Table 32. Op-amp electrical specifications Table continues on the next page... K50 Sub-Family Data Sheet, Rev. 2, 4/2012. 54 Freescale Semiconductor, Inc.

Table 32. Op-amp electrical specifications (continued)

1. The input capacitance is dependant on the package type used.
2. Settling time is measured from the time the Op-amp is enabled until the output settles to within 0.1% of final value. This

time includes Op-amp startup time, output slew, and settle time. K50 Sub-Family Data Sheet, Rev. 2, 4/2012.

6.6.5 Transimpedance amplifier electrical specifications — full range

Table 33. TRIAMP full range operating requirements Table 34. TRIAMP full range operating behaviors K50 Sub-Family Data Sheet, Rev. 2, 4/2012. 56 Freescale Semiconductor, Inc.

6.6.6 Transimpedance amplifier electrical specifications — limited

Table 35. TRIAMP limited range operating requirements Table 36. TRIAMP limited range operating behaviors

6.6.7 Voltage reference electrical specifications

K50 Sub-Family Data Sheet, Rev. 2, 4/2012.

Table 37. VREF full-range operating requirements

1. CL must be connected to VREF_OUT if the VREF_OUT functionality is being used for either an internal or external
2. The load capacitance should not exceed +/-25% of the nominal specified CL value over the operating temperature range of

Table 38. VREF full-range operating behaviors

• current = ± 1.0 mA 200 µV 1, 2 Tstup Buffer startup time — — 20 µs Vvdrift Voltage drift (Vmax - Vmin across the full voltage range) — 2 — mV 1 1. See the chip's Reference Manual for the appropriate settings of the VREF Status and Control register. 2. Load regulation voltage is the difference between the VREF_OUT voltage with no load vs. voltage with defined load

Table 39. VREF limited-range operating requirements Table 40. VREF limited-range operating behaviors K50 Sub-Family Data Sheet, Rev. 2, 4/2012. 58 Freescale Semiconductor, Inc.

6.7 Timers

See General switching specifications.

6.8 Communication interfaces

6.8.1 USB electrical specifications

standards, visit http://www.usb.org.

6.8.2 USB DCD electrical specifications

Table 42. USB DCD electrical specifications K50 Sub-Family Data Sheet, Rev. 2, 4/2012.

6.8.3 USB VREG electrical specifications

Table 43. USB VREG electrical specifications

• VREGIN = 5.0 V and temperature=25C
• Across operating voltage and temperature 650 nA μA ILOADrun Maximum load current — Run mode — — 120 mA ILOADstby Maximum load current — Standby mode — — 1 mA VReg33out Regulator output voltage — Input supply (VREGIN) > 3.6 V
• Run mode
• Standby mode 2.1 3.3 2.8 3.6 3.6 V V VReg33out Regulator output voltage — Input supply (VREGIN) < 3.6 V, pass-through mode 2.1 — 3.6 V 2 COUT External output capacitor 1.76 2.2 8.16 μF ESR External output capacitor equivalent series resistance 1 — 100 mΩ ILIM Short circuit current — 290 — mA 1. Typical values assume VREGIN = 5.0 V, Temp = 25 °C unless otherwise stated. 2. Operating in pass-through mode: regulator output voltage equal to the input voltage minus a drop proportional to ILoad.

6.8.4 DSPI switching specifications (limited voltage range)

used for communicating with slower peripheral devices. Table 44. Master mode DSPI timing (limited voltage range) Table continues on the next page... K50 Sub-Family Data Sheet, Rev. 2, 4/2012. 60 Freescale Semiconductor, Inc.

Table 44. Master mode DSPI timing (limited voltage range) (continued)

1. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
2. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].

Figure 21. DSPI classic SPI timing — master mode Table 45. Slave mode DSPI timing (limited voltage range) K50 Sub-Family Data Sheet, Rev. 2, 4/2012.

Figure 22. DSPI classic SPI timing — slave mode

6.8.5 DSPI switching specifications (full voltage range)

used for communicating with slower peripheral devices. Table 46. Master mode DSPI timing (full voltage range)

1. The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage

range the maximum frequency of operation is reduced.

1. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
2. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].

K50 Sub-Family Data Sheet, Rev. 2, 4/2012. 62 Freescale Semiconductor, Inc.

6.8.6 I2C switching specifications

See General switching specifications.

6.8.7 UART switching specifications

See General switching specifications.

6.8.8 I2S/SAI Switching Specifications

frame sync (FS) signal shown in the following figures.

6.8.8.1 Normal Run, Wait and Stop mode performance over the full

device in Normal Run, Wait and Stop modes. Table 48. I2S/SAI master mode timing in Normal Run, Wait and Stop modes K50 Sub-Family Data Sheet, Rev. 2, 4/2012. 64 Freescale Semiconductor, Inc.

Figure 25. I2S/SAI timing — master modes Table 49. I2S/SAI slave mode timing in Normal Run, Wait and Stop modes

1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear

K50 Sub-Family Data Sheet, Rev. 2, 4/2012.

Figure 26. I2S/SAI timing — slave modes

6.8.8.2 VLPR, VLPW, and VLPS mode performance over the full operating

device in VLPR, VLPW, and VLPS modes. Table 50. I2S/SAI master mode timing in VLPR, VLPW, and VLPS modes K50 Sub-Family Data Sheet, Rev. 2, 4/2012. 66 Freescale Semiconductor, Inc.

Figure 27. I2S/SAI timing — master modes Table 51. I2S/SAI slave mode timing in VLPR, VLPW, and VLPS modes (full

1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear

K50 Sub-Family Data Sheet, Rev. 2, 4/2012.

Figure 28. I2S/SAI timing — slave modes

6.9 Human-machine interfaces (HMI)

6.9.1 TSI electrical specifications

Table 52. TSI electrical specifications

• 2 μA setting (REFCHRG = 0)
• 32 μA setting (REFCHRG = 15) μA 2, 6 IELE Electrode oscillator current source base current
• 2 μA setting (EXTCHRG = 0)
• 32 μA setting (EXTCHRG = 15) μA 2, 7 Pres5 Electrode capacitance measurement precision — 8.3333 38400 fF/count 8 Pres20 Electrode capacitance measurement precision — 8.3333 38400 fF/count 9 Pres100 Electrode capacitance measurement precision — 8.3333 38400 fF/count 10 MaxSens Maximum sensitivity 0.003 12.5 — fF/count 11 Res Resolution — — 16 bits Table continues on the next page... Peripheral operating requirements and behaviors K50 Sub-Family Data Sheet, Rev. 2, 4/2012. 68 Freescale Semiconductor, Inc.

Table 52. TSI electrical specifications (continued)

1. The TSI module is functional with capacitance values outside this range. However, optimal performance is not guaranteed.
2. Fixed external capacitance of 20 pF.
3. REFCHRG = 0, EXTCHRG = 10.
4. The programmable current source value is generated by multiplying the SCANC[REFCHRG] value and the base current.
5. The programmable current source value is generated by multiplying the SCANC[EXTCHRG] value and the base current.
6. Measured with a 5 pF electrode, reference oscillator frequency of 10 MHz, PS = 128, NSCN = 8; Iext = 16.
7. Measured with a 20 pF electrode, reference oscillator frequency of 10 MHz, PS = 128, NSCN = 2; Iext = 16.
8. Measured with a 20 pF electrode, reference oscillator frequency of 10 MHz, PS = 16, NSCN = 3; Iext = 16.
9. Sensitivity defines the minimum capacitance change when a single count from the TSI module changes, it is equal to (Cref

on the following configuration: Iext = 2 μA (EXTCHRG = 0), PS = 128, NSCN = 32, Iref = 32 μA (REFCHRG = 15).

1. Time to do one complete measurement of the electrode. Sensitivity resolution of 0.0133 pF, PS = 0, NSCN = 0, 1
2. REFCHRG=0, EXTCHRG=4, PS=7, NSCN=0F, LPSCNITV=F, LPO is selected (1 kHz), and fixed external capacitance of

20 pF. Data is captured with an average of 7 periods window.

7 Dimensions

7.1 Obtaining package dimensions

Package dimensions are provided in package drawings.

8 Pinout

K50 Sub-Family Data Sheet, Rev. 2, 4/2012.

8.1 K50 Signal Multiplexing and Pin Assignments

The following table shows the signals available on each pin and the locations of these pins on the devices supported by this document. The Port Control Module is responsible for selecting which ALT functionality is available on each pin. MAP BGA LQFP Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort E7 — VDD VDD VDD F7 — VSS VSS VSS E6 1 VDD VDD VDD G7 2 VSS VSS VSS L6 — VSS VSS VSS F1 3 USB0_DPUSB0_DPUSB0_DP F2 4 USB0_DMUSB0_DMUSB0_DM G1 5 VOUT33 VOUT33 VOUT33 G2 6 VREGIN VREGIN VREGIN H1 7 ADC0_DP1/ OP0_DP0 ADC0_DP1/ OP0_DP0 ADC0_DP1/ OP0_DP0 H2 8 ADC0_DM1/ OP0_DM0 ADC0_DM1/ OP0_DM0 ADC0_DM1/ OP0_DM0 J1 9 ADC1_DP1/ OP1_DP0/ OP1_DM1 ADC1_DP1/ OP1_DP0/ OP1_DM1 ADC1_DP1/ OP1_DP0/ OP1_DM1 J2 10 ADC1_DM1/ OP1_DM0 ADC1_DM1/ OP1_DM0 ADC1_DM1/ OP1_DM0 K1 11 PGA0_DP/ ADC0_DP0/ ADC1_DP3 PGA0_DP/ ADC0_DP0/ ADC1_DP3 PGA0_DP/ ADC0_DP0/ ADC1_DP3 K2 12 PGA0_DM/ ADC0_DM0/ ADC1_DM3 PGA0_DM/ ADC0_DM0/ ADC1_DM3 PGA0_DM/ ADC0_DM0/ ADC1_DM3 L1 13 PGA1_DP/ ADC1_DP0/ ADC0_DP3 PGA1_DP/ ADC1_DP0/ ADC0_DP3 PGA1_DP/ ADC1_DP0/ ADC0_DP3 L2 14 PGA1_DM/ ADC1_DM0/ ADC0_DM3 PGA1_DM/ ADC1_DM0/ ADC0_DM3 PGA1_DM/ ADC1_DM0/ ADC0_DM3 F5 15 VDDA VDDA VDDA G5 16 VREFH VREFH VREFH G6 17 VREFL VREFL VREFL F6 18 VSSA VSSA VSSA J3 19 ADC1_SE16/ OP1_OUT/ CMP2_IN2/ ADC0_SE22/ OP0_DP2/ OP1_DP2 ADC1_SE16/ OP1_OUT/ CMP2_IN2/ ADC0_SE22/ OP0_DP2/ OP1_DP2 ADC1_SE16/ OP1_OUT/ CMP2_IN2/ ADC0_SE22/ OP0_DP2/ OP1_DP2 Pinout K50 Sub-Family Data Sheet, Rev. 2, 4/2012. 70 Freescale Semiconductor, Inc.

Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort H3 20 ADC0_SE16/ OP0_OUT/ CMP1_IN2/ ADC0_SE21/ OP0_DP1/ OP1_DP1 ADC0_SE16/ OP0_OUT/ CMP1_IN2/ ADC0_SE21/ OP0_DP1/ OP1_DP1 ADC0_SE16/ OP0_OUT/ CMP1_IN2/ ADC0_SE21/ OP0_DP1/ OP1_DP1 L3 21 VREF_OUT/ CMP1_IN5/ CMP0_IN5/ ADC1_SE18 VREF_OUT/ CMP1_IN5/ CMP0_IN5/ ADC1_SE18 VREF_OUT/ CMP1_IN5/ CMP0_IN5/ ADC1_SE18 K3 22 TRI0_OUT/ OP1_DM2 TRI0_OUT/ OP1_DM2 TRI0_OUT/ OP1_DM2 H4 23 TRI0_DM TRI0_DM TRI0_DM J4 24 TRI0_DP TRI0_DP TRI0_DP H5 25 NC NC NC J5 26 NC NC NC H6 27 CMP2_IN5/ ADC1_SE22 CMP2_IN5/ ADC1_SE22 CMP2_IN5/ ADC1_SE22 K5 28 DAC0_OUT/ CMP1_IN3/ ADC0_SE23/ OP0_DP4/ OP1_DP4 DAC0_OUT/ CMP1_IN3/ ADC0_SE23/ OP0_DP4/ OP1_DP4 DAC0_OUT/ CMP1_IN3/ ADC0_SE23/ OP0_DP4/ OP1_DP4 K4 29 CMP0_IN4/ CMP2_IN3/ ADC1_SE23/ OP0_DP5/ OP1_DP5 CMP0_IN4/ CMP2_IN3/ ADC1_SE23/ OP0_DP5/ OP1_DP5 CMP0_IN4/ CMP2_IN3/ ADC1_SE23/ OP0_DP5/ OP1_DP5 L7 — RTC_ WAKEUP_B RTC_ WAKEUP_B RTC_ WAKEUP_B L4 30 XTAL32 XTAL32 XTAL32 L5 31 EXTAL32 EXTAL32 EXTAL32 K6 32 VBAT VBAT VBAT J6 33 PTA0 JTAG_TCLK/ SWD_CLK/ EZP_CLK TSI0_CH1PTA0 UART0_CTS_ UART0_COL_ b FTM0_CH5 JTAG_TCLK/ SWD_CLK EZP_CLK H8 34 PTA1 JTAG_TDI/ EZP_DI TSI0_CH2PTA1 UART0_RXFTM0_CH6 JTAG_TDIEZP_DI J7 35 PTA2 JTAG_TDO/ TRACE_SWO/ EZP_DO TSI0_CH3PTA2 UART0_TXFTM0_CH7 JTAG_TDO/ TRACE_SWO EZP_DO H9 36 PTA3 JTAG_TMS/ SWD_DIO TSI0_CH4PTA3 UART0_RTS_ b FTM0_CH0 JTAG_TMS/ SWD_DIO J8 37 PTA4/ LLWU_P3 NMI_b/ EZP_CS_b TSI0_CH5PTA4/ LLWU_P3 FTM0_CH1 NMI_b EZP_CS_b E5 — VDD VDD VDD G3 — VSS VSS VSS Pinout K50 Sub-Family Data Sheet, Rev. 2, 4/2012. Freescale Semiconductor, Inc. 71

Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort L10 38 VDD VDD VDD K10 39 VSS VSS VSS L11 40 PTA18 EXTAL0 EXTAL0 PTA18 FTM0_FLT2FTM_CLKIN0 K11 41 PTA19 XTAL0 XTAL0 PTA19 FTM1_FLT0FTM_CLKIN1 LPTMR0_ ALT1 J11 42 RESET_b RESET_b RESET_b G11 43 PTB0/ LLWU_P5 ADC0_SE8/ ADC1_SE8/ TSI0_CH0 ADC0_SE8/ ADC1_SE8/ TSI0_CH0 PTB0/ LLWU_P5 I2C0_SCLFTM1_CH0 FTM1_QD_ PHA G10 44 PTB1 ADC0_SE9/ ADC1_SE9/ TSI0_CH6 ADC0_SE9/ ADC1_SE9/ TSI0_CH6 PTB1 I2C0_SDAFTM1_CH1 FTM1_QD_ PHB G9 45 PTB2 ADC0_SE12/ TSI0_CH7 ADC0_SE12/ TSI0_CH7 PTB2 I2C0_SCLUART0_RTS_ b FTM0_FLT3 G8 46 PTB3 ADC0_SE13/ TSI0_CH8 ADC0_SE13/ TSI0_CH8 PTB3 I2C0_SDAUART0_CTS_ UART0_COL_ b FTM0_FLT0 D10 47 PTB10 ADC1_SE14ADC1_SE14PTB10 SPI1_PCS0UART3_RX FB_AD19 FTM0_FLT1 C10 48 PTB11 ADC1_SE15ADC1_SE15PTB11 SPI1_SCKUART3_TX FB_AD18 FTM0_FLT2 — 49 VSS VSS VSS — 50 VDD VDD VDD B10 51 PTB16 TSI0_CH9TSI0_CH9PTB16 SPI1_SOUTUART0_RX FB_AD17 EWM_IN E9 52 PTB17 TSI0_CH10TSI0_CH10PTB17 SPI1_SIN UART0_TX FB_AD16 EWM_OUT_b D9 53 PTB18 TSI0_CH11TSI0_CH11PTB18 FTM2_CH0I2S0_TX_ BCLK FB_AD15 FTM2_QD_ PHA C9 54 PTB19 TSI0_CH12TSI0_CH12PTB19 FTM2_CH1I2S0_TX_FSFB_OE_b FTM2_QD_ PHB B9 55 PTC0 ADC0_SE14/ TSI0_CH13 ADC0_SE14/ TSI0_CH13 PTC0 SPI0_PCS4PDB0_EXTRG FB_AD14 I2S0_TXD1 D8 56 PTC1/ LLWU_P6 ADC0_SE15/ TSI0_CH14 ADC0_SE15/ TSI0_CH14 PTC1/ LLWU_P6 SPI0_PCS3UART1_RTS_ b FTM0_CH0FB_AD13 I2S0_TXD0 C8 57 PTC2 ADC0_SE4b/ CMP1_IN0/ TSI0_CH15 ADC0_SE4b/ CMP1_IN0/ TSI0_CH15 PTC2 SPI0_PCS2UART1_CTS_ b FTM0_CH1FB_AD12 I2S0_TX_FS B8 58 PTC3/ LLWU_P7 CMP1_IN1CMP1_IN1PTC3/ LLWU_P7 SPI0_PCS1UART1_RXFTM0_CH2CLKOUT I2S0_TX_ BCLK — 59 VSS VSS VSS — 60 VDD VDD VDD A8 61 PTC4/ LLWU_P8 DISABLED PTC4/ LLWU_P8 SPI0_PCS0UART1_TXFTM0_CH3FB_AD11 CMP1_OUT D7 62 PTC5/ LLWU_P9 DISABLED PTC5/ LLWU_P9 SPI0_SCKLPTMR0_ ALT2 I2S0_RXD0FB_AD10 CMP0_OUT C7 63 PTC6/ LLWU_P10 CMP0_IN0CMP0_IN0PTC6/ LLWU_P10 SPI0_SOUTPDB0_EXTRGI2S0_RX_ BCLK FB_AD9 I2S0_MCLK Pinout K50 Sub-Family Data Sheet, Rev. 2, 4/2012. 72 Freescale Semiconductor, Inc.

Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort B7 64 PTC7 CMP0_IN1CMP0_IN1PTC7 SPI0_SIN USB_SOF_ OUT I2S0_RX_FSFB_AD8 A7 65 PTC8 ADC1_SE4b/ CMP0_IN2 ADC1_SE4b/ CMP0_IN2 PTC8 I2S0_MCLKFB_AD7 D6 66 PTC9 ADC1_SE5b/ CMP0_IN3 ADC1_SE5b/ CMP0_IN3 PTC9 I2S0_RX_ BCLK FB_AD6 FTM2_FLT0 C6 67 PTC10 ADC1_SE6bADC1_SE6bPTC10 I2C1_SCL I2S0_RX_FSFB_AD5 C5 68 PTC11/ LLWU_P11 ADC1_SE7bADC1_SE7bPTC11/ LLWU_P11 I2C1_SDA I2S0_RXD1FB_RW_b — 69 VSS VSS VSS — 70 VDD VDD VDD D5 71 PTC16 DISABLED PTC16 UART3_RX FB_CS5_b/ FB_TSIZ1/ FB_BE23_16_ BLS15_8_b C4 72 PTC17 DISABLED PTC17 UART3_TX FB_CS4_b/ FB_TSIZ0/ FB_BE31_24_ BLS7_0_b D4 73 PTD0/ LLWU_P12 DISABLED PTD0/ LLWU_P12 SPI0_PCS0UART2_RTS_ b FB_ALE/ FB_CS1_b/ FB_TS_b D3 74 PTD1 ADC0_SE5bADC0_SE5bPTD1 SPI0_SCKUART2_CTS_ b FB_CS0_b C3 75 PTD2/ LLWU_P13 DISABLED PTD2/ LLWU_P13 SPI0_SOUTUART2_RX FB_AD4 B3 76 PTD3 DISABLED PTD3 SPI0_SIN UART2_TX FB_AD3 A3 77 PTD4/ LLWU_P14 DISABLED PTD4/ LLWU_P14 SPI0_PCS1UART0_RTS_ b FTM0_CH4FB_AD2 EWM_IN A2 78 PTD5 ADC0_SE6bADC0_SE6bPTD5 SPI0_PCS2UART0_CTS_ UART0_COL_ b FTM0_CH5FB_AD1 EWM_OUT_b B2 79 PTD6/ LLWU_P15 ADC0_SE7bADC0_SE7bPTD6/ LLWU_P15 SPI0_PCS3UART0_RXFTM0_CH6FB_AD0 FTM0_FLT0 A1 80 PTD7 DISABLED PTD7 CMT_IRO UART0_TXFTM0_CH7 FTM0_FLT1 A11 — NC NC NC B11 — NC NC NC C11 — NC NC NC E4 — NC NC NC E3 — NC NC NC E2 — NC NC NC F4 — NC NC NC H7 — NC NC NC G4 — NC NC NC F3 — NC NC NC Pinout K50 Sub-Family Data Sheet, Rev. 2, 4/2012. Freescale Semiconductor, Inc. 73

Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort K7 — NC NC NC J9 — NC NC NC K8 — NC NC NC L8 — NC NC NC K9 — NC NC NC L9 — NC NC NC J10 — NC NC NC H10 — NC NC NC H11 — NC NC NC F11 — NC NC NC E11 — NC NC NC D11 — NC NC NC E10 — NC NC NC F10 — NC NC NC F9 — NC NC NC F8 — NC NC NC E8 — NC NC NC B6 — NC NC NC A6 — NC NC NC A5 — NC NC NC B5 — NC NC NC B4 — NC NC NC A4 — NC NC NC A10 — NC NC NC A9 — NC NC NC B1 — NC NC NC C2 — NC NC NC C1 — NC NC NC D2 — NC NC NC D1 — NC NC NC E1 — NC NC NC

8.2 K50 Pinouts

The below figure shows the pinout diagram for the devices supported by this document. Many signals may be multiplexed onto a single pin. To determine what signals can be used on which pin, see the previous section. Pinout K50 Sub-Family Data Sheet, Rev. 2, 4/2012. 74 Freescale Semiconductor, Inc.

Figure 29. K50 80 LQFP Pinout Diagram K50 Sub-Family Data Sheet, Rev. 2, 4/2012.

F USB0_DP G VOUT33 H OP0_DP0 J OP1_DM1 K ADC1_DP3 L ADC0_DP3 PTD5 PTD6/ NC NC NC USB0_DM VREGIN OP0_DM0 OP1_DM0 ADC1_DM3 PGA1_DM/ PTD4/ PTD3 PTD2/ PTD1 NC NC VSS OP1_DP1 OP1_DP2 OP1_DM2 ADC1_SE18 NC NC PTC17 PTD0/ NC NC NC TRI0_DM TRI0_DP OP1_DP5 XTAL32 NC NC PTC11/ PTC16 VDD VDDA VREFH NC NC OP1_DP4 EXTAL32 NC NC PTC10 PTC9 VDD VSSA VREFL ADC1_SE22 PTA0 VBAT VSS PTC8 PTC7 PTC6/ PTC5/ VDD VSS VSS NC PTA2 NC RTC_ PTC4/ PTC3/ PTC2 PTC1/ NC NC PTB3 PTA1 PTA4/ NC NC NC PTC0 PTB19 PTB18 PTB17 NC PTB2 PTA3 NC NC NC NC PTB16 PTB11 PTB10 NC NC PTB1 NC NC VSS VDD ANC BNC CNC DNC ENC FNC GPTB0/ HNC JRESET_b KPTA19 LPTA18WAKEUP_BCMP0_IN5/ CMP1_IN5/ VREF_OUT/ ADC1_DM0/ PGA1_DM/ ADC1_DP0/ PGA1_DP/ ADC0_DP0/ PGA0_DP/ OP0_DP4/ ADC0_SE23/ CMP1_IN3/ DAC0_OUT/ OP0_DP5/ ADC1_SE23/ CMP2_IN3/ CMP0_IN4/ TRI0_OUT/ADC0_DM0/ PGA0_DM/ OP1_DP0/ ADC1_DP1/ OP0_DP2/ ADC0_SE22/ CMP2_IN2/ OP1_OUT/ ADC1_SE16/ ADC1_DM1/ LLWU_P3 CMP2_IN5/ OP0_DP1/ ADC0_SE21/ CMP1_IN2/ OP0_OUT/ ADC0_SE16/ ADC0_DM1/ ADC0_DP1/ LLWU_P5 LLWU_P12 LLWU_P9 LLWU_P6 LLWU_P10 LLWU_P11 LLWU_P13 LLWU_P7LLWU_P15 LLWU_P14 LLWU_P8 Figure 30. K50 81 MAPBGA Pinout Diagram

9 Revision History

The following table provides a revision history for this document. Table 53. Revision History Table continues on the next page...

Revision History

K50 Sub-Family Data Sheet, Rev. 2, 4/2012. 76 Freescale Semiconductor, Inc.

Table 53. Revision History (continued) 2 4/2012 • Replaced TBDs throughout.

• Updated "Power consumption operating behaviors" table.
• Updated "ADC electrical specifications" section.
• Updated "VREF full-range operating behaviors" table.
• Updated "I2S/SAI Switching Specifications" section.
• Updated "TSI electrical specifications" table.

K50 Sub-Family Data Sheet, Rev. 2, 4/2012. Freescale Semiconductor, Inc. 77

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