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Document overview
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Technical content
Features
- Operating Characteristics – Voltage range: 1.71 to 3.6 V Flash write voltage range: 1.71 to 3.6 V – Temperature range (ambient): -40 to 105°C
- Clocks – 3 to 32 MHz crystal oscillator – 32 kHz crystal oscillator – Multi-purpose clock generator
- System peripherals – 10 low-power modes to provide power optimization based on application requirements – 16-channel DMA controller, supporting up to 63 request sources – External watchdog monitor – Software watchdog – Low-leakage wakeup unit
- Security and integrity modules – Hardware CRC module to support fast cyclic redundancy checks – 128-bit unique identification (ID) number per chip
- Human-machine interface – Segment LCD controller supporting up to 36 frontplanes and 8 backplanes, or 40 frontplanes and 4 backplanes, depending on the package size – Low-power hardware touch sensor interface (TSI) – General-purpose input/output
- Analog modules – Two 16-bit SAR ADCs Programmable gain amplifier (PGA) (up to x64) integrated into each ADC – 12-bit DAC – Three analog comparators (CMP) containing a 6-bit DAC and programmable reference input – Voltage reference
- Timers – Programmable delay block – Eight-channel motor control/general purpose/PWM timer – Two 2-channel quadrature decoder/general purpose timers – Periodic interrupt timers – 16-bit low-power timer – Carrier modulator transmitter – Real-time clock
- Communication interfaces – USB full-/low-speed On-the-Go controller with on- chip transceiver – Controller Area Network (CAN) module – Two SPI modules – Two I2C modules – Five UART modules – I2S module Freescale Semiconductor Document Number: K40P100M72SF1 Data Sheet: Technical Data Rev. 2, 4/2012 Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. © 2012 Freescale Semiconductor, Inc.
3.6 Relationship between ratings and operating
6.8.5 DSPI switching specifications (limited voltage
6.8.6 DSPI switching specifications (full voltage range).55 K40 Sub-Family Data Sheet, Rev. 2, 4/2012. 2 Freescale Semiconductor, Inc.
1 Ordering parts
1.1 Determining valid orderable parts
Valid orderable part numbers are provided on the web. To determine the orderable part numbers for this device, go to http://www.freescale.com and perform a part number search for the following device numbers: PK40 and MK40 .
2 Part identification
2.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the values of these fields to determine the specific part you have received.
2.2 Format
Part numbers for this device have the following format: Q K## A M FFF R T PP CC N
2.3 Fields
This table lists the possible values for each field in the part number (not all combinations are valid): Field Description Values Q Qualification status • M = Fully qualified, general market flow
- P = Prequalification K## Kinetis family • K40 A Key attribute • D = Cortex-M4 w/ DSP
- F = Cortex-M4 w/ DSP and FPU M Flash memory type • N = Program flash only
- X = Program flash and FlexMemory Table continues on the next page... Ordering parts K40 Sub-Family Data Sheet, Rev. 2, 4/2012. Freescale Semiconductor, Inc. 3
FFF Program flash memory size • 32 = 32 KB
- 64 = 64 KB
- 128 = 128 KB
- 256 = 256 KB
- 512 = 512 KB
- 1M0 = 1 MB R Silicon revision • Z = Initial
- (Blank) = Main
- A = Revision after main T Temperature range (°C) • V = –40 to 105
- C = –40 to 85
- FT = 48 QFN (7 mm x 7 mm)
- LF = 48 LQFP (7 mm x 7 mm)
- LH = 64 LQFP (10 mm x 10 mm)
- MP = 64 MAPBGA (5 mm x 5 mm)
- LK = 80 LQFP (12 mm x 12 mm)
- MB = 81 MAPBGA (8 mm x 8 mm)
- LL = 100 LQFP (14 mm x 14 mm)
- ML = 104 MAPBGA (8 mm x 8 mm)
- MC = 121 MAPBGA (8 mm x 8 mm)
- LQ = 144 LQFP (20 mm x 20 mm)
- MD = 144 MAPBGA (13 mm x 13 mm)
- MJ = 256 MAPBGA (17 mm x 17 mm) CC Maximum CPU frequency (MHz) • 5 = 50 MHz
- 7 = 72 MHz
- 10 = 100 MHz
- 12 = 120 MHz
- 15 = 150 MHz N Packaging type • R = Tape and reel
- (Blank) = Trays
2.4 Example
This is an example part number: MK40DN512ZVMD10
3 Terminology and guidelines
Terminology and guidelines K40 Sub-Family Data Sheet, Rev. 2, 4/2012. 4 Freescale Semiconductor, Inc.
3.1 Definition: Operating requirement
An operating requirement is a specified value or range of values for a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useful life of the chip.
3.1.1 Example
This is an example of an operating requirement, which you must meet for the accompanying operating behaviors to be guaranteed: Symbol Description Min. Max. Unit VDD 1.0 V core supply voltage 0.9 1.1 V
3.2 Definition: Operating behavior
An operating behavior is a specified value or range of values for a technical characteristic that are guaranteed during operation if you meet the operating requirements and any other specified conditions.
3.2.1 Example
This is an example of an operating behavior, which is guaranteed if you meet the accompanying operating requirements: Symbol Description Min. Max. Unit IWP Digital I/O weak pullup/ pulldown current 10 130 µA
3.3 Definition: Attribute
An attribute is a specified value or range of values for a technical characteristic that are guaranteed, regardless of whether you meet the operating requirements. Terminology and guidelines K40 Sub-Family Data Sheet, Rev. 2, 4/2012. Freescale Semiconductor, Inc. 5
3.3.1 Example
This is an example of an attribute: Symbol Description Min. Max. Unit CIN_D Input capacitance: digital pins — 7 pF
3.4 Definition: Rating
A rating is a minimum or maximum value of a technical characteristic that, if exceeded, may cause permanent chip failure:
- Operating ratings apply during operation of the chip.
- Handling ratings apply when the chip is not powered.
3.4.1 Example
This is an example of an operating rating: Symbol Description Min. Max. Unit VDD 1.0 V core supply voltage –0.3 1.2 V
3.5 Result of exceeding a rating
Failures in time (ppm) The likelihood of permanent chip failure increases rapidly as soon as a characteristic begins to exceed one of its operating ratings. Terminology and guidelines K40 Sub-Family Data Sheet, Rev. 2, 4/2012. 6 Freescale Semiconductor, Inc.
3.6 Relationship between ratings and operating requirements
- No permanent failure - Correct operation Normal operating rangeFatal range Expected permanent failure Fatal range Expected permanent failure Operating rating (max.)Operating requirement (max.)Operating requirement (min.)Operating rating (min.) Operating (power on) Degraded operating range Degraded operating range No permanent failure Handling rangeFatal range Expected permanent failure Fatal range Expected permanent failure Handling rating (max.)Handling rating (min.) Handling (power off) - No permanent failure - Possible decreased life - Possible incorrect operation - No permanent failure - Possible decreased life - Possible incorrect operation
3.7 Guidelines for ratings and operating requirements
Follow these guidelines for ratings and operating requirements:
- Never exceed any of the chip’s ratings.
- During normal operation, don’t exceed any of the chip’s operating requirements.
- If you must exceed an operating requirement at times other than during normal operation (for example, during power sequencing), limit the duration as much as possible.
3.8 Definition: Typical value
A typical value is a specified value for a technical characteristic that:
- Lies within the range of values specified by the operating behavior
- Given the typical manufacturing process, is representative of that characteristic during operation when you meet the typical-value conditions or other specified conditions Typical values are provided as design guidelines and are neither tested nor guaranteed. Terminology and guidelines K40 Sub-Family Data Sheet, Rev. 2, 4/2012. Freescale Semiconductor, Inc. 7
3.8.1 Example 1
This is an example of an operating behavior that includes a typical value: Symbol Description Min. Typ. Max. Unit IWP Digital I/O weak pullup/pulldown current 10 70 130 µA
3.8.2 Example 2
This is an example of a chart that shows typical values for various voltage and temperature conditions: 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 150 °C 105 °C 25 °C –40 °C VDD (V) I (μA)DD_STOP TJ
3.9 Typical value conditions
Typical values assume you meet the following conditions (or other conditions as specified): Symbol Description Value Unit TA Ambient temperature 25 °C VDD 3.3 V supply voltage 3.3 V Terminology and guidelines K40 Sub-Family Data Sheet, Rev. 2, 4/2012. 8 Freescale Semiconductor, Inc.
4 Ratings
4.1 Thermal handling ratings
Symbol Description Min. Max. Unit Notes TSTG Storage temperature –55 150 °C 1 TSDR Solder temperature, lead-free — 260 °C 2 1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life. 2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices.
4.2 Moisture handling ratings
Symbol Description Min. Max. Unit Notes MSL Moisture sensitivity level — 3 — 1 1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices.
4.3 ESD handling ratings
Symbol Description Min. Max. Unit Notes VHBM Electrostatic discharge voltage, human body model -2000 +2000 V 1 VCDM Electrostatic discharge voltage, charged-device model -500 +500 V 2 ILAT Latch-up current at ambient temperature of 105°C -100 +100 mA 1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM). 2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
4.4 Voltage and current operating ratings
Symbol Description Min. Max. Unit VDD Digital supply voltage –0.3 3.8 V Table continues on the next page... Ratings K40 Sub-Family Data Sheet, Rev. 2, 4/2012. Freescale Semiconductor, Inc. 9
- Analog pins are defined as pins that do not have an associated general purpose I/O port function.
5 General
5.1 AC electrical characteristics
Figure 1. Input signal measurement reference
- have C L=30pF loads,
- are configured for fast slew rate (PORTx_PCRn[SRE]=0), and
- are configured for high drive strength (PORTx_PCRn[DSE]=1) 2. input pins
- have their passive filter disabled (PORTx_PCRn[PFE]=0) General K40 Sub-Family Data Sheet, Rev. 2, 4/2012. 10 Freescale Semiconductor, Inc.
5.2 Nonswitching electrical specifications
5.2.1 Voltage and current operating requirements
Table 1. Voltage and current operating requirements
- 2.7 V ≤ V DD ≤ 3.6 V
- 1.7 V ≤ V DD ≤ 2.7 V 0.7 × VDD 0.75 × VDD V V VIL Input low voltage
- 2.7 V ≤ V DD ≤ 3.6 V
- 1.7 V ≤ V DD ≤ 2.7 V 0.35 × VDD 0.3 × VDD V V VHYS Input hysteresis 0.06 × VDD — V IICDIO Digital pin negative DC injection current — single pin
- V IN < VSS-0.3V -5 — mA IICAIO Analog2, EXTAL, and XTAL pin DC injection current — single pin
- V IN < VSS-0.3V (Negative current injection)
- V IN > VDD+0.3V (Positive current injection) mA IICcont Contiguous pin DC injection current —regional limit, includes sum of negative injection currents or sum of positive injection currents of 16 contiguous pins
- Negative current injection
- Positive current injection -25 +25 mA VRAM VDD voltage required to retain RAM 1.2 — V VRFVBAT VBAT voltage required to retain the VBAT register file VPOR_VBAT — V 1. All 5 V tolerant digital I/O pins are internally clamped to VSS through a ESD protection diode. There is no diode connection to VDD. If VIN greater than VDIO_MIN (=VSS-0.3V) is observed, then there is no need to provide current limiting resistors at the pads. If this limit cannot be observed then a current limiting resistor is required. The negative DC injection current limiting resistor is calculated as R=(VDIO_MIN-VIN)/|IIC|. 2. Analog pins are defined as pins that do not have an associated general purpose I/O port function. General K40 Sub-Family Data Sheet, Rev. 2, 4/2012. Freescale Semiconductor, Inc. 11
- All analog pins are internally clamped to VSS and VDD through ESD protection diodes. If VIN is greater than VAIO_MIN
calcualted as R=(VIN-VAIO_MAX)/|IIC|. Select the larger of these two calculated resistances.
5.2.2 LVD and POR operating requirements
Table 2. V DD supply LVD and POR operating requirements
- Level 1 falling (LVWV=00)
- Level 2 falling (LVWV=01)
- Level 3 falling (LVWV=10)
- Level 4 falling (LVWV=11) 2.62 2.72 2.82 2.92 2.70 2.80 2.90 3.00 2.78 2.88 2.98 3.08 V V V V VHYSH Low-voltage inhibit reset/recover hysteresis — high range — ±80 — mV VLVDL Falling low-voltage detect threshold — low range (LVDV=00) 1.54 1.60 1.66 V VLVW1L VLVW2L VLVW3L VLVW4L Low-voltage warning thresholds — low range
- Level 1 falling (LVWV=00)
- Level 2 falling (LVWV=01)
- Level 3 falling (LVWV=10)
- Level 4 falling (LVWV=11) 1.74 1.84 1.94 2.04 1.80 1.90 2.00 2.10 1.86 1.96 2.06 2.16 V V V V VHYSL Low-voltage inhibit reset/recover hysteresis — low range — ±60 — mV VBG Bandgap voltage reference 0.97 1.00 1.03 V tLPO Internal low power oscillator period — factory trimmed 900 1000 1100 μs 1. Rising thresholds are falling threshold + hysteresis voltage
Table 3. VBAT power operating requirements K40 Sub-Family Data Sheet, Rev. 2, 4/2012. 12 Freescale Semiconductor, Inc.
5.2.3 Voltage and current operating behaviors
Table 4. Voltage and current operating behaviors
- 2.7 V ≤ V DD ≤ 3.6 V, IOH = -9mA
- 1.71 V ≤ V DD ≤ 2.7 V, IOH = -3mA VDD – 0.5 VDD – 0.5 V V Output high voltage — low drive strength
- 2.7 V ≤ V DD ≤ 3.6 V, IOH = -2mA
- 1.71 V ≤ V DD ≤ 2.7 V, IOH = -0.6mA VDD – 0.5 VDD – 0.5 V V IOHT Output high current total for all ports — 100 mA VOL Output low voltage — high drive strength
- 2.7 V ≤ V DD ≤ 3.6 V, IOL = 9mA
- 1.71 V ≤ V DD ≤ 2.7 V, IOL = 3mA 0.5 0.5 V V Output low voltage — low drive strength
- 2.7 V ≤ V DD ≤ 3.6 V, IOL = 2mA
- 1.71 V ≤ V DD ≤ 2.7 V, IOL = 0.6mA 0.5 0.5 V V IOLT Output low current total for all ports — 100 mA IIN Input leakage current (per pin) for full temperature range — 1 μA 1 IIN Input leakage current (per pin) at 25°C — 0.025 μA 1 IOZ Hi-Z (off-state) leakage current (per pin) — 1 μA RPU Internal pullup resistors 20 50 kΩ 2 RPD Internal pulldown resistors 20 50 kΩ 3 1. Measured at VDD=3.6V 2. Measured at VDD supply voltage = VDD min and Vinput = VSS 3. Measured at VDD supply voltage = VDD min and Vinput = VDD
5.2.4 Power mode transition operating behaviors
- CPU and system clocks = 72 MHz
- Bus clock = 36 MHz
- Flash clock = 24 MHz General K40 Sub-Family Data Sheet, Rev. 2, 4/2012. Freescale Semiconductor, Inc. 13
Table 5. Power mode transition operating behaviors across the operating temperature range of the chip.
- VLLS1 → RUN — 112 μs
- VLLS2 → RUN — 74 μs
- VLLS3 → RUN — 73 μs
- LLS → RUN — 5.9 μs
- VLPS → RUN — 5.8 μs
- STOP → RUN — 4.2 μs 1. Normal boot (FTFL_OPT[LPBOOT]=1)
5.2.5 Power consumption operating behaviors
Table 6. Power consumption operating behaviors
- @ 1.8V
- @ 3.0V 21.5 21.5 mA mA IDD_RUN Run mode current — all peripheral clocks enabled, code executing from flash
- @ 1.8V
- @ 3.0V
- @ 25°C
- @ 125°C mA mA mA 3, 4 IDD_WAIT Wait mode high frequency current at 3.0 V — all peripheral clocks disabled — 12.5 — mA 2 IDD_WAIT Wait mode reduced frequency current at 3.0 V — all peripheral clocks disabled — 7.2 — mA 5 IDD_VLPR Very-low-power run mode current at 3.0 V — all peripheral clocks disabled — 0.996 — mA 6 Table continues on the next page... General K40 Sub-Family Data Sheet, Rev. 2, 4/2012. 14 Freescale Semiconductor, Inc.
Table 6. Power consumption operating behaviors (continued)
- @ –40 to 25°C
- @ 70°C
- @ 105°C 0.35 0.384 0.628 0.567 0.793 1.2 mA mA mA IDD_VLPS Very-low-power stop mode current at 3.0 V
- @ –40 to 25°C
- @ 70°C
- @ 105°C 5.9 26.1 98.1 32.7 59.8 188 μA μA μA IDD_LLS Low leakage stop mode current at 3.0 V
- @ –40 to 25°C
- @ 70°C
- @ 105°C 2.6 10.3 42.5 8.6 29.1 92.5 μA μA μA IDD_VLLS3 Very low-leakage stop mode 3 current at 3.0 V
- @ –40 to 25°C
- @ 70°C
- @ 105°C 1.9 6.9 28.1 5.8 12.1 41.9 μA μA μA IDD_VLLS2 Very low-leakage stop mode 2 current at 3.0 V
- @ –40 to 25°C
- @ 70°C
- @ 105°C 1.59 4.3 17.5 5.5 9.5 μA μA μA IDD_VLLS1 Very low-leakage stop mode 1 current at 3.0 V
- @ –40 to 25°C
- @ 70°C
- @ 105°C 1.47 2.97 12.41 5.4 8.1 μA μA μA IDD_VBAT Average current with RTC and 32kHz disabled at 3.0 V
- @ –40 to 25°C
- @ 70°C
- @ 105°C 0.19 0.49 2.2 0.22 0.64 3.2 μA μA μA Table continues on the next page... General K40 Sub-Family Data Sheet, Rev. 2, 4/2012. Freescale Semiconductor, Inc. 15
- @ 1.8V
- @ –40 to 25°C
- @ 70°C
- @ 105°C
- @ 3.0V
- @ –40 to 25°C
- @ 70°C
- @ 105°C 0.57 0.90 2.4 0.67 1.0 2.7 0.67 1.2 3.5 0.94 1.4 3.9 μA μA μA μA μA μA 1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See each module's specification for its supply current. 2. 72MHz core and system clock, 36MHz bus clock, and 24MHz flash clock. MCG configured for FEE mode. All peripheral clocks disabled. 3. 72MHz core and system clock, 36MHz bus clock, and 24MHz flash clock. MCG configured for FEE mode. All peripheral clocks enabled. 4. Max values are measured with CPU executing DSP instructions. 5. 25MHz core, system, bus and flash clock. MCG configured for FEI mode. 6. 4 MHz core and system clock, 4 MHz and bus clock, and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral clocks disabled. Code executing from flash. 7. 4 MHz core and system clock, 4 MHz and bus clock, and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral clocks enabled but peripherals are not in active operation. Code executing from flash. 8. 4 MHz core and system clock, 4 MHz and bus clock, and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral clocks disabled. 9. Data reflects devices with 128 KB of RAM. 10. Includes 32kHz oscillator current and RTC operation.
5.2.5.1 Diagram: Typical IDD_RUN operating behavior
- MCG in FBE mode for 50 MHz and lower frequencies. MCG in FEE mode at greater than 50 MHz frequencies.
- USB regulator disabled
- No GPIOs toggled
- Code execution from flash with cache enabled
- For the ALLOFF curve, all peripheral clocks are disabled except FTFL General K40 Sub-Family Data Sheet, Rev. 2, 4/2012. 16 Freescale Semiconductor, Inc.
Figure 2. Run mode supply current vs. core frequency K40 Sub-Family Data Sheet, Rev. 2, 4/2012.
Figure 3. VLPR mode supply current vs. core frequency
5.2.6 Designing with radiated emissions in mind
- Go to http://www.freescale.com.
- Perform a keyword search for “EMC design.”
5.2.7 Capacitance attributes
Table 7. Capacitance attributes Table continues on the next page... K40 Sub-Family Data Sheet, Rev. 2, 4/2012. 18 Freescale Semiconductor, Inc.
Table 7. Capacitance attributes (continued)
5.3 Switching specifications
5.3.1 Device clock specifications
Table 8. Device clock specifications
- The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for any
5.3.2 General switching specifications
K40 Sub-Family Data Sheet, Rev. 2, 4/2012.
Table 9. General switching specifications
- Slew disabled
- 1.71 ≤ V DD ≤ 2.7V
- Slew enabled
- 1.71 ≤ V DD ≤ 2.7V ns ns ns ns Port rise and fall time (low drive strength)
- Slew disabled
- 1.71 ≤ V DD ≤ 2.7V
- Slew enabled
- 1.71 ≤ V DD ≤ 2.7V ns ns ns ns 1. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or may not be recognized. In Stop, VLPS, LLS, and VLLSx modes, the synchronizer is bypassed so shorter pulses can be recognized in that case. 2. The greater synchronous and asynchronous timing must be met. 3. This is the minimum pulse width that is guaranteed to be recognized as a pin interrupt request in Stop, VLPS, LLS, and VLLSx modes. 4. 75pF load 5. 15pF load
5.4 Thermal specifications
K40 Sub-Family Data Sheet, Rev. 2, 4/2012. 20 Freescale Semiconductor, Inc.
5.4.1 Thermal operating requirements
Table 10. Thermal operating requirements
5.4.2 Thermal attributes
100 LQFP Unit Notes
- Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site
K40 Sub-Family Data Sheet, Rev. 2, 4/2012.
- Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
JESD51-3 specification. For the MAPBGA, the board meets the JESD51-9 specification.
- Determined according to JEDEC Standard JESD51-6, Integrated Circuits Thermal Test Method Environmental
- Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental
Conditions—Junction-to-Board. Board temperature is measured on the top surface of the board near the package.
- Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate
between the top of the package and the cold plate.
- Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air).
6 Peripheral operating requirements and behaviors
6.1 Core modules
6.1.1 Debug trace timing specifications
Table 11. Debug trace operating behaviors Figure 4. TRACE_CLKOUT specifications K40 Sub-Family Data Sheet, Rev. 2, 4/2012. 22 Freescale Semiconductor, Inc.
Figure 5. Trace data specifications
6.1.2 JTAG electricals
Table 12. JTAG voltage range electricals
- JTAG
- CJTAG MHz J2 TCLK cycle period 1/J1 — ns J3 TCLK clock pulse width
- JTAG
- CJTAG 100 200 ns ns ns J4 TCLK rise and fall times — 1 ns J5 TMS input data setup time to TCLK rise
- JTAG
- CJTAG 112 ns J6 TDI input data setup time to TCLK rise 8 — ns J7 TMS input data hold time after TCLK rise
- JTAG
- CJTAG 3.4 3.4 ns J8 TDI input data hold time after TCLK rise 3.4 — ns J9 TCLK low to TMS data valid
- JTAG
- CJTAG ns J10 TCLK low to TDO data valid — 48 ns J11 Output data hold/invalid time after clock edge1 — 3 ns 1. They are common for JTAG and CJTAG. Input transition = 1 ns and Output load = 50pf Peripheral operating requirements and behaviors K40 Sub-Family Data Sheet, Rev. 2, 4/2012. Freescale Semiconductor, Inc. 23
Figure 8. Test Access Port timing Figure 9. TRST timing
6.2 System modules
There are no specifications necessary for the device's system modules.
6.3 Clock modules
K40 Sub-Family Data Sheet, Rev. 2, 4/2012.
6.3.1 MCG specifications
Table 13. MCG specifications Table continues on the next page... K40 Sub-Family Data Sheet, Rev. 2, 4/2012. 26 Freescale Semiconductor, Inc.
Table 13. MCG specifications (continued)
- f VCO = 48 MHz
- f VCO = 98 MHz 180 150 ps tfll_acquire FLL target frequency acquisition time — — 1 ms 6 PLL fvco VCO operating frequency 48.0 — 100 MHz Ipll PLL operating current
- PLL @ 96 MHz (f osc_hi_1 = 8 MHz, fpll_ref =
2 MHz, VDIV multiplier = 48)
- PLL @ 48 MHz (f osc_hi_1 = 8 MHz, fpll_ref =
2 MHz, VDIV multiplier = 24)
- f vco = 48 MHz
- f vco = 100 MHz 120 ps ps Jacc_pll PLL accumulated jitter over 1µs (RMS)
- f vco = 48 MHz
- f vco = 100 MHz 1350 600 ps ps Dlock Lock entry frequency tolerance ± 1.49 — ± 2.98 % Dunl Lock exit frequency tolerance ± 4.47 — ± 5.97 % tpll_lock Lock detector detection time — — 150 × 10-6 + 1075(1/ fpll_ref) s 9 1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock mode). 2. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0. 3. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency deviation (Δfdco_t) over voltage and temperature should be considered. 4. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1. 5. The resulting clock frequency must not exceed the maximum specified clock frequency of the device. Peripheral operating requirements and behaviors K40 Sub-Family Data Sheet, Rev. 2, 4/2012. Freescale Semiconductor, Inc. 27
- This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed,
FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.
- Excludes any oscillator currents that are also consuming power while PLL is in operation.
- This specification was obtained using a Freescale developed PCB. PLL jitter is dependent on the noise characteristics of
each PCB and results will vary.
- This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled
6.3.2 Oscillator electrical specifications
This section provides the electrical characteristics of the module.
6.3.2.1 Oscillator DC electrical specifications
Table 14. Oscillator DC electrical specifications
- 32 kHz
- 4 MHz
- 8 MHz (RANGE=01)
- 16 MHz
- 24 MHz
- 32 MHz 500 200 300 950 1.2 1.5 nA μA μA μA mA mA IDDOSC Supply current — high gain mode (HGO=1)
- 32 kHz
- 4 MHz
- 8 MHz (RANGE=01)
- 16 MHz
- 24 MHz
- 32 MHz 400 500 2.5 μA μA μA mA mA mA Cx EXTAL load capacitance — — — 2, 3 Cy XTAL load capacitance — — — 2, 3 Table continues on the next page... Peripheral operating requirements and behaviors K40 Sub-Family Data Sheet, Rev. 2, 4/2012. 28 Freescale Semiconductor, Inc.
Table 14. Oscillator DC electrical specifications (continued)
- VDD=3.3 V, Temperature =25 °C
- See crystal or resonator manufacturer's recommendation
- Cx,Cy can be provided by using either the integrated capacitors or by using external components.
- When low power mode is selected, RF is integrated and must not be attached externally.
- The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any
6.3.2.2 Oscillator frequency specifications
Table 15. Oscillator frequency specifications Table continues on the next page... K40 Sub-Family Data Sheet, Rev. 2, 4/2012.
Table 15. Oscillator frequency specifications (continued)
- Other frequency limits may apply when external clock is being used as a reference for the FLL or PLL.
- When transitioning from FBE to FEI mode, restrict the frequency of the input clock so that, when it is divided by FRDIV, it
remains within the limits of the DCO input clock frequency.
- Proper PC board layout procedures must be followed to achieve specifications.
- Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S register
This section describes the module electrical characteristics. Table 16. 32kHz oscillator DC electrical specifications
- The EXTAL32 and XTAL32 pins should only be connected to required oscillator components and must not be connected to
K40 Sub-Family Data Sheet, Rev. 2, 4/2012. 30 Freescale Semiconductor, Inc.
Table 17. 32kHz oscillator frequency specifications
- Proper PC board layout procedures must be followed to achieve specifications.
6.4 Memories and memory interfaces
6.4.1 Flash electrical specifications
This section describes the electrical characteristics of the flash memory module.
6.4.1.1 Flash timing specifications — program and erase
active and do not include command overhead. Table 18. NVM program/erase timing specifications
- Maximum time based on expectations at cycling end-of-life.
6.4.1.2 Flash timing specifications — commands
Table 19. Flash command timing specifications
- 32 KB data flash
- 256 KB program flash 0.5 1.7 ms ms trd1sec1k Read 1s Section execution time (data flash sector) — — 60 μs 1 trd1sec2k Read 1s Section execution time (program flash sector) — — 60 μs 1 Table continues on the next page... Peripheral operating requirements and behaviors K40 Sub-Family Data Sheet, Rev. 2, 4/2012. Freescale Semiconductor, Inc. 31
Table 19. Flash command timing specifications (continued)
- 32 KB data flash
- 256 KB program flash 122 465 985 ms ms tersscr Erase Flash Sector execution time — 14 114 ms 2 tpgmsec512p tpgmsec512d tpgmsec1kp tpgmsec1kd Program Section execution time
- 512 B program flash
- 512 B data flash
- 1 KB program flash
- 1 KB data flash 2.4 4.7 4.7 9.3 ms ms ms ms trd1all Read 1s All Blocks execution time — — 1.8 ms trdonce Read Once execution time — — 25 μs 1 tpgmonce Program Once execution time — 65 — μs tersall Erase All Blocks execution time — 175 1500 ms 2 tvfykey Verify Backdoor Access Key execution time — — 30 μs 1 tswapx01 tswapx02 tswapx04 tswapx08 Swap Control execution time
- control code 0x01
- control code 0x02
- control code 0x04
- control code 0x08 200 150 150 μs μs μs μs tpgmpart32k Program Partition for EEPROM execution time
- 32 KB FlexNVM ms tsetramff tsetram8k tsetram32k Set FlexRAM Function execution time:
- Control Code 0xFF
- 8 KB EEPROM backup
- 32 KB EEPROM backup 0.3 0.7 0.5 1.0 μs ms ms Byte-write to FlexRAM for EEPROM operation teewr8bers Byte-write to erased FlexRAM location execution time — 175 260 μs 3 Table continues on the next page... Peripheral operating requirements and behaviors K40 Sub-Family Data Sheet, Rev. 2, 4/2012. 32 Freescale Semiconductor, Inc.
- 8 KB EEPROM backup
- 16 KB EEPROM backup
- 32 KB EEPROM backup 340 385 475 1700 1800 2000 μs μs μs Word-write to FlexRAM for EEPROM operation teewr16bers Word-write to erased FlexRAM location execution time — 175 260 μs teewr16b8k teewr16b16k teewr16b32k Word-write to FlexRAM execution time:
- 8 KB EEPROM backup
- 16 KB EEPROM backup
- 32 KB EEPROM backup 340 385 475 1700 1800 2000 μs μs μs Longword-write to FlexRAM for EEPROM operation teewr32bers Longword-write to erased FlexRAM location execution time — 360 540 μs teewr32b8k teewr32b16k teewr32b32k Longword-write to FlexRAM execution time:
- 8 KB EEPROM backup
- 16 KB EEPROM backup
- 32 KB EEPROM backup 545 630 810 1950 2050 2250 μs μs μs 1. Assumes 25MHz flash clock frequency. 2. Maximum times for erase parameters based on expectations at cycling end-of-life. 3. For byte-writes to an erased FlexRAM location, the aligned word containing the byte must be erased.
6.4.1.3 Flash current and power specfications
Table 20. Flash current and power specfications
6.4.1.4 Reliability specifications
Table 21. NVM reliability specifications Table continues on the next page... K40 Sub-Family Data Sheet, Rev. 2, 4/2012.
Table 21. NVM reliability specifications (continued)
- EEPROM backup to FlexRAM ratio = 16
- EEPROM backup to FlexRAM ratio = 128
- EEPROM backup to FlexRAM ratio = 512
- EEPROM backup to FlexRAM ratio = 4096
- EEPROM backup to FlexRAM ratio = 8192 35 K 315 K 1.27 M 10 M 20 M 175 K 1.6 M 6.4 M 50 M 100 M writes writes writes writes writes 1. Typical data retention values are based on measured response accelerated at high temperature and derated to a constant 25°C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in Engineering Bulletin EB619. 2. Cycling endurance represents number of program/erase cycles at -40°C ≤ Tj ≤ 125°C. 3. Write endurance represents the number of writes to each FlexRAM location at -40°C ≤Tj ≤ 125°C influenced by the cycling endurance of the FlexNVM (same value as data flash) and the allocated EEPROM backup per subsystem. Minimum and typical values assume all byte-writes to FlexRAM.
6.4.1.5 Write endurance to FlexRAM for EEPROM
can be set to any of several non-zero values. shown below assume that only one configuration is ever used. K40 Sub-Family Data Sheet, Rev. 2, 4/2012. 34 Freescale Semiconductor, Inc.
- Writes_subsystem — minimum number of writes to each FlexRAM location for subsystem (each subsystem can have different endurance)
- EEPROM — allocated FlexNVM for each EEPROM subsystem based on DEPART; entered with Program Partition command
- EEESPLIT — FlexRAM split factor for subsystem; entered with the Program Partition command
- EEESIZE — allocated FlexRAM based on DEPART; entered with Program Partition command
- Write_efficiency —
- 0.25 for 8-bit writes to FlexRAM
- 0.50 for 16-bit or 32-bit writes to FlexRAM
- n nvmcycd — data flash cycling endurance
Figure 10. EEPROM backup writes to FlexRAM K40 Sub-Family Data Sheet, Rev. 2, 4/2012.
6.4.2 EzPort Switching Specifications
Table 22. EzPort switching specifications Figure 11. EzPort Timing Diagram
6.5 Security and integrity modules
There are no specifications necessary for the device's security and integrity modules. K40 Sub-Family Data Sheet, Rev. 2, 4/2012. 36 Freescale Semiconductor, Inc.
6.6 Analog
6.6.1 ADC electrical specifications
differential pins ADCx_DP0, ADCx_DM0. Table 23. 16-bit ADC operating conditions
1.13 VDDA VDDA V
- 16 bit modes
- 8/10/12 bit modes pF RADIN Input resistance — 2 5 kΩ RAS Analog source resistance 13/12 bit modes fADCK < 4MHz kΩ fADCK ADC conversion clock frequency ≤ 13 bit modes 1.0 18.0 MHz fADCK ADC conversion clock frequency 16 bit modes 2.0 12.0 MHz Table continues on the next page... Peripheral operating requirements and behaviors K40 Sub-Family Data Sheet, Rev. 2, 4/2012. Freescale Semiconductor, Inc. 37
Table 23. 16-bit ADC operating conditions (continued)
- Typical values assume VDDA = 3.0 V, Temp = 25°C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
- This resistance is external to MCU. The analog source resistance should be kept as low as possible in order to achieve the
CAS time constant should be kept to <1ns.
- To use the maximum ADC conversion clock frequency, the ADHSC bit should be set and the ADLPC bit should be clear.
- For guidelines and examples of conversion rate calculation, download the ADC calculator tool: http://cache.freescale.com/
Figure 12. ADC input impedance equivalency diagram K40 Sub-Family Data Sheet, Rev. 2, 4/2012. 38 Freescale Semiconductor, Inc.
Table 24. 16-bit ADC characteristics (V REFH = VDDA, VREFL = VSSA)
- ADLPC=1, ADHSC=0
- ADLPC=1, ADHSC=1
- ADLPC=0, ADHSC=0
- ADLPC=0, ADHSC=1 1.2 3.0 2.4 4.4 2.4 4.0 5.2 6.2 3.9 7.3 6.1 9.5 MHz MHz MHz MHz tADACK = 1/ fADACK Sample Time See Reference Manual chapter for sample times TUE Total unadjusted error
- 12 bit modes
- <12 bit modes ±1.4 ±6.8 ±2.1 LSB4 5 DNL Differential non- linearity
- 12 bit modes
- <12 bit modes ±0.7 ±0.2 -1.1 to +1.9 -0.3 to 0.5 LSB4 5 INL Integral non- linearity
- 12 bit modes
- <12 bit modes ±1.0 ±0.5 -2.7 to +1.9 -0.7 to +0.5 LSB4 5 EFS Full-scale error • 12 bit modes
- <12 bit modes -1.4 -5.4 -1.8 LSB4 VADIN = VDDA EQ Quantization error
- 16 bit modes
- ≤13 bit modes -1 to 0 ±0.5 LSB4 ENOB Effective number of bits 16 bit differential mode
- Avg=32
- Avg=4 16 bit single-ended mode
- Avg=32
- Avg=4 12.8 11.9 12.2 11.4 14.5 13.8 13.9 13.1 bits bits bits bits SINAD Signal-to-noise plus distortion See ENOB 6.02 × ENOB + 1.76 dB THD Total harmonic distortion 16 bit differential mode
- Avg=32 16 bit single-ended mode
- Avg=32 –94 -85 dB dB Table continues on the next page... Peripheral operating requirements and behaviors K40 Sub-Family Data Sheet, Rev. 2, 4/2012. Freescale Semiconductor, Inc. 39
Table 24. 16-bit ADC characteristics (V REFH = VDDA, VREFL = VSSA) (continued)
- Avg=32 16 bit single-ended mode
- Avg=32 dB dB EIL Input leakage error IIn × RAS mV IIn = leakage current (refer to the MCU's voltage and current operating ratings) Temp sensor slope VTEMP25 Temp sensor voltage 25°C — 719 — mV 1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA 2. Typical values assume VDDA = 3.0 V, Temp = 25°C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and the ADLPC bit (low power). For lowest power operation the ADLPC bit should be set, the HSC bit should be clear with 1MHz ADC conversion clock speed. 4. 1 LSB = (VREFH - VREFL)/2N 5. ADC conversion clock <16MHz, Max hardware averaging (AVGE = %1, AVGS = %11) 6. Input data is 100 Hz sine wave. ADC conversion clock <12MHz. 7. Input data is 1 kHz sine wave. ADC conversion clock <12MHz. Peripheral operating requirements and behaviors K40 Sub-Family Data Sheet, Rev. 2, 4/2012. 40 Freescale Semiconductor, Inc.
Table 25. 16-bit ADC with PGA operating conditions
- Typical values assume VDDA = 3.0 V, Temp = 25°C, fADCK = 6 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
- ADC must be configured to use the internal voltage reference (VREF_OUT)
- PGA reference is internally connected to the VREF_OUT pin. If the user wishes to drive VREF_OUT with a voltage other
than the output of the VREF module, the VREF module must be disabled.
- For single ended configurations the input impedance of the driven input is RPGAD/2
- The analog source resistance (RAS), external to MCU, should be kept as minimum as possible. Increased RAS causes drop
in PGA gain without affecting other performances. This is not dependent on ADC clock frequency.
- The minimum sampling time is dependent on input signal frequency and ADC mode of operation. A minimum of 1.25µs
- ADC clock = 18 MHz, ADLSMP = 1, ADLST = 00, ADHSC = 1
- ADC clock = 12 MHz, ADLSMP = 1, ADLST = 01, ADHSC = 1
K40 Sub-Family Data Sheet, Rev. 2, 4/2012. 42 Freescale Semiconductor, Inc.
Table 26. 16-bit ADC with PGA characteristics
- PGAG=1
- PGAG=2
- PGAG=3
- PGAG=4
- PGAG=5
- PGAG=6 0.95 1.9 3.8 7.6 15.2 30.0 58.8 31.6 63.3 1.05 2.1 4.2 8.4 16.6 33.2 67.8 RAS < 100Ω BW Input signal bandwidth
- 16-bit modes
- < 16-bit modes kHz kHz PSRR Power supply rejection ratio Gain=1 — -84 — dB VDDA= 3V ±100mV, fVDDA= 50Hz, 60Hz CMRR Common mode rejection ratio
- Gain=1
- Gain=64 -84 -85 dB dB VCM= 500mVpp, fVCM= 50Hz, 100Hz VOFS Input offset voltage — 0.2 — mV Output offset = VOFS*(Gain+1) TGSW Gain switching settling time — — 10 µs 5 dG/dT Gain drift over full temperature range
- Gain=1
- Gain=64 ppm/°C ppm/°C dG/dVDDA Gain drift over supply voltage
- Gain=1
- Gain=64 0.07 0.14 0.21 0.31 %/V %/V VDDA from 1.71 to 3.6V Table continues on the next page... Peripheral operating requirements and behaviors K40 Sub-Family Data Sheet, Rev. 2, 4/2012. Freescale Semiconductor, Inc. 43
Table 26. 16-bit ADC with PGA characteristics (continued)
- Gain=1
- Gain=64 dB dB 16-bit differential mode, Average=32 THD Total harmonic distortion
- Gain=1
- Gain=64 100 dB dB 16-bit differential mode, Average=32, fin=100Hz SFDR Spurious free dynamic range
- Gain=1
- Gain=64 105 dB dB 16-bit differential mode, Average=32, fin=100Hz ENOB Effective number of bits
- Gain=1, Average=4
- Gain=64, Average=4
- Gain=1, Average=32
- Gain=2, Average=32
- Gain=4, Average=32
- Gain=8, Average=32
- Gain=16, Average=32
- Gain=32, Average=32
- Gain=64, Average=32 11.6 7.2 12.8 11.0 7.9 7.3 6.8 6.8 7.5 13.4 9.6 14.5 14.3 13.8 13.1 12.5 11.5 10.6 bits bits bits bits bits bits bits bits bits 16-bit differential mode,fin=100H z SINAD Signal-to-noise plus distortion ratio See ENOB 6.02 × ENOB + 1.76 dB 1. Typical values assume VDDA =3.0V, Temp=25°C, fADCK=6MHz unless otherwise stated. 2. This current is a PGA module adder, in addition to ADC conversion currents. 3. Between IN+ and IN-. The PGA draws a DC current from the input terminals. The magnitude of the DC current is a strong function of input common mode voltage (VCM) and the PGA gain. 4. Gain = 2PGAG 5. After changing the PGA gain setting, a minimum of 2 ADC+PGA conversions should be ignored. 6. Limit the input signal swing so that the PGA does not saturate during operation. Input signal swing is dependent on the PGA reference voltage and gain setting. Peripheral operating requirements and behaviors K40 Sub-Family Data Sheet, Rev. 2, 4/2012. 44 Freescale Semiconductor, Inc.
6.6.2 CMP and 6-bit DAC electrical specifications
Table 27. Comparator and 6-bit DAC electrical specifications
- CR0[HYSTCTR] = 00
- CR0[HYSTCTR] = 01
- CR0[HYSTCTR] = 10
- CR0[HYSTCTR] = 11 mV mV mV mV VCMPOh Output high VDD – 0.5 — — V VCMPOl Output low — — 0.5 V tDHS Propagation delay, high-speed mode (EN=1, PMODE=1) 20 50 200 ns tDLS Propagation delay, low-speed mode (EN=1, PMODE=0) 80 250 600 ns Analog comparator initialization delay2 — — 40 μs IDAC6b 6-bit DAC current adder (enabled) — 7 — μA INL 6-bit DAC integral non-linearity –0.5 — 0.5 LSB3 DNL 6-bit DAC differential non-linearity –0.3 — 0.3 LSB 1. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD-0.6V. 2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to DACEN, VRSEL, PSEL, MSEL, VOSEL) and the comparator output settling to a stable level. 3. 1 LSB = Vreference/64 Peripheral operating requirements and behaviors K40 Sub-Family Data Sheet, Rev. 2, 4/2012. Freescale Semiconductor, Inc. 45
Figure 15. Typical hysteresis vs. Vin level (VDD=3.3V, PMODE=0) K40 Sub-Family Data Sheet, Rev. 2, 4/2012. 46 Freescale Semiconductor, Inc.
Figure 16. Typical hysteresis vs. Vin level (VDD=3.3V, PMODE=1) Table 28. 12-bit DAC operating requirements
- The DAC reference can be selected to be VDDA or the voltage output of the VREF module (VREF_OUT)
- A small load capacitance (47 pF) can improve the bandwidth performance of the DAC
K40 Sub-Family Data Sheet, Rev. 2, 4/2012.
Table 29. 12-bit DAC operating behaviors
- High power (SP HP)
- Low power (SP LP) 1.2 0.05 1.7 0.12 V/μs CT Channel to channel cross talk — — -80 dB BW 3dB bandwidth
- High power (SP HP)
- Low power (SP LP) 550 kHz 1. Settling within ±1 LSB 2. The INL is measured for 0+100mV to VDACR−100 mV 3. The DNL is measured for 0+100 mV to VDACR−100 mV 4. The DNL is measured for 0+100mV to VDACR−100 mV with VDDA > 2.4V 5. Calculated by a best fit curve from VSS+100 mV to VDACR−100 mV Peripheral operating requirements and behaviors K40 Sub-Family Data Sheet, Rev. 2, 4/2012. 48 Freescale Semiconductor, Inc.
- VDDA = 3.0V, reference select set for VDDA (DACx_CO:DACRFS = 1), high power mode(DACx_C0:LPEN = 0), DAC set
Figure 17. Typical INL error vs. digital code K40 Sub-Family Data Sheet, Rev. 2, 4/2012.
Figure 18. Offset at half scale vs. temperature
6.6.4 Voltage reference electrical specifications
Table 30. VREF full-range operating requirements
- CL must be connected to VREF_OUT if the VREF_OUT functionality is being used for either an internal or external
- The load capacitance should not exceed +/-25% of the nominal specified CL value over the operating temperature range of
K40 Sub-Family Data Sheet, Rev. 2, 4/2012. 50 Freescale Semiconductor, Inc.
Table 31. VREF full-range operating behaviors
- current = ± 1.0 mA 200 µV 1, 2 Tstup Buffer startup time — — 20 µs Vvdrift Voltage drift (Vmax - Vmin across the full voltage range) — 2 — mV 1 1. See the chip's Reference Manual for the appropriate settings of the VREF Status and Control register. 2. Load regulation voltage is the difference between the VREF_OUT voltage with no load vs. voltage with defined load
Table 32. VREF limited-range operating requirements Table 33. VREF limited-range operating behaviors K40 Sub-Family Data Sheet, Rev. 2, 4/2012.
6.7 Timers
See General switching specifications.
6.8 Communication interfaces
6.8.1 USB electrical specifications
standards, visit http://www.usb.org.
6.8.2 USB DCD electrical specifications
Table 35. USB DCD electrical specifications
6.8.3 USB VREG electrical specifications
Table 36. USB VREG electrical specifications
- VREGIN = 5.0 V and temperature=25C
- Across operating voltage and temperature 650 nA μA ILOADrun Maximum load current — Run mode — — 120 mA Table continues on the next page... Peripheral operating requirements and behaviors K40 Sub-Family Data Sheet, Rev. 2, 4/2012. 52 Freescale Semiconductor, Inc.
- Run mode
- Standby mode 2.1 3.3 2.8 3.6 3.6 V V VReg33out Regulator output voltage — Input supply (VREGIN) < 3.6 V, pass-through mode 2.1 — 3.6 V 2 COUT External output capacitor 1.76 2.2 8.16 μF ESR External output capacitor equivalent series resistance 1 — 100 mΩ ILIM Short circuit current — 290 — mA 1. Typical values assume VREGIN = 5.0 V, Temp = 25 °C unless otherwise stated. 2. Operating in pass-through mode: regulator output voltage equal to the input voltage minus a drop proportional to ILoad.
6.8.4 CAN switching specifications
See General switching specifications.
6.8.5 DSPI switching specifications (limited voltage range)
used for communicating with slower peripheral devices. Table 37. Master mode DSPI timing (limited voltage range) Table continues on the next page... K40 Sub-Family Data Sheet, Rev. 2, 4/2012.
Table 37. Master mode DSPI timing (limited voltage range) (continued)
- The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
- The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
Figure 19. DSPI classic SPI timing — master mode Table 38. Slave mode DSPI timing (limited voltage range) K40 Sub-Family Data Sheet, Rev. 2, 4/2012. 54 Freescale Semiconductor, Inc.
Figure 20. DSPI classic SPI timing — slave mode
6.8.6 DSPI switching specifications (full voltage range)
used for communicating with slower peripheral devices. Table 39. Master mode DSPI timing (full voltage range)
- The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage
range the maximum frequency of operation is reduced.
- The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
- The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
K40 Sub-Family Data Sheet, Rev. 2, 4/2012.
6.8.7 I2C switching specifications
See General switching specifications.
6.8.8 UART switching specifications
See General switching specifications.
6.8.9 I2S/SAI Switching Specifications
frame sync (FS) signal shown in the following figures.
6.8.9.1 Normal Run, Wait and Stop mode performance over the full
device in Normal Run, Wait and Stop modes. Table 41. I2S/SAI master mode timing in Normal Run, Wait and Stop modes K40 Sub-Family Data Sheet, Rev. 2, 4/2012.
Figure 23. I2S/SAI timing — master modes Table 42. I2S/SAI slave mode timing in Normal Run, Wait and Stop modes
- Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
K40 Sub-Family Data Sheet, Rev. 2, 4/2012. 58 Freescale Semiconductor, Inc.
Figure 24. I2S/SAI timing — slave modes
6.8.9.2 VLPR, VLPW, and VLPS mode performance over the full operating
device in VLPR, VLPW, and VLPS modes. Table 43. I2S/SAI master mode timing in VLPR, VLPW, and VLPS modes K40 Sub-Family Data Sheet, Rev. 2, 4/2012.
Figure 25. I2S/SAI timing — master modes Table 44. I2S/SAI slave mode timing in VLPR, VLPW, and VLPS modes (full
- Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
K40 Sub-Family Data Sheet, Rev. 2, 4/2012. 60 Freescale Semiconductor, Inc.
Figure 26. I2S/SAI timing — slave modes
6.9 Human-machine interfaces (HMI)
6.9.1 TSI electrical specifications
Table 45. TSI electrical specifications
- 2 μA setting (REFCHRG = 0)
- 32 μA setting (REFCHRG = 15) μA 2, 6 IELE Electrode oscillator current source base current
- 2 μA setting (EXTCHRG = 0)
- 32 μA setting (EXTCHRG = 15) μA 2, 7 Pres5 Electrode capacitance measurement precision — 8.3333 38400 fF/count 8 Pres20 Electrode capacitance measurement precision — 8.3333 38400 fF/count 9 Pres100 Electrode capacitance measurement precision — 8.3333 38400 fF/count 10 MaxSens Maximum sensitivity 0.003 12.5 — fF/count 11 Res Resolution — — 16 bits Table continues on the next page... Peripheral operating requirements and behaviors K40 Sub-Family Data Sheet, Rev. 2, 4/2012. Freescale Semiconductor, Inc. 61
Table 45. TSI electrical specifications (continued)
- The TSI module is functional with capacitance values outside this range. However, optimal performance is not guaranteed.
- Fixed external capacitance of 20 pF.
- REFCHRG = 0, EXTCHRG = 10.
- The programmable current source value is generated by multiplying the SCANC[REFCHRG] value and the base current.
- The programmable current source value is generated by multiplying the SCANC[EXTCHRG] value and the base current.
- Measured with a 5 pF electrode, reference oscillator frequency of 10 MHz, PS = 128, NSCN = 8; Iext = 16.
- Measured with a 20 pF electrode, reference oscillator frequency of 10 MHz, PS = 128, NSCN = 2; Iext = 16.
- Measured with a 20 pF electrode, reference oscillator frequency of 10 MHz, PS = 16, NSCN = 3; Iext = 16.
- Sensitivity defines the minimum capacitance change when a single count from the TSI module changes, it is equal to (Cref
on the following configuration: Iext = 2 μA (EXTCHRG = 0), PS = 128, NSCN = 32, Iref = 32 μA (REFCHRG = 15).
- Time to do one complete measurement of the electrode. Sensitivity resolution of 0.0133 pF, PS = 0, NSCN = 0, 1
- REFCHRG=0, EXTCHRG=4, PS=7, NSCN=0F, LPSCNITV=F, LPO is selected (1 kHz), and fixed external capacitance of
20 pF. Data is captured with an average of 7 periods window.
6.9.2 LCD electrical characteristics
Table 46. LCD electricals
- HREFSEL=0, RVTRIM=1111
- HREFSEL=0, RVTRIM=1000
- HREFSEL=0, RVTRIM=0000
- HREFSEL=1, RVTRIM=1111
- HREFSEL=1, RVTRIM=1000
- HREFSEL=1, RVTRIM=0000 1.11 1.01 0.91 1.84 1.69 1.54 V V V V V V ΔRTRIM VIREG TRIM resolution — — 3.0 % VIREG Table continues on the next page... Peripheral operating requirements and behaviors K40 Sub-Family Data Sheet, Rev. 2, 4/2012. 62 Freescale Semiconductor, Inc.
Table 46. LCD electricals (continued)
- HREFSEL = 0
- HREFSEL = 1 mV mV IVIREG VIREG current adder — RVEN = 1 — 1 — µA 4 IRBIAS RBIAS current adder
- LADJ = 10 or 11 — High load (LCD glass capacitance ≤ 8000 pF)
- LADJ = 00 or 01 — Low load (LCD glass capacitance ≤ 2000 pF) µA µA RRBIAS RBIAS resistor values
- LADJ = 10 or 11 — High load (LCD glass capacitance ≤ 8000 pF)
- LADJ = 00 or 01 — Low load (LCD glass capacitance ≤ 2000 pF) 0.28 2.98 MΩ MΩ VLL2 VLL2 voltage
- HREFSEL = 0
- HREFSEL = 1 2.0 − 5% 3.3 − 5% 2.0 3.3 V V VLL3 VLL3 voltage
- HREFSEL = 0
- HREFSEL = 1 3.0 − 5% 5 − 5% 3.0 V V 1. The actual value used could vary with tolerance. 2. For highest glass capacitance values, LCD_GCR[LADJ] should be configured as specified in the LCD Controller chapter within the device's reference manual. 3. VIREG maximum should never be externally driven to any level other than VDD - 0.15 V 4. 2000 pF load LCD, 32 Hz frame frequency
7 Dimensions
7.1 Obtaining package dimensions
Package dimensions are provided in package drawings. K40 Sub-Family Data Sheet, Rev. 2, 4/2012.
If you want the drawing for this package Then use this document number 100-pin LQFP 98ASS23308W 104-pin MAPBGA 98ASA00344D
8 Pinout
8.1 K40 Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these pins on the devices supported by this document. The Port Control Module is responsible for selecting which ALT functionality is available on each pin. 104 MAP BGA 100 LQFP Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort E4 1 PTE0 ADC1_SE4aADC1_SE4aPTE0 SPI1_PCS1UART1_TX I2C1_SDARTC_CLKOUT E3 2 PTE1/ LLWU_P0 ADC1_SE5aADC1_SE5aPTE1/ LLWU_P0 SPI1_SOUTUART1_RX I2C1_SCLSPI1_SIN E2 3 PTE2/ LLWU_P1 ADC1_SE6aADC1_SE6aPTE2/ LLWU_P1 SPI1_SCKUART1_CTS_ b F4 4 PTE3 ADC1_SE7aADC1_SE7aPTE3 SPI1_SIN UART1_RTS_ b SPI1_SOUT E7 — VDD VDD VDD F7 — VSS VSS VSS H7 5 PTE4/ LLWU_P2 DISABLED PTE4/ LLWU_P2 SPI1_PCS0UART3_TX G4 6 PTE5 DISABLED PTE5 SPI1_PCS2UART3_RX F3 7 PTE6 DISABLED PTE6 SPI1_PCS3UART3_CTS_ b I2S0_MCLK USB_SOF_ OUT E6 8 VDD VDD VDD G7 9 VSS VSS VSS L6 — VSS VSS VSS F1 10 USB0_DPUSB0_DPUSB0_DP F2 11 USB0_DMUSB0_DMUSB0_DM G1 12 VOUT33 VOUT33 VOUT33 G2 13 VREGIN VREGIN VREGIN H1 14 ADC0_DP1ADC0_DP1ADC0_DP1 H2 15 ADC0_DM1ADC0_DM1ADC0_DM1 J1 16 ADC1_DP1ADC1_DP1ADC1_DP1 J2 17 ADC1_DM1ADC1_DM1ADC1_DM1 Pinout K40 Sub-Family Data Sheet, Rev. 2, 4/2012. 64 Freescale Semiconductor, Inc.
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort K1 18 PGA0_DP/ ADC0_DP0/ ADC1_DP3 PGA0_DP/ ADC0_DP0/ ADC1_DP3 PGA0_DP/ ADC0_DP0/ ADC1_DP3 K2 19 PGA0_DM/ ADC0_DM0/ ADC1_DM3 PGA0_DM/ ADC0_DM0/ ADC1_DM3 PGA0_DM/ ADC0_DM0/ ADC1_DM3 L1 20 PGA1_DP/ ADC1_DP0/ ADC0_DP3 PGA1_DP/ ADC1_DP0/ ADC0_DP3 PGA1_DP/ ADC1_DP0/ ADC0_DP3 L2 21 PGA1_DM/ ADC1_DM0/ ADC0_DM3 PGA1_DM/ ADC1_DM0/ ADC0_DM3 PGA1_DM/ ADC1_DM0/ ADC0_DM3 F5 22 VDDA VDDA VDDA G5 23 VREFH VREFH VREFH G6 24 VREFL VREFL VREFL F6 25 VSSA VSSA VSSA L3 26 VREF_OUT/ CMP1_IN5/ CMP0_IN5/ ADC1_SE18 VREF_OUT/ CMP1_IN5/ CMP0_IN5/ ADC1_SE18 VREF_OUT/ CMP1_IN5/ CMP0_IN5/ ADC1_SE18 K5 27 DAC0_OUT/ CMP1_IN3/ ADC0_SE23 DAC0_OUT/ CMP1_IN3/ ADC0_SE23 DAC0_OUT/ CMP1_IN3/ ADC0_SE23 L7 — RTC_ WAKEUP_B RTC_ WAKEUP_B RTC_ WAKEUP_B L4 28 XTAL32 XTAL32 XTAL32 L5 29 EXTAL32 EXTAL32 EXTAL32 K6 30 VBAT VBAT VBAT H5 31 PTE24 ADC0_SE17ADC0_SE17PTE24 UART4_TX EWM_OUT_b J5 32 PTE25 ADC0_SE18ADC0_SE18PTE25 UART4_RX EWM_IN H6 33 PTE26 DISABLED PTE26 UART4_CTS_ b RTC_CLKOUTUSB_CLKIN J6 34 PTA0 JTAG_TCLK/ SWD_CLK/ EZP_CLK TSI0_CH1PTA0 UART0_CTS_ UART0_COL_ b FTM0_CH5 JTAG_TCLK/ SWD_CLK EZP_CLK H8 35 PTA1 JTAG_TDI/ EZP_DI TSI0_CH2PTA1 UART0_RXFTM0_CH6 JTAG_TDIEZP_DI J7 36 PTA2 JTAG_TDO/ TRACE_SWO/ EZP_DO TSI0_CH3PTA2 UART0_TXFTM0_CH7 JTAG_TDO/ TRACE_SWO EZP_DO H9 37 PTA3 JTAG_TMS/ SWD_DIO TSI0_CH4PTA3 UART0_RTS_ b FTM0_CH0 JTAG_TMS/ SWD_DIO J8 38 PTA4/ LLWU_P3 NMI_b/ EZP_CS_b TSI0_CH5PTA4/ LLWU_P3 FTM0_CH1 NMI_b EZP_CS_b K7 39 PTA5 DISABLED PTA5 USB_CLKINFTM0_CH2 CMP2_OUTI2S0_TX_ BCLK JTAG_TRST_ b Pinout K40 Sub-Family Data Sheet, Rev. 2, 4/2012. Freescale Semiconductor, Inc. 65
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort E5 40 VDD VDD VDD G3 41 VSS VSS VSS K8 42 PTA12 CMP2_IN0CMP2_IN0PTA12 CAN0_TX FTM1_CH0 I2S0_TXD0FTM1_QD_ PHA L8 43 PTA13/ LLWU_P4 CMP2_IN1CMP2_IN1PTA13/ LLWU_P4 CAN0_RXFTM1_CH1 I2S0_TX_FSFTM1_QD_ PHB K9 44 PTA14 DISABLED PTA14 SPI0_PCS0UART0_TX I2S0_RX_ BCLK I2S0_TXD1 L9 45 PTA15 DISABLED PTA15 SPI0_SCKUART0_RX I2S0_RXD0 J10 46 PTA16 DISABLED PTA16 SPI0_SOUTUART0_CTS_ UART0_COL_ b I2S0_RX_FSI2S0_RXD1 H10 47 PTA17 ADC1_SE17ADC1_SE17PTA17 SPI0_SIN UART0_RTS_ b I2S0_MCLK L10 48 VDD VDD VDD K10 49 VSS VSS VSS L11 50 PTA18 EXTAL0 EXTAL0 PTA18 FTM0_FLT2FTM_CLKIN0 K11 51 PTA19 XTAL0 XTAL0 PTA19 FTM1_FLT0FTM_CLKIN1 LPTMR0_ ALT1 J11 52 RESET_b RESET_b RESET_b G11 53 PTB0/ LLWU_P5 LCD_P0/ ADC0_SE8/ ADC1_SE8/ TSI0_CH0 LCD_P0/ ADC0_SE8/ ADC1_SE8/ TSI0_CH0 PTB0/ LLWU_P5 I2C0_SCLFTM1_CH0 FTM1_QD_ PHA LCD_P0 G10 54 PTB1 LCD_P1/ ADC0_SE9/ ADC1_SE9/ TSI0_CH6 LCD_P1/ ADC0_SE9/ ADC1_SE9/ TSI0_CH6 PTB1 I2C0_SDAFTM1_CH1 FTM1_QD_ PHB LCD_P1 G9 55 PTB2 LCD_P2/ ADC0_SE12/ TSI0_CH7 LCD_P2/ ADC0_SE12/ TSI0_CH7 PTB2 I2C0_SCLUART0_RTS_ b FTM0_FLT3LCD_P2 G8 56 PTB3 LCD_P3/ ADC0_SE13/ TSI0_CH8 LCD_P3/ ADC0_SE13/ TSI0_CH8 PTB3 I2C0_SDAUART0_CTS_ UART0_COL_ b FTM0_FLT0LCD_P3 E11 57 PTB7 LCD_P7/ ADC1_SE13 LCD_P7/ ADC1_SE13 PTB7 LCD_P7 D11 58 PTB8 LCD_P8 LCD_P8 PTB8 UART3_RTS_ b LCD_P8 E10 59 PTB9 LCD_P9 LCD_P9 PTB9 SPI1_PCS1UART3_CTS_ b LCD_P9 D10 60 PTB10 LCD_P10/ ADC1_SE14 LCD_P10/ ADC1_SE14 PTB10 SPI1_PCS0UART3_RX FTM0_FLT1LCD_P10 C10 61 PTB11 LCD_P11/ ADC1_SE15 LCD_P11/ ADC1_SE15 PTB11 SPI1_SCKUART3_TX FTM0_FLT2LCD_P11 B10 62 PTB16 LCD_P12/ TSI0_CH9 LCD_P12/ TSI0_CH9 PTB16 SPI1_SOUTUART0_RX EWM_IN LCD_P12 Pinout K40 Sub-Family Data Sheet, Rev. 2, 4/2012. 66 Freescale Semiconductor, Inc.
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort E9 63 PTB17 LCD_P13/ TSI0_CH10 LCD_P13/ TSI0_CH10 PTB17 SPI1_SIN UART0_TX EWM_OUT_bLCD_P13 D9 64 PTB18 LCD_P14/ TSI0_CH11 LCD_P14/ TSI0_CH11 PTB18 CAN0_TX FTM2_CH0I2S0_TX_ BCLK FTM2_QD_ PHA LCD_P14 C9 65 PTB19 LCD_P15/ TSI0_CH12 LCD_P15/ TSI0_CH12 PTB19 CAN0_RXFTM2_CH1I2S0_TX_FS FTM2_QD_ PHB LCD_P15 F10 66 PTB20 LCD_P16 LCD_P16 PTB20 CMP0_OUTLCD_P16 F9 67 PTB21 LCD_P17 LCD_P17 PTB21 CMP1_OUTLCD_P17 F8 68 PTB22 LCD_P18 LCD_P18 PTB22 CMP2_OUTLCD_P18 E8 69 PTB23 LCD_P19 LCD_P19 PTB23 SPI0_PCS5 LCD_P19 B9 70 PTC0 LCD_P20/ ADC0_SE14/ TSI0_CH13 LCD_P20/ ADC0_SE14/ TSI0_CH13 PTC0 SPI0_PCS4PDB0_EXTRG I2S0_TXD1LCD_P20 D8 71 PTC1/ LLWU_P6 LCD_P21/ ADC0_SE15/ TSI0_CH14 LCD_P21/ ADC0_SE15/ TSI0_CH14 PTC1/ LLWU_P6 SPI0_PCS3UART1_RTS_ b FTM0_CH0 I2S0_TXD0LCD_P21 C8 72 PTC2 LCD_P22/ ADC0_SE4b/ CMP1_IN0/ TSI0_CH15 LCD_P22/ ADC0_SE4b/ CMP1_IN0/ TSI0_CH15 PTC2 SPI0_PCS2UART1_CTS_ b FTM0_CH1 I2S0_TX_FSLCD_P22 B8 73 PTC3/ LLWU_P7 LCD_P23/ CMP1_IN1 LCD_P23/ CMP1_IN1 PTC3/ LLWU_P7 SPI0_PCS1UART1_RXFTM0_CH2CLKOUT I2S0_TX_ BCLK LCD_P23 — 74 VSS VSS VSS A11 75 VLL3 VLL3 VLL3 A10 76 VLL2 VLL2 VLL2 A9 77 VLL1 VLL1 VLL1 B11 78 VCAP2 VCAP2 VCAP2 C11 79 VCAP1 VCAP1 VCAP1 A8 80 PTC4/ LLWU_P8 LCD_P24 LCD_P24 PTC4/ LLWU_P8 SPI0_PCS0UART1_TXFTM0_CH3 CMP1_OUTLCD_P24 D7 81 PTC5/ LLWU_P9 LCD_P25 LCD_P25 PTC5/ LLWU_P9 SPI0_SCKLPTMR0_ ALT2 I2S0_RXD0 CMP0_OUTLCD_P25 C7 82 PTC6/ LLWU_P10 LCD_P26/ CMP0_IN0 LCD_P26/ CMP0_IN0 PTC6/ LLWU_P10 SPI0_SOUTPDB0_EXTRGI2S0_RX_ BCLK I2S0_MCLKLCD_P26 B7 83 PTC7 LCD_P27/ CMP0_IN1 LCD_P27/ CMP0_IN1 PTC7 SPI0_SIN USB_SOF_ OUT I2S0_RX_FS LCD_P27 A7 84 PTC8 LCD_P28/ ADC1_SE4b/ CMP0_IN2 LCD_P28/ ADC1_SE4b/ CMP0_IN2 PTC8 I2S0_MCLK LCD_P28 D6 85 PTC9 LCD_P29/ ADC1_SE5b/ CMP0_IN3 LCD_P29/ ADC1_SE5b/ CMP0_IN3 PTC9 I2S0_RX_ BCLK FTM2_FLT0LCD_P29 C6 86 PTC10 LCD_P30/ ADC1_SE6b LCD_P30/ ADC1_SE6b PTC10 I2C1_SCL I2S0_RX_FS LCD_P30 C5 87 PTC11/ LLWU_P11 LCD_P31/ ADC1_SE7b LCD_P31/ ADC1_SE7b PTC11/ LLWU_P11 I2C1_SDA I2S0_RXD1 LCD_P31 Pinout K40 Sub-Family Data Sheet, Rev. 2, 4/2012. Freescale Semiconductor, Inc. 67
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort B6 — PTC12 LCD_P32 LCD_P32 PTC12 UART4_RTS_ b LCD_P32 A6 — PTC13 LCD_P33 LCD_P33 PTC13 UART4_CTS_ b LCD_P33 A5 — PTC14 LCD_P34 LCD_P34 PTC14 UART4_RX LCD_P34 — 88 VSS VSS VSS — 89 VDD VDD VDD D5 90 PTC16 LCD_P36 LCD_P36 PTC16 UART3_RX LCD_P36 C4 91 PTC17 LCD_P37 LCD_P37 PTC17 UART3_TX LCD_P37 B4 92 PTC18 LCD_P38 LCD_P38 PTC18 UART3_RTS_ b LCD_P38 A4 — PTC19 LCD_P39 LCD_P39 PTC19 UART3_CTS_ b LCD_P39 D4 93 PTD0/ LLWU_P12 LCD_P40 LCD_P40 PTD0/ LLWU_P12 SPI0_PCS0UART2_RTS_ b LCD_P40 D3 94 PTD1 LCD_P41/ ADC0_SE5b LCD_P41/ ADC0_SE5b PTD1 SPI0_SCKUART2_CTS_ b LCD_P41 C3 95 PTD2/ LLWU_P13 LCD_P42 LCD_P42 PTD2/ LLWU_P13 SPI0_SOUTUART2_RX LCD_P42 B3 96 PTD3 LCD_P43 LCD_P43 PTD3 SPI0_SIN UART2_TX LCD_P43 A3 97 PTD4/ LLWU_P14 LCD_P44 LCD_P44 PTD4/ LLWU_P14 SPI0_PCS1UART0_RTS_ b FTM0_CH4 EWM_IN LCD_P44 A2 98 PTD5 LCD_P45/ ADC0_SE6b LCD_P45/ ADC0_SE6b PTD5 SPI0_PCS2UART0_CTS_ UART0_COL_ b FTM0_CH5 EWM_OUT_bLCD_P45 B2 99 PTD6/ LLWU_P15 LCD_P46/ ADC0_SE7b LCD_P46/ ADC0_SE7b PTD6/ LLWU_P15 SPI0_PCS3UART0_RXFTM0_CH6 FTM0_FLT0LCD_P46 A1 100 PTD7 LCD_P47 LCD_P47 PTD7 CMT_IRO UART0_TXFTM0_CH7 FTM0_FLT1LCD_P47 K3 — NC NC NC H4 — NC NC NC J3 — NC NC NC H3 — NC NC NC K4 — NC NC NC J9 — NC NC NC J4 — NC NC NC H11 — NC NC NC F11 — NC NC NC B1 — NC NC NC C2 — NC NC NC C1 — NC NC NC D2 — NC NC NC D1 — NC NC NC E1 — NC NC NC Pinout K40 Sub-Family Data Sheet, Rev. 2, 4/2012. 68 Freescale Semiconductor, Inc.
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort B5 — NC NC NC
8.2 K40 Pinouts
The below figure shows the pinout diagram for the devices supported by this document. Many signals may be multiplexed onto a single pin. To determine what signals can be used on which pin, see the previous section. Pinout K40 Sub-Family Data Sheet, Rev. 2, 4/2012. Freescale Semiconductor, Inc. 69
98 PTD5
97 PTD4/LLWU_P14
96 PTD3
95 PTD2/LLWU_P13
94 PTD1
93 PTD0/LLWU_P12
92 PTC18
91 PTC17
90 PTC16
89 VDD
88 VSS
80 PTC4/LLWU_P8
83 PTC7
84 PTC8
85 PTC9
86 PTC10
87 PTC11/LLWU_P11
100 PTD7
Figure 27. K40 100 LQFP Pinout Diagram K40 Sub-Family Data Sheet, Rev. 2, 4/2012. 70 Freescale Semiconductor, Inc.
F USB0_DP G VOUT33 H ADC0_DP1 J ADC1_DP1 K ADC1_DP3 L ADC0_DP3 PTD5 PTD6/ NC NC PTE2/ USB0_DM VREGIN ADC0_DM1 ADC1_DM1 ADC1_DM3 ADC0_DM3 PTD4/ PTD3 PTD2/ PTD1 PTE1/ PTE6 VSS NC NC NC ADC1_SE18 PTC19 PTC18 PTC17 PTD0/ PTE0 PTE3 PTE5 NC NC NC XTAL32 PTC14 NC PTC11/ PTC16 VDD VDDA VREFH PTE24 PTE25 ADC0_SE23 EXTAL32 PTC13 PTC12 PTC10 PTC9 VDD VSSA VREFL PTE26 PTA0 VBAT VSS PTC8 PTC7 PTC6/ PTC5/ VDD VSS VSS PTE4/ PTA2 PTA5 RTC_ PTC4/ PTC3/ PTC2 PTC1/ PTB23 PTB22 PTB3 PTA1 PTA4/ PTA12 PTA13/ VLL1 PTC0 PTB19 PTB18 PTB17 PTB21 PTB2 PTA3 NC PTA14 PTA15 VLL2 PTB16 PTB11 PTB10 PTB9 PTB20 PTB1 PTA17 PTA16 VSS VDD A VLL3 BVCAP2 CVCAP1 DPTB8 EPTB7 FNC GPTB0/ HNC JRESET_b KPTA19 LPTA18CMP0_IN5/ CMP1_IN5/ VREF_OUT/ ADC1_DM0/ PGA1_DM/ ADC1_DP0/ PGA1_DP/ LLWU_P4 WAKEUP_B ADC0_DP0/ PGA0_DP/ ADC0_DM0/ PGA0_DM/ CMP1_IN3/ DAC0_OUT/ LLWU_P3 LLWU_P2 LLWU_P5 LLWU_P14 LLWU_P8 LLWU_P15 LLWU_P7 LLWU_P13 LLWU_P11 LLWU_P10 LLWU_P12 LLWU_P9 LLWU_P6 LLWU_P0 LLWU_P1 Figure 28. K40 104 MAPBGA Pinout Diagram
9 Revision History
The following table provides a revision history for this document. Table 47. Revision History Table continues on the next page...
Revision History
K40 Sub-Family Data Sheet, Rev. 2, 4/2012. Freescale Semiconductor, Inc. 71
Table 47. Revision History (continued) 2 4/2012 • Replaced TBDs throughout.
- Updated "Power consumption operating behaviors" table.
- Updated "ADC electrical specifications" section.
- Updated "VREF full-range operating behaviors" table.
- Updated "I2S/SAI Switching Specifications" section.
- Updated "TSI electrical specifications" table.
K40 Sub-Family Data Sheet, Rev. 2, 4/2012. 72 Freescale Semiconductor, Inc.
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