K3519PQ-XH KEC | Alldatasheet
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Technical content
- 4. 29 1/3 SEMICONDUCTOR TECHNICAL DATA K3519PQ-XH Common-Drain Dual N-Channel Enhancement Mode Field Effect Transistor Revision No : 0 General Description The K3519PQ-XH is a Dual N-channel MOSFET designed for use as a bi-directional load switch, facilitated by its common-drain configuration.
FEATURES
¡¤Low on-state resistance RDS(ON)1 = 16m¥ØMAX (VGS=4.5V, IS=1.0A) RDS(ON)2 = 17m¥ØMAX (VGS=3.9V, IS=1.0A) RDS(ON)3 = 20m¥ØMAX (VGS=3.5V, IS=1.0A) MAXIMUM RATING (Ta=25¡ÉUnless otherwise noted) Rg Rg D D 180 10 +_ 2000 1080 S2S1 BOTTOM : COMMON DRAIN CHARACTERISTIC SYMBOL RATING UNIT Drain-Source Voltage VDSS 24 V Gate-Source Voltage VGSS ¡¾12 V Storage Temperature Range Tstg -55¡150 ¡É Equivalent Circuit
- 4. 29 2/3 K3519PQ-XH Revision No : 0 Electrical Characteristics (Ta=25¡ÉUnless otherwise noted) CHARACTERISTIC SYMBOL TEST CONDITION MIN TYP MAX UNIT Drain to Source Breakdown Voltage V(BR)DSS ID = 250¥ìA, VGS = 0V 24 - - V Gate to Source Breakdown Voltage V(BR)GSS IG = ¡¾100§Ë, VDS = 0V ¡¾12 ¡¾14 - V Drain Cut-off Current IDSS VDS = 24V, VGS = 0V - - 1.0 §Ë Gate to Source Leakage Current IGSS VGS = ¡¾12V, VDS = 0V - - ¡¾10 §Ë Gate to Source Threshold Voltage Vth VDS=VGS, ID=250 A 0.5 1.1 1.5 V Drain to Source On Resistance RDS(on) VGS = 4.5V, ID = 1.0A - 12.0 16.0 m¥Ø VGS = 3.9V, ID = 1.0A - 13.0 17.0 m¥Ø VGS = 3.5V, ID = 1.0A - 14.5 20.0 m¥Ø Gate Resistance Rg f=1MHz - 3.0 - k§Ù Input Capacitance Ciss VDS = 10V, VGS = 0V, f=1MHz - 600 - pFOutput Capacitance Coss - 115 - Reverse Transfer Capacitance Crss - 83 - Total Gate Charge Qg VDD=10V, VGS=3.9V, IS=4.0A - 6.0 - nCGate-Source Charge Qgs - 0.8 - Gate-Drain Charge Qgd - 2.5 - Source-Drain Forward Voltage VSD VGS = 0V, IS = 1.0A 0.50 0.70 0.86 V
- 4. 29 3/3 K3519PQ-XH Revision No : 0 2000 1080 S2S1 BOTTOM : COMMON DRAIN DIE INFORMATION CONTENTS VALUE Wafer size 8 inch notch type Wafer thickness 180um Front Metal A§¤-4um Back Metal Ti/Ni/Ag-1.4um Passivation Layer Yes Die Size (with scribe lane) 2000¡¿1080§2 Scribe lane width 60§ Gate Pad Size 170¡¿163§2 Die edge to gate Pad 84§ Die edge to Source Pad 70§ Gross Die(per Wafer) 13,470ea