K32W1480 NXP

Document overview

  • Manufacturer or author: NXP Semiconductors
  • PDF pages: 90

Technical content

Datasheet sections

  • 1 Ratings
  • 1.1 Thermal handling ratings
  • 1.2 Moisture handling ratings
  • 1.3 ESD and Latch-Up Ratings
  • 1.4 Voltage and current maximum ratings
  • 1.5 Required Power-On-Reset (POR) Sequencing
  • 1.6 Power Sequence
  • 2 General
  • 2.1 AC electrical characteristics
  • 2.2 Nonswitching electrical specifications
  • 2.2.2 HVD, LVD, and POR operating requirements
  • 2.2.3 Voltage and current operating behaviors
  • 2.2.4 On-chip regulator electrical specifications
  • 2.2.4.1 DCDC converter specifications
  • 2.2.4.2 LDO_SYS electrical specifications
  • 2.2.4.3 LDO_CORE electrical specifications
  • 2.2.5 Smart power switch
  • 2.2.7 Power consumption operating behaviors
  • 2.2.7.1 Power Consumption Operating Behaviors
  • 2.2.7.2 SoC Power Consumption
  • 2.2.7.3 Typical power-down mode RAM current adders
  • 2.2.7.4 Low power mode peripheral power
  • 2.2.8 EMC radiated emissions operating behaviors
  • 2.2.9 Designing with radiated emissions in mind
  • 2.2.10 Capacitance attributes
  • 2.3 Switching specifications
  • 2.3.1 Device clock specifications
  • 2.3.2 General switching specifications
  • 2.4 Thermal specifications
  • 2.4.1 Thermal operating requirements
  • 2.4.2 Thermal attributes
  • 3 Peripheral operating requirements and behaviors
  • 3.1 Core modules
  • 3.1.1 SWD electricals
  • 3.2 Clock modules
  • 3.2.1 Reference oscillator specification
  • 3.2.3 Free-running oscillator FRO-192M
  • 3.2.4 Free-running oscillator FRO-6M specifications
  • 3.2.5 Free-running oscillator FRO-32K specifications
  • 3.2.6 Free-running oscillator FRO-16K specifications
  • 3.3 Memories and memory interfaces
  • 3.3.1 Flash electrical specifications
  • 3.3.1.1 Flash Read wait state control specifications
  • 3.3.1.2 Flash timing specifications
  • 3.3.1.3 Flash high voltage current behavior
  • 3.3.1.4 Flash reliability specifications
  • 3.4 Radio modules
  • 3.4.2 Receiver Feature Summary
  • 3.4.3 Transmit and PLL Feature Summary
  • 3.5 Analog
  • 3.5.1 ADC electrical specifications
  • 3.5.3 Voltage reference electrical specifications
  • 3.6 Timers
  • 3.7 Communication interfaces
  • 3.7.1 LPUART
  • 3.7.2 LPSPI switching specifications
  • 3.7.3 Inter-Integrated Circuit Interface (I2C)
  • 3.7.4 Improved Inter-Integrated Circuit Interface
  • 3.8 Human Machine Interface (HMI) modules
  • 3.8.1 General Purpose Input/Output (GPIO)
  • 3.8.2 Flexible IO controller (FlexIO)
  • 4 Package dimensions
  • 4.1 Obtaining package dimensions
  • 5 Pinout
  • 5.1 Pinout Table
  • 5.2 Recommended connection for unused analog
  • 5.3 Pinouts diagram
  • 6 Ordering parts
  • 6.1 Determining valid orderable parts
  • 7 Part identification
  • 7.1 Part number format
  • 7.2 Example
  • 7.3 Package marking
  • 7.3.1 Package marking information
  • 8 Terminology and guidelines
  • 8.1 Definitions
  • 8.2 Examples
  • 8.3 Typical-value conditions

The K32W14x product family is a low-power, highly secure, single chip multiprotocol wireless MCU that integrates a high performance Bluetooth Low Energy version 5.3 radio and an IEEE 802.15.4 radio supporting Thread, Matter and Zigbee. The K32W14x implements a tri-core architecture to isolate the connectivity, computing and security capabilities. The multiprotocol radio is energy efficient, supports full simultaneous dual- PAN to enable Thread and Zigbee, and designed for Wi-Fi coexistence. The radio is supported with tested software stacks for Matter, Thread, Zigbee and Bluetooth Low Energy for standalone and hosted applications to enable a range of IoT and industrial applications. The K32W14x integrates a state-of-the-art, scalable security architecture including Arm® TrustZone®-M, a resource domain controller and an isolated EdgeLock™ Secure Enclave supporting hardware cryptographic accelerators, random number generators, key generation, storage and management, and secure debug. Flash memory contents can optionally be stored as encrypted data and then decrypted on-the-fly enabling protection of sensitive data and algorithms. The K32W14x implements a flexible power efficient architecture to extend battery life and reduce energy footprint in IoT devices Application core

  • Up to 96 MHz Arm Cortex®-M33 core
  • TrustZone-M, IEEE 754 FPU, DSP, MPU, NVIC, SysTick
  • 8 KB Code Cache to improve performance and efficiency
  • 1 MB flash memory
  • 128 KB SRAM
  • Secure Boot ROM
  • Bluetooth LE Controller stack and transceiver drivers contained in on-chip radio memory, preserving more on- chip system memory for host stack and application space Target applications
  • Smart Home IoT — Smart Home environmental, occupancy, and security sensors — Home Gateways and Bridges — Smart Lighting EdgeLock Secure Enclave
  • Secure boot and debug
  • Trusted resource domain controller (TRDC) providing programmable control mechanisms for independent processing domains including embedded memory and peripherals — Privilege/user — Data only — Execute only — Read-only access — Secure/Non-secure
  • Advanced flash access protection — Write/Erase protection, Execute only, Data only access control — Optional encryption and on-the-fly decryption using a PRINCE XEX block cipher mode
  • Hardware encryption and decryption Table continues on the next page... K32W1480VFTBT K32W1480VFTBR 48HVQFN 7 x 7 x 0.85 mm; Pitch 0.5 mm K32W1480 K32W14x Product Family Ultra-low-power, Highly Secure, Multiprotocol Wireless MCU Rev. 3 — 12/2022 Data Sheet: Technical Data NXP reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. General Business Information

— Smart Plugs — Access Control — HVACs and Thermostats — Window Shades

  • Industrial/IoT — Positioning/Localization — Building Control and Monitoring — Building HVAC Control — Fire and Security — Smart Lighting — Access Control Narrow Band Radio Unit
  • Dedicated CM3 core running at up to 64 MHz
  • 256 kB Flash supporting upgradable software radio
  • 88 KB SRAM optimized for link layer support
  • IEEE 802.15.4 Radio — IEEE 802.15.4–2015 compliant radio — –103 dBm 250 kbps Receive Sensitivity — Programmable Transmit Output Power up to +10 dBm — Improved Enhanced ACK timing support in the 802.15.4 hardware which enables synchronized broadcasts to a larger number of sleepy end devices – for example, synchronous window blinds actuation — Supports Dual PAN which allows a single radio to participate in two 802.15.4 Personal Area Networks — Modulation Types: 2 Level FSK, GFSK, MSK, GMSK — Single ended bidirectional RF port — Low external component counts for low cost, small form-factor designs
  • Bluetooth Low Energy radio core — Up to 24 simultaneous connections — –106 dBm 125 kbps Long Range Receive Sensitivity — –102 dBm 500 kbps Long Range Receive Sensitivity — Symmetric Key Encryption ◦ AES-128/192/256 ◦ ECB, CBC, CFB, OFB, CTR, GCM, CMAC, and CCM Modes ◦ ChaCha20 — Asymmetric Key Encryption ◦ RSA-2048/3072/4096 ◦ ECC NIST P–192/224/256/384/521 ◦ Curve25519 — Key Exchange Algorithms ◦ ECDH(E) ◦ SPAKE2+ ◦ JPAKE — Digital Signature Algorithms ◦ ECDSA ◦ Ed25519 — Hash Algorithms ◦ SHA2-224/256/384/512 ◦ Poly1305
  • Secure key generation, storage, and management
  • Pseudo (PRNG) and True Random Number Generator (TRNG) with 512-bits entropy supporting NIST SP 800-90A and SP 800-90B
  • Support for secure over-the-air (OTA) firmware updates
  • Four digital tamper pins with optional interrupt and seconds timestamp upon trigger
  • Universally Unique ID (UUID) programmed by NXP during factory programming
  • 24-bit unique IEEE media access control (MAC) subaddress
  • Factory Root of Trust programming Low-power consumption (DCDC 3.6 V, 25 ºC)
  • Typical active core current: < 5.3 mA at 96 MHz (< 55 μA/MHz)
  • Transceiver current (DC-DC buck mode, 3.3 V supply) — Typical RX: 4.7 mA — Typical TX at 0 dBm: 4.6 mA Table continues on the next page... NXP Semiconductors K32W14x Product Family, Rev. 3, 12/2022 Data Sheet: Technical Data General Business Information 2 / 90

— –97.5 dBm 1 Mbps Receive Sensitivity — –95 dBm 2 Mbps Receiver Sensitivity — Programmable Transmit Output Power up to +10 dBm — Data Rates: 125 kbps, 500 kbps, 1 Mbps, and 2 Mbps — Modulation Types: 2 Level FSK, GFSK, MSK, GMSK — Integrated memories in radio containing Bluetooth LE Controller Stack and radio drivers — On-chip balun with single ended bidirectional RF port — Low external component counts for low cost, small form-factor designs Safety

  • Memory Protection Unit (MPU)
  • Register write protection
  • Illegal memory access
  • Flash area protection
  • SRAM Error Correction Code (ECC) and SRAM parity error check
  • Clock Frequency Accuracy Measurement Circuit (CAC) using Signal Frequency Analyzer (SFA) module
  • Cyclic Redundancy Check (CRC) calculator
  • Two internal, independent, and one external watchdog timers
  • Clock loss detection
  • Main oscillator stop detection (Loss of lock detection)
  • Low voltage / high voltage detection System peripherals
  • DC/DC converter supporting buck and bypass operating modes
  • Asynchronous DMA controller with per channel access permissions (secure/non-secure)
  • Two internal and one external watchdog monitors
  • Nested vectored interrupt controller
  • Wakeup unit for power down modes Analog modules — Typical TX at 10 dBm: 18.7 mA
  • Less than 3 μA in Power-down mode with real-time clock (RTC) active and 32 KB SRAM retention
  • Less than 1.5 μA in Deep Power-down mode with RTC active
  • Multiple power-down modes supporting currents as low as 300 nA
  • Ultra-low leakage Smart Power Switch with less than 100 nA sleep current with exit from internal timer or GPIO. Clocks
  • 32 MHz RF crystal oscillator
  • 32.768 kHz crystal oscillator
  • Internal 192 MHz high frequency free running oscillator providing 48/64/96 MHz clock
  • Internal low frequency free running oscillator providing 6 MHz clock
  • Internal low-power free running oscillator providing 32 kHz clock Communication interfaces
  • Two Low Power UART (LPUART) modules
  • Two Low Power SPI modules and one MIPI-I3C module
  • Two Low Power I2C (LPI2C) modules supporting the System Management Bus (SMBus) Specification, version
  • One programmable FlexIO module supporting emulation of UART, I2C, I2S, SPI, Camera IF, LCD RGB, PWM/ Waveform generation Timers
  • One 2-channel 32-bit timers (LPTPM)
  • Two 6-channel 32-bit timers (LPTPM) with PWM capability and DMA support
  • Two 32-bit low-power timers (LPTMR) or pulse counters with compare features
  • 4-channel 32-bit low-power periodic interrupt timer (LPIT) with DMA support
  • One 56-bit timestamp timer
  • 32-bit seconds real time counter (RTC) with 32-bit alarm and independent power supply
  • Signal frequency analyzer (SFA) provides facilities for measurement of clock period/frequency as well as time between triggers Table continues on the next page... NXP Semiconductors K32W14x Product Family, Rev. 3, 12/2022 Data Sheet: Technical Data General Business Information 3 / 90
  • 16-bit single ended SAR Analog-to-digital converter (ADC) up to 2 Msps
  • Two 6-bit High-speed analog comparators (CMP) with 8-bit digital-to-analog converter (DAC)
  • 1.0 V to 2.1 V Voltage Reference (Vref) Operating characteristics
  • Temperature range (ambient): –40 °C to 105 °C
  • Temperature range (junction): –40 °C to 125 °C
  • DC/DC voltage range: 1.71 V to 3.6 V
  • Bypass voltage range: 1.71 V to 3.6 V Input supply voltage options:
  • Integrated DCDC regulator 1.71 V–3.6 V providing power to Core_LDO regulator, SYS_LDO regulators, and Radio
  • Integrated Core_LDO regulator 1.2 V–3.6 V powering the core digital domain
  • Integrated SYS_LDO regulator 1.71 V to 3.6 V powering the SYS domain
  • DCDC and Core_LDO regulators can support bypass modes
  • Radio Analog: 1.2 V–3.6 V
  • Radio PA: 0.9 V–2.4 V Human Machine Interface modules
  • General-purpose input/output (GPIO)

Table 1. Ordering Information

1 MB/128

Table 2. Device Revision Number Table 3. Related Resources structure and function (operation) of a device. for a particular device mask set.

1 MB Flash

96 MHz

Figure 1. K32W1480 block diagram

8.4 Relationship between ratings and operating

8.5 Guidelines for ratings and operating

1 Ratings

1.1 Thermal handling ratings

Table 4. Thermal handling ratings

  1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
  2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic

Solid State Surface Mount Devices.

1.2 Moisture handling ratings

Table 5. Moisture handling ratings

  1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic

Solid State Surface Mount Devices.

1.3 ESD and Latch-Up Ratings

Table 6. ESD and Latch-Up Ratings

  1. Determined according to JEDEC Standard JS-001-2017, For Electrostatic Discharge (ESD) Sensitivity Testing, Human

Body Model (HBM) - Component Level.

  1. Determined according to JEDEC Standard JS-002-2018, For Electrostatic Discharge (ESD) Sensitivity Testing, Charged-

Device Model (CDM) - Device Level .

  1. Determined according to JEDEC Standard JESD78F, IC Latch-Up Test.

1.4 Voltage and current maximum ratings

Table 7. Voltage and current maximum ratings Table continues on the next page...

Table 7. Voltage and current maximum ratings (continued)

  1. The part supports 2.75 V for up to 20 s over lifetime to allow fuse programming
  2. The Max. of the VIN cannot be greater than the voltage applied to the VDD_IO_x.

1.5 Required Power-On-Reset (POR) Sequencing

inputs on power-up must not exceed VDD voltage maximums. Figure 2. VDD_CORE/VDD_IO_ABC Powering Sequence

1.6 Power Sequence

Table 8. Power Sequence

  1. All domains can be powered at the same time. If external sources are used, make sure they start at the same time or they

follow the order in the sequence.

2 General

2.1 AC electrical characteristics

20 % and 80 % points, as shown in the following figure. Figure 3. Input signal measurement reference

2.2 Nonswitching electrical specifications

2.2.1 Voltage and current operating requirements

Table 9. Voltage and current operating requirements Table continues on the next page...

Table 9. Voltage and current operating requirements (continued)

  • Normal mode
  • Fuse Programming 1.8 2.25 1.98 2.75 V VDD_DCDC Supply voltage DCDC regulator 1.8 3.6 V 1 VDD_IO_D Supply voltage for LDO_SYS regulator, PortD 1.86 3.6 V 2 VDD_LDO_ CORE Supply voltage for LDO_CORE regulator 1.25 3.6 V VDD_RF Supply voltage for OSC and radio analog 1.175 3.6 V VPA_2P4GH z Supply voltage for 2.4 GHz radio power amplifier 0.9 2.4 V VDD_IO_AB C Supply voltage for PortA, PortB, Port C, and CMPs 1.71 3.6 V 3 VDD_ANA Supply voltage for ADC, DAC, and VREF 1.71 3.6 V VSS - VSS_ANA VSS-to-VSS_ANA differential voltage –0.1 0.1 V VIH Input high voltage
  • 1.71 V ≤ VDD_IO_ABC ≤ 3.6 V
  • 1.86 V ≤ VDD_IO_D ≤ 3.6 V 0.7 × VDD_I O_ABC 0.7 × VDD_I O_D V VIL Input low voltage
  • 1.71 V ≤ VDD_IO_ABC ≤ 3.6 V
  • 1.86 V ≤ VDD_IO_D ≤ 3.6 V 0.3 × VDD_I O_ABC 0.3 × VDD_I O_D V VHYS Input hysteresis 0.1 × VDD_I O_X — V IICIO IO pin DC injection current — single pin
  • VIN < VSS – 0.3 V (negative current injection)
  • VIN > VDD + 0.3 V (positive current injection) mA 5, 6 VODPU Open drain pullup voltage level VDD_IO_X VDD_IO_X V 7 1. If DCDC is unused, then input supply should be tied to GND through a 10 kΩ resistor. 2. When LDO_SYS is bypassed, the input supply voltage is 1.8 V to 1.98 V and VDD_IO_D must be externally connected to VDD_SYS 3. If none of the PortA, PortB, and PortC pins are being used, then the VDD_IO_ABC can be left floating. 4. VIH and VIL for PTD0 are based of VDD_SYS instead of VDD_IO_D NXP Semiconductors General K32W14x Product Family, Rev. 3, 12/2022 Data Sheet: Technical Data General Business Information 11 / 90
  1. All I/O pins are internally clamped to VSS and VDD_IO_x through an ESD protection diode. If VIN is greater than

limiting resistors at the pads. If this limit cannot be observed, then a current limiting resistor is required.

  1. This device does not allow pin injection current. User must ensure that VIN is kept within the Voltage Maximum Ratings.
  2. Open drain outputs must be pulled to whichever supply voltage corresponds to that IO, VDD_IO_X as appropriate.

2.2.2 HVD, LVD, and POR operating requirements

  • VDD_IO_ABC
  • VDD_CORE
  • VDD_SYS For VDD_SYS, it has Power-on-reset (POR) power supervisor circuits.

Table 10. VDD_IO_ABC supply HVD, LVD, and POR Operating Ratings Table 11. VDD_CORE supply HVD and LVD Operating Ratings Table continues on the next page...

Table 11. VDD_CORE supply HVD and LVD Operating Ratings (continued)

  1. Same value applies to all conditions.

Table 12. VDD_SYS supply HVD and LVD Operating Ratings

  1. When fuses are being programmed VDD_SYS is raised to 2.5 V nominal. This is outside the HVD bounds, so HVD

2.2.3 Voltage and current operating behaviors

Table 13. Voltage and current operating behaviors Table continues on the next page...

Table 13. Voltage and current operating behaviors (continued)

  • 2.7 V ≤ VDD_IO_X ≤ 3.6 V, IOH = 4 mA
  • 1.71 V ≤ VDD_IO_ABC < 2.7 V, IOH = 2.5 mA
  • 1.86 V ≤ VDD_IO_D < 2.7 V, IOH = 2.5 mA VDD_IO_X – 0.5 — — V VOH Output high voltage — High drive strength
  • 2.7 V ≤ VDD_IO_X ≤ 3.6 V, IOH = 6 mA
  • 1.71 V ≤ VDD_IO_ABC < 2.7 V, IOH = 3.75 mA
  • 1.86 V ≤ VDD_IO_D < 2.7 V, IOH = 3.75 mA VDD_IO_X – 0.5 — — V 1,2 IOHT Output high current total for all ports — — 100 mA VOL Output low voltage — Normal drive strength
  • 2.7 V ≤ VDD_IO_X ≤ 3.6 V, IOL = 4 mA
  • 1.71 V ≤ VDD_IO_ABC < 2.7 V, IOL = 2.5 mA
  • 1.86 V ≤ VDD_IO_D < 2.7 V, IOH = 2.5 mA — — 0.5 V 1,3 VOL Output low voltage — High drive strength
  • 2.7 V ≤ VDD_IO_X ≤ 3.6 V, IOL = 6 mA
  • 1.71 V ≤ VDD_IO_ABC < 2.7 V, IOL = 3.75 mA
  • 1.86 V ≤ VDD_IO_D < 2.7 V, IOL = 3.75 mA — — 0.5 V 1,3,2 IOLT Output low current total for all ports — — 100 mA IIN Input leakage current (per pin) for full temperature range — — 1 μA 4 IIN Input leakage current (per pin) at 25 °C — — 0.025 μA 4 IIN Input leakage current (total all pins) for full temperature range — — 41 μA 4 IOZ Hi-Z (off-state) leakage current (per pin) — — 1 μA RPU Internal pullup resistors 33 50 75 kΩ RPU (I3C) Internal pullup resistors 1.1 2 2.833 kΩ 5 RPD Internal pulldown resistors 33 50 75 kΩ RHPU High-resistance pullup option (PORTx_PCRy[PV] = 1) 0.67 — 1.5 MΩ 6 RHPD High-resistance pulldown option (PORTx_PCRy[PV] = 1) 0.67 — 1.5 MΩ 6 1. When setting DSE1=1, the same VOH / VOL is met with IOH / IOL doubled. 2. RTC signals are always configured in high drive mode 3. Open drain outputs must be pulled to VDD_IO_X. 4. Measured at VDD_IO_X = 3.6 V. 5. Only I3C pins support this option 6. Only Port D pins support this option. NXP Semiconductors General K32W14x Product Family, Rev. 3, 12/2022 Data Sheet: Technical Data General Business Information 14 / 90

2.2.4 On-chip regulator electrical specifications

2.2.4.1 DCDC converter specifications

Table 14. DCDC Converter Specifications

  • Normal drive strength
  • Low drive strength
  • SPC_DCD_CFG[FREQ_CNTRL_ON]=1 105 mA mA mA 1, 3 LX DCDC inductor value 0.47 1 2.2 µH 4 ESR External inductor equivalent series resistance — 110 — mΩ 5 COUT DCDC capacitance value 6 22 30 µF 6 VRIPPLE DCDC voltage ripple
  • In normal drive strength
  • In low drive strength mV fburst DCDC burst frequency 3 5 8 MHz 7 fburst_acc DCDC burst frequency accuracy — 10 — % 7 1. The system DCDC converter generates 1.8 V at DCDC_LX by default. The DCDC can be used to power VDD_RF, VDD_LDO_CORE, and external components as long as the max ILOAD is not exceeded. 2. The VDD_DCDC input supply to DCDC must be at least 500 mV higher than the desired output at DCDC_LX. 3. The maximum load current during boot up shall not exceed 60 mA. 4. Recommended inductor value is 1 µH to 1.5 µH. If the inductor is < 1 µH, the DCDC efficiency is not guaranteed 5. The maximum recommended ESR is 250 mΩ (not a hard limit). 6. The variation in capacitance of the capacitor at DCDC_LX due to aging, temperature, and voltage degradation must not exceed the Min./Max. values. 7. FREQ_CNTRL_ON = 1. NXP Semiconductors General K32W14x Product Family, Rev. 3, 12/2022 Data Sheet: Technical Data General Business Information 15 / 90

Figure 4. Efficiency vs Load current in Normal drive

Figure 5. Efficiency vs Load current in Low-power drive

2.2.4.2 LDO_SYS electrical specifications

Table 15. LDO_SYS electrical specifications

  • LDO_SYS input supply voltage (Regulation mode)
  • LDO_SYS input supply voltage (Bypass mode)
  • Fuse programming mode 1.86 1.8 2.75 3.6 1.98 3.6 V 1 VOUT_SYS LDO_SYS regulator output voltage
  • Normal drive mode
  • Fuse Programming mode 1.71 2.25 1.8 2.5 1.98 2.75 V 2,3,4,5 ILOAD LDO_SYS maximum load current Table continues on the next page... NXP Semiconductors General K32W14x Product Family, Rev. 3, 12/2022 Data Sheet: Technical Data General Business Information 17 / 90

Table 15. LDO_SYS electrical specifications (continued)

  • Normal drive mode
  • Low drive mode
  • Fuse programming mode mA mA mA IDD LDO_SYS power consumption
  • Normal drive mode
  • Low drive mode 100 μA nA COUT External output capacitor — 1.5 10 μF CDEC External output decoupling capacitor — 0.1 — μF ESR External output capacitor equivalent series resistance — 30 — mΩ IINRUSH LDO_SYS inrush current — — 120 mA 7 1. Regulator will automatically switch to passthrough (means the regulator driver is fully ON) with the supply is below 1.95 V. 2. The LDO_SYS converter generates 1.8 V by default at VOUT_SYS. VOUT_SYS can be used to power VDD_SYS, VDD_RF, VDD_IO_X, VDD_ANA, and external components as long as the max ILOAD is not exceeded. 3. VOUT_SYS and VDD_SYS are connected together. 4. VDD_IO_D must be at least 150 mV higher than the desired VOUT_SYS. 5. LDO_SYS can be used to program efuse and in this configuration the output voltage can range between 2.25 V and 2.75 V 6. In normal drive strength, LDO_SYS draws ~100 μA for every 20 mA of load current. 7. This is for 1.5 μF external output capacitor. If the capacitor has 10 μF value, this value should be 300 mA instead.

2.2.4.3 LDO_CORE electrical specifications

Table 16. LDO_CORE electrical specifications

  • Normal drive strength
  • Low drive strength 1.0 1.0 1.15 1.15 V ILOAD LDO_CORE max load current
  • Normal mode - VDD_LDO_CORE ≥ 1.5 V
  • Normal mode - VDD_LDO_CORE < 1.5 V
  • Low-power mode - VDD_LDO_CORE ≥ 1.5 V
  • Low-power mode - VDD_LDO_CORE < 1.5 V mA Table continues on the next page... NXP Semiconductors General K32W14x Product Family, Rev. 3, 12/2022 Data Sheet: Technical Data General Business Information 18 / 90

Table 16. LDO_CORE electrical specifications (continued)

  • Normal drive strength - VDD_LDO_CORE ≥ 1.5 V
  • Normal drive strength - VDD_LDO_CORE < 1.5 V
  • Low drive strength - VDD_LDO_CORE ≥ 1.5 V
  • Low drive strength - VDD_LDO_CORE < 1.5 V 150 0.05 0.05 μA IINRUSH LDO_CORE inrush current — — 5 x ILOAD mA 1. To bypass LDO_CORE, tie VDD_LDO_CORE to VDD_CORE 2. The VDD_LDO_CORE input supply must also be at least 250 mV higher than the desired output at VOUT_CORE. 3. In normal drive strength, LDO_CORE draws ~40 μA for every 20 mA of load current. In low drive strength, LDO_CORE draws ~50 nA for every 100 μA of load current.

Table 17. LDO_CORE external device electrical specifications

2.2.5 Smart power switch

SWITCH_WAKEUP_B pulldown voltage is 0.7 V, duration time should be larger than 1 µs. Table 18. Smart power switch

2.2.6 Power mode transition operating behaviors

Table 19. Power mode transition operating behaviors

2.2.7 Power consumption operating behaviors

by each power domain in the corresponding KW45 power mode configuration.

  • Specifications below only include power for the MCU itself
  • On top of the device’s IDD current consumption, external loads applied to pins of the device need to be considered
  • Efficiency of regulators (on-chip or off-chip) used to generate supply voltages should be considered The maximum values stated in the following sections represent characterized results equivalent to the mean plus three times the standard deviation (mean + 6 sigma).

2.2.7.1 Power Consumption Operating Behaviors

Table 20. Power Consumption Operating Behaviors Table continues on the next page...

Table 20. Power Consumption Operating Behaviors (continued) Table continues on the next page...

Table continues on the next page...

Table continues on the next page...

  1. All regulators are disabled. Voltages are come from external supplies. External 3.3V supply for VDD_SWITCH, VDD_ANA,
  2. All regulators are disabled. Voltages are come from external supplies. External 3.3V supply for VDD_SWITCH, VDD_ANA,
  3. 8 KB of retained RAM correspond to the last RAM block and is powered by the standby LDO in smart power switch domain
  4. External 3.3 V supply to Smart Power Switch. Power switch output connected to DCDC_IN, LDO_SYS, VDD_ANA, VDD_IO_D

2.2.7.2 SoC Power Consumption

Table 21. SoC POwer Consumption

2.2.7.3 Typical power-down mode RAM current adders

currents are measured in power-down mode, but RAM adder should be similar for other modes. Table 22. Typical power-down mode RAM current adders Table continues on the next page...

Table 22. Typical power-down mode RAM current adders (continued)

2.2.7.4 Low power mode peripheral power consumption adders

Table 23. Low power mode peripheral power consumption adders Table continues on the next page...

Table 23. Low power mode peripheral power consumption adders (continued) generating the clock signal. Table continues on the next page...

2.2.8 EMC radiated emissions operating behaviors

EMC measurements to IC-level IEC standards are available from NXP on request.

2.2.9 Designing with radiated emissions in mind

  1. Go to https://www.nxp.com/.
  2. Perform a keyword search for “EMC design”.

2.2.10 Capacitance attributes

Table 24. Capacitance attributes

2.3 Switching specifications

2.3.1 Device clock specifications

Table 25. Device clock specifications By default, VDD_CORE = 1.0 V, fCPU_CLK/fBUS_CLK = 32 MHz, fSLOW_CLK = 16 MHz.

2.3.2 General switching specifications

Table 26. General switching specifications Table continues on the next page...

Table 26. General switching specifications (continued)

  • 1.71 ≤ VDD_IO_x < 2.7 V — Fast slew rate (SRE = 0; DSE = 1) — Slow slew rate (SRE = 1; DSE = 1) 2.9 2.4 6.1 ns ns ns ns I2C/I3C I/O pins — Normal drive, fast slew rate (SRE = 0; DSE = ) — Normal drive, slow slew rate (SRE = 1; DSE = 0) — High drive, fast slew rate (SRE = 0; DSE = 1) — High drive, slow slew rate (SRE = 1; DSE = 1)
  • 1.71 ≤ VDD_IO_x < 2.7 V — Normal drive, fast slew rate (SRE = 0; DSE = 0) — Normal drive, slow slew rate (SRE = 1; DSE = 0) — High drive, fast slew rate (SRE = 0; DSE = 1) — High drive, slow slew rate (SRE = 1; DSE = 1) 6.1 2.8 5.6 2.8 6.4 2.3 5.7 ns ns ns ns ns ns ns ns Reset and NMI pins
  • 1.71 ≤ VDD_IO_x < 2.7 V 3.3 4.3 6.7 ns ns 1. The synchronous and asynchronous timing must be met. 2. This is the shortest pulse that is guaranteed to be recognized. 3. Load is 25 pF. Drive strength and slew rate are configured using PORTx_PCRn[DSE] and PORTx_PCRn[SRE]. 4. Load is 25 pF for DSE=0 or DSE=1. Load is 50 pF for DSE=2 or DSE=3. Drive strength and slew rate are configured using PORTx_PCRn[DSE1], PORTx_PCRn[DSE], and PORTx_PCRn[SRE]. 5. Load is 25 pF.

2.4 Thermal specifications

2.4.1 Thermal operating requirements

Table 27. Thermal operating requirements

2.4.2 Thermal attributes

Table 28. Thermal attributes

  1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions

—Natural Convection (Still Air).

3 Peripheral operating requirements and behaviors

3.1 Core modules

3.1.1 SWD electricals

Table 29. SWD timing

Figure 6. Serial wire clock input timing Figure 7. Serial wire data timing

3.2 Clock modules

3.2.1 Reference oscillator specification

temperature, mechanical, and aging excursions. The table below shows typical specifications for the Crystal Oscillator. Table 30. Reference Crystal Specification Table continues on the next page...

Table 30. Reference Crystal Specification (continued)

applications

–50 — 50 ppm 5 Total reference oscillator tolerance for IEEE 802.15.4 applications –40 — 40 ppm 5 CL Load capacitance 6 8 10 pF 2,6 C0 Shunt capacitance 0.469 0.67 0.871 pF 2,6 Cm1 Motional capacitance 1.435 2.05 2.665 fF 2, 6 Lm1 Motional inductance 8.47 12.1 15.73 mH 2,6 Rm1 Motional resistance — 25 50 Ohms 2 ESR Equivalent series resistance — 50 60 Ohms 2, 7 Pd Maximum crystal drive — — 200 µW 2 TS Trim sensitivity 6.30 9.00 11.70 ppm/pF 2,6 TOSC Oscillator Startup Time — 500 — μs 8 1. Full temperature range of this device. A reduced range can be chosen to meet application needs. 2. Recommended crystal specification. 3. Combination of frequency stability variation over desired temperature range and frequency variation due to aging over desired lifetime of system. 4. Variation due to temperature, process, and aging of MCU. 5. Sum of crystal initial frequency tolerance, crystal frequency stability and aging, oscillator variation, and PCB manufacturing variation must not exceed this value. 6. Typical is target. 30 % tolerances shown. 7. ESR = Rm1 * (1 + [C0/CL])^2. 8. Time from oscillator enables to clock ready. Dependent on the complete hardware configuration of the oscillator. NXP Semiconductors Peripheral operating requirements and behaviors K32W14x Product Family, Rev. 3, 12/2022 Data Sheet: Technical Data General Business Information 33 / 90

Figure 8. Crystal Electrical Block Diagram Table 31. 32 kHz oscillator electrical specifications

  • Period jitter (RMS)
  • Accumulated jitter over 1 ms (RMS) ns ESR Crystal equivalent series resistance — — 80/150 kΩ 1 Cpara Parasitic capacitance of EXTAL32 and XTAL32 — 1 2 pF tstart Crystal start-up time — 1000 8000 ms 2 IOSC_32k Current consumption
  • OFF mode
  • ON mode 0.5 100 — nA Vpp Peak-to-peak amplitude of oscillation — 0.2 — V 3 Table continues on the next page... NXP Semiconductors Peripheral operating requirements and behaviors K32W14x Product Family, Rev. 3, 12/2022 Data Sheet: Technical Data General Business Information 34 / 90

Table 31. 32 kHz oscillator electrical specifications (continued)

  1. Maximum value is 80 kOhms for parasitic capacitances higher than 1 pF, and 150 kOhms for parasitic capacitances
  2. Proper PC board layout procedures must be followed to achieve specifications.
  3. When a crystal is being used with the 32 kHz oscillator, the EXTAL32 and XTAL32 pins should only be connected to

required oscillator components and must not be connected to any other devices.

  1. This specification is for an externally supplied clock driven to EXTAL32 and does not apply to any other clock input. The

oscillator remains enabled and XTAL32 must be left unconnected.

  1. The parameter specified is a peak-to-peak value and VIH and VIL specifications do not apply. The voltage of the applied

clock must be within the range of VSS to VDD_IO_D. It is recommended that the oscillator margin be measured on the actual application PCB with the target crystal.

3.2.3 Free-running oscillator FRO-192M specifications

Table 32. FRO-192M specifications

  • Open loop
  • Closed loop (using accurate clock source as reference) ±0.25 tstartup Start-up time
  • Oscillation time with initial accuracy of ±20 % to ±2 % of enable signal assertion
  • Oscillation time within ±2 % from enable signal assertion μs μs fos Frequency overshoot during startup — — 2 % jitper • Period jitter RMS 1
  • Accumulated jitter over 1 μs 375 ps jitcyc Cycle to Cycle jitter RMS — 60 — ps Ifro192m Current consumption — 40 100 μA 1. Reference clock = 192 MHz. NXP Semiconductors Peripheral operating requirements and behaviors K32W14x Product Family, Rev. 3, 12/2022 Data Sheet: Technical Data General Business Information 35 / 90

3.2.4 Free-running oscillator FRO-6M specifications

Table 33. FRO-6M specifications

  • open loop
  • closed loop (using accurate clock source as reference) ±0.6 tstartup Start-up time
  • Oscillation time with initial accuracy of -20 % to +2 % of enable signal assertion
  • Oscillation time within ± 2 % from enable signal assertion μs μs fos Frequency overshoot during startup — 10 — % Ifro6m Current consumption — — 4 μA

3.2.5 Free-running oscillator FRO-32K specifications

Table 34. FRO-32K specifications

  • open loop — — ±2 % TRIMstep Trimming step — 0.03 — % tstartup Start-up time — — 120 μs fos Frequency overshoot during startup
  • Trimmed — 10 — % Ifro32k Current consumption — 350 — nA

3.2.6 Free-running oscillator FRO-16K specifications

Table 35. FRO-16K specifications

  • Over –40 °C~125 °C temperature range — — ±6 % Table continues on the next page... NXP Semiconductors Peripheral operating requirements and behaviors K32W14x Product Family, Rev. 3, 12/2022 Data Sheet: Technical Data General Business Information 36 / 90

Table 35. FRO-16K specifications (continued)

  1. FRO-16K is in Power Switch block, which is powered by min 1.9 V VDD_SWITCH
  2. The Typical value (70 nA) of current consumption includes 20 nA POR current consumption in stable running period.

3.3 Memories and memory interfaces

3.3.1 Flash electrical specifications

This section describes the electrical characteristics of the flash memory module.

3.3.1.1 Flash Read wait state control specifications

and low-power modes. The following requirements must be met. Table 36. Recommend RWSC settings on K32W (for MCU flash and Radio Flash)

3.3.1.2 Flash timing specifications

a command is not included in the following table. Table 37. Flash command time specifications Table continues on the next page...

Table 37. Flash command time specifications (continued)

  1. Time to abort the command may significantly impact the time to execute the command.
  2. Measured from the time PERDY is cleared.

3.3.1.3 Flash high voltage current behavior

Table 38. Flash high voltage current behavior

  1. See the Power Management chapter in the reference manual for the specific VDD_IO_x voltage supply powering the flash

3.3.1.4 Flash reliability specifications

Table 39. Flash reliability specifications Table continues on the next page...

Table 39. Flash reliability specifications (continued)

100 K 500 K — cycles 3

  1. Typical data retention values are based on measured response accelerated at high temperature and derated to a constant
  2. Sector cycling endurance represents the number of Program/Erase cycles on a single sector at -40 °C ≤ Tj ≤ 125 °C.
  3. For devices with a single flash block, sectors must be located within the last 256 KB of the flash main memory. For devices

with two flash blocks, sectors must be located within the last 256 KB of each flash main memory.

3.4 Radio modules

Table 40. 2.4 GHz radio transceiver specifications

  1. Voltage required at this rail depends on the desired output power. See Transmit and PLL Feature Summary for the
  2. VPA_2P4GHZ is internally connected to the VDD_RF pin. When not powered externally, VPA_2P4GHZ = VDD_RF - 0.275

V. An internal regulator prevents VPA_2P4GHZ from going above 2.4 V when powered through the VDD_RF pin.

  1. Bluetooth LE. Other modes have different requirements

3.4.2 Receiver Feature Summary

Table 41. Top-level Receiver Specifications (TA = 25 °C, nominal process unless otherwise noted) Table continues on the next page...

Table 41. Top-level Receiver Specifications (TA = 25 °C, nominal process unless otherwise noted) (continued) offset (Wanted signal at –67 dBm, BER < 0.1 %. offset (Wanted signal at –67 dBm, BER < 0.1 %. Table continues on the next page...

offset (Wanted signal at –67 dBm, BER < 0.1 %. offset (Wanted signal at –67 dBm, BER < 0.1 %. offset (Wanted signal at –67 dBm, BER < 0.1 %. offset (Wanted signal at –67 dBm, BER < 0.1 %. offset (Wanted signal at –67 dBm, BER < 0.1 %. offset (Wanted signal at –67 dBm, BER < 0.1 %. offset (Wanted signal at –67 dBm, BER < 0.1 %. Table continues on the next page...

offset (Wanted signal at –67 dBm, BER < 0.1 %. ±10 MHz – Wanted signal at –67 dBm, BER < 0.1 %. MHz to 12750 MHz (Wanted signal at –67 dBm, BER < 0. offset (Wanted signal at –67 dBm, BER < 0.1 %. offset (Wanted signal at –67 dBm, BER < 0.1 %. offset (Wanted signal at –67 dBm, BER < 0.1 %. Table continues on the next page...

offset (Wanted signal at –67 dBm, BER < 0.1 %. at 3 dBm above sensitivity, PER 1 %).

23 MHz

Table continues on the next page...

1 GHz or 4 GHz < fc < 5 GHz or fc > 6 GHz (Wanted

signal 3 dB over reference sensitivity level, PER <1 %.

  1. All the RX parameters are measured at the RF pins.
  2. Transceiver power consumption.
  3. Variation across temperature (-40 °C to 105 °C) is up to 3 dB.
  4. Receiver noise Figure is computed from RF pin to composite (I+jQ) ADC output
  5. With RSSI_CTRL_0.RSSI_ADJ field calibrated to account for antenna to RF input losses.
  6. With one point calibration over frequency and temperature.
  7. Exceptions allowed for twice the reference clock frequency(fref) multiples.
  8. Measured at 0.1 % BER using 37 byte long packets in maximum gain mode and nominal conditions.
  9. Bluetooth LE adjacent and alternate selectivity performance is measured with modulated interference signals.
  10. Exceptions allowed for multiple of XTAL frequency
  11. Exceptions allowed for carrier frequency sub harmonics.
  12. Exceptions allowed for carrier frequency harmonics.
  13. Exception to the 10 MHz > freq offset ≤ 80 MHz out-of-band blocking limit allowed for frequency offsets of twice the

Table 42. Receiver Specifications with Generic FSK Modulations

  1. Selectivity measured with an unmodulated blocker.
  2. Variation across temperature (-40 °C to 105 °C) is up to 3 dB.

3.4.3 Transmit and PLL Feature Summary

  • Supports constant envelope modulation of 2.4 GHz ISM frequency band.
  • Fast PLL Lock time: < 25 µs
  • Reference Frequency: — 32 MHz crystals supported for Bluetooth LE and Generic FSK modes

Table 43. Top-level Transmitter Specifications (TA = 25 °C, nominal process unless otherwise noted) Table continues on the next page...

Table 43. Top-level Transmitter Specifications (TA = 25 °C, nominal process unless otherwise noted) (continued) Table continues on the next page...

30 MHz to 1 GHz, Peak detector, RBW=100 kHz — — — –60 dBm

1 GHz to 26 GHz, Peak detector, RBW = 1 MHz, based

  1. All the TX parameters are measured at test hardware SMA connector.
  2. Transceiver power consumption. NBU running at @16 MHz.
  3. To obtain current consumption at higher output power use the formula ITXndBm15.4=ITXndBm15.4+(ITXndBm-ITX0dBm) where n is
  4. Measured at RF pins, with VPA_2P4GHz ≥ 2.4 V.
  5. Variation across temperature (-40 °C to 105 °C) is up to 3 dB.
  6. Measured at the RF pins single supply configuration VDD_RF = VDD_LDO_CORE = 1.25V
  7. Maximum drift of carrier frequency of the PLL during a Bluetooth LE packet with a nominal 32 MHz reference crystal.
  8. Harmonic levels based on recommended 2 component match for TX output power ≤ 5 dBm. Transmit harmonic levels
  9. Measured at Pout > 5 dBm and recommended high-power TX match.
  10. Measured as per IEEE Standard 802.15.4
  11. Offset EVM is computed at one point per symbol, by combining the I value from the beginning of each symbol and the Q
  12. Measured at PRF, Max and recommended TX match.

Figure 9. TX Pout (dBm) as function TX-PA Power Code at RF pins Table 44. Transmit Output Power as a function of PA_POWER VPA_2P4GHZ = 1 V / 0 dBm output power target Table continues on the next page...

Figure 10. TX Pout (dBm) as function TX-PA Power Code at 7 dBm Table 45. Transmit Output Power as a function of PA_POWER VPA_2P4GHZ = 1.6 V / 7 dBm output power target Table continues on the next page...

Figure 11. TX Pout (dBm) as function TX-PA Power Code at 10 dBm Table 46. Transmit Output Power as a function of PA_POWER VPA_2P4GHZ = 2.2 V / 10 dBm output Table continues on the next page...

Table 46. Transmit Output Power as a function of PA_POWER VPA_2P4GHZ = 2.2 V / 10 dBm output (continued)

3.5 Analog

3.5.1 ADC electrical specifications

Table 47. 16-bit ADC operating conditions Table continues on the next page...

Table 47. 16-bit ADC operating conditions (continued)

  • Low-power mode (PWRSEL=00)
  • High-speed 16b mode (PWRSEL = 10)
  • High-speed 12b mode (PWRSEL = 10) MHz MHz MHz CADIN Input capacitance — 3.7 4.63 pF Cp Parasitic Cap of pad /package — 2 3 pF RAS Analog source resistance (external) — — 5 kΩ 6 RADIN • High-speed dedicated input channel (CH0:3) — VDD_ANA ≥ 1.71 V — VDD_ANA ≥ 2.1 V — VDD_ANA ≥ 2.5 V
  • Standard external input channel (Ch4:7) — VDD_ANA ≥ 1.71 V — VDD_ANA ≥ 2.1 V — VDD_ANA ≥ 2.5 V
  • Standard muxed input channel (Ch4:11) — VDD_ANA ≥ 1.71 V — VDD_ANA ≥ 2.1 V — VDD_ANA ≥ 2.5 V 0.95 0.95 0.95 1.35 1.35 1.35 1.65 1.65 1.65 1.7 1.6 1.4 3.25 2.15 1.75 7.25 3.05 2.35 kΩ 7,8 1. Typical values assume VDD_ANA= 3.0 V, Temp = 25 °C, fADCK = 24 MHz, unless otherwise stated. Typical values are for reference only, and are not tested in production. 2. DC potential difference. 3. For devices that do not have a dedicated VREFL and VSS_ANA pins, VREFL and VSS_ANA are tied to VSS internally. 4. If VREFH is less than VDD_ANA, then voltage inputs greater than VREFH but less than VDD_ANA are allowed but result in a full scale conversion result 5. ADC selected inputs and unselected dedicated inputs must not exceed VDD_ANA during an ADC conversion. Unselected muxed inputs may exceed VDD_ANA but must not exceed the IO supply associated with the inputs (VDD_IO_X) when a conversion is in progress. If an ADC input may exceed these levels, then a minimum of 1 K series resistance must be used between the source and the ADC input pin. 6. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as possible. 7. There are several types of ADC inputs. To see which channels correspond to which type of ADC inputs, see channel index map in reference manual 8. If the input come through a mux in the IO pad, add the IO Mux Resistance Adder value to the resistance for the channel type NXP Semiconductors Peripheral operating requirements and behaviors K32W14x Product Family, Rev. 3, 12/2022 Data Sheet: Technical Data General Business Information 54 / 90

Figure 12. ADC input impedance equivalency diagram Table 48. 16-bit ADC characteristics (VREFH = VDD_ANA, VREFL = VSS_ANA)

  • PWREN=0, Conversions triggered at 1 kS/s
  • PWREN=1, No Conversions
  • Low-power, single-ended mode, 6 MHz
  • Low-power, or dual-SE mode, 6 MHz
  • Low-power, single-ended mode, 24 MHz
  • Low-power, or dual-SE mode, 24 MHz
  • High-speed, single-ended mode, 48 MHz
  • High-speed, or dual-SE mode, 48 MHz 2.2 160 340 500 415 580 940 1500 215 440 640 530 750 1200 1950 μA μA μA μA μA μA μA μA ITS Temp Sensor Current Adder — 40 50 μA CSMP ADC Sample cycles 3.5 — 131.5 cycles 3 CCONV ADC conversion cycles 24 — 152 cycles CRATE ADC conversion rate — — 0.857 MS/s 4 Table continues on the next page... NXP Semiconductors Peripheral operating requirements and behaviors K32W14x Product Family, Rev. 3, 12/2022 Data Sheet: Technical Data General Business Information 55 / 90

Table 48. 16-bit ADC characteristics (VREFH = VDD_ANA, VREFL = VSS_ANA) (continued)

  • Low-power mode
  • High-speed mode (16-bits)
  • High-speed mode (12-bits) 3.16 TSMP_REQ Required Sample Time See equation — — ns 5 TAZ_REQ Required Auto-zero Time
  • Low-power mode
  • High-power mode (16-bits)
  • High-power mode (12-bits) 291.7 72.9 58.3 ns 5 TSMP Sample Time External inputs See equation — — ns 5 TSMP_INT Internal channel sample time 1.5 — — μs 6 DNL Differential non-linearity — ±0.7 +1.4/–0.95 LSB7 8 INL Integral non-linearity — ±2.0 +4.0/–2.0 LSB7 8 ZSE Zero-scale error (VADIN = VREFL) — ±1.0 ±2.0 LSB7 8 FSE Full-scale error (VADIN=V REFH) — ±2.0 +2.0/–8.0 LSB7 8 TUE Total unadjusted error — ±4.0 ±10.0 LSB7 8 ENOB Effective number of bits
  • Differential mode — 0.5 MS/s — 2 MS/s
  • Single-ended mode — 0.5 MS/s — 2 MS/s 12.7 12.0 12.4 11.5 13.5 12.7 13.1 12.2 bits 8,9 SINAD Signal-to-noise plus distortion
  • Differential mode — 0.5 MS/s — 2 MS/s
  • Single-ended mode — 0.5 MS/s — 2 MS/s dB 8,9 THD Total harmonic distortion 85 92 — dB 8,10 SFDR Spurious free dynamic range 86 94 — dB 8,10 Table continues on the next page... NXP Semiconductors Peripheral operating requirements and behaviors K32W14x Product Family, Rev. 3, 12/2022 Data Sheet: Technical Data General Business Information 56 / 90
  • T=–40 °C to 105 °C
  • T=–40 °C to 125 °C ±1.5 °C 13 1. Typical values assume VDD_ANA = 3.0 V, Temp = 25 °C, fADCK = 24 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 2. The ADC supply current depends on the ADC conversion clock speed, conversion rate and power mode. Typical value show is at 6 MHz, 24 MHz, and 48 MHz. For lowest power operation, PWRSEL should be set to 00. 3. Must meet minimum TSMP requirement. 4. Maximum conversion rate for high-speed mode is with FADCK = 48 MHz. Maximum conversion rate for low-power mode is FADCK = 24 MHz and 7.5 sample cycles (to meet the minimum auto-zero time requirement). 5. Required sample time is dictated by external components RAS, CAS, internal components RADIN, CADIN, CP, and desired sample accuracy in bits. Calculated it with formula: T SMP_REQ = B*IN(2)*[RAS*(CAS*CP)+ (RAS + R ADIN)* CADIN(typ). Required auto-zero time is for ADC comparator offset cancellation. The chosen sample time should be no less than maximum of the two: TSMP = max(TSMP_REQ,TAZ_REQ). 6. Internal channel inputs are those that do not come from external source (temperature sensor, bandgap). 7. 1 LSB = (VREFH - VREFL)/2N (N=14 bits), for 16-bit specifications, multiply by 4. 8. All accuracy numbers assume the ADC is calibrated with VREFH=VDD_ANA and using a high-speed dedicated input channel. 9. Dynamic results assume Fin = 1 kHz sinewave, AVGS = 0 for 2 MS/s, AVGS = 4 for 0.5 MS/s. 10. Dynamic results assume Fin = 1 kHz sinewave, no averaging. 11. Set the power up delay (PUDLY) according to the ADC start-up time if PWREN=0. 12. Ilkg = leakage current (Refer to pin leakage specification in the packaged device's voltage and current operating ratings). 13. The temperature sensor can be calibrated to a ± 0.5% precision after board assembly by using a 3 temperature calibration flow with accurate ± 0.15 % temperature chamber.

3.5.2 CMP and 8-bit DAC electrical specifications

Table 49. Comparator and 8-bit DAC electrical specifications

  • High-speed mode (EN=1, HPMD=1)
  • Normal mode (EN=1, HPMD=0, NPMD=0)
  • Nano mode (EN=1, HPMD=0, NPMD=1) 200 400 μA μA nA VAIN Analog input voltage VSS_ANA — VDD_ANA V 1 VAIO Analog input offset voltage
  • High-speed mode
  • Normal mode mV mV Table continues on the next page... NXP Semiconductors Peripheral operating requirements and behaviors K32W14x Product Family, Rev. 3, 12/2022 Data Sheet: Technical Data General Business Information 57 / 90

Table 49. Comparator and 8-bit DAC electrical specifications (continued)

  • Nano mode — — 40 mV VH Analog comparator hysteresis
  • CR0[HYSTCTR] = 00
  • CR0[HYSTCTR] = 01
  • CR0[HYSTCTR] = 10
  • CR0[HYSTCTR] = 11 mV mV mV mV tD Propagation delay
  • High-speed mode, 100 mV overdrive, power > 1.71 V
  • High-speed mode, 30 mV overdrive, power > 1.71 V
  • Normal mode, 30 mV overdrive, power > 1.71 V
  • Nano mode, 30 mV overdrive, power > 1.71 V 600 ns ns ns μs tinit Analog comparator initialization delay — — 40 μs 4 IDAC8b 8-bit DAC current adder (enabled)
  • High-power mode (EN=1, PMODE=1)
  • Low-power mode (EN=1, PMODE=0) μA μA INL 8-bit DAC integral non-linearity
  • Low/High power mode, supply power > 1.71 V –1.0 — +1.0 LSB 5 DNL 8-bit DAC differential non-linearity
  • Low/High power mode, power > 1.71 V –1.0 — +1.0 LSB 5 1. For devices that do not have a dedicated VSS_ANA pin, VSS_ANA is tied to VSS internally. 2. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD_ANA–0.6 V. 3. Overdrive does not include input offset voltage or hysteresis. 4. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to CMP_DACCR[DACEN], CMP_DACCR[VRSEL], CMP_DACCR[VOSEL], CMP_MUXCR[PSEL], and CMP_MUXCR[MSEL]), and the comparator output settling to a stable level. 5. 1 LSB = Vreference/256. Typical hysteresis NXP Semiconductors Peripheral operating requirements and behaviors K32W14x Product Family, Rev. 3, 12/2022 Data Sheet: Technical Data General Business Information 58 / 90

Figure 15. Typical hysteresis vs. Vin level (VDD = 3.3 V, HPMD = 0, NPMD = 1)

3.5.3 Voltage reference electrical specifications

Table 50. VREF operating requirements

  1. CL must be connected to VREFO if the VREFO functionality is being used for either an internal or external reference.

Table 51. VREF operating behaviors

1.0 V low-power reference voltage

Table continues on the next page...

Table 51. VREF operating behaviors (continued)

  1. See the chip's Reference Manual for the appropriate settings of the VREF Status and Control register.
  2. Vvrefo max is also ≤ VDD_ANA - 600 mV.
  3. Load regulation voltage is the difference between the VREFO voltage with no load vs. voltage with defined load.

3.6 Timers

See General switching specifications.

3.7 Communication interfaces

3.7.1 LPUART

See General switching specifications.

3.7.2 LPSPI switching specifications

of the transfer attributes are programmable. The following tables provide timing characteristics for classic SPI timing modes. Table 52. LPSPI master mode timing

  • LPSPI0
  • LPSPI1 MHz MHz LP2 SPSCK period 2 x tperiph 2048 x tperiph ns 2 LP3 Enable lead time 1/2 — tperiph 2 LP4 Enable lag time 1/2 — tperiph 2 LP5 Clock (SPSCK) high or low time tSPSCK/2 - 3 tSPSCK/2 ns — LP6 Data setup time (inputs) 8 — ns — LP7 Data hold time (inputs) 0 — ns — LP8 Data valid (after SPSCK edge) — 6 ns — LP9 Data hold time (outputs) 2 — ns — 1. The frequency of operation is also limited to a minimum of fperiph/2048 and a max of fperiph/2, where fperiph is the LPSPI peripheral functional clock. 2. tperiph = 1/fperiph. NXP Semiconductors Peripheral operating requirements and behaviors K32W14x Product Family, Rev. 3, 12/2022 Data Sheet: Technical Data General Business Information 61 / 90

Table 53. LPSPI slave mode timing (continued)

  1. The frequency of operation is also limited to a minimum of fperiph/2048 and a max of fperiph/4, where fperiph is the LPSPI

peripheral functional clock.

  1. Time to data active from high-impedance stat.
  2. Hold time to high-impedance state.

Figure 18. LPSPI slave mode timing (CPHA = 0)

Figure 19. LPSPI slave mode timing (CPHA = 1)

3.7.3 Inter-Integrated Circuit Interface (I2C) specifications

Table 54. I 2C timing Hold time (repeated) START condition.

  1. The master mode I2C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves
  1. A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the VIH(min) of the SCL

signal) to bridge the undefined region of the falling edge of SCL.

  1. The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal.
  2. Input signal Slew = 10 ns and Output Load = 50 pF
  3. Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty.
  4. A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement tSU; DAT ≥ 250 ns must

1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification) before the SCL line is released.

  1. Cb = total capacitance of the one bus line in pF.

Table 55. I 2C 1 Mbps timing period, the first clock pulse is generated.

  1. Cb = total capacitance of the one bus line in pF. The max Cb value is 50 pF.

Table 56. I2C HS mode timing1 first clock pulse is generated. Table continues on the next page...

Table 56. I2C HS mode timing1 (continued)

  1. Only PTB4/5, PTA18/19, PTC0/1, PTC4/5 pin can support Fast+ (3 MHz) mode.
  2. A device must internally provide a data hold time to bridge the undefined part between VIH and VIL of the falling edge of
  3. Cb = total capacitance of the one bus line in pF. The max Cb value is 50 pF.

Figure 20. Timing definition for devices on the I2C bus

3.7.4 Improved Inter-Integrated Circuit Interface (MIPI-I3C) specifications

Unless otherwise specified, MIPI-I3C specifications are timed to/from the VIH and/or VIL signal points. Table 57. MIPI-I3C specifications when communicating with legacy I2C devices Table continues on the next page...

Table 57. MIPI-I3C specifications when communicating with legacy I2C devices (continued)

  1. Cb = total capacitance of the one bus line in pF.

Table 58. MIPI-I3C open drain mode specifications

  • ENTAS0
  • ENTAS1
  • ENTAS2
  • ENTAS3 38.4 n 38.4 n 38.4 n 38.4 n 1 μ 100 μ 2 m 50 m s s s s tCBP Clock before STOP (P) condition tCAS(min)/2 — ns tMMOverlap Current master to secondary master overlap time during handoff tDIG_OD_L — ns tAVAL Bus available condition 1 — μs tIDLE Bus idle condition 1 — ms tMMLock Time internal where new master not driving SDA low tAVAL — μs 1. Cb = total capacitance of the one bus line in pF.

Table 59. MIPI-I3C push-pull specifications for SDR and HDR-DDR modes Table continues on the next page...

Table 59. MIPI-I3C push-pull specifications for SDR and HDR-DDR modes (continued)

  • Master mode
  • Slave mode tCR + 3 and tCF + 3 ns tSU_PP SDA signal setup 3 — — ns tCASr Clock after repeated START (Sr) tCAS (min) — — ns tCBSr Clock before repeated START (Sr) tCAS (min)/2 — — ns Cb Capacitive load per bus line — — 50 pF 1. When communicating with an I3C Device on a mixed Bus, the tDIG_H_MIXED period must be constrained in order to make sure that I2C devices do not interpret I3C signaling as valid I2C signaling. NXP Semiconductors Peripheral operating requirements and behaviors K32W14x Product Family, Rev. 3, 12/2022 Data Sheet: Technical Data General Business Information 68 / 90

0.3 X V DD

0.7 X V DD

Figure 21. I3C legacy mode timing Figure 22. tDIG_H and tDIG_L

Figure 23. Timing definition for devices on the I3C bus

3.8 Human Machine Interface (HMI) modules

3.8.1 General Purpose Input/Output (GPIO)

See General switching specifications.

3.8.2 Flexible IO controller (FlexIO)

Table 60. FlexIO Timing Specifications

  1. Assumes pins muxed on same VDD_IO domain with same load

4 Package dimensions

4.1 Obtaining package dimensions

Package dimensions are provided in package drawings. To find a package drawing, go to nxp.com and perform a keyword search for the drawing’s document number: If you want the drawing for this package Then use this document number 48-pin QFN SOT619-17(D)

5 Pinout

5.1 Pinout Table

48QFN Pin Name ALT0 ALT1 ALT2 ALT3 ALT4 ALT ALT6 ALT7 ALT8 ALT ALT1 ALT11 Wakeu p

2 PTB4 PTB4 LPS

PI1_ PCS LPUA RT1_ CTS_ b LPI2 C1_ SDA I3C0 _SD A TRG MUX0 _IN0 FLE XIO0 _D3 WUU0 _P15

3 PTB5 PTB5 LPS

PI1_ PCS LPUA RT1_ RTS_ b LPI2 C1_ SCL I3C0 _SC L TRG MUX0 _OUT FLE XIO0 _D3

4 VDD_IO_

VDD_I O_ABC

5 SWITCH

_WAKEU P_B SWITC H_WA KEUP_ B

6 VDD_SW

VDD_S WITCH

7 VOUT_S

VOUT_ SWITC H

8 PTA0 PTA0 CMP

0_O UT LPUA RT0_ CTS_ b RF_ GPO _11 TPM 0_C FLEXI O0_D SWD _DIO WUU0 _P0

9 PTA1 PTA1 CMP

1_O UT LPUA RT0_ RTS_ b RF_ GPO _10 TPM 0_C FLEXI O0_D SWD _CLK Table continues on the next page... NXP Semiconductors Package dimensions K32W14x Product Family, Rev. 3, 12/2022 Data Sheet: Technical Data General Business Information 71 / 90

Table continued from the previous page... 48QFN Pin Name ALT0 ALT1 ALT2 ALT3 ALT4 ALT ALT6 ALT7 ALT8 ALT ALT1 ALT11 Wakeu p

10 PTA4 ADC0_

CMP0_ IN0 PTA4 RF_G PO_9 TPM 0_CL KIN TRA CE_ SW O FLEXI O0_D BOO T_C ONFI G WUU0 _P2/ RF_XT AL_OU T_ENA BLE

11 PTA16 ADC0_

PI0_ PCS EWM 0_OU T_b LPI2 C0_ SCL S TPM 0_C LPUA RT0_ RX RF_ GPO FLE XIO0 _D5 RF_NO T_ALL OWED

12 PTA17 ADC0_

PI0_ SIN EWM 0_IN LPI2 C0_ SDA S TPM 0_C LPUA RT0_ TX RF_ GPO RF_G PO_8 FLE XIO0 _D6 RF_EX T_XTA L_REQ UEST/ RF_GP O_7 WUU0 _P3/ RF_NO T_ALL OWED

13 PTA18 CMP1_

PI0_ SOU T LPUA RT0_ CTS_ b LPI2 C0_ SDA TPM 0_C RF_G PO_0 LPUA RT0_ RX SPC0_ LPREQ

14 PTA19 CMP1_

PI0_ SCK LPUA RT0_ RTS_ b LPI2 C0_ SCL TPM 0_C RF_G PO_1 WUU0 _P4

15 VDD_LD

O_CORE VDD_L DO_C ORE

16 VDD_CO

VOUT_C ORE VDD_C ORE/ VOUT_ CORE

17 PTA20 ADC0_

CMP0_ IN3 PTA2 LPS PI0_ PCS LPUA RT0_ TX EW M0_I N TPM 0_C RF_G PO_2 FLEXI O0_D

18 PTA21 ADC0_

CMP0_ IN2 PTA2 LPS PI0_ PCS LPUA RT0_ RX EW M0_ OUT TPM 0_C RF_G PO_3 RF_ GPO FLEXI O0_D RF_ GPO _10 WUU0 _P5

19 VSS_DC

VSS_D CDC Table continues on the next page... NXP Semiconductors Pinout K32W14x Product Family, Rev. 3, 12/2022 Data Sheet: Technical Data General Business Information 72 / 90

Table continued from the previous page... 48QFN Pin Name ALT0 ALT1 ALT2 ALT3 ALT4 ALT ALT6 ALT7 ALT8 ALT ALT1 ALT11 Wakeu p

20 DCDC_L

X DCDC_ LX

21 VDD_IO_

VDD_DC DC VDD_I O_D/ VDD_D CDC

22 VOUT_S

VDD_SY S VOUT_ SYS/ VDD_S YS

23 PTD0 ADC0_

T_b

24 PTD1 ADC0_

0_LP REQ NMI_b RF_ GPO

25 PTD2 ADC0_

_ALT TAMP ER0 RF_ GPO

26 PTD3 ADC0_

_ALT TAMP ER1 RF_ GPO TRG MUX0 _IN2

27 PTD4 XTAL3

_ALT TAMP ER2

28 PTD5 EXTAL

_ALT

29 VDD_AN

A VDD_A NA

30 VREFO VREF

O

49 VREFL1 VREFL

31 XTAL_O

XTAL_ OUT

32 XTAL XTAL

33 EXTAL EXTAL

Table continues on the next page... NXP Semiconductors Pinout K32W14x Product Family, Rev. 3, 12/2022 Data Sheet: Technical Data General Business Information 73 / 90

Table continued from the previous page... 48QFN Pin Name ALT0 ALT1 ALT2 ALT3 ALT4 ALT ALT6 ALT7 ALT8 ALT ALT1 ALT11 Wakeu p

34 VDD_RF VDD_R

F

35 ANT_2P4

ANT_2 P4GHZ

36 VPA_2P4

VPA_2 P4GHZ

37 PTC0 PTC0 LPS

PI1_ PCS I3C0 _SD A TPM 1_C LPI2 C1_S CL FLE XIO0 _D1 WUU0 _P7

38 PTC1 PTC1 LPS

PI1_ PCS I3C0 _SC L TPM 1_C LPI2 C1_S DA FLE XIO0 _D1 WUU0 _P8

39 PTC2 PTC2 LPS

PI1_ SOU T LPUA RT1_ RX LPI2 C1_ SCL S TPM 1_C I3C0 _PU R FLE XIO0 _D1 WUU0 _P9

40 PTC3 PTC3 LPS

PI1_ SCK LPUA RT1_ TX LPI2 C1_ SDA S TPM 1_C FLE XIO0 _D1

41 VDD_CO

VDD_C ORE

42 PTC4 PTC4 LPS

PI1_ SIN LPI2 C1_ SCL TPM2 _CH0 FLE XIO0 _D2 WUU0 _P10

43 PTC5 PTC5 LPS

PI1_ PCS LPI2 C1_ SDA TPM 1_C TPM2 _CH1 FLE XIO0 _D2

44 PTC6 ADC0_

PI1_ PCS TPM 1_C FLE XIO0 _D2 WUU0 _P11

45 PTC7 DISAB

0_IN TRG MUX0 _OUT SFA 0_CL K TPM 1_C LKI N TPM2 _CLKI N CLK OUT FLE XIO0 _D2 WUU0 _P12/ NMI_b/ RF_NO T_ALL OWED Table continues on the next page... NXP Semiconductors Pinout K32W14x Product Family, Rev. 3, 12/2022 Data Sheet: Technical Data General Business Information 74 / 90

Table continued from the previous page...

46 PTB0 ADC0_

47 PTB1 ADC0_

48 PTB2 ADC0_

1 PTB3 ADC0_

49 VSS VSS

5.2 Recommended connection for unused analog and digital pins

Table 61. Recommended connection for unused interfaces also be disabled in software. also be disabled in software. regulator should also be disabled in software. tied to VSS through a 10 kΩ resistor. Table continues on the next page...

Table 61. Recommended connection for unused interfaces (continued) should also be disabled in software. Power VDD_SWITCH Must be powered Powers FRO16 and a portion of RAM. Table continues on the next page...

5.3 Pinouts diagram

a single pin. To determine what signals can be used on which pin, see the previous section. Figure 24. 48-pin QFN package pinout diagram

6 Ordering parts

6.1 Determining valid orderable parts

7 Part identification

Part numbers for the device have fields that identify the specific part. Use the values of these fields to determine the specific part.

7.1 Part number format

Table 62. Part number fields descriptions

  • B = Production Mask Set PT Packaging Type • R = Tape and Reel
  • T = Tray

7.2 Example

7.3 Package marking

Table 63. Package marking Table continues on the next page...

Table 63. Package marking (continued)

  • P = Production Mask Set

7.3.1 Package marking information

  • First line: aaaaaa
  • Second line: aaaaaa
  • Third line: mmmmm
  • Fourth line: xxxywwxx

Table 64. Package marking

8 Terminology and guidelines

8.1 Definitions

Table continues on the next page...

Table continued from the previous page... Term Definition

  • Operating ratings apply during operation of the chip.
  • Handling ratings apply when the chip is not powered. The likelihood of permanent chip failure increases rapidly as soon as a characteristic begins to exceed one of its operating ratings. NOTE Operating requirement A specified value or range of values for a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useful life of the chip Operating behavior A specified value or range of values for a technical characteristic that are guaranteed during operation if you meet the operating requirements and any other specified conditions Typical value A specified value for a technical characteristic that:
  • Lies within the range of values specified by the operating behavior
  • Is representative of that characteristic during operation when you meet the typical-value conditions or other specified conditions Typical values are provided as design guidelines and are neither tested nor guaranteed. NOTE

8.2 Examples

Operating rating: Operating requirement: Operating behavior that includes a typical value: EXAMPLE EXAMPLEEXAMPLE EXAMPLE NXP Semiconductors Terminology and guidelines K32W14x Product Family, Rev. 3, 12/2022 Data Sheet: Technical Data General Business Information 80 / 90

8.3 Typical-value conditions

8.4 Relationship between ratings and operating requirements

8.5 Guidelines for ratings and operating requirements

  • Never exceed any of the chip’s ratings.
  • During normal operation, don’t exceed any of the chip’s operating requirements.
  • If you must exceed an operating requirement at times other than during normal operation (for example, during power sequencing), limit the duration as much as possible.

9 Abbreviations and Acronyms

The following table provides the list of abbreviations and acronyms their definitions. Table 65. Abbreviations and Acronyms and their definition Table continues on the next page...

Table 65. Abbreviations and Acronyms and their definition (continued) Table continues on the next page...

The following table provides a revision history for this document. Table 66. Revision History

0 Aug 2021 Initial release

1 Sept 2021 • Editorial updates

  • Updated the Front Matter Content
  • Updated the part number to K32W1480VFTAT to add 'T' for Tray
  • Updated the EdgeLock Secure Enclave in K32W1480 block diagram
  • Removed the bullet of 0 to 40 °C in Δffro16K in Free-running oscillator FRO-16K specifications
  • Updated the maximum values of Flash timing specifications
  • Updated the Voltage and current operating requirements table
  • Updated the typical value of VLVDV_HYS_IO_ABC and VHVD_HYS_SYS in HVD, LVD, and POR operating requirements
  • Updated the typical values of VDD_CORE supply HVD and LVD Operating Ratings table in HVD, LVD, and POR operating requirements
  • Updated tPOR in Power mode transition operating behaviors table
  • Updated the description and values of VDD_IO_D in LDO_SYS electrical specifications Table continues on the next page... NXP Semiconductors

Revision history

K32W14x Product Family, Rev. 3, 12/2022 Data Sheet: Technical Data General Business Information 83 / 90

Table 66. Revision History (continued)

  • Updated the description of I2C/I3C/I/O pins in General switching specifications
  • Updated Voltage and current operating behaviors table
  • Added Typical hysteresis vs. Vin level (VDD = 3.3 V, HPMD = 1) chart, Typical hysteresis vs. Vin level (VDD = 3.3 V, HPMD = 0, NPMD = 1), and Typical hysteresis vs. Vin level (VDD = 3.3 V, HPMD = 0, NPMD = 0) in CMP and 8-bit DAC electrical specifications
  • Updated maximum value of CL in VREF operating requirements and values of Vdev in Voltage reference electrical specifications
  • Updated VDD_ANA symbol to VDD_IO_ABC and the maximum value of VREFH to VDD_IO_ABC in CMP and 8-bit DAC electrical specifications
  • Removed the references of NVM and ATx in pinout table Pinout Table
  • Updated Transmit and PLL Feature Summary and Receiver Feature Summary
  • Removed the references of SUOX and SOX from 32 kHz oscillator electrical specifications
  • Updated Power Consumption Operating Behaviors table

2 Dec 2021 • Updated the values under low-power consumption section in Front Matter Content

  • Updated Front Matter
  • Editorial updates
  • Added SIM_SDID value in Device Revision table
  • Updated the values of IICIO, and added another footnote to IICIO in Table 9
  • Updated the first footnote in Table 14
  • Updated the maximum value of ILOAD at Normal drive mode in Table 15
  • Updated ILOAD parameter in Table 16
  • Updated Table 20
  • Updated the values of Jitosc and vec_extal32 in Table 31
  • Added typical values to all parameters in Table 39
  • Added new parameter VPA_2P4GHz in Table 40
  • Updated the values amd added footnotes in Table 41
  • Updated Table 42
  • Updated the values of fADCK and RADIN in Table 47
  • Updated Table 48
  • Updated Table 49
  • Updated typical and maximum value of Vacc in Table 51
  • Added maximum value of fSCL and minimum value of tSU_PP in Table 59
  • Added Abbreviations and Acronyms Table continues on the next page... NXP Semiconductors

K32W14x Product Family, Rev. 3, 12/2022 Data Sheet: Technical Data General Business Information 84 / 90

  • Updated Table 43
  • Removed NVM_SDO and RF_UART signals from Pinout Table
  • Updated Table 30

3 Dec 2022 • Updated Front Matter Content

  • Added SoC Power Consumption
  • Updated minimum and maximum value of Electrostatic discharge voltage, charged- device model (antenna pin) in ESD and Latch-Up Ratings to -250 V and +250 V
  • Updated complete ESD and Latch-Up Ratings
  • Updated the minimum Target VDD_CORE in Table 11 to 1.05 V
  • Updated Bluetooth LE 5.2 to Bluetooth LE 5.3 all over the document
  • Updated the ambient temperature from 120 °C to 105 °C all over the document
  • Updated the SIM_SDID in Device Revision Number table
  • Updated ARM to Arm in block diagram
  • Update the minimum value of VDD_CORE and VDD_LDO_CORE in Voltage and current operating requirements
  • Updated the values of VOUT_DCDC in Table 14
  • Removed VswitchWakeup and tswitchWakeup from Smart power switch
  • Removed the maximum value of SELBLE1M, 4+ MHz in Table 41
  • Removed 26 MHz from Reference frequency bullet in Transmit and PLL Feature Summary
  • Updated the values in Power Consumption Operating Behaviors
  • Updated the maximum value of IEEE 802.15.4 Error Vector Magnitude in Table 43 from 4 % to 5 %
  • Updated Table 62
  • Updated Package marking
  • Updated First Line of Package marking information from aaaaaaa to aaaaaa
  • Updated the minimum value and maximum value of VOUT_CORE for low drive strength in LDO_CORE electrical specifications
  • Updated the values of tPWDN and tDPWDN and removed tPOR and tPORFAST in Power mode transition operating behaviors
  • Updated Table 23 to show IDD values of 25 °C only
  • Added the values to Typical power-down mode RAM current adders
  • Updated Reference oscillator specification
  • Updated typical value of fref in 2.4 GHz radio transceiver electrical specification to show

32 MHz only

Table continues on the next page... K32W14x Product Family, Rev. 3, 12/2022 Data Sheet: Technical Data General Business Information 85 / 90

  • Added footnotes to Table 41 and Transmit and PLL Feature Summary
  • Removed the second footnote in Table 42
  • Updated the "K32W1480VFTAT" and "K32W1480VFTAR" to "K32W1480VFTBT" and "K32W1480VFTBR" respectively all over the document
  • Updated the frequency from 48 MHz to 64 MHz in "Dedicated CM3 core running at up to 48MHz" in front matter NXP Semiconductors

K32W14x Product Family, Rev. 3, 12/2022 Data Sheet: Technical Data General Business Information 86 / 90

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Please be aware that important notices concerning this document and the product(s) described herein, have been included in section 'Legal information'. © NXP B.V. 2022. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 12/2022 Document identifier: K32W1480