K32L2B11VFT0A

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Technical content

48 MHz Arm® Cortex®-M0+ and 64/128/256 KB Flash

The K32 L2B series is optimized for cost-sensitive and battery- powered applications requiring low-power USB connectivity and an optional segment LCD (SLCD). The product offers:

• Optional low power segment LCD up to 24x8 or 28x4
• USB FS 2.0 device without requiring an external crystal
• Embedded ROM with boot loader for flexible program upgrade
• High accuracy internal voltage and clock reference
• FlexIO to support any standard and customized serial peripheral emulation
• Down to 54 uA/MHz in very low power run mode and 1.96 uA in deep sleep mode (RAM + RTC retained) Core Processor
• Arm ® Cortex®-M0+ core up to 48 MHz Memories
• 64/128/256 KB program flash memory
• 32 KB SRAM
• 16 KB ROM with build-in bootloader
• 32-byte backup register System
• 4-channel asynchronous DMA controller
• Watchdog
• Low-leakage wakeup unit
• Two-pin Serial Wire Debug (SWD) programming and debug interface
• Micro Trace Buffer
• Bit manipulation engine
• Interrupt controller Clocks
• 48 MHz high accuracy (up to 0.5%) internal reference clock
• 8 MHz/2 MHz high accuracy (up to 3%) internal reference clock
• 1 KHz reference clock active under all low-power modes (except VLLS0)
• 32–40 KHz and 3–32 MHz crystal oscillator Peripherals
• SLCD supporting up to 24x8 or 28x4 segments
• USB full-speed 2.0 device controller supporting crystal-less operation
• One UART module supporting ISO7816, operating up to 1.5 Mbit/s
• Two low-power UART modules supporting asynchronous operation in low-power modes
• Two I2C modules and I2C0 supporting up to 1 Mbit/s
• Two 16-bit SPI modules supporting up to 24 Mbit/s
• One FlexIO module supporting emulation of additional UART, SPI, I2C, PWM and other serial modules, etc.
• One 16-bit 461 ksps ADC module with high accuracy internal voltage reference (Vref) and up to 16 channels
• High-speed analog comparator containing a 6-bit DAC for programmable reference input
• One 12-bit DAC
• 1.2 V internal voltage reference I/O
• Up to 50 general-purpose input/output pins (GPIO) and 6 high-drive pad K32L2B31Vxx0A K32L2B21Vxx0A K32L2B11Vxx0A

32 QFN

5x5 mm P 0.5 mm

48 QFN

7x7 mm P 0.5 mm

64 LQFP

10x10 mm P 0.5 mm

64 BGA

5x5 mm P 0.5 mm NXP Semiconductors K32L2B3x Data Sheet: Technical Data Rev. 3, 09/2020 NXP reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products.

• Voltage range: 1.71 to 3.6 V
• Flash write voltage range: 1.71 to 3.6 V
• Temperature range: –40 to 105 °C Packages
• 64 LQFP 10mm x 10mm, 0.5 mm pitch, 1.6 mm thickness
• 64 MAPBGA 5mm x 5mm, 0.5 mm pitch, 1.23 mm thickness
• 48 QFN 7mm x 7mm, 0.5 mm pitch, 0.65 mm thickness
• 32 QFN 5mm x 5mm, 0.5 mm pitch, 0.65 mm thickness Low Power
• Down to 54 μA/MHz in very low power run mode
• Down to 1.96 μA in VLLS3 mode (RAM + RTC retained)
• Six flexible static modes Timers
• One 6-channel Timer/PWM module
• Two 2-channel Timer/PWM modules
• One low-power timer
• Periodic interrupt timer
• Real time clock Security and Integrity
• 80-bit unique identification number per chip
• Advanced flash security Related Resources Type Description Resource Selector Guide The NXP Selector Guide is a web-based tool that features interactive application wizards and a dynamic product selector. Selector Guide Reference Manual The Reference Manual contains a comprehensive description of the structure and function (operation) of a device. K32L2B3xRM1 Data Sheet The Data Sheet includes electrical characteristics and signal connections. This document. Chip Errata The chip mask set Errata provides additional or corrective information for a particular device mask set. K32L2B_1N71K1 Package drawing Package dimensions are provided in package drawings. 64-LQFP: 98ASS23234W, 64- MAPBGA: 98ASA00420D, 32- QFN: 98ASA00615D, 48-QFN: 98ASA00616D1 1. To find the associated resource, go to http://www.nxp.com and perform a search using this term. 2 K32 L2B Microcontroller, Rev. 3, 09/2020 NXP Semiconductors

4.1 K32 L2B Signal Multiplexing and Pin Assignments

4.2 K32 L2B Signal Multiplexing and Pin Assignments

K32 L2B Microcontroller, Rev. 3, 09/2020 3 NXP Semiconductors

1 Ordering information

The following chips are available for ordering. Table 1. Ordering information

1. INT: interrupt pin numbers; HD: high drive pin numbers

2 Overview

Ordering information

4 K32 L2B Microcontroller, Rev. 3, 09/2020 NXP Semiconductors

32 KB RAM

16 KB ROM

Figure 1. System diagram The crossbar switch connects bus masters and slaves using a crossbar switch structure.

2.1 System features

The following sections describe the high-level system features.

2.1.1 Arm Cortex-M0+ core

targeting microcontroller cores focused on very cost sensitive, low power applications. is upward compatible with other Cortex-M profile processors.

2.1.2 NVIC

also differs in number of interrupt sources and supports 32 interrupt vectors.

2.1.3 AWIC

Table 2. AWIC stop wake-up sources Table continues on the next page...

Table 2. AWIC stop wake-up sources (continued)

2.1.4 Memory

• 32 KB of embedded RAM accessible (read/write) at CPU clock speed with 0 wait states.
• The non-volatile memory is divided into two arrays
• Up to 256 KB of embedded program memory
• 16 KB ROM (built-in bootloader to support UART, I2C, USB, and SPI interfaces) The program flash memory contains a 16-byte flash configuration field that stores default protection settings and security information. The page size of program flash is 1 KB. The protection setting can protect 32 regions of the program flash memory from unintended erase or program operations. The security circuitry prevents unauthorized access to RAM or flash contents from debug port.
• System register file This device contains a 32-byte register file that is powered in all power modes. Also, it retains contents during low power modes and is reset only during a power-on reset. Overview K32 L2B Microcontroller, Rev. 3, 09/2020 7 NXP Semiconductors

2.1.5 Reset and boot

The following table lists all the reset sources supported by this device. Table 3. Reset source

1. Except PMC_LVDSC1[LVDV] and PMC_LVDSC2[LVWV]
2. Only if RESET is used to wake from VLLS mode.
3. Except SMC_PMCTRL, SMC_STOPCTRL, SMC_PMSTAT
4. Except RCM_RPFC, RCM_RPFW, RCM_FM

• internal flash
• ROM Overview 8 K32 L2B Microcontroller, Rev. 3, 09/2020 NXP Semiconductors

field. Below is boot flow chart for this device. Figure 2. Boot flow chart address, otherwise, it remaps to flash address.

2.1.6 Clock options

provide the required performance and optimize the power consumption. in full speed mode to achieve the required accuracy. system clock on reset. The LIRC oscillator cannot be used in any VLLS modes. The LPO generates a 1 kHz clock and cannot be used in VLLS0 mode.

kHz) on the RTC_CLKIN pin for use with the RTC. For more details on the clock operations and configurations, see Reference Manual. The following figure is a high level block diagram of the clock generation. Figure 3. Clock block diagram during operation in various operational modes. The following table summarizes the clocks associated with each module. Table 4. Module clocks Table continues on the next page...

Table 4. Module clocks (continued) Table continues on the next page...

2.1.7 Security

flash information via ROM boot loader commands. factory and loaded to SIM register after power-on reset.

2.1.8 Power management

power versus performance requirements of the application can be selected. analog, logic, and memory can be retained or disabled to conserve power. NVIC, AWIC, or the LLWU, please refer to the Reference Manual. Table 6. Peripherals states in different operational modes Run mode Run In Run mode, all device modules are operational. except the Low Voltage Detect (LVD) monitor, which is disabled. frequency except the Low Voltage Detect (LVD) monitor, which is disabled. The MCU core is placed into Sleep mode. Table continues on the next page...

Table 6. Peripherals states in different operational modes (continued) be used to wake up from an interrupt. SPI, TPM, UART, USB, and COP are static, but retain their programming. drive their previous values. RTC are operational in all VLLS modes. VREF are not operational but continue driving. operational but continue driving. POR detection circuit can be enabled or disabled.

2.1.9 LLWU

continues to detect wake-up events until the user has acknowledged the wake-up event.

Table 7. Wakeup source

2.1.10 Debug controller

2 breakpoints and 2 watchpoints. simple execution trace capability for the Cortex-M0+ processor.

2.1.11 COP

can run from bus clock, LPO, 8/2 MHz internal oscillator or external crystal oscillator. Optional window mode can detect deviations in program flow or system frequency.

• Support multiple clock input, 1 kHz clock(LPO), bus clock, 8/2 MHz internal reference clock, external crystal oscillator
• Can work in Stop/VLPS and Debug mode Overview K32 L2B Microcontroller, Rev. 3, 09/2020 15 NXP Semiconductors

• Configurable for short and long timeout values, the longest timeout is up to 262 seconds
• Support window mode

2.2 Peripheral features

The following sections describe the features of each peripherals of the chip.

2.2.1 Segment LCD (SLCD)

The SLCD module is a CMOS charge pump voltage inverter that is designed for low- voltage and low-power operation. SLCD is designed to generate the appropriate waveforms to drive multiplexed numeric, alphanumeric, or custom segment LCD panels. SLCD also has several timing and control settings that can be software configured depending on the application's requirements. Timing and control consists of registers and control logic for:

• LCD frame frequency
• Duty cycle selection
• Front plane/back plane selection and enabling
• Blink modes and frequency
• Operation in low-power modes

2.2.2 BME

The Bit Manipulation Engine (BME) provides hardware support for atomic read- modify-write memory operations to the peripheral address space in Cortex-M0+ based microcontrollers. It reduces up to 30% of the code size and up to 9% of the cycles for bit-oriented operations to peripheral registers. The BME supports unsigned bit field extract, load-and-set 1-bit, load-and-clear 1-bit, bit field insert, logical AND/OR/XOR operations with byte, halfword or word-sized data type. Overview 16 K32 L2B Microcontroller, Rev. 3, 09/2020 NXP Semiconductors

2.2.3 DMA and DMAMUX

The DMA controller module enables fast transfers of data, which provides an efficient way to move blocks of data with minimal processor interaction. The DMA controller in this device implements four channels which can be routed from up to 63 DMA request sources through DMA MUX module. Some of the peripheral request sources have asynchronous DMA capability which can be used to wake MCU from Stop mode. The peripherals which have such capability include . The DMA channel 0 and 1 can be periodically triggered by PIT via DMA MUX. Main features are listed below:

• Dual-address transfers via 32-bit master connection to the system bus and data transfers in 8-, 16-, or 32-bit blocks
• Supports programmable source and destination address and transfer size, optional modulo addressing from 16 bytes to 256 KB
• Automatic updates of source and destination addresses
• Auto-alignment feature for source or destination accesses allows block transfers to occur at the optimal size based on the address, byte count,and programmed size, which significantly improves the speed of block transfer
• Automatic single or double channel linking allows the current DMA channel to automatically trigger a DMA request to the linked channels without CPU intervention For more information on asynchronous DMA, see AN4631.

2.2.4 TPM

This device contains three low power TPM modules (TPM). All TPM modules are functional in Stop/VLPS mode if the clock source is enabled. The TPM features include:

• TPM clock mode is selectable from external clock input, internal clock source, external crystal input clock, MCGIRCLK clock or clocking from MCGFLLCLK and MCGPLLCLK/2
• Prescaler divide-by 1, 2, 4, 8, 16, 32, 64, or 128
• TPM includes a 16-bit counter
• Includes 6 channels that can be configured for input capture, output compare, edge-aligned PWM mode, or center-aligned PWM mode
• Support the generation of an interrupt and/or DMA request per channel or counter overflow Overview K32 L2B Microcontroller, Rev. 3, 09/2020 17 NXP Semiconductors

• Support selectable trigger input to optionally reset or cause the counter to start or stop incrementing
• Support the generation of hardware triggers when the counter overflows and per channel

2.2.5 ADC

This device contains one ADC module. This ADC module supports hardware triggers from TPM, LPTMR, PIT, RTC, external trigger pin and CMP output. It supports wakeup of MCU in low power mode when using internal clock source or external crystal clock. ADC module has the following features:

• Linear successive approximation algorithm with up to 16-bit resolution
• Up to four pairs of differential and 17 single-ended external analog inputs
• Support selectable 16-bit, 13-bit, 11-bit, and 9-bit differential output mode, or 16- bit, 12-bit, 10-bit, and 8-bit single-ended output modes
• Single or continuous conversion
• Configurable sample time and conversion speed/power
• Selectable clock source up to four
• Operation in low-power modes for lower noise
• Asynchronous clock source for lower noise operation with option to output the clock
• Selectable hardware conversion trigger
• Automatic compare with interrupt for less-than, greater-than or equal-to, within range, or out-of-range, programmable value
• Temperature sensor
• Hardware average function up to 32x
• Selectable voltage reference: external or alternate
• Self-calibration mode

2.2.5.1 Temperature sensor

This device integrates one temperature sensor internally connected to the input channel of AD26, see for details of the linearity factor. The sensor provides good linearity, but it has to be calibrated to gain good accuracy, see also AN3031. We recommend to use internal reference voltage as ADC reference with long sample time. Overview 18 K32 L2B Microcontroller, Rev. 3, 09/2020 NXP Semiconductors

2.2.6 VREF

The Voltage Reference (VREF) can supply an accurate voltage output (1.2V typically) trimmed in 0.5 mV steps. It can be used in applications to provide a reference voltage to external devices or used internally as a reference to analog peripherals such as the ADC or CMP. The VREF supports the following programmable buffer modes:

• Bandgap on only, used for stabilization and startup
• High power buffer mode
• Low-power buffer mode
• Buffer disabled The VREF voltage output signal, bonded on VREFH for 48 QFN, 64 LQFP and 64 MAPBGA packages and on PTE30 for 32 QFN packages, can be used by both internal and external peripherals in low and high power buffer mode. A 100 nF capacitor must always be connected between this pin and VSSA if the VREF is used. This capacitor must be as close to VREF_OUT pin as possible.

2.2.7 CMP

The device contains one high-speed comparator and two 8-input multiplexers for both the inverting and non-inverting inputs of the comparator. Each CMP input channel connects to both muxes. The CMP includes one 6-bit DAC, which provides a selectable voltage reference for various user application cases. Besides, the CMP also has several module-to-module interconnects in order to facilitate ADC triggering, TPM triggering, and interfaces. The CMP has the following features:

• Inputs may range from rail to rail
• Programmable hysteresis control
• Selectable interrupt on rising-edge, falling-edge, or both rising or falling edges of the comparator output
• Selectable inversion on comparator output
• Capability to produce a wide range of outputs such as sampled, digitally filtered
• External hysteresis can be used at the same time that the output filter is used for internal functions
• Two software selectable performance levels: shorter propagation delay at the expense of higher power and Low power with longer propagation delay Overview K32 L2B Microcontroller, Rev. 3, 09/2020 19 NXP Semiconductors

• DMA transfer support
• Functional in all modes of operation except in VLLS0 mode
• The filter functions are not available in Stop, VLPS, LLS, or VLLSx modes
• Integrated 6-bit DAC with selectable supply reference source and can be power down to conserve power
• Two 8-to-1 channel mux

2.2.8 DAC

The 12-bit Digital-to-Analog Converter (DAC) is a low-power, general-purpose DAC. The output of the DAC can be placed on an external pin or set as one of the inputs to the analog comparator, op-amps, or ADC. The features of the DAC module include:

• On-chip programmable reference generator output. The voltage output range is from 1⁄4096 Vin to Vin, and the step is 1⁄4096 Vin, where Vin is the input voltage.
• Vin can be selected from two reference sources.
• Static operation in Normal Stop mode.
• 2-word data buffer supported with multiple operation modes.
• DMA support.

2.2.9 RTC

The RTC is an always powered-on block that remains active in all low power modes. The time counter within the RTC is clocked by a 32.768 kHz clock sourced from an external crystal using the oscillator or clock directly from RTC_CLKIN pin. RTC is reset on power-on reset, and a software reset bit in RTC can also initialize all RTC registers. The RTC module has the following features

• 32-bit seconds counter with roll-over protection and 32-bit alarm
• 16-bit prescaler with compensation that can correct errors between 0.12 ppm and 3906 ppm
• Register write protection with register lock mechanism
• 1 Hz square wave or second pulse output with optional interrupt Overview 20 K32 L2B Microcontroller, Rev. 3, 09/2020 NXP Semiconductors

2.2.10 PIT

The Periodic Interrupt Timer (PIT) is used to generate periodic interrupt to the CPU. It has two independent channels and each channel has a 32-bit counter. Both channels can be chained together to form a 64-bit counter. Channel 0 can be used to periodically trigger DMA channel 0, and channel 1 can be used to periodically trigger DMA channel 1. Either channel can be programmed as an ADC trigger source, or TPM trigger source. Channel 0 can be programmed to trigger DAC. The PIT module has the following features:

• Each 32-bit timers is able to generate DMA trigger
• Each 32-bit timers is able to generate timeout interrupts
• Two timers can be cascaded to form a 64-bit timer
• Each timer can be programmed as ADC/TPM trigger source
• Timer 0 is able to trigger DAC

2.2.11 LPTMR

The low-power timer (LPTMR) can be configured to operate as a time counter with optional prescaler, or as a pulse counter with optional glitch filter, across all power modes, including the low-leakage modes. It can also continue operating through most system reset events, allowing it to be used as a time of day counter. The LPTMR module has the following features:

• 16-bit time counter or pulse counter with compare
• Optional interrupt can generate asynchronous wakeup from any low-power mode
• Hardware trigger output
• Counter supports free-running mode or reset on compare
• Configurable clock source for prescaler/glitch filter
• Configurable input source for pulse counter

2.2.12 UART

This device contains a basic universal asynchronous receiver/transmitter (UART) module with DMA function supported. Generally, this module is used in RS-232, RS-485, and other communications. It also supports LIN slave operation and ISO7816. Overview K32 L2B Microcontroller, Rev. 3, 09/2020 21 NXP Semiconductors

The UART module has the following features:

• Full-duplex operation
• 13-bit baud rate selection with /32 fractional divide, based on the module clock frequency
• Programmable 8-bit or 9-bit data format
• Programmable transmitter output polarity
• Programmable receive input polarity
• Up to 14-bit break character transmission.
• 11-bit break character detection option
• Two receiver wakeup methods with idle line or address mark wakeup
• Address match feature in the receiver to reduce address mark wakeup ISR overhead
• Ability to select MSB or LSB to be the first bit on wire
• Support for ISO 7816 protocol to interface with SIM cards and smart cards
• Receiver framing error detection
• Hardware parity generation and checking
• 1/16 bit-time noise detection
• DMA interface

2.2.13 LPUART

This product contains two Low-Power UART modules, both of their clock sources are selectable from IRC48M, IRC8M/2M or external crystal clock, and can work in Stop and VLPS modes. They also support 4x to 32x data oversampling rate to meet different applications. The LPUART module has the following features:

• Programmable baud rates (13-bit modulo divider) with configurable oversampling ratio from 4x to 32x
• Transmit and receive baud rate can operate asynchronous to the bus clock and can be configured independently of the bus clock frequency, support operation in Stop mode
• Interrupt, DMA or polled operation
• Hardware parity generation and checking
• Programmable 8-bit, 9-bit or 10-bit character length
• Programmable 1-bit or 2-bit stop bits
• Three receiver wakeup methods
• Idle line wakeup
• Address mark wakeup
• Receive data match
• Automatic address matching to reduce ISR overhead: Overview 22 K32 L2B Microcontroller, Rev. 3, 09/2020 NXP Semiconductors

• Address mark matching
• Idle line address matching
• Address match start, address match end
• Optional 13-bit break character generation / 11-bit break character detection
• Configurable idle length detection supporting 1, 2, 4, 8, 16, 32, 64 or 128 idle characters
• Selectable transmitter output and receiver input polarity

2.2.14 SPI

This device contains two SPI modules. SPI modules support 8-bit and 16-bit modes. FIFO function is available only on SPI1 module. The SPI modules have the following features:

• Full-duplex or single-wire bidirectional mode
• Programmable transmit bit rate
• Double-buffered transmit and receive data register
• Serial clock phase and polarity options
• Slave select output
• Mode fault error flag with CPU interrupt capability
• Control of SPI operation during wait mode
• Selectable MSB-first or LSB-first shifting
• Programmable 8- or 16-bit data transmission length
• Receive data buffer hardware match feature
• 64-bit FIFO mode for high speed/large amounts of data transfers
• Support DMA

2.2.15 I2C

This device contains two I2C modules, which support up to 1 Mbits/s by dual buffer features, and address match to wake MCU from the low power mode. I2C modules support DMA transfer, and the interrupt condition can trigger DMA request when DMA function is enabled. The I2C modules have the following features:

• Support for system management bus (SMBus) specification, version 2
• Software programmable for one of 64 different serial clock frequencies
• Software-selectable acknowledge bit
• Arbitration-lost interrupt with automatic mode switching from master to slave Overview K32 L2B Microcontroller, Rev. 3, 09/2020 23 NXP Semiconductors

• Calling address identification interrupt
• START and STOP signal generation and detection
• Repeated-START signal generation and detection
• Acknowledge bit generation and detection
• Bus busy detection
• General call recognition
• 10-bit address extension
• Programmable input glitch filter
• Low power mode wakeup on slave address match
• Range slave address support
• DMA support
• Double buffering support to achieve higher baud rate

2.2.16 USB

This device contains one USB module which implements a USB2.0 full-speed compliant peripheral and interfaces to the on-chip USBFS transceiver. It implements keep-alive feature to avoid re-enumerating when exiting from low power modes and enables HIRC48M to allow crystal-less USB operation. The USBFS has the following features:

• USB 1.1 and 2.0 compliant full-speed device controller
• 16 bidirectional end points
• DMA or FIFO data stream interfaces
• Low-power consumption
• HIRC48 with clock-recovery is supported to eliminate the 48 MHz crystal. It is used for USB device-only implementation.
• USB keeps alive in low power mode down to VLPS and is able to wake MCU from low power mode

2.2.17 FlexIO

The FlexIO is a highly configurable module providing a wide range of protocols including, but not limited to UART, I2C, SPI, Camera IF, LCD RGB, PWM/Waveform generation. The module supports programmable baud rates independent of bus clock frequency, with automatic start/stop bit generation. The FlexIO module has the following features: Overview 24 K32 L2B Microcontroller, Rev. 3, 09/2020 NXP Semiconductors

• Functional in VLPR/VLPW/Stop/VLPS mode provided the clock it is using remains enabled
• Four 32-bit double buffered shift registers with transmit, receive, and data match modes, and continuous data transfer
• The timing of the shifter's shift, load and store events are controlled by the highly flexible 16-bit timer assigned to the shifter
• Two or more shifters can be concatenated to support large data transfer sizes
• Each 16-bit timers operates independently, supports for reset, enable and disable on a variety of internal or external trigger conditions with programmable trigger polarity
• Flexible pin configuration supporting output disabled, open drain, bidirectional output data and output mode
• Supports interrupt, DMA or polled transmit/receive operation

2.2.18 Port control and GPIO

The Port Control and Interrupt (PORT) module provides support for port control, digital filtering, and external interrupt functions. The GPIO data direction and output data registers control the direction and output data of each pin when the pin is configured for the GPIO function. The GPIO input data register displays the logic value on each pin when the pin is configured for any digital function, provided the corresponding Port Control and Interrupt module for that pin is enabled. The PORT module has the following features:

• all PIN support interrupt enable
• Configurable edge (rising, falling, or both) or level sensitive interrupt type
• Support DMA request
• Asynchronous wake-up in low-power modes
• Configurable pullup, pulldown, and pull-disable on select pins
• Configurable high and low drive strength on selected pins
• Configurable fast and slow slew rates on selected pins
• Configurable passive filter on selected pins
• Individual mux control field supporting analog or pin disabled, GPIO, and up to chip-specific digital functions
• Pad configuration fields are functional in all digital pin muxing modes. The GPIO module has the following features:
• Port Data Input register visible in all digital pin-multiplexing modes
• Port Data Output register with corresponding set/clear/toggle registers Overview K32 L2B Microcontroller, Rev. 3, 09/2020 25 NXP Semiconductors

• Port Data Direction register
• GPIO support single-cycle access via fast GPIO.

3 Memory map

Figure 4. Memory map

4 Pinouts

4.1 K32 L2B Signal Multiplexing and Pin Assignments (LQFP

and MAPBGA) The following table shows the signals available on each pin and the locations of these pins on the devices supported by this document. The Port Control Module is responsible for selecting which ALT functionality is available on each pin. NOTE VREFH can act as VREF_OUT when VREFV1 module is enabled. NOTE When FTFA_FOPT[RESET_PIN_CONFIG]=0, the PTA20 pin acts as RESET_B function only during the POR. After POR, this pin cannot be used as the RESET function. Then, writing to PORTA_PCR20[MUX]=0x1, the PTA20 pin will act as GPIO function (with setting value of ALT1). When FTFA_FOPT[RESET_PIN_CONFIG]=1, the PTA20 pin acts as RESET_B and cannot switch to GPIO function regardless of PORTA_PCR20[MUX]'s setting value. MAP BGA LQFP Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 A1 1 PTE0 LCD_P48 LCD_P48 PTE0/ CLKOUT32K SPI1_MISOLPUART1_TXRTC_CLKOUTCMP0_OUTI2C1_SDA LCD_P48 B1 2 PTE1 LCD_P49 LCD_P49 PTE1 SPI1_MOSILPUART1_RX SPI1_MISOI2C1_SCL LCD_P49 — 3 VDD VDD VDD C4 4 VSS VSS VSS E1 5 USB0_DP USB0_DP USB0_DP D1 6 USB0_DM USB0_DM USB0_DM E2 7 VOUT33 VOUT33 VOUT33 D2 8 VREGIN VREGIN VREGIN G1 9 PTE20 LCD_P59/ ADC0_DP0/ ADC0_SE0 LCD_P59/ ADC0_DP0/ ADC0_SE0 PTE20 TPM1_CH0LPUART0_TX FXIO0_D4 LCD_P59 Pinouts K32 L2B Microcontroller, Rev. 3, 09/2020 27 NXP Semiconductors

Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 F1 10 PTE21 LCD_P60/ ADC0_DM0/ ADC0_SE4a LCD_P60/ ADC0_DM0/ ADC0_SE4a PTE21 TPM1_CH1LPUART0_RX FXIO0_D5 LCD_P60 G2 11 PTE22 ADC0_DP3/ ADC0_SE3 ADC0_DP3/ ADC0_SE3 PTE22 TPM2_CH0UART2_TX FXIO0_D6 F2 12 PTE23 ADC0_DM3/ ADC0_SE7a ADC0_DM3/ ADC0_SE7a PTE23 TPM2_CH1UART2_RX FXIO0_D7 F4 13 VDDA VDDA VDDA G4 14 VREFH VREFH VREFH G3 15 VREFL VREFL VREFL F3 16 VSSA VSSA VSSA H1 17 PTE29 CMP0_IN5/ ADC0_SE4b CMP0_IN5/ ADC0_SE4b PTE29 TPM0_CH2TPM_CLKIN0 H2 18 PTE30 DAC0_OUT/ ADC0_SE23/ CMP0_IN4 DAC0_OUT/ ADC0_SE23/ CMP0_IN4 PTE30 TPM0_CH3TPM_CLKIN1LPUART1_TXLPTMR0_ ALT1 H3 19 PTE31 DISABLED PTE31 TPM0_CH4 H4 20 PTE24 DISABLED PTE24 TPM0_CH0 I2C0_SCL H5 21 PTE25 DISABLED PTE25 TPM0_CH1 I2C0_SDA D3 22 PTA0 SWD_CLK PTA0 TPM0_CH5 SWD_CLK D4 23 PTA1 DISABLED PTA1 LPUART0_RXTPM2_CH0 E5 24 PTA2 DISABLED PTA2 LPUART0_TXTPM2_CH1 D5 25 PTA3 SWD_DIO PTA3 I2C1_SCL TPM0_CH0 SWD_DIO G5 26 PTA4 NMI_b PTA4 I2C1_SDA TPM0_CH1 NMI_b F5 27 PTA5 DISABLED PTA5 USB_CLKINTPM0_CH2 H6 28 PTA12 DISABLED PTA12 TPM1_CH0 G6 29 PTA13 DISABLED PTA13 TPM1_CH1 G7 30 VDD VDD VDD H7 31 VSS VSS VSS H8 32 PTA18 EXTAL0 EXTAL0 PTA18 LPUART1_RXTPM_CLKIN0 G8 33 PTA19 XTAL0 XTAL0 PTA19 LPUART1_TXTPM_CLKIN1 LPTMR0_ ALT1 F8 34 PTA20 RESET_b F7 35 PTB0/ LLWU_P5 LCD_P0/ ADC0_SE8 LCD_P0/ ADC0_SE8 PTB0/ LLWU_P5 I2C0_SCL TPM1_CH0 LCD_P0 F6 36 PTB1 LCD_P1/ ADC0_SE9 LCD_P1/ ADC0_SE9 PTB1 I2C0_SDA TPM1_CH1 LCD_P1 E7 37 PTB2 LCD_P2/ ADC0_SE12 LCD_P2/ ADC0_SE12 PTB2 I2C0_SCL TPM2_CH0 LCD_P2 E8 38 PTB3 LCD_P3/ ADC0_SE13 LCD_P3/ ADC0_SE13 PTB3 I2C0_SDA TPM2_CH1 LCD_P3 E6 39 PTB16 LCD_P12 LCD_P12 PTB16 SPI1_MOSILPUART0_RXTPM_CLKIN0SPI1_MISO LCD_P12 Pinouts 28 K32 L2B Microcontroller, Rev. 3, 09/2020 NXP Semiconductors

Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 D7 40 PTB17 LCD_P13 LCD_P13 PTB17 SPI1_MISOLPUART0_TXTPM_CLKIN1SPI1_MOSI LCD_P13 D6 41 PTB18 LCD_P14 LCD_P14 PTB18 TPM2_CH0 LCD_P14 C7 42 PTB19 LCD_P15 LCD_P15 PTB19 TPM2_CH1 LCD_P15 D8 43 PTC0 LCD_P20/ ADC0_SE14 LCD_P20/ ADC0_SE14 PTC0 EXTRG_INaudioUSB_ SOF_OUT CMP0_OUT LCD_P20 C6 44 PTC1/ LLWU_P6/ RTC_CLKIN LCD_P21/ ADC0_SE15 LCD_P21/ ADC0_SE15 PTC1/ LLWU_P6/ RTC_CLKIN I2C1_SCL TPM0_CH0 LCD_P21 B7 45 PTC2 LCD_P22/ ADC0_SE11 LCD_P22/ ADC0_SE11 PTC2 I2C1_SDA TPM0_CH1 LCD_P22 C8 46 PTC3/ LLWU_P7 LCD_P23 LCD_P23 PTC3/ LLWU_P7 SPI1_SCK LPUART1_RXTPM0_CH2CLKOUT LCD_P23 E3 47 VSS VSS VSS E4 — VDD VDD VDD C5 48 VLL3 VLL3 VLL3 A6 49 VLL2 VLL2/ LCD_P4 VLL2/ LCD_P4 PTC20 LCD_P4 B5 50 VLL1 VLL1/ LCD_P5 VLL1/ LCD_P5 PTC21 LCD_P5 B4 51 VCAP2 VCAP2/ LCD_P6 VCAP2/ LCD_P6 PTC22 LCD_P6 A5 52 VCAP1 VCAP1/ LCD_P39 VCAP1/ LCD_P39 PTC23 LCD_P39 B8 53 PTC4/ LLWU_P8 LCD_P24 LCD_P24 PTC4/ LLWU_P8 SPI0_SS LPUART1_TXTPM0_CH3 LCD_P24 A8 54 PTC5/ LLWU_P9 LCD_P25 LCD_P25 PTC5/ LLWU_P9 SPI0_SCK LPTMR0_ ALT2 CMP0_OUTLCD_P25 A7 55 PTC6/ LLWU_P10 LCD_P26/ CMP0_IN0 LCD_P26/ CMP0_IN0 PTC6/ LLWU_P10 SPI0_MOSIEXTRG_IN SPI0_MISO LCD_P26 B6 56 PTC7 LCD_P27/ CMP0_IN1 LCD_P27/ CMP0_IN1 PTC7 SPI0_MISOaudioUSB_ SOF_OUT SPI0_MOSI LCD_P27 C3 57 PTD0 LCD_P40 LCD_P40 PTD0 SPI0_SS TPM0_CH0 FXIO0_D0 LCD_P40 A4 58 PTD1 LCD_P41/ ADC0_SE5b LCD_P41/ ADC0_SE5b PTD1 SPI0_SCK TPM0_CH1 FXIO0_D1 LCD_P41 C2 59 PTD2 LCD_P42 LCD_P42 PTD2 SPI0_MOSIUART2_RXTPM0_CH2SPI0_MISOFXIO0_D2 LCD_P42 B3 60 PTD3 LCD_P43 LCD_P43 PTD3 SPI0_MISOUART2_TXTPM0_CH3SPI0_MOSIFXIO0_D3 LCD_P43 A3 61 PTD4/ LLWU_P14 LCD_P44 LCD_P44 PTD4/ LLWU_P14 SPI1_SS UART2_RXTPM0_CH4 FXIO0_D4 LCD_P44 C1 62 PTD5 LCD_P45/ ADC0_SE6b LCD_P45/ ADC0_SE6b PTD5 SPI1_SCK UART2_TXTPM0_CH5 FXIO0_D5 LCD_P45 B2 63 PTD6/ LLWU_P15 LCD_P46/ ADC0_SE7b LCD_P46/ ADC0_SE7b PTD6/ LLWU_P15 SPI1_MOSILPUART0_RX SPI1_MISOFXIO0_D6 LCD_P46 A2 64 PTD7 LCD_P47 LCD_P47 PTD7 SPI1_MISOLPUART0_TX SPI1_MOSIFXIO0_D7 LCD_P47 Pinouts K32 L2B Microcontroller, Rev. 3, 09/2020 29 NXP Semiconductors

4.2 K32 L2B Signal Multiplexing and Pin Assignments (QFN)

The following table shows the signals available on each pin and the locations of these pins on the devices supported by this document. The Port Control Module is responsible for selecting which ALT functionality is available on each pin. NOTE When FTFA_FOPT[RESET_PIN_CONFIG]=0, the PTA20 pin acts as RESET_B function only during the POR. After POR, this pin cannot be used as the RESET function. Then, writing to PORTA_PCR20[MUX]=0x1, the PTA20 pin will act as GPIO function (with setting value of ALT1). When FTFA_FOPT[RESET_PIN_CONFIG]=1, the PTA20 pin acts as RESET_B and cannot switch to GPIO function regardless of PORTA_PCR20[MUX]'s setting value. QFN QFN Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 — 1 VDD VDD VDD — 7 PTE20 ADC0_DP0/ ADC0_SE0 ADC0_DP0/ ADC0_SE0 PTE20 TPM1_CH0LPUART0_TX FXIO0_D4 — 8 PTE21 ADC0_DM0/ ADC0_SE4a ADC0_DM0/ ADC0_SE4a PTE21 TPM1_CH1LPUART0_RX FXIO0_D5 — 10 VREFH VREFH VREFH — 11 VREFL VREFL VREFL — 13 PTE29 CMP0_IN5/ ADC0_SE4b CMP0_IN5/ ADC0_SE4b PTE29 TPM0_CH2TPM_CLKIN0 — 15 PTE24 DISABLED PTE24 TPM0_CH0 I2C0_SCL — 16 PTE25 DISABLED PTE25 TPM0_CH1 I2C0_SDA — 29 PTB2 ADC0_SE12ADC0_SE12PTB2 I2C0_SCL TPM2_CH0 — 30 PTB3 ADC0_SE13ADC0_SE13PTB3 I2C0_SDA TPM2_CH1 — 31 PTB16 DISABLED PTB16 SPI1_MOSILPUART0_RXTPM_CLKIN0SPI1_MISO — 32 PTB17 DISABLED PTB17 SPI1_MISOLPUART0_TXTPM_CLKIN1SPI1_MOSI — 33 PTC0 ADC0_SE14ADC0_SE14PTC0 EXTRG_INaudioUSB_ SOF_OUT CMP0_OUT — 41 PTD0 DISABLED PTD0 SPI0_SS TPM0_CH0 FXIO0_D0 — 42 PTD1 ADC0_SE5bADC0_SE5bPTD1 SPI0_SCK TPM0_CH1 FXIO0_D1 — 43 PTD2 DISABLED PTD2 SPI0_MOSIUART2_RXTPM0_CH2SPI0_MISOFXIO0_D2 — 44 PTD3 DISABLED PTD3 SPI0_MISOUART2_TXTPM0_CH3SPI0_MOSIFXIO0_D3 1 — PTE0 DISABLED PTE0/ CLKOUT32K SPI1_MISOLPUART1_TXRTC_CLKOUTCMP0_OUTI2C1_SDA 2 2 VSS VSS VSS Pinouts 30 K32 L2B Microcontroller, Rev. 3, 09/2020 NXP Semiconductors

Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 3 3 USB0_DP USB0_DP USB0_DP 4 4 USB0_DM USB0_DM USB0_DM 5 5 VOUT33 VOUT33 VOUT33 6 6 VREGIN VREGIN VREGIN 7 9 VDDA VDDA VDDA 8 12 VSSA VSSA VSSA 9 14 PTE30 DAC0_OUT/ ADC0_SE23/ CMP0_IN4 DAC0_OUT/ ADC0_SE23/ CMP0_IN4 PTE30 TPM0_CH3TPM_CLKIN1LPUART1_TXLPTMR0_ ALT1 10 17 PTA0 SWD_CLK PTA0 TPM0_CH5 SWD_CLK 11 18 PTA1 DISABLED PTA1 LPUART0_RXTPM2_CH0 12 19 PTA2 DISABLED PTA2 LPUART0_TXTPM2_CH1 13 20 PTA3 SWD_DIO PTA3 I2C1_SCL TPM0_CH0 SWD_DIO 14 21 PTA4 NMI_b PTA4 I2C1_SDA TPM0_CH1 NMI_b 15 22 VDD VDD VDD 16 23 VSS VSS VSS 17 24 PTA18 EXTAL0 EXTAL0 PTA18 LPUART1_RXTPM_CLKIN0 18 25 PTA19 XTAL0 XTAL0 PTA19 LPUART1_TXTPM_CLKIN1 LPTMR0_ ALT1 19 26 PTA20 RESET_b 20 27 PTB0/ LLWU_P5 ADC0_SE8ADC0_SE8PTB0/ LLWU_P5 I2C0_SCL TPM1_CH0 21 28 PTB1 ADC0_SE9ADC0_SE9PTB1 I2C0_SDA TPM1_CH1 22 34 PTC1/ LLWU_P6/ RTC_CLKIN ADC0_SE15ADC0_SE15PTC1/ LLWU_P6/ RTC_CLKIN I2C1_SCL TPM0_CH0 23 35 PTC2 ADC0_SE11ADC0_SE11PTC2 I2C1_SDA TPM0_CH1 24 36 PTC3/ LLWU_P7 DISABLED PTC3/ LLWU_P7 SPI1_SCK LPUART1_RXTPM0_CH2CLKOUT 25 37 PTC4/ LLWU_P8 DISABLED PTC4/ LLWU_P8 SPI0_SS LPUART1_TXTPM0_CH3 26 38 PTC5/ LLWU_P9 DISABLED PTC5/ LLWU_P9 SPI0_SCK LPTMR0_ ALT2 CMP0_OUT 27 39 PTC6/ LLWU_P10 CMP0_IN0CMP0_IN0PTC6/ LLWU_P10 SPI0_MOSIEXTRG_IN SPI0_MISO 28 40 PTC7 CMP0_IN1CMP0_IN1PTC7 SPI0_MISOaudioUSB_ SOF_OUT SPI0_MOSI 29 45 PTD4/ LLWU_P14 DISABLED PTD4/ LLWU_P14 SPI1_SS UART2_RXTPM0_CH4 FXIO0_D4 30 46 PTD5 ADC0_SE6bADC0_SE6bPTD5 SPI1_SCK UART2_TXTPM0_CH5 FXIO0_D5 31 47 PTD6/ LLWU_P15 ADC0_SE7bADC0_SE7bPTD6/ LLWU_P15 SPI1_MOSILPUART0_RX SPI1_MISOFXIO0_D6 32 48 PTD7 DISABLED PTD7 SPI1_MISOLPUART0_TX SPI1_MOSIFXIO0_D7 Pinouts K32 L2B Microcontroller, Rev. 3, 09/2020 31 NXP Semiconductors

4.3 Pin properties

The following table lists the pin properties of 64 LQFP/MAPBGA package.

64 MAPBGA

Pullup/ pulldown setting after POR Slew rate after POR Passive pin filter after POR Open drain Pin interrupt

1 A1 PTE0 ND Hi-Z — SS N N N

2 B1 PTE1 ND Hi-Z — SS N N N

9 G1 PTE20 ND Hi-Z — SS N N N

10 F1 PTE21 ND Hi-Z — SS N N N

11 G2 PTE22 ND Hi-Z — SS N N N

12 F2 PTE23 ND Hi-Z — SS N N N

17 H1 PTE29 ND Hi-Z — SS N N N

18 H2 PTE30 ND Hi-Z — SS N N N

19 H3 PTE31 ND Hi-Z — SS N N N

20 H4 PTE24 ND Hi-Z — SS N N N

21 H5 PTE25 ND Hi-Z — SS N N N

22 D3 PTA0 ND L PD SS N N Y

23 D4 PTA1 ND Hi-Z — SS N N Y

24 E5 PTA2 ND Hi-Z — SS N N Y

Table continues on the next page... Pinouts 32 K32 L2B Microcontroller, Rev. 3, 09/2020 NXP Semiconductors

Pullup/ pulldown setting after POR Slew rate after POR Passive pin filter after POR Open drain Pin interrupt

25 D5 PTA3 ND H PU FS N N Y

26 G5 PTA4 ND H PU SS N N Y

27 F5 PTA5 ND Hi-Z — SS N N Y

28 H6 PTA12 ND Hi-Z — SS N N Y

29 G6 PTA13 ND Hi-Z — SS N N Y

32 H8 PTA18 ND Hi-Z — SS N N Y

33 G8 PTA19 ND Hi-Z — SS N N Y

34 F8 PTA20 ND H PU SS Y Y Y

35 F7 PTB0/LLWU_P5 HD Hi-Z — SS N N N

36 F6 PTB1 HD Hi-Z — SS N N N

37 E7 PTB2 ND Hi-Z — SS N N N

38 E8 PTB3 ND Hi-Z — SS N N N

39 E6 PTB16 ND Hi-Z — FS N N N

40 D7 PTB17 ND Hi-Z — FS N N N

41 D6 PTB18 ND Hi-Z — SS N N N

42 C7 PTB19 ND Hi-Z — SS N N N

43 D8 PTC0 ND Hi-Z — SS N N Y

44 C6 PTC1/LLWU_P6/

RTC_CLKIN ND Hi-Z — SS N N Y

45 B7 PTC2 ND Hi-Z — SS N N Y

46 C8 PTC3/LLWU_P7 HD Hi-Z — FS N N Y

Table continues on the next page... Pinouts K32 L2B Microcontroller, Rev. 3, 09/2020 33 NXP Semiconductors

Pullup/ pulldown setting after POR Slew rate after POR Passive pin filter after POR Open drain Pin interrupt

53 B8 PTC4/LLWU_P8 HD Hi-Z — FS N N Y

54 A8 PTC5/LLWU_P9 ND Hi-Z — FS N N Y

55 A7 PTC6/LLWU_P10 ND Hi-Z — FS N N Y

56 B6 PTC7 ND Hi-Z — FS N N Y

57 C3 PTD0 ND Hi-Z — SS N N Y

58 A4 PTD1 ND Hi-Z — SS N N Y

59 C2 PTD2 ND Hi-Z — SS N N Y

60 B3 PTD3 ND Hi-Z — SS N N Y

61 A3 PTD4/LLWU_P14 ND Hi-Z — FS N N Y

62 C1 PTD5 ND Hi-Z — FS N N Y

63 B2 PTD6/LLWU_P15 HD Hi-Z — FS N N Y

64 A2 PTD7 HD Hi-Z — FS N N Y

The following table lists the pin properties of 32/48 QFN package. Pullup/ pulldown setting after POR Slew rate after POR Passive pin filter after POR Open drain Pin interrupt Table continues on the next page... Pinouts 34 K32 L2B Microcontroller, Rev. 3, 09/2020 NXP Semiconductors

Pullup/ pulldown setting after POR Slew rate after POR Passive pin filter after POR Open drain Pin interrupt — 7 PTE20 ND Hi-Z — SS N N N — 8 PTE21 ND Hi-Z — SS N N N — 13 PTE29 ND Hi-Z — SS N N N — 15 PTE24 ND Hi-Z — SS N N N — 16 PTE25 ND Hi-Z — SS N N N — 29 PTB2 ND Hi-Z — SS N N N — 30 PTB3 ND Hi-Z — SS N N S — 31 PTB16 ND Hi-Z — FS N N N — 32 PTB17 ND Hi-Z — FS N N N — 33 PTC0 ND Hi-Z — SS N N Y — 41 PTD0 ND Hi-Z — SS N N Y — 42 PTD1 ND Hi-Z — SS N N Y — 43 PTD2 ND Hi-Z — SS N N Y — 44 PTD3 ND Hi-Z — SS N N Y 1 — PTE0 ND Hi-Z — SS N N N 9 14 PTE30 ND Hi-Z — SS N N N 10 17 PTA0 ND L PD SS N N Y 11 18 PTA1 ND Hi-Z — SS N N Y 12 19 PTA2 ND Hi-Z — SS N N Y 13 20 PTA3 ND H PU FS N N Y Table continues on the next page... Pinouts K32 L2B Microcontroller, Rev. 3, 09/2020 35 NXP Semiconductors

Pullup/ pulldown setting after POR Slew rate after POR Passive pin filter after POR Open drain Pin interrupt 14 21 PTA4 ND H PU SS N N Y 17 24 PTA18 ND Hi-Z — SS N N Y 18 25 PTA19 ND Hi-Z — SS N N Y 19 26 PTA20 ND H PU SS Y Y Y 20 27 PTB0/LLWU_P5 HD Hi-Z — SS N N N 21 28 PTB1 HD Hi-Z — SS N N N 22 34 PTC1/LLWU_P6/ RTC_CLKIN ND Hi-Z — SS N N Y 23 35 PTC2 ND Hi-Z — SS N N Y 24 36 PTC3/LLWU_P7 HD Hi-Z — FS N N Y 25 37 PTC4/LLWU_P8 HD Hi-Z — FS N N Y 26 38 PTC5/LLWU_P9 ND Hi-Z — FS N N Y 27 39 PTC6/LLWU_P10 ND Hi-Z — FS N N Y 28 40 PTC7 ND Hi-Z — FS N N Y 29 45 PTD4/LLWU_P14 ND Hi-Z — FS N N Y 30 46 PTD5 ND Hi-Z — FS N N Y 31 47 PTD6/LLWU_P15 HD Hi-Z — FS N N Y 32 48 PTD7 HD Hi-Z — FS N N Y Properties Abbreviation Descriptions Driver strength ND Normal drive HD High drive Default status after POR Hi-Z High impendence H High level L Low level Pullup/ pulldown setting after POR PD Pulldown PU Pullup Table continues on the next page... Pinouts 36 K32 L2B Microcontroller, Rev. 3, 09/2020 NXP Semiconductors

1. When I2C module is enabled and a pin is functional for I2C, this pin is (pseudo-) open drain enabled. When UART or
2. PTA20 is a true open drain pin that must never be pulled above VDD.

4.4 Module Signal Description Tables

in the module's chapter. They also briefly describe the signal function and direction.

4.4.1 Core modules

Table 9. SWD signal descriptions Debug mode. This pin is pulled down internally.

4.4.2 System modules

Table 10. System signal descriptions Table continues on the next page...

Table 10. System signal descriptions (continued) Table 11. LLWU signal descriptions

4.4.3 Clock modules

Table 12. OSC signal descriptions

4.4.4 Analog

This table presents the signal descriptions of the ADC0 module. Table 13. ADC0 signal descriptions Table continues on the next page...

Table 13. ADC0 signal descriptions (continued) This table presents the signal descriptions of the CMP0 module. Table 14. CMP0 signal descriptions Table 15. VREF signal descriptions

4.4.5 Timer Modules

Table 16. TPM0 signal descriptions Table 17. TPM1 signal descriptions Table continues on the next page...

Table 17. TPM1 signal descriptions (continued) Table 18. TPM2 signal descriptions Table 19. LPTMR0 signal descriptions Table 20. RTC signal descriptions

1. RTC_CLKOUT can also be driven with OSCERCLK via SIM control bit SIM_SOPT[RCTCLKOUTSEL]

4.4.6 Communication interfaces

Table 21. USB FS Signal Descriptions

Table 22. SPI0 signal descriptions Table 23. SPI1 signal descriptions Table 24. I 2C0 signal descriptions Table 25. I 2C1 signal descriptions Table 26. LPUART0 signal descriptions

Table 27. LPUART1 signal descriptions Table 28. UART2 signal descriptions Table 29. FlexIO signal descriptions

4.4.7 Human-machine interfaces (HMI)

Table 30. GPIO Signal Descriptions Table 31. LCD Signal Descriptions Table continues on the next page...

Table 31. LCD Signal Descriptions (continued)

4.5 K32 L2B LQFP and MAPBGA pinouts

Figure 5. 64 LQFP Pinout diagram

Figure 6. 64 MAPBGA Pinout diagram

4.6 K32 L2B QFN Pinouts

The figure below shows the 32 QFN pinouts.

Figure 7. 32 QFN Pinout diagram (transparent top view) The figure below shows the 48 QFN pinouts.

Figure 8. 48 QFN Pinout diagram (transparent top view)

4.7 Package dimensions

Figure 9. 64-pin LQFP package dimensions 1

1. DIMENSIONS ARE IN MILLIMETERS.
2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994.
3. DATUMS A, B AND D TO BE DETERMINDE AT DATUM PLANE H.
4. DIMENSIONS TO BE DETERMINED AT SEATING PLANE C.
5. THIS DIMENSION DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION AND ADJACENT LEAD SHALL NOT BE LESS THAN 0.07 MM.

1. THIS DIMENSION DOES NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION

DIMENSION INCLUDING MOLD MISMATCH.

1. EXACT SHAPE OF EACH CORNER IS OPTIONAL.
2. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN

0.1 MM AND 0.25 MM FROM THE LEAD TIP. Figure 10. 64-pin LQFP package dimensions 2

1.23 MAX

1. ALL DIMENSIONS IN MILLIMETERS.
2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994.
3. MAXIMUM SOLDER BALL DIAMETER MEASURED PARALLEL TO DATUM A.
4. DATUM A, THE SEATING PLANE, IS DETERMINED BY THE SPHERICAL CROWNS OF THE
5. PARALLELISM MEASUREMENT SHALL EXCLUDE ANY EFFECT OF MARK ON TOP SURFACE

Figure 11. 64-pin MAPBGA package dimension

Figure 12. 48-pin QFN package dimension 1

0.1 C//

0.08 C 4

1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994.
3. THIS IS A NON-JEDEC REGISTERED PACKAGE.
4. COPLANARITY APPLIES TO LEADS AND DIE ATTACH FLAG.
5. MIN. METAL GAP SHOULD BE 0.2 MM.

Figure 13. 48-pin QFN package dimension 2

Figure 14. 32-pin QFN package dimension 1

0.65 0.50 0.05 0.00 (0.2) (0.5) // 0.1 C 32X 0.08 C C SEATING PLANE DETAIL G VIEW ROTATED 90℃W NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETERS. 2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994. 3. THIS IS A NON-JEDEC REGISTERED PACKAGE. 4. COPLANARITY APPLIES TO LEADS AND DIE ATTACH FLAG. 5. MIN. METAL GAP SHOULD BE 0.2 MM. Figure 15. 32-pin QFN package dimension 2

5 Electrical characteristics

5.1 Ratings

Electrical characteristics

54 K32 L2B Microcontroller, Rev. 3, 09/2020 NXP Semiconductors

5.1.1 Thermal handling ratings

Table 32. Thermal handling ratings

1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic

Solid State Surface Mount Devices.

5.1.2 Moisture handling ratings

Table 33. Moisture handling ratings

1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic

Solid State Surface Mount Devices.

5.1.3 ESD handling ratings

Table 34. ESD handling ratings

1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for

Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.

1. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.

5.1.4 Voltage and current operating ratings

Table 35. Voltage and current operating ratings Table continues on the next page... K32 L2B Microcontroller, Rev. 3, 09/2020 55 NXP Semiconductors

Table 35. Voltage and current operating ratings (continued)

5.2 General

5.2.1 AC electrical characteristics

Figure 16. Input signal measurement reference output pins have the following characteristics.

• C L=30 pF loads
• Slew rate disabled
• Normal drive strength

5.2.2 Nonswitching electrical specifications

56 K32 L2B Microcontroller, Rev. 3, 09/2020 NXP Semiconductors

5.2.2.1 Voltage and current operating requirements

Table 36. Voltage and current operating requirements

• 2.7 V ≤ V DD ≤ 3.6 V
• 1.7 V ≤ V DD ≤ 2.7 V 0.7 × VDD 0.75 × VDD V V VIL Input low voltage
• 2.7 V ≤ V DD ≤ 3.6 V
• 1.7 V ≤ V DD ≤ 2.7 V 0.35 × VDD 0.3 × VDD V V VHYS Input hysteresis 0.06 × VDD — V IICIO IO pin negative DC injection current — single pin
• V IN < VSS-0.3V -3 — mA IICcont Contiguous pin DC injection current —regional limit, includes sum of negative injection currents of 16 contiguous pins
• Negative current injection -25 — mA VODPU Open drain pullup voltage level VDD VDD V 2 VRAM VDD voltage required to retain RAM 1.2 — V 1. All I/O pins are internally clamped to VSS through a ESD protection diode. There is no diode connection to VDD. If VIN greater than VIO_MIN (= VSS-0.3 V) is observed, then there is no need to provide current limiting resistors at the pads. If this limit cannot be observed then a current limiting resistor is required. The negative DC injection current limiting resistor is calculated as R = (VIO_MIN - VIN)/|IICIO|. 2. Open drain outputs must be pulled to VDD.

5.2.2.2 LVD and POR operating requirements

Table 37. V DD supply LVD and POR operating requirements

• Level 1 falling (LVWV = 00)
• Level 2 falling (LVWV = 01) 2.62 2.72 2.82 2.70 2.80 2.90 2.78 2.88 2.98 V V V Table continues on the next page...

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Table 37. V DD supply LVD and POR operating requirements (continued)

• Level 4 falling (LVWV = 11) 2.92 3.00 3.08 V VHYSH Low-voltage inhibit reset/recover hysteresis — high range — ±60 — mV VLVDL Falling low-voltage detect threshold — low range (LVDV=00) 1.54 1.60 1.66 V VLVW1L VLVW2L VLVW3L VLVW4L Low-voltage warning thresholds — low range
• Level 1 falling (LVWV = 00)
• Level 2 falling (LVWV = 01)
• Level 3 falling (LVWV = 10)
• Level 4 falling (LVWV = 11) 1.74 1.84 1.94 2.04 1.80 1.90 2.00 2.10 1.86 1.96 2.06 2.16 V V V V VHYSL Low-voltage inhibit reset/recover hysteresis — low range — ±40 — mV VBG Bandgap voltage reference 0.97 1.00 1.03 V tLPO Internal low-power oscillator period — factory trimmed 900 1000 1100 μs 1. Rising thresholds are falling threshold + hysteresis voltage

5.2.2.3 Voltage and current operating behaviors

Table 38. Voltage and current operating behaviors

• 2.7 V ≤ V DD ≤ 3.6 V, IOH = –5 mA
• 1.71 V ≤ V DD ≤ 2.7 V, IOH = –1.5 mA VDD – 0.5 VDD – 0.5 V V VOH Output high voltage — high drive pad
• 2.7 V ≤ V DD ≤ 3.6 V, IOH = –18 mA
• 1.71 V ≤ V DD ≤ 2.7 V, IOH = –6 mA VDD – 0.5 VDD – 0.5 V V IOHT Output high current total for all ports — 100 mA VOL Output low voltage — normal drive pad
• 2.7 V ≤ V DD ≤ 3.6 V, IOL = 5 mA
• 1.71 V ≤ V DD ≤ 2.7 V, IOL = 1.5 mA 0.5 0.5 V V VOL Output low voltage — high drive pad
• 2.7 V ≤ V DD ≤ 3.6 V, IOL = 18 mA
• 1.71 V ≤ V DD ≤ 2.7 V, IOL = 6 mA 0.5 0.5 V V IOLT Output low current total for all ports — 100 mA Table continues on the next page...

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Table 38. Voltage and current operating behaviors (continued)

1. PTB0, PTB1, PTC3, PTC4, PTD6, and PTD7 I/O have both high drive and normal drive capability selected by the

associated PTx_PCRn[DSE] control bit. All other GPIOs are normal drive only.

1. Measured at VDD supply voltage = VDD min and Vinput = VSS

5.2.2.4 Power mode transition operating behaviors

• CPU and system clocks = 48 MHz
• Bus and flash clock = 24 MHz
• HIRC clock mode

Table 39. Power mode transition operating behaviors

• VLLS0 → RUN 152 166 μs
• VLLS1 → RUN 152 166 μs
• VLLS3 → RUN 104 μs
• LLS → RUN 7.5 μs
• VLPS → RUN 7.5 μs
• STOP → RUN 7.5 μs 1. Normal boot (FTFA_FOPT[LPBOOT]=11)

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5.2.2.5 Power consumption operating behaviors

The maximum values stated in the following table represent characterized results equivalent to the mean plus three times the standard deviation (mean + 3 sigma). NOTE The while (1) test is executed with flash cache enabled. Table 40. Power consumption operating behaviors

• at 25 °C
• at 105 °C 5.76 6.04 6.40 6.68 mA IDD_RUNCO Running While(1) loop in flash in compute operation mode—48M HIRC mode, 48 MHz core / 24 MHz flash, VDD = 3.0 V
• at 25 °C
• at 105 °C 3.21 3.49 3.85 4.13 mA IDD_RUN Run mode current—48M HIRC mode, running CoreMark in Flash all peripheral clock disable 48 MHz core/24 MHz flash, VDD = 3.0 V
• at 25 °C
• at 105 °C 6.45 6.75 7.09 7.39 mA IDD_RUN Run mode current—48M HIRC mode, running CoreMark in flash all peripheral clock disable, 24 MHz core/12 MHz flash, VDD = 3.0 V
• at 25 °C
• at 105 °C 3.95 4.23 4.59 4.87 mA IDD_RUN Run mode current—48M HIRC mode, running CoreMark in Flash all peripheral clock disable 12 MHz core/6 MHz flash, VDD = 3.0 V
• at 25 °C
• at 105 °C 2.68 2.96 3.32 3.60 mA IDD_RUN Run mode current—48M HIRC mode, running CoreMark in Flash all peripheral clock enable 48 MHz core/24 MHz flash, VDD = 3.0 V
• at 25 °C
• at 105 °C 8.08 8.39 8.72 9.03 mA Table continues on the next page...

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Table 40. Power consumption operating behaviors (continued)

• at 25 °C
• at 105 °C 3.90 4.21 4.54 4.85 mA IDD_RUN Run mode current—48M HIRC mode, running While(1) loop in Flash all peripheral clock disable, 24 MHz core/12 MHz flash, VDD = 3.0 V
• at 25 °C
• at 105 °C 2.66 2.94 3.30 3.58 mA IDD_RUN Run mode current—48M HIRC mode, Running While(1) loop in Flash all peripheral clock disable, 12 MHz core/6 MHz flash, VDD = 3.0 V
• at 25 °C
• at 105 °C 2.03 2.31 2.67 2.95 mA IDD_RUN Run mode current—48M HIRC mode, Running While(1) loop in Flash all peripheral clock enable, 48 MHz core/24 MHz flash, VDD = 3.0 V
• at 25 °C
• at 105 °C 5.52 5.83 6.16 6.47 mA IDD_RUN Run mode current—48M HIRC mode, running While(1) loop in SRAM all peripheral clock disable, 48 MHz core/24 MHz flash, VDD = 3.0 V
• at 25 °C
• at 105 °C 5.29 5.56 5.93 6.20 mA IDD_RUN Run mode current—48M HIRC mode, running While(1) loop in SRAM all peripheral clock enable, 48 MHz core/24 MHz flash, VDD = 3.0 V
• at 25 °C
• at 105 °C 6.91 7.19 7.55 7.91 mA IDD_VLPRCO Very Low Power Run Core Mark in Flash in Compute Operation mode: Core@4 MHz, Flash @1 MHz, VDD = 3.0 V
• at 25 °C 826 907 μA IDD_VLPRCO Very-low-power-run While(1) loop in SRAM in compute operation mode— 8 MHz LIRC mode, 4 MHz core / 1 MHz flash, VDD = 3.0 V
• at 25 °C 405 486 μA IDD_VLPRCO Very-low-power run While(1) loop in SRAM in compute operation mode:—2 MHz LIRC mode, 2 MHz core / 0.5 MHz flash, VDD = 3.0 V
• at 25 °C 154 235 μA Table continues on the next page...

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• at 25 °C 108 189 μA IDD_VLPR Very-low-power run mode current— 2 MHz LIRC mode, While(1) loop in flash all peripheral clock disable, 125 kHz core / 31.25 kHz flash, VDD = 3.0 V
• at 25 °C 120 μA IDD_VLPR Very-low-power run mode current— 8 MHz LIRC mode, While(1) loop in flash all peripheral clock disable, 4 MHz core / 1 MHz flash, VDD = 3.0 V
• at 25 °C 249 330 μA IDD_VLPR Very-low-power run mode current— 8 MHz LIRC mode, While(1) loop in flash all peripheral clock enable, 4 MHz core / 1 MHz flash, VDD = 3.0 V
• at 25 °C 337 418 μA IDD_VLPR Very-low-power run mode current— 8 MHz LIRC mode, While(1) loop in SRAM in all peripheral clock disable, 4 MHz core / 1 MHz flash, VDD = 3.0 V
• at 25 °C 416 497 μA IDD_VLPR Very-low-power run mode current— 8 MHz LIRC mode, While(1) loop in SRAM all peripheral clock enable, 4 MHz core / 1 MHz flash, VDD = 3.0 V
• at 25 °C 494 575 μA IDD_VLPR Very-low-power run mode current—2 MHz LIRC mode, While(1) loop in SRAM in all peripheral clock disable, 2 MHz core / 0.5 MHz flash, VDD = 3.0 V
• at 25 °C 166 247 μA IDD_VLPR Very-low-power run mode current—2 MHz LIRC mode, While(1) loop in SRAM all peripheral clock disable, 125 kHz core / 31.25 kHz flash, VDD = 3.0 V
• at 25 °C 131 μA IDD_VLPR Very-low-power run mode current—2 MHz LIRC mode, While(1) loop in SRAM all peripheral clock enable, 2 MHz core / 0.5 MHz flash, VDD = 3.0 V
• at 25 °C 208 289 μA IDD_WAIT Wait mode current—core disabled, 48 MHz system/24 MHz bus, flash disabled (flash doze enabled), all peripheral clocks disabled, MCG_Lite under HIRC mode, VDD = 3.0 V 1.81 1.89 mA IDD_WAIT Wait mode current—core disabled, 24 MHz system/12 MHz bus, flash disabled (flash doze enabled), all peripheral clocks disabled, MCG_Lite under HIRC mode, VDD = 3.0 V 1.22 1.39 mA Table continues on the next page...

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4 MHz system/ 1 MHz bus and flash, all

• at 25 °C and below
• at 50 °C
• at 85 °C
• at 105 °C 161.93 181.45 236.29 390.33 171.82 191.96 271.17 465.58 μA IDD_VLPS Very-low-power stop mode current at 3.0 V
• at 25 °C and below
• at 50 °C
• at 85 °C
• at 105 °C 3.31 10.43 34.14 104.38 5.14 17.68 61.06 164.44 μA IDD_VLPS Very-low-power stop mode current at 1.8 V
• at 25 °C and below
• at 50 °C
• at 85 °C
• at 105 °C 3.21 10.26 33.49 102.92 5.22 17.62 60.19 162.20 μA IDD_LLS Low-leakage stop mode current, all peripheral disable, at 3.0 V
• at 25 °C and below
• at 50 °C
• at 70 °C
• at 85 °C
• at 105 °C 2.06 4.72 8.13 13.34 41.08 3.33 6.85 13.30 24.70 52.43 μA IDD_LLS Low-leakage stop mode current with RTC current, at 3.0 V 2.46 3.73 μA Table continues on the next page...

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• at 25 °C and below
• at 50 °C
• at 70 °C
• at 85 °C
• at 105 °C 5.12 8.53 13.74 41.48 7.25 11.78 18.91 52.83 IDD_LLS Low-leakage stop mode current with RTC current, at 1.8 V
• at 25 °C and below
• at 50 °C
• at 70 °C
• at 85 °C
• at 105 °C 2.35 4.91 8.32 13.44 40.47 2.70 6.75 11.78 18.21 51.85 μA IDD_VLLS3 Very-low-leakage stop mode 3 current, all peripheral disable, at 3.0 V
• at 25 °C and below
• at 50 °C
• at 70 °C
• at 85 °C
• at 105 °C 1.45 3.37 5.76 9.72 30.41 1.85 4.39 8.48 14.30 37.50 μA IDD_VLLS3 Very-low-leakage stop mode 3 current with RTC current, at 3.0 V
• at 25 °C and below
• at 50 °C
• at 70 °C
• at 85 °C
• at 105 °C 2.05 3.97 6.36 10.32 31.01 2.45 4.99 9.08 14.73 38.10 μA IDD_VLLS3 Very-low-leakage stop mode 3 current with RTC current, at 1.8 V
• at 25 °C and below
• at 50 °C
• at 70 °C
• at 85 °C
• at 105 °C 1.96 3.86 6.23 10.21 30.25 2.36 5.67 8.53 13.37 37.02 μA IDD_VLLS1 Very-low-leakage stop mode 1 current all peripheral disabled at 3.0 V
• at 25 °C and below
• at 50°C
• at 70°C 0.66 1.78 2.55 0.80 3.87 4.26 μA Table continues on the next page...

64 K32 L2B Microcontroller, Rev. 3, 09/2020 NXP Semiconductors

• at 85°C
• at 105 °C 4.83 16.42 6.64 20.49 IDD_VLLS1 Very-low-leakage stop mode 1 current RTC enabled at 3.0 V
• at 25 °C and below
• at 50°C
• at 70°C
• at 85°C
• at 105 °C 1.26 2.38 3.15 5.43 17.02 1.40 4.47 4.86 7.24 21.09 μA IDD_VLLS1 Very-low-leakage stop mode 1 current RTC enabled at 1.8 V
• at 25 °C and below
• at 50°C
• at 70°C
• at 85°C
• at 105 °C 1.16 1.96 2.78 4.85 15.78 1.30 2.28 3.37 6.88 18.81 μA IDD_VLLS0 Very-low-leakage stop mode 0 current all peripheral disabled (SMC_STOPCTRL[PORPO] = 0) at 3.0 V
• at 25 °C and below
• at 50 °C
• at 70 °C
• at 85 °C
• at 105 °C 0.35 1.25 2.53 4.40 16.09 0.47 1.44 3.24 5.24 19.29 μA IDD_VLLS0 Very-low-leakage stop mode 0 current all peripheral disabled (SMC_STOPCTRL[PORPO] = 1) at 3 V
• at 25 °C and below
• at 50 °C
• at 70 °C
• at 85 °C
• at 105 °C 0.18 1.09 2.25 4.25 15.95 0.28 1.31 2.94 5.10 19.10 μA 1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See each module's specification for its supply current. 2. MCG_Lite configured for HIRC mode. CoreMark benchmark compiled using IAR 7.10 with optimization level high, optimized for balanced. 3. RTC uses external 32 kHz crystal as clock source, and the current includes ERCLK32K power consumption.

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Table 41. Low power mode peripheral adders — typical value IEREFSTEN4MHz External 4 MHz crystal clock adder. mode with the crystal enabled. modes with the crystal enabled.

• VLLS1
• VLLS3
• LLS
• VLPS
• STOP 440 440 490 510 510 490 490 490 560 560 540 540 540 560 560 560 560 560 560 560 570 570 570 610 610 580 580 680 680 680 nA ILPTMR LPTMR peripheral adder measured by placing the device in VLLS1 mode with LPTMR enabled using LPO. 100 200 nA ICMP CMP peripheral adder measured by placing the device in VLLS1 mode with CMP enabled using the 6-bit DAC and a single external input for compare. Includes 6-bit DAC power consumption. 22 22 22 22 22 22 µA IUART UART peripheral adder measured by placing the device in STOP or VLPS mode with selected clock source waiting for RX data at 115200 baud rate. Includes selected clock source power consumption.
• IRC8M (8 MHz internal reference clock)
• IRC2M (2 MHz internal reference clock) 114 114 114 114 114 114 µA Table continues on the next page...

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Table 41. Low power mode peripheral adders — typical value (continued)

• IRC8M (8 MHz internal reference clock)
• IRC2M (2 MHz internal reference clock) 147 147 147 147 147 147 µA IBG Bandgap adder when BGEN bit is set and device is placed in VLPx or VLLSx mode. 45 45 45 45 45 45 µA IADC ADC peripheral adder combining the measured values at VDD and VDDA by placing the device in STOP or VLPS mode. ADC is configured for low power mode using the internal clock and continuous conversions. 330 330 330 330 330 330 µA ILCD LCD peripheral adder measured by placing the device in VLLS1 mode with external 32 kHz crystal enabled by means of the OSC0_CR[EREFSTEN, EREFSTEN] bits. VIREG disabled, resistor bias network enabled, 1/8 duty cycle, 8 x 36 configuration for driving 288 Segments,

32 Hz frame rate, no LCD glass

external crystal) power consumption.

5.2.2.5.1 Diagram: Typical IDD_RUN operating behavior

• MCG-Lite in HIRC for run mode, and LIRC for VLPR mode
• USB regulator disabled
• No GPIOs toggled
• Code execution from flash
• For the ALLOFF curve, all peripheral clocks are disabled except FTFA

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Figure 17. Run mode supply current vs. core frequency 68 K32 L2B Microcontroller, Rev. 3, 09/2020 NXP Semiconductors

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C urrent C onsumption on VDD (A)C urrent C onsumption on VDD (A) Figure 18. VLPR mode current vs. core frequency

5.2.2.6 EMC performance

guidance specifically targeted at optimizing EMC performance.

• AN2321: Designing for Board Level Electromagnetic Compatibility
• AN1050: Designing for Electromagnetic Compatibility (EMC) with HCMOS Microcontrollers
• AN1263: Designing for Electromagnetic Compatibility with Single-Chip Microcontrollers

70 K32 L2B Microcontroller, Rev. 3, 09/2020 NXP Semiconductors

• AN2764: Improving the Transient Immunity Performance of Microcontroller- Based Applications
• AN1259: System Design and Layout Techniques for Noise Reduction in MCU- Based Systems

5.2.2.7 Capacitance attributes

Table 42. Capacitance attributes

5.2.3 Switching specifications

5.2.3.1 Device clock specifications

Table 43. Device clock specifications

1. The maximum value of system clock, core clock, bus clock, and flash clock under normal run mode can be 3% higher

than the specified maximum frequency when IRC 48 MHz is used as the clock source.

1. The frequency limitations in VLPR and VLPS modes here override any frequency specification listed in the timing
2. The LPTMR can be clocked at this speed in VLPR or VLPS only when the source is an external pin.

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5.2.3.2 General switching specifications

These general-purpose specifications apply to all signals configured for GPIO and UART signals. Table 44. General switching specifications

1. The synchronous and asynchronous timing must be met.
2. This is the shortest pulse that is guaranteed to be recognized.

5.2.4 Thermal specifications

5.2.4.1 Thermal operating requirements

Table 45. Thermal operating requirements

1. Maximum TA can be exceeded only if the user ensures that TJ does not exceed the maximum. The simplest method to

determine TJ is: TJ = TA + RθJA × chip power dissipation.

5.2.4.2 Thermal attributes

Table 46. Thermal attributes Table continues on the next page... 72 K32 L2B Microcontroller, Rev. 3, 09/2020 NXP Semiconductors

Table 46. Thermal attributes (continued)

1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental

Method Environmental Conditions—Forced Convection (Moving Air).

1. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental

Conditions—Junction-to-Board.

1. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate

between the top of the package and the cold plate.

1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental

Conditions—Natural Convection (Still Air).

1. Thermal characterization parameter indicating the temperature difference between package bottom center and the

parameter is written as Psi-JB.

5.3 Peripheral operating requirements and behaviors

5.3.1 Core modules

5.3.1.1 SWD electricals

Table 47. SWD full voltage range electricals Table continues on the next page... K32 L2B Microcontroller, Rev. 3, 09/2020 73 NXP Semiconductors

5.3.2 System modules

There are no specifications necessary for the device's system modules.

5.3.3 Clock modules

5.3.3.1 MCG-Lite specifications

Table 48. IRC48M specification

1. The maximum value represents characterized results equivalent to mean plus or minus three times the standard

Table 49. IRC8M/2M specification K32 L2B Microcontroller, Rev. 3, 09/2020 75 NXP Semiconductors

Figure 21. IRC8M Frequency Drift vs Temperature curve

5.3.3.2 Oscillator electrical specifications

5.3.3.2.1 Oscillator DC electrical specifications

Table 50. Oscillator DC electrical specifications

• 32 kHz
• 4 MHz
• 8 MHz (RANGE=01)
• 16 MHz 500 200 300 950 1.2 nA μA μA μA mA Table continues on the next page...

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Table 50. Oscillator DC electrical specifications (continued)

• 24 MHz
• 32 MHz — 1.5 — mA IDDOSC Supply current — high gain mode (HGO=1)
• 32 kHz
• 4 MHz
• 8 MHz (RANGE=01)
• 16 MHz
• 24 MHz
• 32 MHz 400 500 2.5 μA μA μA mA mA mA Cx EXTAL load capacitance — — — 2, 3 Cy XTAL load capacitance — — — 2, 3 RF Feedback resistor — low-frequency, low-power mode (HGO=0) — — — MΩ 2, 4 Feedback resistor — low-frequency, high-gain mode (HGO=1) — 10 — MΩ Feedback resistor — high-frequency, low-power mode (HGO=0) — — — MΩ Feedback resistor — high-frequency, high-gain mode (HGO=1) — 1 — MΩ RS Series resistor — low-frequency, low-power mode (HGO=0) — — — kΩ Series resistor — low-frequency, high-gain mode (HGO=1) — 200 — kΩ Series resistor — high-frequency, low-power mode (HGO=0) — — — kΩ Series resistor — high-frequency, high-gain mode (HGO=1) kΩ Vpp5 Peak-to-peak amplitude of oscillation (oscillator mode) — low-frequency, low-power mode (HGO=0) — 0.6 — V Peak-to-peak amplitude of oscillation (oscillator mode) — low-frequency, high-gain mode (HGO=1) — VDD — V Peak-to-peak amplitude of oscillation (oscillator mode) — high-frequency, low-power mode (HGO=0) — 0.6 — V Peak-to-peak amplitude of oscillation (oscillator mode) — high-frequency, high-gain mode (HGO=1) — VDD — V 1. VDD=3.3 V, Temperature =25 °C 2. See crystal or resonator manufacturer's recommendation

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1. Cx,Cy can be provided by using the integrated capacitors when the low frequency oscillator (RANGE = 00) is used. For all other cases external capacitors must be used. 4. When low power mode is selected, RF is integrated and must not be attached externally. 5. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any other devices.

5.3.3.2.2 Oscillator frequency specifications

Table 51. Oscillator frequency specifications

1. Other frequency limits may apply when external clock is being used as a reference for the FLL
2. When transitioning from FEI or FBI to FBE mode, restrict the frequency of the input clock so that, when it is divided by

FRDIV, it remains within the limits of the DCO input clock frequency.

1. Proper PC board layout procedures must be followed to achieve specifications.
2. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S

5.3.4 Memories and memory interfaces

5.3.4.1 Flash electrical specifications

This section describes the electrical characteristics of the flash memory module. 78 K32 L2B Microcontroller, Rev. 3, 09/2020 NXP Semiconductors

5.3.4.1.1 Flash timing specifications — program and erase

The following specifications represent the amount of time the internal charge pumps are active and do not include command overhead. Table 52. NVM program/erase timing specifications

1. Maximum time based on expectations at cycling end-of-life.

5.3.4.1.2 Flash timing specifications — commands

Table 53. Flash command timing specifications

• 128 KB program flash 1.7 ms trd1sec1k Read 1s Section execution time (flash sector) — — 60 μs 1 tpgmchk Program Check execution time — — 45 μs 1 trdrsrc Read Resource execution time — — 30 μs 1 tpgm4 Program Longword execution time — 65 145 μs — tersblk128k Erase Flash Block execution time
• 128 KB program flash 600 ms tersscr Erase Flash Sector execution time — 14 114 ms 2 trd1all Read 1s All Blocks execution time — — 1.8 ms 1 trdonce Read Once execution time — — 25 μs 1 tpgmonce Program Once execution time — 65 — μs — tersall Erase All Blocks execution time — 175 1300 ms 2 tvfykey Verify Backdoor Access Key execution time — — 30 μs 1 tersallu Erase All Blocks Unsecure execution time — 175 1300 ms 2 1. Assumes 25 MHz flash clock frequency. 2. Maximum times for erase parameters based on expectations at cycling end-of-life.

5.3.4.1.3 Flash high voltage current behaviors

Table 54. Flash high voltage current behaviors Table continues on the next page... K32 L2B Microcontroller, Rev. 3, 09/2020 79 NXP Semiconductors

Table 54. Flash high voltage current behaviors (continued)

5.3.4.1.4 Reliability specifications

Table 55. NVM reliability specifications

1. Typical data retention values are based on measured response accelerated at high temperature and derated to a
2. Cycling endurance represents number of program/erase cycles at –40 °C ≤ Tj ≤ 125 °C.

5.3.5 Security and integrity modules

There are no specifications necessary for the device's security and integrity modules.

5.3.6 Analog

5.3.6.1 ADC electrical specifications

Table 56. 16-bit ADC operating conditions

1.13 VDDA VDDA V 3

Table continues on the next page... 80 K32 L2B Microcontroller, Rev. 3, 09/2020 NXP Semiconductors

Table 56. 16-bit ADC operating conditions (continued)

• All other modes VREFL VREFL 31/32 × VREFH VREFH V — CADIN Input capacitance
• 16-bit mode
• 8-bit / 10-bit / 12-bit modes pF — RADIN Input series resistance — 2 5 kΩ — RAS Analog source resistance (external) 13-bit / 12-bit modes fADCK < 4 MHz kΩ fADCK ADC conversion clock frequency ≤ 13-bit mode 1.0 — 24 MHz 5 fADCK ADC conversion clock frequency 16-bit mode 2.0 — 12.0 MHz 5 Crate ADC conversion rate ≤ 13-bit modes No ADC hardware averaging Continuous conversions enabled, subsequent conversion time 20.000 1200 ksps Crate ADC conversion rate 16-bit mode No ADC hardware averaging Continuous conversions enabled, subsequent conversion time 37.037 461.467 ksps 1. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for reference only, and are not tested in production. 2. DC potential difference. 3. VREFH can act as VREF_OUT when VREFV1 module is enabled. 4. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as possible. The results in this data sheet were derived from a system that had < 8 Ω analog source resistance. The RAS/CAS time constant should be kept to < 1 ns. 5. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear. 6. For guidelines and examples of conversion rate calculation, download the ADC calculator tool.

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Figure 22. ADC input impedance equivalency diagram Table 57. 16-bit ADC characteristics (V REFH = VDDA, VREFL = VSSA)

• ADLPC = 1, ADHSC = 0
• ADLPC = 1, ADHSC = 1
• ADLPC = 0, ADHSC = 0
• ADLPC = 0, ADHSC = 1 1.2 2.4 3.0 4.4 2.4 4.0 5.2 6.2 3.9 6.1 7.3 9.5 MHz MHz MHz MHz tADACK = 1/ fADACK Sample Time See Reference Manual chapter for sample times TUE Total unadjusted error
• 12-bit modes
• <12-bit modes ±1.4 ±6.8 ±2.1 LSB4 5 DNL Differential non- linearity
• 12-bit modes
• <12-bit modes ±0.7 ±0.2 –1.1 to +1.9 –0.3 to 0.5 LSB4 5 INL Integral non-linearity • 12-bit modes
• <12-bit modes ±1.0 ±0.5 –2.7 to +1.9 LSB4 5 Table continues on the next page...

82 K32 L2B Microcontroller, Rev. 3, 09/2020 NXP Semiconductors

Table 57. 16-bit ADC characteristics (V REFH = VDDA, VREFL = VSSA) (continued)

• <12-bit modes –1.4 –5.4 –1.8 LSB4 VADIN = VDDA5 EQ Quantization error • 16-bit modes
• ≤13-bit modes –1 to 0 ±0.5 LSB4 ENOB Effective number of bits 16-bit differential mode
• Avg = 32
• Avg = 4 16-bit single-ended mode
• Avg = 32
• Avg = 4 12.8 11.9 12.2 11.4 14.5 13.8 13.9 13.1 bits bits bits bits SINAD Signal-to-noise plus distortion See ENOB 6.02 × ENOB + 1.76 dB THD Total harmonic distortion 16-bit differential mode
• Avg = 32 16-bit single-ended mode
• Avg = 32 -94 -85 dB dB SFDR Spurious free dynamic range 16-bit differential mode
• Avg = 32 16-bit single-ended mode
• Avg = 32 dB dB EIL Input leakage error IIn × RAS mV IIn = leakage current (refer to the MCU's voltage and current operating ratings) Temp sensor slope Across the full temperature range of the device 1.55 1.62 1.69 mV/°C 8 VTEMP25 Temp sensor voltage 25 °C 706 716 726 mV 8 1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA 2. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and ADC_CFG1[ADLPC] (low power). For lowest power operation, ADC_CFG1[ADLPC] must be set, the ADC_CFG2[ADHSC] bit must be clear with 1 MHz ADC conversion clock speed.

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1. 1 LSB = (VREFH - VREFL)/2N 5. ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11) 6. Input data is 100 Hz sine wave. ADC conversion clock < 12 MHz. 7. Input data is 1 kHz sine wave. ADC conversion clock < 12 MHz. 8. ADC conversion clock < 3 MHz Typical ADC 16-bit Differential ENOB vs ADC Clock 100Hz, 90% FS Sine Input ENOB ADC Clock Frequency (MHz) 15.00 14.70 14.40 14.10 13.80 13.50 13.20 12.90 12.60 12.30 12.00 1 2 3 4 5 6 7 8 9 10 12 11 Hardware Averaging Disabled Averaging of 4 samples Averaging of 8 samples Averaging of 32 samples

Figure 23. Typical ENOB vs. ADC_CLK for 16-bit differential mode Figure 24. Typical ENOB vs. ADC_CLK for 16-bit single-ended mode

5.3.6.2 Voltage reference electrical specifications

84 K32 L2B Microcontroller, Rev. 3, 09/2020 NXP Semiconductors

Table 58. VREF full-range operating requirements

1. CL must be connected to VREF_OUT if the VREF_OUT functionality is being used for either an internal or external
2. The load capacitance should not exceed +/-25% of the nominal specified CL value over the operating temperature

VREF_SC[REGEN] and VREF_SC[ICOMPEN] bits to 1. Table 59. VREF full-range operating behaviors

• current = ± 1.0 mA 200 µV 1, 2 Tstup Buffer startup time — — 100 µs Tchop_osc_st up Internal bandgap start-up delay with chop oscillator enabled — — 35 ms — Vvdrift Voltage drift (Vmax -Vmin across the full voltage range) — 2 — mV 1 1. See the chip's Reference Manual for the appropriate settings of the VREF Status and Control register. 2. Load regulation voltage is the difference between the VREF_OUT voltage with no load vs. voltage with defined load

Table 60. VREF limited-range operating requirements K32 L2B Microcontroller, Rev. 3, 09/2020 85 NXP Semiconductors

Table 61. VREF limited-range operating behaviors

5.3.6.3 CMP and 6-bit DAC electrical specifications

Table 62. Comparator and 6-bit DAC electrical specifications

• CR0[HYSTCTR] = 00
• CR0[HYSTCTR] = 01
• CR0[HYSTCTR] = 10
• CR0[HYSTCTR] = 11 mV mV mV mV VCMPOh Output high VDD – 0.5 — — V VCMPOl Output low — — 0.5 V tDHS Propagation delay, high-speed mode (EN=1, PMODE=1) 20 50 200 ns tDLS Propagation delay, low-speed mode (EN=1, PMODE=0) 80 250 600 ns Analog comparator initialization delay2 — — 40 μs IDAC6b 6-bit DAC current adder (enabled) — 7 — μA INL 6-bit DAC integral non-linearity –0.5 — 0.5 LSB3 DNL 6-bit DAC differential non-linearity –0.3 — 0.3 LSB 1. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD–0.6 V. 2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to CMP_DACCR[DACEN], CMP_DACCR[VRSEL], CMP_DACCR[VOSEL], CMP_MUXCR[PSEL], and CMP_MUXCR[MSEL]) and the comparator output settling to a stable level. 3. 1 LSB = Vreference/64

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0.1 Vin level (V) CMP Hystereris (V) 0.05 0.01 0.02 0.03 0.08 0.07 0.06 0.04 Figure 25. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0) K32 L2B Microcontroller, Rev. 3, 09/2020 87 NXP Semiconductors

0.1 0.02 0.04 0.06 0.18 0.14 0.12 0.08 0.16 Vin level (V) CMP Hysteresis (V) Figure 26. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1) Table 63. 12-bit DAC operating requirements

1. The DAC reference can be selected to be VDDA or VREF_OUT.
2. A small load capacitance (47 pF) can improve the bandwidth performance of the DAC.

88 K32 L2B Microcontroller, Rev. 3, 09/2020 NXP Semiconductors

5.3.6.4.2 12-bit DAC operating behaviors Table 64. 12-bit DAC operating behaviors

• High power (SP HP)
• Low power (SP LP) 1.2 0.05 1.7 0.12 V/μs BW 3dB bandwidth
• High power (SP HP)
• Low power (SP LP) 550 kHz 1. Settling within ±1 LSB 2. The INL is measured for 0 + 100 mV to VDACR −100 mV 3. The DNL is measured for 0 + 100 mV to VDACR −100 mV 4. The DNL is measured for 0 + 100 mV to VDACR −100 mV with VDDA > 2.4 V 5. Calculated by a best fit curve from VSS + 100 mV to VDACR − 100 mV 6. VDDA = 3.0 V, reference select set for VDDA (DACx_CO:DACRFS = 1), high power mode (DACx_C0:LPEN = 0), DAC set to 0x800, temperature range is across the full range of the device

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DAC12 INL (LSB) 500 1000 1500 2000 2500 3000 3500 4000 Figure 27. Typical INL error vs. digital code 90 K32 L2B Microcontroller, Rev. 3, 09/2020 NXP Semiconductors

Temperature °C DAC12 Mid Level Code Voltage 25 55 85 105 125 1.499 -40 1.4985 1.498 1.4975 1.497 1.4965 1.496 Figure 28. Offset at half scale vs. temperature

5.4 Timers

See General switching specifications.

5.5 Communication interfaces

5.5.1 USB electrical specifications

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The IRC48M do not meet the USB jitter specifications for certification for Host mode operation. This device cannot support Host mode operation.

5.5.2 USB VREG electrical specifications

Table 65. USB VREG electrical specifications

• VREGIN = 5.0 V and temperature=25 °C
• Across operating voltage and temperature 650 nA μA ILOADrun Maximum load current — Run mode — — 120 mA ILOADstby Maximum load current — Standby mode — — 1 mA VReg33out Regulator output voltage — Input supply (VREGIN) > 3.6 V
• Run mode
• Standby mode 2.1 3.3 2.8 3.6 3.6 V V VReg33out Regulator output voltage — Input supply (VREGIN) < 3.6 V, pass-through mode 2.1 — 3.6 V 2 COUT External output capacitor 1.76 2.2 8.16 μF ESR External output capacitor equivalent series resistance 1 — 100 mΩ ILIM Short circuit current — 290 — mA 1. Typical values assume VREGIN = 5.0 V, Temp = 25 °C unless otherwise stated. 2. Operating in pass-through mode: regulator output voltage equal to the input voltage minus a drop proportional to ILoad.

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5.5.3 SPI switching specifications

The Serial Peripheral Interface (SPI) provides a synchronous serial bus with master and slave operations. Many of the transfer attributes are programmable. The following tables provide timing characteristics for classic SPI timing modes. See the SPI chapter of the chip's Reference Manual for information about the modified transfer formats used for communicating with slower peripheral devices. All timing is shown with respect to 20% VDD and 80% VDD thresholds, unless noted, as well as input signal transitions of 3 ns and a 30 pF maximum load on all SPI pins. Table 66. SPI master mode timing on slew rate disabled pads

1. For SPI0 fperiph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS).

Table 67. SPI master mode timing on slew rate enabled pads Table continues on the next page... K32 L2B Microcontroller, Rev. 3, 09/2020 93 NXP Semiconductors

Table 67. SPI master mode timing on slew rate enabled pads (continued)

1. For SPI0 fperiph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS).
2. If configured as an output.

Figure 29. SPI master mode timing (CPHA = 0) 94 K32 L2B Microcontroller, Rev. 3, 09/2020 NXP Semiconductors

<<CLASSIFICATION>> <<NDA MESSAGE>> 6 7 MSB IN 2 BIT 6 . . . 1 MASTER MSB OUT 2 MASTER LSB OUT 10 11 PORT DATA PORT DATA 3 10 11 4 1.If configured as output (OUTPUT) (CPOL=0) SPSCK SPSCK (CPOL=1) SS 1 (OUTPUT) (OUTPUT) MOSI (OUTPUT) MISO (INPUT) LSB INBIT 6 . . . 1 Figure 30. SPI master mode timing (CPHA = 1) Table 68. SPI slave mode timing on slew rate disabled pads

1. For SPI0 fperiph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS).
2. Time to data active from high-impedance state
3. Hold time to high-impedance state

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Table 69. SPI slave mode timing on slew rate enabled pads

1. For SPI0 fperiph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS).
2. Time to data active from high-impedance state
3. Hold time to high-impedance state

Figure 31. SPI slave mode timing (CPHA = 0) 96 K32 L2B Microcontroller, Rev. 3, 09/2020 NXP Semiconductors

BIT 6 . . . 1 MSB OUT SLAVE LSB OUT 12 13 3 12 13 SLAVE see note (INPUT) (CPOL=0) SPSCK SPSCK (CPOL=1) SS (INPUT) (INPUT) MOSI (INPUT) MISO (OUTPUT) NOTE: Not defined LSB INBIT 6 . . . 1 Figure 32. SPI slave mode timing (CPHA = 1)

5.5.4 I2C

5.5.4.1 Inter-Integrated Circuit Interface (I2C) timing

Table 70. I2C timing Hold time (repeated) START condition. K32 L2B Microcontroller, Rev. 3, 09/2020 97 NXP Semiconductors

1. The maximum SCL Clock Frequency in Fast mode with maximum bus loading can be achieved only when using the high drive pins across the full voltage range and when using the normal drive pins and VDD ≥ 2.7 V. 2. The master mode I2C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves acknowledge this address byte, then a negative hold time can result, depending on the edge rates of the SDA and SCL lines. 3. The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal. 4. Input signal Slew = 10 ns and Output Load = 50 pF 5. Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty. 6. A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement tSU; DAT ≥ 250 ns must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, then it must output the next data bit to the SDA line trmax + tSU; DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification) before the SCL line is released. 7. Cb = total capacitance of the one bus line in pF.

Table 71. I 2C 1Mbit/s timing period, the first clock pulse is generated.

1. The maximum SCL clock frequency of 1 Mbit/s can support maximum bus loading when using the high drive pins across
2. Cb = total capacitance of the one bus line in pF.

Figure 33. Timing definition for devices on the I2C bus 98 K32 L2B Microcontroller, Rev. 3, 09/2020 NXP Semiconductors

5.5.5 UART

See General switching specifications.

5.6 Human-machine interfaces (HMI)

5.6.1 LCD electrical characteristics

Table 72. LCD electricals

• GCR[FFR]=0
• GCR[FFR]=1 23.3 46.6 73.1 146.2 Hz Hz CLCD LCD charge pump capacitance — nominal value — 100 — nF CBYLCD LCD bypass capacitance — nominal value — 100 — nF 1 CGlass LCD glass capacitance — 2000 8000 pF 2 VIREG VIREG
• RVTRIM=0000
• RVTRIM=1000
• RVTRIM=0100
• RVTRIM=1100
• RVTRIM=0010
• RVTRIM=1010
• RVTRIM=0110
• RVTRIM=1110
• RVTRIM=0001
• RVTRIM=1001
• RVTRIM=0101
• RVTRIM=1101
• RVTRIM=0011
• RVTRIM=1011
• RVTRIM=0111
• RVTRIM=1111 0.91 0.92 0.93 0.94 0.96 0.97 0.98 0.99 1.01 1.02 1.03 1.05 1.06 1.07 1.08 1.09 V 3 ΔRTRIM VIREG TRIM resolution — — 3.0 % VIREG IVIREG VIREG current adder — RVEN = 1 — 1 — µA IRBIAS RBIAS current adder Table continues on the next page...

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Table 72. LCD electricals (continued)

• LADJ = 10 or 11 — High load (LCD glass capacitance ≤ 8000 pF)
• LADJ = 00 or 01 — Low load (LCD glass capacitance ≤ 2000 pF) µA µA RRBIAS RBIAS resistor values
• LADJ = 10 or 11 — High load (LCD glass capacitance ≤ 8000 pF)
• LADJ = 00 or 01 — Low load (LCD glass capacitance ≤ 2000 pF) 0.28 2.98 MΩ MΩ VLL1 VLL1 voltage — — VIREG V 4 VLL2 VLL2 voltage — — 2 x VIREG V 4 VLL3 VLL3 voltage — — 3 x VIREG V 4 VLL1 VLL1 voltage — — VDDA / 3 V 5 VLL2 VLL2 voltage — — VDDA / 1.5 V 5 VLL3 VLL3 voltage — — VDDA V 5 1. The actual value used could vary with tolerance. 2. For highest glass capacitance values, LCD_GCR[LADJ] should be configured as specified in the LCD Controller chapter within the device's reference manual. 3. VIREG maximum should never be externally driven to any level other than VDD - 0.15 V 4. VLL1, VLL2 and VLL3 are a function of VIREG only when the regulator is enabled (GCR[RVEN]=1) and the charge pump is enabled (GCR[CPSEL]=1). 5. VLL1, VLL2 and VLL3 are a function of VDDA only under either of the following conditions:
• The charge pump is enabled (GCR[CPSEL]=1), the regulator is disabled (GCR[RVEN]=0), and VLL3 = V DDA through the internal power switch (GCR[VSUPPLY]=0).
• The resistor bias string is enabled (GCR[CPSEL]=0), the regulator is disabled (GCR[RVEN]=0), and VLL3 is connected to VDDA externally (GCR[VSUPPLY]=1).

6 Design considerations

6.1 Hardware design considerations

voltages higher than maximum-rated voltages to this high-impedance circuit.

6.1.1 Printed circuit board recommendations

• Place connectors or cables on one edge of the board and do not place digital circuits between connectors.
• Drivers and filters for I/O functions must be placed as close to the connectors as possible. Connect TVS devices at the connector to a good ground. Connect filter capacitors at the connector to a good ground. Consider to add ferrite bead or inductor to some sensitive lines.
• Physically isolate analog circuits from digital circuits if possible.
• Place input filter capacitors as close to the MCU as possible.
• For best EMC performance, route signals as transmission lines; use a ground plane directly under LQFP packages; and solder the exposed pad (EP) to ground directly under QFN packages.

6.1.2 Power delivery system

Consider the following items in the power delivery system:

• Use a plane for ground.
• Use a plane for MCU VDD supply if possible.
• Always route ground first, as a plane or continuous surface, and never as sequential segments.
• Always route the power net as star topology, and make each power trace loop as minimum as possible.
• Route power next, as a plane or traces that are parallel to ground traces.
• Place bulk capacitance, 10 μF or more, at the entrance of the power plane.
• Place bypass capacitors for MCU power domain as close as possible to each VDD/VSS pair, including VDDA/VSSA and VREFH/VREFL.
• The minimum bypass requirement is to place 0.1 μF capacitors positioned as near as possible to the package supply pins.
• Take special care to minimize noise levels on the VREFH/VREFL inputs. An option is to use the internal reference voltage (output 1.2 V typically) as the ADC reference. NOTE The internally-generated Voltage Reference Output (VREF_OUT) is bonded to the VREFH pin on some packages and to PTE30 on other packages. When VREF_OUT is used, a 0.1 μF capacitor is required as a filter. Do not connect any other supply voltage to the pin that has VREF_OUT activated. Design considerations K32 L2B Microcontroller, Rev. 3, 09/2020 101 NXP Semiconductors

6.1.3 Analog design

small compared to the sample period. Figure 34. RC circuit for ADC input external clamp diodes must be included to protect against transient over-voltages. Figure 35. High voltage measurement with an ADC input

6.1.4 Digital design

Ensure that all I/O pins cannot get pulled above VDD (Max I/O is VDD+0.3V).

• RESET_b pin The RESET_b pin is an open-drain I/O pin that has an internal pullup resistor. An external RC circuit is recommended to filter noise as shown in the following figure. The resistor value must be in the range of 4.7 kΩ to 10 kΩ; the recommended capacitance value is 0.1 μF. The RESET_b pin also has a selectable digital filter to reject spurious noise. D D C C B B A A EXTAL XTAL OSCILLATOR EXTAL XTAL OSCILLATOR EXTAL XTAL OSCILLATOR EXTAL XTAL OSCILLATOR EXTAL XTAL OSCILLATOR EXTAL XTAL OSCILLATOR MCU ADCx MCU ADCx MCU RESET_b MCU NMI_b MCU RESET_b Supervisor Chip OUT Active high, open drain RESET_b SWD_DIO SWD_CLK Analog input High voltage input RESET_b VDD VDD VDD VDD VDD VDD Drawing Title: Size Document Number Rev Date: Sheet of Page Title: ICAP Classification: FCP: FIUO: PUBI: SCH-XXXXX PDF: SPF-XXXXX X <Title> C Friday, February 06, 2015 <PageTitle> 1 1 Drawing Title: Size Document Number Rev Date: Sheet of Page Title: ICAP Classification: FCP: FIUO: PUBI: SCH-XXXXX PDF: SPF-XXXXX X <Title> C Friday, February 06, 2015 <PageTitle> 1 1 Drawing Title: Size Document Number Rev Date: Sheet of Page Title: ICAP Classification: FCP: FIUO: PUBI: SCH-XXXXX PDF: SPF-XXXXX X <Title> C Friday, February 06, 2015 <PageTitle> 1 1 R 1 2 0.1uF 1 2 Cx 0.1uF RESONATOR 1 3 Cy Cx CRYSTAL HDR_5X2 1 2 3 4 7 8 9 10 Cy 10k 10k CRYSTAL 0.1uF 10k CRYSTAL 1 2 1 2 C RESONATOR 1 3 1 2 10k 10k RF 1 2 RS BAT54SW 1 2 RS RS C RF 1 2 RS 1 2 RF 1 2 CRYSTAL

Figure 36. Reset circuit the range of 100 Ω to 1 kΩ depending on the external reset chip drive strength. Select the open-drain output from the supervisor chip.

Figure 39. SWD debug interface

• Low leakage stop mode wakeup Select low leakage wakeup pins (LLWU_Px) to wake the MCU from one of the low leakage stop modes (LLS/VLLSx). See the pinout table for pin selection.
• Unused pin Unused GPIO pins must be left floating (no electrical connections) with the MUX field of the pin’s PORTx_PCRn register equal to 0:0:0. This disables the digital input path to the MCU. If the USB module is not used, leave the USB data pins (USB0_DP, USB0_DM) floating.

6.1.5 Crystal oscillator

MCU clock system, refer to the following table and diagrams. The feedback resistor, RF, is incorporated internally with the low power oscillators. An external feedback is required when using high gain (HGO=1) mode. used for high frequency crystals and resonators.

Figure 43. Crystal connection – Diagram 4

6.2 Software considerations

market. Featured software and tools are listed below.

• NXP Freedom Development Platform: http://www.nxp.com/freedom
• Tower System Development Platform: http://www.nxp.com/tower IDEs for K32 L2B MCUs
• MCUXpresso: https://mcuxpresso.nxp.com Run-time Software
• K32 L2B SDK: http://mcuxpresso.nxp.com For all other partner-developed software and tools, visit http://www.nxp.com/partners.

7 Part identification

7.1 Description

values of these fields to determine the specific part you have received.

7.2 Format

7.3 Fields

Table 74. Part number fields descriptions

• B= Sub-family B FS Flash size • 1 = 64 KB
• 2 = 128 KB
• 3 = 256 KB
• 4 = 512 KB SPF Special Feature • 0 = Dual core
• 1 = Single core T Temperature range (°C) • V = -40 to 105
• FT = 48 QFN
• MP = 64 BGA
• LH = 64 LQFP FR Frequency (MHz) • 0 = 0 - 50 MHz SR Silicon Revision • A = Initial Mask Set
• B = 1 st Major Spin PT Packaging Type • R = Std Reel Part identification 108 K32 L2B Microcontroller, Rev. 3, 09/2020 NXP Semiconductors

7.4 Example

This is an example part number: K32L2B31VLH0A

8 Small package marking

In order to save space, small package devices use special marking on the chip. Q FS FF TP Field Description Values Q Qualification status K=M PK=P FS Family L2B=K32L2B family FF Program flash memory size 6=64 KB 7=128 KB 8=256 KB TP Temperature range V=-40 to 105 for all 4 packages For example: KL2B6V = K32L2B11VFM0A

9 Package marking information

The K32L2B 64LQFP package has the following top-side marking:

• First line: aaaaaaaa
• Second line: aaaaa
• Third line: mmmmm
• Fourth line: xxxyywwx The K32L2B 64MAPBGA package has the following top-side marking:
• First line: aaaaaa
• Second line: mmmmm
• Third line: xxywx The K32L2B 48QFN package has the following top-side marking: Small package marking K32 L2B Microcontroller, Rev. 3, 09/2020 109 NXP Semiconductors

• First line: aaaaaa
• Second line: mmmmm
• Third line: xxywx The K32L2B 32QFN package has the following top-side marking:
• First line: aaaaaa
• Second line: mmmmm
• Third line: xxywx The detailed code format for these identifiers is show in the table below. Identifier Description a Part number code, refer to the "Part identification" section. m Mask set y Work year w Work week x NXP internal use The following table provides a revision history for this document.

Table 75. Revision History

3 September

• Updated value of ADC to 461 ksps from 818 in front page of the Data sheet.
• Removed "RESET_b" from ALT7 column and "PTA20" from ALT1 column corresponding to PTA20 pin in K32 L2B Signal Multiplexing and Pin Assignments (LQFP and MAPBGA) and K32 L2B Signal Multiplexing and Pin Assignments (QFN). Also added the following note: When FTFA_FOPT[RESET_PIN_CONFIG]=0, PTA20 value.
• Added Package marking information and Small package marking.
• Removed "OTG/On the Go" references.

2 December

• Added Related Resources table in front page of the Data sheet.
• Corrected description of PD/PU in Table 8 Pin Properties section.
• Updated values in "Default" column for pins 1, 2, 9, 10, 49-52 in K32 L2B Signal Multiplexing and Pin Assignments (LQFP and MAPBGA).
• Added EXTRG_IN signal in TPM signal descriptions and Table 29.

1 September

• Removed support of CRC throughout.
• Replaced name of function pin VREFO with VREF_OUT.
• Changed the high drive pin number to 6 for 48 QFN in Ordering information.
• Updated flash and RAM in Figure 1. System diagram in the Overview section. Table continues on the next page...

Revision History

110 K32 L2B Microcontroller, Rev. 3, 09/2020 NXP Semiconductors

Table 75. Revision History (continued)

• Added DAC topic to the "Peripheral Features" section.
• Updated memory addresses and peripherals in Memory map.
• Updated 32 QFN and 48 QFN pinouts and diagrams to remove usage of USB_VDD pin.
• Updated pin names in Pin properties. Split the table into two, each for 64 LQFP/ MAPBGA and 32/48 QFN packages.
• Added thermal attributes for 32 QFN and 48 QFN packages in Thermal attributes.
• Updated part number format and fields in Format and Fields. 0 July 2019 • Initial release (internal).

K32 L2B Microcontroller, Rev. 3, 09/2020 111 NXP Semiconductors

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