K30P100M100SF2

K30P100M100SF2 FREESCALE | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 61

Technical content

Features

• Operating Characteristics – Voltage range: 1.71 to 3.6 V Flash write voltage range: 1.71 to 3.6 V – Temperature range (ambient): -40 to 105°C
• Performance – Up to 100 MHz ARM Cortex-M4 core with DSP instructions delivering 1.25 Dhrystone MIPS per MHz
• Memories and memory interfaces – Up to 512 KB program flash memory on non- FlexMemory devices – Up to 128 KB RAM – Serial programming interface (EzPort)
• Clocks – 3 to 32 MHz crystal oscillator – 32 kHz crystal oscillator – Multi-purpose clock generator
• System peripherals – 10 low-power modes to provide power optimization based on application requirements – Memory protection unit with multi-master protection – 16-channel DMA controller, supporting up to 64 request sources – External watchdog monitor – Software watchdog – Low-leakage wakeup unit
• Security and integrity modules – Hardware CRC module to support fast cyclic redundancy checks – 128-bit unique identification (ID) number per chip
• Human-machine interface – Segment LCD controller supporting up to 40 frontplanes and 8 backplanes, or 44 frontplanes and 4 backplanes Low-power hardware touch sensor interface (TSI) – General-purpose input/output
• Analog modules – Two 16-bit SAR ADCs – Programmable gain amplifier (up to x64) integrated into each ADC – 12-bit DAC – Three analog comparators (CMP) containing a 6-bit DAC and programmable reference input – Voltage reference
• Timers – Programmable delay block – Eight-channel motor control/general purpose/PWM timer – Two 2-channel quadrature decoder/general purpose timers – Periodic interrupt timers – 16-bit low-power timer – Carrier modulator transmitter – Real-time clock
• Communication interfaces – Two Controller Area Network (CAN) modules – Three SPI modules – Two I2C modules – Five UART modules – Secure Digital host controller (SDHC) – I2S module Freescale Semiconductor Document Number: K30P100M100SF2 Data Sheet: Product Preview Rev. 4, 3/2011 This document contains information on a product under development. Freescale reserves the right to change or discontinue this product without notice. © 2010–2011 Freescale Semiconductor, Inc. Preliminary

3.6 Relationship between ratings and operating

6.8.2 DSPI switching specifications (low-speed mode)..46

6.8.3 DSPI switching specifications (high-speed mode) 47

K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. 2 Preliminary Freescale Semiconductor, Inc.

1 Ordering parts

1.1 Determining valid orderable parts

Valid orderable part numbers are provided on the web. To determine the orderable part numbers for this device, go to http://www.freescale.com and perform a part number search for the following device numbers: PK30 and MK30.

2 Part identification

2.1 Description

Part numbers for the chip have fields that identify the specific part. You can use the values of these fields to determine the specific part you have received.

2.2 Format

Part numbers for this device have the following format: Q K## M FFF T PP CCC N

2.3 Fields

This table lists the possible values for each field in the part number (not all combinations are valid): Field Description Values Q Qualification status • M = Fully qualified, general market flow

• P = Prequalification K## Kinetis family • K30 M Flash memory type • N = Program flash only
• X = Program flash and FlexMemory Table continues on the next page... Ordering parts K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Preliminary 3

FFF Program flash memory size • 32 = 32 KB

• 64 = 64 KB
• 128 = 128 KB
• 256 = 256 KB
• 512 = 512 KB
• 1M0 = 1 MB T Temperature range (°C) • V = –40 to 105
• C = –40 to 85
• FT = 48 QFN (7 mm x 7 mm)
• LF = 48 LQFP (7 mm x 7 mm)
• EX = 64 QFN (9 mm x 9 mm)
• LH = 64 LQFP (10 mm x 10 mm)
• LK = 80 LQFP (12 mm x 12 mm)
• MB = 81 MAPBGA (8 mm x 8 mm)
• LL = 100 LQFP (14 mm x 14 mm)
• MC = 121 MAPBGA (8 mm x 8 mm)
• LQ = 144 LQFP (20 mm x 20 mm)
• MD = 144 MAPBGA (13 mm x 13 mm)
• MF = 196 MAPBGA (15 mm x 15 mm)
• MJ = 256 MAPBGA (17 mm x 17 mm) CCC Maximum CPU frequency (MHz) • 50 = 50 MHz
• 72 = 72 MHz
• 100 = 100 MHz
• 120 = 120 MHz
• 150 = 150 MHz N Packaging type • R = Tape and reel
• (Blank) = Trays

2.4 Example

This is an example part number: MK30N512VMD100

3 Terminology and guidelines

3.1 Definition: Operating requirement

An operating requirement is a specified value or range of values for a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useful life of the chip. Terminology and guidelines K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. 4 Preliminary Freescale Semiconductor, Inc.

3.1.1 Example

This is an example of an operating requirement, which you must meet for the accompanying operating behaviors to be guaranteed: Symbol Description Min. Max. Unit VDD 1.0 V core supply voltage 0.9 1.1 V

3.2 Definition: Operating behavior

An operating behavior is a specified value or range of values for a technical characteristic that are guaranteed during operation if you meet the operating requirements and any other specified conditions.

3.2.1 Example

This is an example of an operating behavior, which is guaranteed if you meet the accompanying operating requirements: Symbol Description Min. Max. Unit IWP Digital I/O weak pullup/ pulldown current 10 130 µA

3.3 Definition: Attribute

An attribute is a specified value or range of values for a technical characteristic that are guaranteed, regardless of whether you meet the operating requirements.

3.3.1 Example

This is an example of an attribute: Symbol Description Min. Max. Unit CIN_D Input capacitance: digital pins — 7 pF Terminology and guidelines K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Preliminary 5

3.4 Definition: Rating

A rating is a minimum or maximum value of a technical characteristic that, if exceeded, may cause permanent chip failure:

• Operating ratings apply during operation of the chip.
• Handling ratings apply when the chip is not powered.

3.4.1 Example

This is an example of an operating rating: Symbol Description Min. Max. Unit VDD 1.0 V core supply voltage –0.3 1.2 V

3.5 Result of exceeding a rating

Failures in time (ppm) The likelihood of permanent chip failure increases rapidly as soon as a characteristic begins to exceed one of its operating ratings. Terminology and guidelines K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. 6 Preliminary Freescale Semiconductor, Inc.

3.6 Relationship between ratings and operating requirements

• No permanent failure - Correct operation Normal operating range Limited operating range - No permanent failure - Possible decreased life - Possible incorrect operation Fatal range - Probable permanent failure Limited operating range - No permanent failure - Possible decreased life - Possible incorrect operation Handling range - No permanent failure Fatal range - Probable permanent failure Operating or handling rating (max.)Operating requirement (max.)Operating requirement (min.)Operating or handling rating (min.)

3.7 Guidelines for ratings and operating requirements

Follow these guidelines for ratings and operating requirements:

• Never exceed any of the chip’s ratings.
• During normal operation, don’t exceed any of the chip’s operating requirements.
• If you must exceed an operating requirement at times other than during normal operation (for example, during power sequencing), limit the duration as much as possible.

3.8 Definition: Typical value

A typical value is a specified value for a technical characteristic that:

• Lies within the range of values specified by the operating behavior
• Given the typical manufacturing process, is representative of that characteristic during operation when you meet the typical-value conditions or other specified conditions Typical values are provided as design guidelines and are neither tested nor guaranteed.

3.8.1 Example 1

This is an example of an operating behavior that includes a typical value: Terminology and guidelines K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Preliminary 7

Symbol Description Min. Typ. Max. Unit IWP Digital I/O weak pullup/pulldown current 10 70 130 µA

3.8.2 Example 2

This is an example of a chart that shows typical values for various voltage and temperature conditions: 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 150 °C 105 °C 25 °C –40 °C VDD (V) I (μA)DD_STOP TJ

3.9 Typical value conditions

Typical values assume you meet the following conditions (or other conditions as specified): Symbol Description Value Unit TA Ambient temperature 25 °C VDD 3.3 V supply voltage 3.3 V

4 Ratings

K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. 8 Preliminary Freescale Semiconductor, Inc.

4.1 Thermal handling ratings

Symbol Description Min. Max. Unit Notes TSTG Storage temperature –55 150 °C 1 TSDR Solder temperature, lead-free — 260 °C 2 Solder temperature, leaded — 245 1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life. 2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices.

4.2 Moisture handling ratings

Symbol Description Min. Max. Unit Notes MSL Moisture sensitivity level — 3 — 1 1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices.

4.3 ESD handling ratings

Symbol Description Min. Max. Unit Notes VHBM Electrostatic discharge voltage, human body model -2000 +2000 V 1 VCDM Electrostatic discharge voltage, charged-device model -500 +500 V 2 ILAT Latch-up current at ambient temperature of 85°C -100 +100 mA 1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM). 2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.

4.4 Voltage and current operating ratings

Symbol Description Min. Max. Unit VDD Digital supply voltage –0.3 3.8 V IDD Digital supply current — 185 mA VDIO Digital input voltage (except RESET, EXTAL, and XTAL) –0.3 5.5 V Table continues on the next page... Ratings K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Preliminary 9

5 General

5.1 Nonswitching electrical specifications

5.1.1 Voltage and current operating requirements

Table 1. Voltage and current operating requirements

• 2.7 V ≤ V DD ≤ 3.6 V
• 1.7 V ≤ V DD ≤ 2.7 V 0.7 × VDD 0.75 × VDD V V VIL Input low voltage
• 2.7 V ≤ V DD ≤ 3.6 V
• 1.7 V ≤ V DD ≤ 2.7 V 0.35 × VDD 0.3 × VDD V V VHYS Input hysteresis 0.06 × VDD — V IIC DC injection current — single pin
• V IN < VSS –0.2 mA DC injection current — total MCU limit, includes sum of all stressed pins
• V IN < VSS mA VRAM VDD voltage required to retain RAM 1.2 — V VRFVBAT VBAT voltage required to retain the VBAT register file TBD — V General K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. 10 Preliminary Freescale Semiconductor, Inc.

1. All functional non-supply pins are internally clamped to VSS, and induce an injection current when VIN is less than VSS. The

limited to the value specified.

5.1.2 LVD and POR operating requirements

Table 2. V DD supply LVD and POR operating requirements

• Level 1 falling (LVWV=00)
• Level 2 falling (LVWV=01)
• Level 3 falling (LVWV=10)
• Level 4 falling (LVWV=11) TBD TBD TBD TBD 2.70 2.80 2.90 3.00 TBD TBD TBD TBD V V V V VHYSH Low-voltage inhibit reset/recover hysteresis — high range 60 mV VLVDL Falling low-voltage detect threshold — low range (LVDV=00) TBD 1.60 TBD V VLVW1L VLVW2L VLVW3L VLVW4L Low-voltage warning thresholds — low range
• Level 1 falling (LVWV=00)
• Level 2 falling (LVWV=01)
• Level 3 falling (LVWV=10)
• Level 4 falling (LVWV=11) TBD TBD TBD TBD 1.80 1.90 2.00 2.10 TBD TBD TBD TBD V V V V VHYSL Low-voltage inhibit reset/recover hysteresis — low range 40 mV VBG Bandgap voltage reference TBD 1.00 TBD V tLPO Internal low power oscillator period factory trimmed TBD 1000 TBD μs 1. Rising thresholds are falling threshold + hysteresis voltage

Table 3. VBAT power operating requirements K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.

5.1.3 Voltage and current operating behaviors

Table 4. Voltage and current operating behaviors

• 2.7 V ≤ V DD ≤ 3.6 V, IOH = -10mA
• 1.71 V ≤ V DD ≤ 2.7 V, IOH = -3mA VDD – 0.5 VDD – 0.5 V V Output high voltage — low drive strength
• 2.7 V ≤ V DD ≤ 3.6 V, IOH = -2mA
• 1.71 V ≤ V DD ≤ 2.7 V, IOH = -0.6mA VDD – 0.5 VDD – 0.5 V V IOHT Output high current total for all ports — 100 mA VOL Output low voltage — high drive strength
• 2.7 V ≤ V DD ≤ 3.6 V, IOL = 10mA
• 1.71 V ≤ V DD ≤ 2.7 V, IOL = 3mA 0.5 0.5 V V Output low voltage — low drive strength
• 2.7 V ≤ V DD ≤ 3.6 V, IOL = 2mA
• 1.71 V ≤ V DD ≤ 2.7 V, IOL = 0.6mA 0.5 0.5 V V IOLT Output low current total for all ports — 100 mA IIN Input leakage current (per pin) — 1 μA 1 IOZ Hi-Z (off-state) leakage current (per pin) — 1 μA RPU Internal pullup resistors 30 50 kΩ 2 RPD Internal pulldown resistors 30 50 kΩ 3 1. Measured at VDD=3.6V 2. Measured at VDD supply voltage = VDD min and Vinput = VSS 3. Measured at VDD supply voltage = VDD min and Vinput = VDD

5.1.4 Power mode transition operating behaviors

• CPU and system clocks = 100 MHz
• Bus clock = 50 MHz
• Flash clock = 25 MHz General K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. 12 Preliminary Freescale Semiconductor, Inc.

Table 5. Power mode transition operating behaviors across the operating temperature range of the chip.

• RUN → VLLS1
• VLLS1 → RUN 4.1 123.8 μs μs RUN → VLLS2 → RUN
• RUN → VLLS2
• VLLS2 → RUN 4.1 49.3 μs μs RUN → VLLS3 → RUN
• RUN → VLLS3
• VLLS3 → RUN 4.1 49.2 μs μs RUN → LLS → RUN
• RUN → LLS
• LLS → RUN 4.1 5.9 μs μs RUN → STOP → RUN
• RUN → STOP
• STOP → RUN 4.1 4.2 μs μs RUN → VLPS → RUN
• RUN → VLPS
• VLPS → RUN 4.1 5.8 μs μs 1. Normal boot (FTFL_OPT[LPBOOT]=1)

5.1.5 Power consumption operating behaviors

Table 6. Power consumption operating behaviors

• @ 1.8V
• @ 3.0V TBD TBD mA mA Table continues on the next page... General K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Preliminary 13

Table 6. Power consumption operating behaviors (continued)

• @ 1.8V
• @ 3.0V TBD TBD mA mA IDD_RUN_M AX Run mode current — all peripheral clocks enabled and peripherals active, code executing from flash
• @ 1.8V
• @ 3.0V TBD TBD mA mA IDD_WAIT Wait mode high frequency current at 3.0 V — all peripheral clocks disabled — 35 TBD mA 2 IDD_WAIT Wait mode reduced frequency current at 3.0 V — all peripheral clocks disabled — 15 TBD mA 5 IDD_STOP Stop mode current at 3.0 V — 0.4 TBD mA IDD_VLPR Very-low-power run mode current at 3.0 V — all peripheral clocks disabled — 1.25 TBD mA 6 IDD_VLPR Very-low-power run mode current at 3.0 V — all peripheral clocks enabled — TBD TBD mA 7 IDD_VLPW Very-low-power wait mode current at 3.0 V — 1.05 TBD mA 8 IDD_VLPS Very-low-power stop mode current at 3.0 V — 50 TBD μA IDD_LLS Low leakage stop mode current at 3.0 V — 12 TBD μA IDD_VLLS3 Very low-leakage stop mode 3 current at 3.0 V
• 128KB RAM devices TBD μA IDD_VLLS2 Very low-leakage stop mode 2 current at 3.0 V — 4 TBD μA IDD_VLLS1 Very low-leakage stop mode 1 current at 3.0 V — 2 TBD μA IDD_VBAT Average current when CPU is not accessing RTC registers at 3.0 V — 550 TBD nA 9 1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See each module's specification for its supply current. 2. 100MHz core and system clock, 50MHz bus clock, and 25MHz flash clock . MCG configured for FEI mode. All peripheral clocks disabled. 3. 100MHz core and system clock, 50MHz bus clock, and 25MHz flash clock. MCG configured for FEI mode. All peripheral clocks enabled, but peripherals are not in active operation. 4. 100MHz core and system clock, 50MHz bus clock, and 25MHz flash clock. MCG configured for FEI mode. All peripheral clocks enabled, and peripherals are in active operation. 5. 25MHz core and system clock, 25MHz bus clock, and 12.5MHz flash clock. MCG configured for FEI mode. 6. 2 MHz core, system, and bus clock and 1MHz flash clock. MCG configured for fast IRCLK mode. All peripheral clocks disabled. Code executing from flash. 7. 2 MHz core, system, and bus clock and 1MHz flash clock. MCG configured for fast IRCLK mode. All peripheral clocks enabled but peripherals are not in active operation. Code executing from flash. 8. 2 MHz core, system, and bus clock and 1MHz flash clock. MCG configured for fast IRCLK mode. All peripheral clocks disabled. 9. Includes 32kHz oscillator current and RTC operation. General K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. 14 Preliminary Freescale Semiconductor, Inc.

5.1.5.1 Diagram: Typical IDD_RUN operating behavior

• MCG in FEI mode (39.0625 kHz IRC), except for 1 MHz core (FBE)
• All peripheral clocks disabled except FTFL
• LVD disabled
• No GPIOs toggled
• Code execution from flash

Figure 1. Run mode supply current vs. core frequency — all peripheral clocks disabled

• MCG in FEI mode (39.0625 kHz IRC), except for 1 MHz core (FBE)
• All peripheral clocks enabled but peripherals are not in active operation
• LVD disabled
• No GPIOs toggled
• Code execution from flash General K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Preliminary 15

Figure 2. Run mode supply current vs. core frequency — all peripheral clocks enabled

5.1.6 EMC radiated emissions operating behaviors

Table 7. EMC radiated emissions operating behaviors

1. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions, 150

Wideband TEM (GTEM) Cell Method. K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. 16 Preliminary Freescale Semiconductor, Inc.

1. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and Wideband

Circuits—TEM/Wideband TEM (GTEM) Cell Method.

5.1.7 Designing with radiated emissions in mind

1. Go to http://www.freescale.com.
2. Perform a keyword search for “EMC design.”

5.1.8 Capacitance attributes

Table 8. Capacitance attributes

5.2 Switching specifications

5.2.1 Device clock specifications

K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.

5.2.2 General switching specifications

• Slew disabled
• Slew enabled ns ns Port rise and fall time (low drive strength)
• Slew disabled
• Slew enabled ns ns 1. The greater synchronous and asynchronous timing must be met. 2. This is the shortest pulse that is guaranteed to be recognized. 3. 75pF load 4. 15pF load

5.3 Thermal specifications

5.3.1 Thermal operating requirements

Table 9. Thermal operating requirements K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. 18 Preliminary Freescale Semiconductor, Inc.

5.3.2 Thermal attributes

RθJMA Thermal resistance, junction to ambient (200 ft./min. RθJMA Thermal resistance, junction to ambient (200 ft./min.

1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental

Environmental Conditions—Forced Convection (Moving Air).

6 Peripheral operating requirements and behaviors

• have C L=30pF loads,
• are configured for fast slew rate (PORTx_PCRn[SRE]=0), and
• are configured for high drive strength (PORTx_PCRn[DSE]=1) 2. input pins
• have their passive filter disabled (PORTx_PCRn[PFE]=0)

6.1 Core modules

6.1.1 Debug trace timing specifications

Table 10. Debug trace operating behaviors Table continues on the next page... K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.

Table 10. Debug trace operating behaviors (continued) Figure 3. TRACE_CLKOUT specifications Figure 4. Trace data specifications

6.1.2 JTAG electricals

Table 11. JTAG limited voltage range electricals

• Boundary Scan
• JTAG and CJTAG
• Serial Wire Debug MHz J2 TCLK cycle period 1/J1 — ns Table continues on the next page... Peripheral operating requirements and behaviors K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. 20 Preliminary Freescale Semiconductor, Inc.

Table 11. JTAG limited voltage range electricals (continued)

• Boundary Scan
• JTAG and CJTAG
• Serial Wire Debug ns J4 TCLK rise and fall times — 3 ns J5 Boundary scan input data setup time to TCLK rise 20 — ns J6 Boundary scan input data hold time after TCLK rise 0 — ns J7 TCLK low to boundary scan output data valid — 25 ns J8 TCLK low to boundary scan output high-Z — 25 ns J9 TMS, TDI input data setup time to TCLK rise 8 — ns J10 TMS, TDI input data hold time after TCLK rise 1 — ns J11 TCLK low to TDO data valid — 17 ns J12 TCLK low to TDO high-Z — 17 ns J13 TRST assert time 100 — ns J14 TRST setup time (negation) to TCLK high 8 — ns

Table 12. JTAG full voltage range electricals

• Boundary Scan
• JTAG and CJTAG
• Serial Wire Debug MHz J2 TCLK cycle period 1/J1 — ns J3 TCLK clock pulse width
• Boundary Scan
• JTAG and CJTAG
• Serial Wire Debug 12.5 ns J4 TCLK rise and fall times — 3 ns J5 Boundary scan input data setup time to TCLK rise 20 — ns J6 Boundary scan input data hold time after TCLK rise 0 — ns J7 TCLK low to boundary scan output data valid — 25 ns J8 TCLK low to boundary scan output high-Z — 25 ns J9 TMS, TDI input data setup time to TCLK rise 8 — ns Table continues on the next page... Peripheral operating requirements and behaviors K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Preliminary 21

Figure 7. Test Access Port timing Figure 8. TRST timing

6.2 System modules

There are no specifications necessary for the device's system modules.

6.3 Clock modules

K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.

6.3.1 MCG specifications

Table 13. MCG specifications Table continues on the next page... K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. 24 Preliminary Freescale Semiconductor, Inc.

Table 13. MCG specifications (continued)

• PLL @ 96 MHz (f osc_hi_1=8MHz, fpll_ref=2MHz, VDIV multiplier=48) — 950 — µA 8 fpll_ref PLL reference frequency range 2.0 — 4.0 MHz Jcyc_pll PLL period jitter — 400 — ps 9, 10 Jacc_pll PLL accumulated jitter over 1µs window — TBD — ps 9, 10 Dlock Lock entry frequency tolerance ± 1.49 — ± 2.98 % Dunl Lock exit frequency tolerance ± 4.47 — ± 5.97 % tpll_lock Lock detector detection time — — 0.15 + 1075(1/ fpll_ref) ms 11 1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock mode). 2. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0. 3. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency deviation (Δfdco_t) over voltage and temperature should be considered. 4. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1. 5. The resulting clock frequency must not exceed the maximum specified clock frequency of the device. 6. This specification was obtained at TBD frequency. 7. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed, DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running. 8. Excludes any oscillator currents that are also consuming power while PLL is in operation. 9. This specification was obtained using a Freescale developed PCB. PLL jitter is dependent on the noise characteristics of each PCB and results will vary. 10. This specification was obtained at internal frequency of TBD. 11. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled (BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes it is already running. Peripheral operating requirements and behaviors K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Preliminary 25

6.3.2 Oscillator electrical specifications

This section provides the electrical characteristics of the module.

6.3.2.1 Oscillator DC electrical specifications

Table 14. Oscillator DC electrical specifications

• 32 kHz
• 4 MHz
• 8 MHz
• 16 MHz
• 24 MHz
• 32 MHz 500 200 300 700 1.2 1.5 nA μA μA μA mA mA IDDOSC Supply current — high gain mode (HGO=1)
• 32 kHz
• 4 MHz
• 8 MHz
• 16 MHz
• 24 MHz
• 32 MHz 400 800 1.5 μA μA μA mA mA mA Cx EXTAL load capacitance — — — 2, 3 Cy XTAL load capacitance — — — 2, 3 RF Feedback resistor — low-frequency, low-power mode (HGO=0) — — — MΩ 2, 4 Feedback resistor — low-frequency, high-gain mode (HGO=1) — 10 — MΩ Feedback resistor — high-frequency, low-power mode (HGO=0) — — — MΩ Feedback resistor — high-frequency, high-gain mode (HGO=1) — 1 — MΩ Table continues on the next page... Peripheral operating requirements and behaviors K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. 26 Preliminary Freescale Semiconductor, Inc.

Table 14. Oscillator DC electrical specifications (continued)

1. VDD=3.3 V, Temperature =25 °C
2. See crystal or resonator manufacturer's recommendation
3. Cx,Cy can be provided by using either the integrated capacitors or by using external components.
4. When low power mode is selected, RF is integrated and must not be attached externally.
5. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any

6.3.2.2 Oscillator frequency specifications

Table 15. Oscillator frequency specifications Table continues on the next page... K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.

Table 15. Oscillator frequency specifications (continued)

1. Other frequency limits may apply when external clock is being used as a reference for the FLL or PLL
2. Proper PC board layout procedures must be followed to achieve specifications.
3. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S register

This section describes the module electrical characteristics. Table 16. 32kHz oscillator DC electrical specifications Table 17. 32kHz oscillator frequency specifications

1. Proper PC board layout procedures must be followed to achieve specifications.

6.4 Memories and memory interfaces

K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. 28 Preliminary Freescale Semiconductor, Inc.

6.4.1 Flash (FTFL) electrical specifications

This section describes the electrical characteristics of the FTFL module.

6.4.1.1 Flash timing specifications — program and erase

active and do not include command overhead. Table 18. NVM program/erase timing specifications

1. Maximum time based on expectations at cycling end-of-life.

6.4.1.2 Flash timing specifications — commands

Table 19. Flash command timing specifications

• 256 KB data flash 1.4 ms trd1sec2k Read 1s Section execution time (flash sector) — — 40 μs 1 tpgmchk Program Check execution time — — 35 μs 1 trdrsrc Read Resource execution time — — 35 μs 1 tpgm4 Program Longword execution time — 50 TBD μs tersblk256k Erase Flash Block execution time
• 256 KB data flash 160 800 ms tersscr Erase Flash Sector execution time — 20 100 ms 2 tpgmsec512 tpgmsec1k tpgmsec2k Program Section execution time
• 512 B flash
• 1 KB flash
• 2 KB flash TBD TBD TBD TBD TBD TBD ms ms ms trd1all Read 1s All Blocks execution time — — 2.8 ms trdonce Read Once execution time — — 35 μs 1 tpgmonce Program Once execution time — 50 TBD μs Table continues on the next page... Peripheral operating requirements and behaviors K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Preliminary 29

Table 19. Flash command timing specifications (continued)

1. Assumes 25MHz flash clock frequency.
2. Maximum times for erase parameters based on expectations at cycling end-of-life.

6.4.1.3 Flash (FTFL) current and power specfications

Table 20. Flash (FTFL) current and power specfications

6.4.1.4 Reliability specifications

Table 21. NVM reliability specifications

1. Typical data retention values are based on intrinsic capability of the technology measured at high temperature derated to
2. Data retention is based on Tjavg = 55°C (temperature profile over the lifetime of the application).
3. Cycling endurance represents number of program/erase cycles at -40°C ≤ Tj ≤ 125°C.

6.4.2 EzPort Switching Specifications

Table 22. EzPort switching specifications Table continues on the next page... K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. 30 Preliminary Freescale Semiconductor, Inc.

Table 22. EzPort switching specifications (continued) Figure 9. EzPort Timing Diagram

6.5 Security and integrity modules

There are no specifications necessary for the device's security and integrity modules.

6.6 Analog

6.6.1 ADC electrical specifications

K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.

Table 23. 16-bit ADC operating conditions

1.13 VDDA VDDA V

• 16 bit modes
• 8/10/12 bit modes pF RADIN Input resistance — 2 5 kΩ RAS Analog source resistance 13/12 bit modes fADCK < 4MHz kΩ fADCK ADC conversion clock frequency ≤13 bit modes 1.0 18.0 MHz fADCK ADC conversion clock frequency 16 bit modes 2.0 12.0 MHz Crate ADC conversion rate ≤13 bit modes No ADC hardware averaging Continuous conversions enabled Peripheral clock = 50MHz 18.484 818.330 Ksps Table continues on the next page... Peripheral operating requirements and behaviors K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. 32 Preliminary Freescale Semiconductor, Inc.

Table 23. 16-bit ADC operating conditions (continued)

1. Typical values assume VDDA = 3.0 V, Temp = 25°C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for

reference only and are not tested in production.

1. This resistance is external to MCU. The analog source resistance should be kept as low as possible in order to achieve the

CAS time constant should be kept to <1ns.

1. In order to use the maximum ADC conversion clock frequency ADHSC bit should be set and the ADLPC should be clear.
2. In order to use the maximum ADC conversion clock frequency ADHSC bit should be set and the ADLPC should be clear.
3. For guidelines and examples of conversion rate calculation please download the ADC calculator tool http://
4. For guidelines and examples of conversion rate calculation please download the ADC calculator tool http://

Figure 10. ADC input impedance equivalency diagram K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.

Table 24. 16-bit ADC characteristics (V REFH = VDDA, VREFL = VSSA)

• ADLPC=1, ADHSC=0
• ADLPC=1, ADHSC=1
• ADLPC=0, ADHSC=0
• ADLPC=0, ADHSC=1 2.4 4.0 5.2 6.2 MHz MHz MHz MHz tADACK = 1/ fADACK Sample Time See Reference Manual chapter for sample times Conversion Time The ADC calculator tool can be used to determine ADC conversion times for different ADC configurations: http://cache.freescale.com/files/soft_dev_tools/software/app_software/ converters/ADC_CALCULATOR_CNV.zip?fpsp=1 TUE Total unadjusted error
• ≤13 bit modes
• <12 bit modes ±0.8 ±0.5 ±TBD LSB4 ADC conversion clock <12MHz, Max hardware averaging (AVGE = %1, AVGS = %11) DNL Differential non- linearity
• ≤13 bit modes
• <12 bit modes ±0.7 ±0.2 ±TBD ±0.5 LSB4 ADC conversion clock <12MHz, Max hardware averaging (AVGE = %1, AVGS = %11) INL Integral non- linearity
• ≤13 bit modes
• <12 bit modes ±1.0 ±0.5 ±TBD ±TBD LSB4 Max averaging EFS Full-scale error • ≤13 bit modes
• <12 bit modes ±0.4 ±1.0 ±TBD ±TBD LSB4 VADIN = VDDA EQ Quantization error
• 16 bit modes
• ≤13 bit modes -1 to 0 ±0.5 LSB4 Table continues on the next page... Peripheral operating requirements and behaviors K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. 34 Preliminary Freescale Semiconductor, Inc.

Table 24. 16-bit ADC characteristics (V REFH = VDDA, VREFL = VSSA) (continued)

• Avg=32
• Avg=1 16 bit single-ended mode
• Avg=32
• Avg=1 TBD TBD TBD TBD 13.6 13.2 TBD TBD TBD TBD TBD TBD bits bits bits bits SINAD Signal-to-noise plus distortion See ENOB 6.02 × ENOB + 1.76 dB THD Total harmonic distortion 16 bit differential mode
• Avg=32 16 bit single-ended mode
• Avg=32 -94 TBD TBD TBD dB dB SFDR Spurious free dynamic range 16 bit differential mode
• Avg=32 16 bit single-ended mode
• Avg=32 TBD TBD TBD dB dB EIL Input leakage error IIn × RAS mV IIn = leakage current (refer to the MCU's voltage and current operating ratings) Temp sensor slope
• –40°C to 25°C
• 25°C to 105°C TBD TBD mV/°C mV/°C VTEMP25 Temp sensor voltage 25°C — TBD — mV 1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA 2. Typical values assume VDDA = 3.0 V, Temp = 25°C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and the ADLPC bit (low power). For lowest power operation the ADLPC bit should be set, the HSC bit should be clear with 1MHz ADC conversion clock speed. 4. 1 LSB = (VREFH - VREFL)/2N 5. Input data is 1 kHz sine wave. FIGURE TBD

Figure 11. Typical TUE vs. ADC conversion rate 12-bit single-ended mode K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.

Figure 12. Typical ENOB vs. Averaging for 16-bit differential and 16-bit single-ended Table 25. 16-bit ADC with PGA operating conditions

1. Typical values assume VDDA = 3.0 V, Temp = 25°C, fADCK = 6 MHz unless otherwise stated. Typical values are for

reference only and are not tested in production.

1. ADC must be configured to use the internal voltage reference (VREFOUT)
2. PGA reference connected to the VREFOUT pin. If the user wishes to drive VREFOUT with a voltage other than the output

of the VREF module, the VREF module must be disabled.

1. For single ended configurations the input impedence of the driven input is 1/2.
2. The analog source resistance (RAS), external to MCU, should be kept as minimum as possible. Increased RAS causes drop

in PGA gain without affecting other performances. This is not dependent on ADC clock frequency.

1. The minimum sampling time is dependent on input signal frequency and ADC mode of operation. A minimum of 1.25µs

Table 26. 16-bit ADC with PGA characteristics Table continues on the next page... K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. 36 Preliminary Freescale Semiconductor, Inc.

Table 26. 16-bit ADC with PGA characteristics (continued)

• PGAG=1
• PGAG=2
• PGAG=3
• PGAG=4
• PGAG=5
• PGAG=6 TBD TBD TBD TBD TBD TBD TBD 0.98 1.99 3.97 7.95 15.8 31.4 61.2 TBD TBD TBD TBD TBD TBD TBD RAS < 100Ω BW Input signal bandwidth
• 16-bit modes
• < 16-bit modes kHz kHz PSRR Power supply rejection ration Gain=1 TBD TBD — dB VDDA= 3V ±100mV, fVDDA= 50Hz, 60Hz CMRR Common mode rejection ratio
• Gain=1
• Gain=64 TBD TBD TBD TBD dB dB VCM= 500mVpp, fVCM= 50Hz, 100Hz VOFS Input offset voltage — 0.2 TBD mV Gain=1, ADC Averaging=32 TGSW Gain switching settling time — — 10 µs 5 dG/dT Gain drift over temperature
• Gain=1
• Gain=64 TBD TBD TBD TBD ppm/°C ppm/°C 0 to 50°C dVOFS/dT Offset drift over temperature Gain=1 — TBD TBD ppm/°C 0 to 50°C, ADC Averaging=32 dG/dVDDA Gain drift over supply voltage
• Gain=1
• Gain=64 TBD TBD TBD TBD %/V %/V VDDA from 1.71 to 3.6V EIL Input leakage error All modes IIn × RAS mV IIn = leakage current (refer to the MCU's voltage and current operating ratings) VPP,DIFF Maximum differential input signal swing where VX = VREFPGA × 0.583 V 6 SNR Signal-to-noise ratio
• Gain=1
• Gain=64 TBD TBD 83.0 57.5 dB dB 16-bit differential mode, Average=32 Table continues on the next page... Peripheral operating requirements and behaviors K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Preliminary 37

• Gain=1
• Gain=64 TBD TBD 89.4 90.0 dB dB 16-bit differential mode, Average=32, fin=500Hz SFDR Spurious free dynamic range
• Gain=1
• Gain=64 TBD TBD 90.9 77.0 dB dB 16-bit differential mode, Average=32, fin=500Hz ENOB Effective number of bits
• Gain=1, Average=4
• Gain=1, Average=8
• Gain=64, Average=4
• Gain=64, Average=8
• Gain=1, Average=32
• Gain=2, Average=32
• Gain=4, Average=32
• Gain=8, Average=32
• Gain=16, Average=32
• Gain=32, Average=32
• Gain=64, Average=32 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 12.3 12.7 8.4 8.7 13.3 13.1 12.5 11.8 11.1 10.2 9.3 bits bits bits bits bits bits bits bits bits bits bits 16-bit differential mode, fin=500Hz SINAD Signal-to-noise plus distortion ratio See ENOB 6.02 × ENOB + 1.76 dB 1. Typical values assume VDDA =3.0V, Temp=25°C, fADCK=6MHz unless otherwise stated. 2. Between IN+ and IN-. The PGA draws a DC current from the input terminals. The magnitude of the DC current is a strong function if input common mode voltage (VCM) and the PGA gain. 3. This is the input leakage current of the module in addition to the PAD leakage current. 4. Gain = 2PGAG 5. When the PGA gain is changed, it takes some time to settle the output for the ADC to work properly. During a gain switching, a few ADC outputs should be discarded (minimum two data samples, may be more depending on ADC sampling rate and time of the switching). 6. Limit the input signal swing so that the PGA does not saturate during operation. Input signal swing is dependent on the PGA reference voltage and gain setting.

6.6.2 CMP and 6-bit DAC electrical specifications

Table 27. Comparator and 6-bit DAC electrical specifications Table continues on the next page... K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. 38 Preliminary Freescale Semiconductor, Inc.

Table 27. Comparator and 6-bit DAC electrical specifications (continued)

• CR0[HYSTCTR] = 00
• CR0[HYSTCTR] = 01
• CR0[HYSTCTR] = 10
• CR0[HYSTCTR] = 11 mV mV mV mV VCMPOh Output high VDD – 0.5 — — V VCMPOl Output low — — 0.5 V tDHS Propagation delay, high-speed mode (EN=1, PMODE=1) 20 50 200 ns tDLS Propagation delay, low-speed mode (EN=1, PMODE=0) 120 250 600 ns Analog comparator initialization delay2 — — TBD ns IDAC6b 6-bit DAC current adder (enabled) — 7 — μA INL 6-bit DAC integral non-linearity –0.5 — 0.5 LSB3 DNL 6-bit DAC differential non-linearity –0.3 — 0.3 LSB 1. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD-0.6V. 2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to DACEN, VRSEL, PSEL, MSEL, VOSEL) and the comparator output settling to a stable level. 3. 1 LSB = Vreference/64 Peripheral operating requirements and behaviors K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Preliminary 39

Figure 13. Typical hysteresis vs. Vin level (VDD=3.3V, PMODE=0) K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. 40 Preliminary Freescale Semiconductor, Inc.

Figure 14. Typical hysteresis vs. Vin level (VDD=3.3V, PMODE=1) Table 28. 12-bit DAC operating requirements

1. The DAC reference can be selected to be VDDA or the voltage output of the VREF module (VREFO)
2. A small load capacitance (47 pF) can improve the bandwidth performance of the DAC

K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.

Table 29. 12-bit DAC operating behaviors

1 TBD — μs 1

• High power (SP HP)
• Low power (SP LP) 1.2 0.05 1.7 0.12 V/μs CT Channel to channel cross talk — — -80 dB BW 3dB bandwidth
• High power (SP HP)
• Low power (SP LP) 550 kHz 1. Settling within ±1 LSB 2. The INL is measured for 0+100mV to VDACR−100 mV 3. The DNL is measured for 0+100 mV to VDACR−100 mV 4. The DNL is measured for 0+100mV to VDACR−100 mV with VDDA > 2.4V Peripheral operating requirements and behaviors K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. 42 Preliminary Freescale Semiconductor, Inc.

1. Calculated by a best fit curve from VSS+100 mV to VREF−100 mV

Figure 15. Typical INL error vs. digital code K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.

Figure 16. Offset at half scale vs. temperature

6.6.4 Voltage reference electrical specifications

Table 30. VREF full-range operating requirements Table 31. VREF full-range operating behaviors Table continues on the next page... K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. 44 Preliminary Freescale Semiconductor, Inc.

Table 31. VREF full-range operating behaviors (continued) Table 32. VREF limited-range operating requirements Table 33. VREF limited-range operating behaviors Figure 17. Typical output vs.temperature Figure 18. Typical output vs. VDD

6.7 Timers

See General switching specifications.

6.8 Communication interfaces

K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.

6.8.1 CAN switching specifications

See General switching specifications.

6.8.2 DSPI switching specifications (low-speed mode)

used for communicating with slower peripheral devices. Table 34. Master mode DSPI timing (low-speed mode)

1. The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage

range the maximum frequency of operation is reduced. Figure 19. DSPI classic SPI timing — master mode K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. 46 Preliminary Freescale Semiconductor, Inc.

Table 35. Slave mode DSPI timing (low-speed mode) Figure 20. DSPI classic SPI timing — slave mode

6.8.3 DSPI switching specifications (high-speed mode)

used for communicating with slower peripheral devices. Table 36. Master mode DSPI timing (high-speed mode) Table continues on the next page... K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.

Table 36. Master mode DSPI timing (high-speed mode) (continued) Figure 21. DSPI classic SPI timing — master mode Table 37. Slave mode DSPI timing (high-speed mode) K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. 48 Preliminary Freescale Semiconductor, Inc.

Figure 22. DSPI classic SPI timing — slave mode

6.8.4 I2C switching specifications

See General switching specifications.

6.8.5 UART switching specifications

See General switching specifications.

6.8.6 SDHC specifications

appropriately to arrive at timing specs/constraints for the physical interface. Table 38. SDHC switching specifications Table continues on the next page... K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.

Figure 23. SDHC timing

6.8.7 I2S switching specifications

(I2S_FS) shown in the figures below. Table 39. I2S master mode timing Table continues on the next page... K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. 50 Preliminary Freescale Semiconductor, Inc.

Table 39. I2S master mode timing (continued) Figure 24. I2S timing — master mode Table 40. I2S slave mode timing Table continues on the next page... K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.

Table 40. I2S slave mode timing (continued) Figure 25. I2S timing — slave modes

6.9 Human-machine interfaces (HMI)

6.9.1 TSI electrical specifications

Table 41. TSI electrical specifications Table continues on the next page... K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. 52 Preliminary Freescale Semiconductor, Inc.

Table 41. TSI electrical specifications (continued)

1. The TSI module is functional with capacitance values outside this range. However, optimal performance is not guaranteed.
2. The programmable current source value is generated by multiplying the SCANC[REFCHRG] value and the base current.
3. Measured with a 5 pF electrode, reference oscillator frequency of 10 MHz, PS = 128, NSCN = 8; Iext = 16.
4. Measured with a 20 pF electrode, reference oscillator frequency of 10 MHz, PS = 128, NSCN = 2; Iext = 16.
5. Measured with a 20 pF electrode, reference oscillator frequency of 10 MHz, PS = 16, NSCN = 3; Iext = 16.
6. Measured with a 20 pF electrode, reference oscillator frequency of ~5 MHz (IREF = 5 μA, REFCHRG = 4), PS = 128,
7. Typical value depends on the configuration used.
8. Time to do one complete measurement of the electrode. Sensitivity resolution of 0.0133 pF, PS = 0, NSCN = 0, 1

electrode, DELVOL = 2, EXTCHRG = 15.

6.9.2 LCD electrical characteristics

Table 42. LCD electricals

• HREFSEL = 0
• HREFSEL = 1 0.89 1.49 1.00 1.67 1.15 1.85 V V ΔRTRIM VIREG TRIM resolution 3.0 — — % VIREG — VIREG ripple
• HREFSEL = 0
• HREFSEL = 1 mV mV IVIREG VIREG current adder — RVEN = 1 — 1 — µA 3 IRBIAS RBIAS current adder
• HREFSEL = 0
• HREFSEL = 1 µA µA Table continues on the next page... Peripheral operating requirements and behaviors K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Preliminary 53

Table 42. LCD electricals (continued)

• LADJ = 00 or 01 — Low load (LCD glass capacitance ≤ 2000 pF)
• LADJ = 10 or 11 — High load (LCD glass capacitance ≤ 8000 pF) 0.28 2.98 MΩ MΩ VLL2 VLL2 voltage
• HREFSEL = 0
• HREFSEL = 1 2.0 − 5% 3.3 − 5% 2.0 3.3 V V VLL3 VLL3 voltage
• HREFSEL = 0
• HREFSEL = 1 3.0 − 5% 5 − 5% 3.0 V V 1. The actual value used could vary with tolerance. 2. VIREG maximum should never be externally driven to any level other than VDD - 0.15 V 3. 2000 pF load LCD, 32 Hz frame frequency

7 Dimensions

7.1 Obtaining package dimensions

Package dimensions are provided in package drawings.

8 Pinout

8.1 K30 Signal Multiplexing and Pin Assignments

for selecting which ALT functionality is available on each pin. K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. 54 Preliminary Freescale Semiconductor, Inc.

P Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort

1 PTE0 ADC1_SE4aADC1_SE4aPTE0 SPI1_PCS1UART1_TXSDHC0_D1 I2C1_SDA

2 PTE1 ADC1_SE5aADC1_SE5aPTE1 SPI1_SOUTUART1_RXSDHC0_D0 I2C1_SCL

3 PTE2 ADC1_SE6aADC1_SE6aPTE2 SPI1_SCKUART1_CTS

SDHC0_DCL K

4 PTE3 ADC1_SE7aADC1_SE7aPTE3 SPI1_SIN UART1_RTS

SDHC0_CM D

5 PTE4 DISABLED PTE4 SPI1_PCS0UART3_TXSDHC0_D3

6 PTE5 DISABLED PTE5 SPI1_PCS2UART3_RXSDHC0_D2

7 PTE6 DISABLED PTE6 SPI1_PCS3UART3_CTS

I2S0_MCLK I2S0_CLKIN

8 VDD VDD VDD

9 VSS VSS VSS

10 PTE16 ADC0_SE4aADC0_SE4aPTE16 SPI0_PCS0UART2_TXFTM_CLKIN

FTM0_FLT3

11 PTE17 ADC0_SE5aADC0_SE5aPTE17 SPI0_SCKUART2_RXFTM_CLKIN

LPT00_ALT3

12 PTE18 ADC0_SE6aADC0_SE6aPTE18 SPI0_SOUTUART2_CTS

I2C0_SDA

13 PTE19 ADC0_SE7aADC0_SE7aPTE19 SPI0_SIN UART2_RTS

I2C0_SCL

14 ADC0_DP1ADC0_DP1ADC0_DP1

15 ADC0_DM1ADC0_DM1ADC0_DM1

16 ADC1_DP1ADC1_DP1ADC1_DP1

17 ADC1_DM1ADC1_DM1ADC1_DM1

18 PGA0_DP/

ADC0_DP0/ ADC1_DP3 PGA0_DP/ ADC0_DP0/ ADC1_DP3 PGA0_DP/ ADC0_DP0/ ADC1_DP3

19 PGA0_DM/

ADC0_DM0/ ADC1_DM3 PGA0_DM/ ADC0_DM0/ ADC1_DM3 PGA0_DM/ ADC0_DM0/ ADC1_DM3

20 PGA1_DP/

ADC1_DP0/ ADC0_DP3 PGA1_DP/ ADC1_DP0/ ADC0_DP3 PGA1_DP/ ADC1_DP0/ ADC0_DP3

21 PGA1_DM/

ADC1_DM0/ ADC0_DM3 PGA1_DM/ ADC1_DM0/ ADC0_DM3 PGA1_DM/ ADC1_DM0/ ADC0_DM3

22 VDDA VDDA VDDA

23 VREFH VREFH VREFH

24 VREFL VREFL VREFL

25 VSSA VSSA VSSA

26 VREF_OUT/

CMP1_IN5/ CMP0_IN5/ ADC1_SE18 VREF_OUTVREF_OUT/ CMP1_IN5/ CMP0_IN5/ ADC1_SE18 Pinout K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Preliminary 55

P Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort

27 DAC0_OUT/

CMP1_IN3/ ADC0_SE23 DAC0_OUTDAC0_OUT/ CMP1_IN3/ ADC0_SE23

28 XTAL32 XTAL32 XTAL32

29 EXTAL32 EXTAL32 EXTAL32

30 VBAT VBAT VBAT

31 PTE24 ADC0_SE17ADC0_SE17PTE24 CAN1_TX UART4_TX EWM_OUT_

b

32 PTE25 ADC0_SE18ADC0_SE18PTE25 CAN1_RX UART4_RX EWM_IN

33 PTE26 DISABLED PTE26 UART4_CTS

RTC_CLKO UT

34 PTA0 JTAG_TCLK/

SWD_CLK/ EZP_CLK TSI0_CH1 PTA0 UART0_CTS FTM0_CH5 JTAG_TCLK/ SWD_CLK EZP_CLK

35 PTA1 JTAG_TDI/

EZP_DI TSI0_CH2 PTA1 UART0_RXFTM0_CH6 JTAG_TDI EZP_DI

36 PTA2 JTAG_TDO/

TRACE_SW O/EZP_DO TSI0_CH3 PTA2 UART0_TXFTM0_CH7 JTAG_TDO/ TRACE_SW O EZP_DO

37 PTA3 JTAG_TMS/

SWD_DIO TSI0_CH4 PTA3 UART0_RTS FTM0_CH0 JTAG_TMS/ SWD_DIO

38 PTA4 NMI_b/

EZP_CS_b TSI0_CH5 PTA4 FTM0_CH1 NMI_b EZP_CS_b

39 PTA5 DISABLED PTA5 FTM0_CH2 CMP2_OUTI2S0_RX_BC

JTAG_TRST

40 VDD VDD VDD

41 VSS VSS VSS

42 PTA12 CMP2_IN0CMP2_IN0PTA12 CAN0_TX FTM1_CH0 I2S0_TXD FTM1_QD_P

43 PTA13 CMP2_IN1CMP2_IN1PTA13 CAN0_RX FTM1_CH1 I2S0_TX_FSFTM1_QD_P

44 PTA14 DISABLED PTA14 SPI0_PCS0UART0_TX I2S0_TX_BC

45 PTA15 DISABLED PTA15 SPI0_SCKUART0_RX I2S0_RXD

46 PTA16 DISABLED PTA16 SPI0_SOUTUART0_CTS

I2S0_RX_FS

47 PTA17 ADC1_SE17ADC1_SE17PTA17 SPI0_SIN UART0_RTS

I2S0_MCLKI2S0_CLKIN

48 VDD VDD VDD

49 VSS VSS VSS

50 PTA18 EXTAL EXTAL PTA18 FTM0_FLT2FTM_CLKIN

51 PTA19 XTAL XTAL PTA19 FTM1_FLT0FTM_CLKIN

LPT0_ALT1

52 RESET_b RESET_b RESET_b

K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. 56 Preliminary Freescale Semiconductor, Inc.

P Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort

53 PTB0 LCD_P0/

ADC0_SE8/ ADC1_SE8/ TSI0_CH0 LCD_P0/ ADC0_SE8/ ADC1_SE8/ TSI0_CH0 PTB0 I2C0_SCL FTM1_CH0 FTM1_QD_P HA LCD_P0

54 PTB1 LCD_P1/

ADC0_SE9/ ADC1_SE9/ TSI0_CH6 LCD_P1/ ADC0_SE9/ ADC1_SE9/ TSI0_CH6 PTB1 I2C0_SDA FTM1_CH1 FTM1_QD_P HB LCD_P1

55 PTB2 LCD_P2/

ADC0_SE12/ TSI0_CH7 LCD_P2/ ADC0_SE12/ TSI0_CH7 PTB2 I2C0_SCL UART0_RTS FTM0_FLT3LCD_P2

56 PTB3 LCD_P3/

ADC0_SE13/ TSI0_CH8 LCD_P3/ ADC0_SE13/ TSI0_CH8 PTB3 I2C0_SDA UART0_CTS FTM0_FLT0LCD_P3

57 PTB7 LCD_P7/

ADC1_SE13 LCD_P7/ ADC1_SE13 PTB7 LCD_P7

58 PTB8 LCD_P8 LCD_P8 PTB8 UART3_RTS

LCD_P8

59 PTB9 LCD_P9 LCD_P9 PTB9 SPI1_PCS1UART3_CTS

LCD_P9

60 PTB10 LCD_P10/

ADC1_SE14 LCD_P10/ ADC1_SE14 PTB10 SPI1_PCS0UART3_RX FTM0_FLT1LCD_P10

61 PTB11 LCD_P11/

ADC1_SE15 LCD_P11/ ADC1_SE15 PTB11 SPI1_SCKUART3_TX FTM0_FLT2LCD_P11

62 PTB16 LCD_P12/

TSI0_CH9 LCD_P12/ TSI0_CH9 PTB16 SPI1_SOUTUART0_RX EWM_IN LCD_P12

63 PTB17 LCD_P13/

TSI0_CH10 LCD_P13/ TSI0_CH10 PTB17 SPI1_SIN UART0_TX EWM_OUT_ b LCD_P13

64 PTB18 LCD_P14/

TSI0_CH11 LCD_P14/ TSI0_CH11 PTB18 CAN0_TX FTM2_CH0I2S0_TX_BC LK FTM2_QD_P HA LCD_P14

65 PTB19 LCD_P15/

TSI0_CH12 LCD_P15/ TSI0_CH12 PTB19 CAN0_RX FTM2_CH1I2S0_TX_FS FTM2_QD_P HB LCD_P15

66 PTB20 LCD_P16 LCD_P16 PTB20 SPI2_PCS0 CMP0_OUTLCD_P16

67 PTB21 LCD_P17 LCD_P17 PTB21 SPI2_SCK CMP1_OUTLCD_P17

68 PTB22 LCD_P18 LCD_P18 PTB22 SPI2_SOUT CMP2_OUTLCD_P18

69 PTB23 LCD_P19 LCD_P19 PTB23 SPI2_SIN SPI0_PCS5 LCD_P19

70 PTC0 LCD_P20/

ADC0_SE14/ TSI0_CH13 LCD_P20/ ADC0_SE14/ TSI0_CH13 PTC0 SPI0_PCS4PDB0_EXTR G I2S0_TXD LCD_P20

71 PTC1 LCD_P21/

ADC0_SE15/ TSI0_CH14 LCD_P21/ ADC0_SE15/ TSI0_CH14 PTC1 SPI0_PCS3UART1_RTS FTM0_CH0 LCD_P21

72 PTC2 LCD_P22/

ADC0_SE4b/ CMP1_IN0/ TSI0_CH15 LCD_P22/ ADC0_SE4b/ CMP1_IN0/ TSI0_CH15 PTC2 SPI0_PCS2UART1_CTS FTM0_CH1 LCD_P22

73 PTC3 LCD_P23/

CMP1_IN1 LCD_P23/ CMP1_IN1 PTC3 SPI0_PCS1UART1_RXFTM0_CH2 LCD_P23 Pinout K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Preliminary 57

P Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort

74 VSS VSS VSS

75 VLL3 VLL3 VLL3

76 VLL2 VLL2 VLL2

77 VLL1 VLL1 VLL1

78 VCAP2 VCAP2 VCAP2

79 VCAP1 VCAP1 VCAP1

80 PTC4 LCD_P24 LCD_P24 PTC4 SPI0_PCS0UART1_TXFTM0_CH3 CMP1_OUTLCD_P24

81 PTC5 LCD_P25 LCD_P25 PTC5 SPI0_SCK LPT0_ALT2 CMP0_OUTLCD_P25

82 PTC6 LCD_P26/

CMP0_IN0 LCD_P26/ CMP0_IN0 PTC6 SPI0_SOUTPDB0_EXTR G LCD_P26

83 PTC7 LCD_P27/

CMP0_IN1 LCD_P27/ CMP0_IN1 PTC7 SPI0_SIN LCD_P27

84 PTC8 LCD_P28/

ADC1_SE4b/ CMP0_IN2 LCD_P28/ ADC1_SE4b/ CMP0_IN2 PTC8 I2S0_MCLKI2S0_CLKIN LCD_P28

85 PTC9 LCD_P29/

ADC1_SE5b/ CMP0_IN3 LCD_P29/ ADC1_SE5b/ CMP0_IN3 PTC9 I2S0_RX_BC LK FTM2_FLT0LCD_P29

86 PTC10 LCD_P30/

ADC1_SE6b/ CMP0_IN4 LCD_P30/ ADC1_SE6b/ CMP0_IN4 PTC10 I2C1_SCL I2S0_RX_FS LCD_P30

87 PTC11 LCD_P31/

ADC1_SE7b LCD_P31/ ADC1_SE7b PTC11 I2C1_SDA I2S0_RXD LCD_P31

88 VSS VSS VSS

89 VDD VDD VDD

90 PTC16 LCD_P36 LCD_P36 PTC16 CAN1_RX UART3_RX LCD_P36

91 PTC17 LCD_P37 LCD_P37 PTC17 CAN1_TX UART3_TX LCD_P37

92 PTC18 LCD_P38 LCD_P38 PTC18 UART3_RTS

LCD_P38

93 PTD0 LCD_P40 LCD_P40 PTD0 SPI0_PCS0UART2_RTS

LCD_P40

94 PTD1 LCD_P41/

ADC0_SE5b LCD_P41/ ADC0_SE5b PTD1 SPI0_SCKUART2_CTS LCD_P41

95 PTD2 LCD_P42 LCD_P42 PTD2 SPI0_SOUTUART2_RX LCD_P42

96 PTD3 LCD_P43 LCD_P43 PTD3 SPI0_SIN UART2_TX LCD_P43

97 PTD4 LCD_P44 LCD_P44 PTD4 SPI0_PCS1UART0_RTS

FTM0_CH4 EWM_IN LCD_P44

98 PTD5 LCD_P45/

ADC0_SE6b LCD_P45/ ADC0_SE6b PTD5 SPI0_PCS2UART0_CTS FTM0_CH5 EWM_OUT_ b LCD_P45

99 PTD6 LCD_P46/

ADC0_SE7b LCD_P46/ ADC0_SE7b PTD6 SPI0_PCS3UART0_RXFTM0_CH6 FTM0_FLT0LCD_P46

100 PTD7 LCD_P47 LCD_P47 PTD7 CMT_IRO UART0_TXFTM0_CH7 FTM0_FLT1LCD_P47

K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. 58 Preliminary Freescale Semiconductor, Inc.

8.2 K30 Pinouts

The below figure shows the pinout diagram for the devices supported by this document. used on which pin, see the previous section.

98 PTD5

97 PTD4

96 PTD3

95 PTD2

94 PTD1

93 PTD0

92 PTC18

91 PTC17

90 PTC16

89 VDD

88 VSS

80 PTC4

83 PTC7

84 PTC8

85 PTC9

86 PTC10

87 PTC11

100 PTD7

Figure 26. K30 100 LQFP Pinout Diagram K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.

9 Revision History

The following table provides a revision history for this document. Table 43. Revision History

Revision History

K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. 60 Preliminary Freescale Semiconductor, Inc.

How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, EL516

2100 East Elliot Road

Tempe, Arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.com/support Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7

81829 Muenchen, Germany

+44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) www.freescale.com/support Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo 153-0064 Japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com Asia/Pacific: Freescale Semiconductor China Ltd. Exchange Building 23F No. 118 Jianguo Road Chaoyang District Beijing 100022 China +86 10 5879 8000 support.asia@freescale.com For Literature Requests Only: Freescale Semiconductor Literature Distribution Center 1-800-441-2447 or +1-303-675-2140 Fax: +1-303-675-2150 LDCForFreescaleSemiconductor@hibbertgroup.com Document Number: K30P100M100SF2 Rev. 4, 3/2011 Preliminary Information in this document is provided solely to enable system and sofware implementers to use Freescale Semiconductors products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any liability, including without limitation consequential or incidental damages. "Typical" parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals", must be validated for each customer application by customer's technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claims alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. RoHS-compliant and/or Pb-free versions of Freescale products have the functionality and electrical characteristics as their non-RoHS-complaint and/or non-Pb-free counterparts. For further information, see http://www.freescale.com or contact your Freescale sales representative. For information on Freescale's Environmental Products program, go to http://www.freescale.com/epp. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2010–2011 Freescale Semiconductor, Inc.