K24C02 ETC1 | Alldatasheet
Document overview
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Technical content
K24C02 / K24C04 / K24C08 / K24C16
2K bits (25 6 X 8) / 4K bits (51 2 X 8) / 8K bits (102 4 X 8) / 16K bits (204 8 X 8) Two-wire Serial EEPROM K24C02/K24C04/K24C08/K24C16 Wide Voltage Operation - VCC = 1.7V to 5.5V Operating Ambient Temperature: -40℃ to +85℃ Internally Organized: - K24C02, 256 X 8 (2K bits) - K24C04, 512 X 8 (4K bits) - K24C08, 1024 X 8 (8K bits) - K24C16, 2048 X 8 (16K bits) Two-wire Serial Interface Schmitt Trigger, Filtered Inputs for Noise Suppression Bidirectional Data Transfer Protocol 1 MHz (5V), 400 kHz (1.7V, 2.5V, 2.7V) Compatibility Write Protect Pin for Hardware Data Protection 8-byte Page (2K), 16-byte Page (4K, 8K, 16K) Write Modes Partial Page Writes Allowed Self-timed Write Cycle (5 ms max) High-reliability - Endurance: 1 Million Write Cycles - Data Retention: 100 Years 8-lead PDIP/SOP/MSOP/TSSOP, 8-pad DFN, and SOT23-5
Features
The K24C0 2/K24C0 4/K24C0 8/K24C1 6 provid es 204 8/409 6/819 2/1638 4 bits of seria l electrically erasabl e and programmabl e read-on ly memor y (EEPROM) organize d as 256/512/102 4/204 8 word s of 8 bits each. The device is optimized for use in many indu stria l and comme rcial appl ications wher e low-powe r and low -voltage oper ation are essential. The K24C0 2/K24C0 4/K24C0 8/K24C1 6 is availabl e in spac e-saving 8-lea d PDIP, 8-lea d SOP, 8-lea d MSOP, 8-lea d TSSOP, 8-pa d DFN, and SO T23- 5 package s and is accessed via a two-wir e seria l interface. Pin Configuration Pin Name A0 - A2 SDA SCL GND WP VCC Write Protect Address Inputs Serial Data Serial Clock Input Ground Power Supply Founctions Table 1: Pin Configuration SDA SCL WP VCC1 5GND SDA SCL WP VCC1 GND SDA SCL WP VCC1 GND 8 - l e a d P D I P 8 - l e a d S O P 8 - l e a d T S S O P packages SDA SCL WP VCC1 GND 8 - l e a d M S O P SDA SCL WP VCC A0 GND 8 - p a d D F N S O T 2 3 - 5 1 5 SDA GND SCL WP V CC Bottom view
2K bits (256 X 8) / 4K bits (512 X 8) / 8K bits (1024 X 8) / 16K bits (2048 X 8) Two-wire Serial EEPROM .002.. Block Diagram SDA SCL WP VCC GND START STOP LOGIC SERIAL CONTROL LOGIC DEVICE ADDRESS COMPARATOR DATA WORD ADDRESS COUNTER LOAD COMP LOAD INC Y DECODER HIGH VOLTAGE PUMP/TIMING EN DATA RECOVERY EEPROM SERIAL MUX X DECODER DOUT/ACKNOWLEDGEDIN DOUT V 1 . 7 K24C02/K24C04/K24C08/K24C16 Summer 2012
2K bits (25 6 X 8) / 4K bits (51 2 X 8) / 8K bits (102 4 X 8) / 16K bits (204 8 X 8) Two-wire Serial EEPROM Pin Descriptions DEVICE/PAGE ADDRESSE S (A2, A1 and A0): The A2, A1 and A0 pins are device addr ess inp uts that are har d wire d for the K24C0 2. Eight 2K dev ices may be addr essed on a singl e bus system (device addr essing is discussed in detail unde r the Device Address ing section ). The K24C0 4 use s the A2 and A1 inp uts for har d wir e addr essing and a total of four 4K devices may be addr essed on a singl e bus system. The A0 pin is a no conne ct and can be conne cted to groun d. The K24C0 8 only uses the A2 inp ut for hardwir e addr essing and a total of two 8K devices may be addr essed on a singl e bus system. The A0 and A1 pins are no conn ects and can be conne cted to groun d. The K24C1 6 doe s not use the devic e addre ss pins, whi ch lim its the numbe r of devices on a singl e bus to one. The A0, A1, and A2 pins are no conne cts and can be conn ected to groun d. SERIAL DATA (SDA): The SDA pin is bi-dir ectiona l for seria l data transfer. This pin is open-drai n driven and may be wire -ORed with any numbe r of other open-drai n or open - coll ector devices. SERIAL CLOCK (SCL): The SCL inp ut is use d to positive edg e clock data into each EEPROM device and neg ative edg e clock data out of eac h dev ice. WRITE PROTECT (WP) : The K24C0 2/K24C0 4/K24C0 8/K24C1 6 has a Write Protect pin that provide s hardwar e data protection. The Write Protect pin allow s norma l rea d/write oper ation s whe n conne cted to groun d (GND). When the Write Protect pin is conn ected to VCC, the write protection feature is enable d and oper ates as show n in the followin g Memory Organization K24C0 2, 2K SERIAL EEPROM: Internall y organ ized with 32 page s of 8 bytes each, the 2K requir es an 8-b it data wor d addre ss for rando m wor d addres sing. K24C0 4, 4K SERIAL EEPROM: Internall y organize d with 32 page s of 16 bytes each, the 4K requir es a 9-b it data wor d addr ess for rando m wor d addr essing. K24C0 8, 8K SERIAL EEPROM: Internall y organ ized with 64 page s of 16 bytes each, the 8K requir es a 10-b it data wor d addre ss for rando m wor d addres sing. K24C1 6, 16K SERIAL EEPROM: Internal ly organ ized with 128 page s of 16 bytes each, the 16K require s an 11-b it data wor d addres s for rando m wor d addre ssing. Table 2: Write Protect WP Pin Status Part of the Array Protected K24C16 Full (16K) Array K24C08 Full (8K) Array K24C04 Full (4K) Array K24C02 Full (2K) Array Normal Read / Write Operations At VCC At GND K24C02/K24C04/K24C08/K24C16
CLOCK and DATA TRANSITION S: The SDA pin is normal ly pull ed high with an extern al device. Data on the SDA pin may chan ge only duri ng SCL low time peri ods (see to Figu re 1 on page 4). Data chan ges duri ng SCL high peri ods will indi cate a start or stop condition as defined below. START CONDITIO N: A hig h-to-l ow transition of SDA with SCL high is a start condition which must pre cede any other comma nd (see to Figu re 2 on page 4). STOP CONDITIO N: A low-to-hi gh transition of SDA with SCL high is a stop condition. After a read sequen ce, the stop comma nd will place the EEPROM in a standby pow er mode (see Figu re 2 on page 4). ACKNOWLEDGE: All add resses and data words are seria lly transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a "0" to acknowled ge that it has received each word. This happ ens duri ng the ninth clock cycle. STANDBY MODE: The K24C0 2/K24C0 4/K24C0 8/K24C 16 features a low-pow er stand by mode which is enabl ed: upon(a) power- up and (b) after the receipt of the STOP bit and the comp letion of any intern al ope rations MEMORY RESET: After an interr uption in protocol, pow er loss or system reset, any two-wi re part can be reset by followi ng these steps: 1. Clock up to 9 cycles. 2. Look for SDA high in each cycle whi le SCL is high. 3. Create a start condition. Figure 1: Data Validity Figure 2: Start and Stop Definition SDA SCL START STOP SDA SCL DATA CHANGE DATA STABLE DATA STABLE K24C02/K24C04/K24C08/K24C16 Two-wire Serial EEPROM 2K bits (25 6 X 8) / 4K bits (51 2 X 8) / 8K bits (102 4 X 8) / 16K bits (204 8 X 8)
2K bits (25 6 X 8) / 4K bits (51 2 X 8) / 8K bits (102 4 X 8) / 16K bits (204 8 X 8) Two-wire Serial EEPROM Figure 3: Output Acknowledge Device Addressing The 2K, 4K, 8K and 16K EEPROM dev ices all requir e an 8-b it device addr ess wor d followin g a start cond ition to enabl e the chip for a rea d or write oper ation (se e to Figur e 4 on pag e 7). The device addre ss wor d consists of a mand atory "1", "0" seque nce for the first four most sign ificant bits as show n. This is commo n to all the Seria l EE PROM dev ices. The next 3 bits are the A2, A1 and A0 dev ice addres s bits for the 2K EEPROM. These 3 bits must compa re to thei r corre spondin g hardwire d inp ut pins. The 4K EEPROM onl y uses the A2 and A1 dev ice addr ess bits with the thir d bit bein g a memo ry pag e addr ess bit. The two device addr ess bits must compar e to thei r corre spondin g hardwire d inp ut pin s. The A0 pin is no conne ct. The 8K EEPROM onl y uses the A2 dev ice addre ss bit with the next 2 bits bein g for memo ry pag e addr essing. The A2 bit must compar e to its corre spondin g hard-wire d inp ut pin. The A1 and A0 pin s are no conne ct. The 16K doe s not use any dev ice addre ss bits but instead the 3 bits are used for memo ry pag e addr essing. These pag e addres sing bits on the 4K, 8K and 16K dev ices shoul d be cons idere d the most sign ificant bits of the data wor d addr ess which follo ws. The A0, A1 and A2 pins are no conn ect. The eig hth bit of the device addre ss is the rea d/write oper ation sele ct bit. A rea d oper ation is initiated if this bit is hig h and a write oper ation is initiated if this bit is low. Upo n a compar e of the device addr ess, the EE PROM wil l output a "0". If a compar e is not mad e, the chip wil l return to a standb y state. SCL DATA IN DATA OUT 8 9 ACKNOWLEDGE START K24C02/K24C04/K24C08/K24C16
2K bits (25 6 X 8) / 4K bits (51 2 X 8) / 8K bits (102 4 X 8) / 16K bits (204 8 X 8) Two-wire Serial EEPROM Write Operations BYTE WRITE: A write oper ation requir es an 8-b it data word addr ess followi ng the device addr ess word and acknowledgme nt. Upo n recei pt of this addre ss, the EEPROM wil l agai n respon d with a "0" and then clock in the first 8-b it data wor d. Followin g recei pt of the 8-b it data wor d, the EEPROM wil l output a "0" and the addr essing device, such as a microc ontroll er, must termin ate the write sequenc e with a stop cond ition. At this time the EEPROM enters an internal ly time d write cycle, tWR, to the nonvol atile memo ry. All inp uts are disable d durin g this write cycle and the EEPROM wil l not respon d until the write is compl ete (se e Figur e 5 on pag e 7). PAGE WRITE: The 2K EEPROM is capabl e of an 8-b yte pag e write, and the 4K, 8K and 16K devices are capabl e of 16- byte pag e writes. A pag e write is initiated the sam e as a byte write, but the micr ocontrolle r does not send a stop cond ition after the first data wor d is clocked in. Instead, after the EEPROM acknowledg es receipt of the first data wor d, the micr ocontrolle r can transmit up to seven (2K) or fifteen (4K, 8K, 16K) mor e data word s. The EEPROM wil l respon d with a "0" after each data wor d received. The microco ntrolle r must termin ate the pag e write seque nce with a stop cond ition (see Figur e 6 on pag e 7). The data wor d addre ss lowe r thre e (2K) or four (4K, 8K, 16K) bits are internal ly increme nted followi ng the receipt of each data wor d. The highe r data wor d addre ss bits are not increme nted, retainin g the memo ry pag e row location. When the wor d addr ess, internal ly gener ated, reach es the pag e bounda ry, the followin g byte is placed at the beginnin g of the same pag e. If mor e than eig ht (2K) or sixteen (4K, 8K, 16K) data word s are transmitted to the EEPROM, the data wor d addres s wil l "rol l over" and previou s data wil l be overwr itten. ACKNOWLEDGE POLLING: Once the internall y time d write cycle has started and the EEPROM inp uts are disable d, acknowledg e pollin g can be initiated. This invo lves sendin g a start cond ition followe d by the device addr ess wor d. The rea d/write bit is represe ntative of the oper ation desire d. Only if the interna l write cycle has compl eted wil l the EEPROM respon d with a "0", allowin g the rea d or write sequenc e to continu e. Read Operations Rea d oper ation s are initiated the sam e way as write oper ations with the exception that the rea d/write sele ct bit in the device addr ess wor d is set to "1". Ther e are thre e rea d oper ation s: curre nt addr ess rea d, rando m addr ess rea d and seque ntial rea d. CURRENT ADDRESS READ: The interna l data wor d addr ess counter mai ntains increme nted by one. accessed addr ess, the last and This addre ss stays vali d betwee n oper ation s as lon g as the chip * intern al data word addre ss cou nter mai ntains only lowe r 8 bits of the For 16K EE PROM, we als o provid e special addres sing prod uct for certain applic ation s, that is, . the last accessed addre ss, the highe r 3 bits (P2, P1, P0) wil l follo w the dev ice addres s inp ut at eac h curre nt addre ss rea d. So, plea se contact your deale r for specia l orderin g. powe r is mai ntaine d. The addr ess "rol l ove r" rea d is from the last byte of the last memo ry pag e to the first byte of the first pag e. The addre ss "rol l ove r" durin g durin g write is from the last byte of the curre nt pag e to the first byte of the same pag e. Once the device addre ss with the rea d/write sel ect bit set to "1" is clocked in and acknowledge d by the EEPROM, the curre nt addre ss data wor d is seriall y clocke d out. The micr ocontrolle r does not respon d with an inp ut "0" but does gener ate a followin g stop cond ition (se e Figur e 7 on pag e 8). K24C02/K24C04/K24C08/K24C16
2K bits (25 6 X 8) / 4K bits (51 2 X 8) / 8K bits (102 4 X 8) / 16K bits (204 8 X 8) Two-wire Serial EEPROM Read Operations RANDOM READ: A rando m rea d require s a "dum my" byte write seque nce to loa d in the data wor d addr ess. Once the device addr ess wor d and data wor d addre ss are clocked in and acknowledge d by the EEPROM, the micr ocontrolle r must gener ate another start cond ition. The microco ntrolle r now initiates a curre nt addr ess rea d by sendin g a device addre ss with the rea d/write select bit hig h. The EEPROM acknowledg es the device addr ess and serial ly clocks out the data wor d. The micr ocontrolle r doe s not respon d with a "0" but does gener ate a followin g stop cond ition (see Figur e 8 on pag e 8). SEQUENT IAL READ: Seque ntial read s are initiated by either a curre nt addr ess rea d or a rando m addr ess rea d. After the microcontrolle r receive s a data wor d, it respond s with an acknowledg e. As lon g as the EEPROM receives an acknowledg e, it wil l continu e to increme nt the data wor d addr ess and serial ly clock out seque ntial data word s. When the memo ry addre ss lim it is reache d, the data wor d addr ess wil l "rol l over" and the seque ntial rea d wil l continu e. The seque ntial rea d oper ation is termin ated whe n the micr ocontrolle r does not respon d with a "0" but does gener ate a followin g stop cond ition (se e Figur e 9 on pag e 8). Figure 4: Device Address Figure 5: Byte Write Figure 6: Page Write SDA LINE S T A R T M S B DEVICE ADDRESS L S B R W A C K M S B L S B A C K DATA A C K S T O P WORD ADDRESS W R I T ESDA LINE S T A R T M S B DEVICE ADDRESS L S B R W A C K M S B L S B A C K DATA ( n ) A C K WORD ADDRESS A C K DATA ( n+1 ) A C K S T O PDATA ( n+x ) W R I T E 2K 1 0 1 0 A2 A1 A0 R/W MSB LSB 4K 1 0 1 0 A2 A1 P0 R/W 8K 1 0 1 0 A2 P1 P0 R/W 16K 1 0 1 0 P2 P1 P0 R/W K24C02/K24C04/K24C08/K24C16
2K bits (25 6 X 8) / 4K bits (51 2 X 8) / 8K bits (102 4 X 8) / 16K bits (204 8 X 8) Two-wire Serial EEPROM Figure 7: Current Address Read Figure 8: Random Read Figure 9: Sequential Read SDA LINE S T A R T M S B DEVICE ADDRESS L S B R W A C K N O A C K S T O P R E A D DATA SDA LINE S T A R T M S B DEVICE ADDRESS L S B R W A C K M S B L S B A C K WORD ADDRESS W R I T E S T A R T M S B DEVICE ADDRESS L S B R W A C K N O A C K S T O P R E A D DATA DUMMY WRITE DEVICE ADDRESS R W A C K DATA( n ) A C K A C K DATA( n+1 ) DATA( n+2 ) R E A D SDA LINE A C K N O A C K S T O PDATA( n+x ) K24C02/K24C04/K24C08/K24C16
2K bits (256 X 8) / 4K bits (512 X 8) / 8K bits (1024 X 8) / 16K bits (2048 X 8) Two-wire Serial EEPROM Absolute Maximum Stress Ratings
Electrical Characteristics
Comments Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. Applicable over recommended operating range from: TA = -40℃ to +85℃, ~VCC = +1.7V to +5.5V (unless otherwise noted) Parameter Supply Voltage Supply Current VCC = 5.0V Supply Current VCC = 5.0V Standby Current 5.5 1.0 3.0 3.0 Max. READ at 400 kHz WRITE at 400 kHz V IN = VCC or GND Condition 1.7 Min. VCC ICC1 ICC2 ISB Symbol 0.4 2.0 Typ. V mA mA Unit A Input Leakage Current Output Leakage Current Input Low Level Output Low Level V CC =1.7V Output Low Level VCC =5.0V Input High Level Output Low Level VCC =3.0V 3.0 3.0 VCC x 0.3 0.2 0.4 VCC + 0.3 0.4 VIN = VCC or GND VOUT = VCC or GND IOL = 0.15 mA IOL = 3.0 mA IOL = 2.1 mA -0.3 VCC x 0.7 ILI ILO VIL1 VOL1 VOL3 VIH1 VOL2 0.05 V V V V V A A Pin Capacitance Applicable over recommended operating range from TA = 25℃, f = 1.0 MHz, VCC = +1.7V Parameter Input/Output Capacitance (SDA) Input Capacitance (A0, A1, A2, Max. VIN = 0V Condition Min. CI/O CIN Symbol Typ. pF pF Unit SCL) VI/O = 0V K24C02/K24C04/K24C08/K24C16 Input Low Level Input High Level VCC x 0.2 VCC + 0.3 -0.3 VCC x 0.7 VIL2 VIH2 V V ~VCC = 1.8V to 5.5V VCC = 1.8V to 5.5V VCC = 1.7V VCC = 1.7V
Input rise and fall time: 50 ns 2K bits (256 X 8) / 4K bits (512 X 8) / 8K bits (1024 X 8) / 16K bits (2048 X 8) Two-wire Serial EEPROM Applicable over recommended operating range from TA = -40℃ to +85℃, VCC = +1.7V to +5.5V, CL = 1 TTL Gate and 100 pF (unless otherwise noted) Note Parameter Clock Frequency, SCL Clock Pulse Width Low Clock Pulse Width High Start Hold Time Clock Low to Data Out Valid Noise Suppression Time Time the bus must be free before a new transmission can start Start Setup Time Data In Hold Time Data In Setup Time Data Out Hold Time Write Cycle Time Inputs Fall Time(1) Inputs Rise Time(1) Stop Setup Time fSCL tLOW tHIGH tHD.STA tAA tI tBUF tSU.STA tHD.DAT tSU.DAT tDH tWR 1.2 0.6 0.6 0.05 1.2 0.6 100 0.6 1.5 400 0.9 300 0.3 0.6 0.4 0.25 0.05 0.5 0.25 100 0.25 1.5 1000 0.55 100 0.3 kHz ns ns ms ns tF tR tSU.STO Max. Units Min. Symbol Typ. 1.7v ≤ Vcc < 2.5v Max.Min. Typ. s s s s s s s s s 1. This parameter is characterized and is not 100% tested. 2. AC measurement conditions: RL (connects to VCC): 1.3 k (2.5V, 5V), 10 k (1.7V) Input pulse voltages: 0.3 VCC to 0.7 VCC Input and output timing reference voltages: 0.5 VCC The value of RL should be concerned according to the actual loading on the user's system. ns 5.0V, 25℃, Byte Mode 1M - - - - - Write CyclesEndurance 2.5v ≤ Vcc ≤ 5.5v K24C02/K24C04/K24C08/K24C16
2K bits (25 6 X 8) / 4K bits (51 2 X 8) / 8K bits (102 4 X 8) / 16K bits (204 8 X 8) Two-wire Serial EEPROM 8-lead PDIP package diagram K24C02/K24C04/K24C08/K24C16 COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN MAX N e BB L b eA eB eC c A 3.60 4.00 A1 0.51 - A2 3.10 3.50 A3 1.50 1.70 b 0.44 0.53 b1 0.43 0.48 B 1.52 BSC c 0.25 0.31 c1 0.24 0.26 D 9.05 9.45 E1 6.15 6.55 e 2.54 BSC eA 7.62 BSC eB 7.62 9.50 eC 0 0.94 L 3.00 - Top View Side View End View D b c1 c Base Metal With Plating Section B-B
2K bits (25 6 X 8) / 4K bits (51 2 X 8) / 8K bits (102 4 X 8) / 16K bits (204 8 X 8) Two-wire Serial EEPROM 8-lead SOP package diagram K24C02/K24C04/K24C08/K24C16 COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN MAX A1 0.10 0.25 A 1.35 1.75 b 0.31 0.51 C 0.17 0.25 D 4.70 5.10 E1 3.80 4.00 E 5.79 6.20 e 1.27 BSC L θ 0.40 1.27 0° 8° Side View Top View End View e B D A N E C L θ
2K bits (25 6 X 8) / 4K bits (51 2 X 8) / 8K bits (102 4 X 8) / 16K bits (204 8 X 8) Two-wire Serial EEPROM 8-lead TSSOP package diagram K24C02/K24C04/K24C08/K24C16 COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN MAX D 2.80 3.20 6.20 6.60E E1 4.20 4.60 A – 1.20 A2 0.80 1.15 b 0.19 0.30 e 0.65 BSC L 0.45 0.75 θ
1.00 BSC
A Lθ D 123 N b E e 0° 8°
2K bits (25 6 X 8) / 4K bits (51 2 X 8) / 8K bits (102 4 X 8) / 16K bits (204 8 X 8) Two-wire Serial EEPROM 8-lead MSOP package diagram K24C02/K24C04/K24C08/K24C16 COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN MAX A1 0.05 0.15 A - 1.10 A2 0.75 0.95 A3 0.30 0.40 b 0.29 0.38 b1 0.28 0.33 c 0.15 0.20 0.14 0.16c1 D E 2.90 3.10 E1 2.90 3.10 e 0.65 BSC L 0.40 0.70 L1 0.95 BSC θ 0° 8° 4.70 5.10 Side View Top View End View e b D A N E C L θ b c1 c Base Metal With Plating Section B-B BB
2K bits (25 6 X 8) / 4K bits (51 2 X 8) / 8K bits (102 4 X 8) / 16K bits (204 8 X 8) Two-wire Serial EEPROM 8-pad DFN package diagram K24C02/K24C04/K24C08/K24C16 COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN MAX b 0.18 0.30 c 0.18 0.25 A 0.70 0.80 A1 - 0.05 D 1.90 2.10 D2 1.50 REF e 0.50 BSC
1.50 BSC
1.60 BSC
E 2.90 3.10 L 0.30 0.50 h 0.20 0.30 A1D 1 2 E A b h L e Nd c Top View End View Bottom View Side View h
2K bits (25 6 X 8) / 4K bits (51 2 X 8) / 8K bits (102 4 X 8) / 16K bits (204 8 X 8) Two-wire Serial EEPROM 5-lead SOT package diagram K24C02/K24C04/K24C08/K24C16 5 4 L End View AA2 b e D Side View 3 θ1 Top View E COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN MAX A 1.05 1.30 A1 0 0.10 A2 1.00 1.20 A3 0.55 0.75 0.30 0.50 0.33 0.38 0.10 0.21 0.14 2.60 3.00 1.40 0.16 1.80
0.95 BSC
0.30 0.60 0° 8° b c E 2.72 3.12D L e θ BB b c1 c Base Metal With Plating Section B-B
2K bits (256 X 8) / 4K bits (512 X 8) / 8K bits (1024 X 8) / 16K bits (2048 X 8) Two-wire Serial EEPROM
Ordering Information
1.Prefix 2.Series Name 24: Two-wire (I2C) Interface 3.EEPROM Density C02 = 2K bits C04 = 4K bits C08 = 8K bits C16 = 16K bits 4.Package Type D = PDIP S = SOP T = TSSOP M = MSOP 5.Temperature Range 6.Pack Type T = Tube R = Tape & Reel 7.Plating Technology Blank = Standard SnPb plating G = RoHS compliant 8.Operating Voltage A = 1.7 to 5.5 V - X X X X X 1 2 3 4 5 6 7 8 Part Number: K 24 XXX K 24 XXX (version) Product Name: Product Datasheet Change Notice 1.0 Package type update Initial version Dec., 2006 Version Content Date Design version & Package type update Datasheet Revision History K24C02/K24C04/K24C08/K24C16 N = DFN O = SOT I = Industry (-40℃ to +85℃) S = Green, level 1 X = Green, level 3 1.2 1.3 Dec., 2008 Jan., 2011 Code Number update 1.4 May., 2011 Ordering information update 1.5 Jan., 2012 Available package types Model K24C02 K24C04 √ √K24C08 K24C16 PDIP SOP TSSOP MSOP DFN SOT23 Add Vcc=1.7v 1.6 Mar., 2012 Isb updated1.7 Jul., 2012
2K bits (25 6 X 8) / 4K bits (51 2 X 8) / 8K bits (102 4 X 8) / 16K bits (204 8 X 8) Two-wire Serial EEPROM Disclaimers The inform ation in this public ation has bee n carefully chec ked and is beli eved to be entire ly accurate at the time of public ation. HUAJIE assume s no respons ibil ity, how ever, for possibl e erro rs or omissions, or for any conseque nces resu lting from the use of the inform ation containe d herei n. HUAJI E reserves the rig ht to make change s in its prod ucts or prod uct spec ifications with the intent to impro ve function or desi gn at any time and without notice and is not requir ed to upd ate this docume ntation to reflect such change s. This public ation doe s not convey to a purch aser of semicondu ctor devices describe d herei n any licens e unde r the patent rig hts of HUAJIE or other s. HUAJI E makes no warra nty, represe ntation, or guara ntee regardin g the suitabil ity of its prod ucts for any particula r purp ose, nor doe s HUAJIE assum e any liabil ity arising out of the appl ication or use of any produ ct or circuit and spec ifical ly dis clai ms any and all liabi lity, includi ng without limitation any conseque ntial or incide ntal damage s. " Typ. " param eters can and do vary in differe nt appl ications. All oper ating param eters, includin g " Typ. " must be valid ated for eac h custome r applic ation by the custome r's technical experts. HUAJI E produ cts are not designe d, intende d, or authoriz ed for use as compone nts in systems intende d for surgi cal impla nt into the body, for other appl ications intende d to suppo rt or sustain life, or for any other appli cation in which the failur e of the HUAJIE prod uct coul d create a situation wher e persona l inju ry or death may occur. Shoul d the Buye r purch ase or use a HUAJIE prod uct for any such uni ntende d or una uthoriz ed appl ication, the Buye r shal l indemn ify and hol d HUAJIE and its officers, empl oyees, subs idiari es, affili ates, and distrib utors harml ess again st all claim s, costs, damage s, expens es, and reasonabl e attorne y fees arising out of, either dire ctly or indire ctly, any clai m of persona l inju ry or death that may be associated with such uni ntende d or una uthor ized use, eve n if such clai m allege s that HUAJIE was neglige nt regardin g the design or man ufacture of said produ ct. K24C Seri es (I2C Bus) Seria l EE PROM Data Sheet, Revisio n 1.7 201 2 HUAJIE All rig hts reserved. No part of this public ation may be reprod uced, store d in a retriev al system, or transmitted in any form or by any mean s, ele ctric or mechani cal, by photocopying, recordin g, or otherw ise, without the prio r written consent of HUAJIE. K24C02/K24C04/K24C08/K24C16