K24C02C

K24C08C ETC | Alldatasheet

Document overview

• Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
• PDF pages: 20

Technical content

K24C02C / K24C04 / K24C08C / K24C16B

2K bits (256 X 8) / 4K bits (512 X 8) / 8K bits (1024 X 8) / 16K bits (2048 X 8) Two-wire Serial EEPROM K24C02C/K24C04/K24C08C/K24C16B ?Wide Voltage Operation - VCC = 1.8V to 5.5V ?Operating Ambient Temperature: -40 C to +85 C ?Internally Organized: - K24C02C, 256 X 8 (2K bits) - K24C04, 512 X 8 (4K bits) - K24C08C, 1024 X 8 (8K bits) - K24C16B, 2048 X 8 (16K bits) ?Two-wire Serial Interface ?Schmitt Trigger, Filtered Inputs for Noise Suppression ?Bidirectional Data Transfer Protocol ?1 MHz (5V), 400 kHz (1.8V, 2.5V, 2.7V) Compatibility ?Write Protect Pin for Hardware Data Protection ?8-byte Page (2K), 16-byte Page (4K, 8K, 16K) Write Modes ?Partial Page Writes Allowed ?Self-timed Write Cycle (5 ms max) ?High-reliability - Endurance: 1 Million Write Cycles - Data Retention: 100 Years ?8-lead PDIP/SOP/MSOP/TSSOP, 8-pad DFN, and SOT23-5

Features

The K24C02C/K24C04/K24C08C/K24C16B provides 2048/4096/8192/16384 bits of serial electrically erasable and programmable read-only memory (EEPROM) organized as 256/512/1024/2048 words of 8 bits each. The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. The K24C02C/K24C04/K24C08C/K24C16B is available in space-saving 8-lead PDIP , 8-lead SOP , 8-lead MSOP, 8-lead TSSOP, 8-pad DFN, and SOT23-5 packages and is accessed via a two-wire serial interface. Pin Configuration Pin Name A0 - A2 SDA SCL GND WP VCC Write Protect Address Inputs Serial Data Serial Clock Input Ground Power Supply Founctions ?Table 1: Pin Configuration SDA SCL WP VCC1 5GND SDA SCL WP VCC1 GND SDA SCL WP VCC1 GND 8-lead PDI P 8-lead SOP 8-lead TSSOP packages SDA SCL WP VCC1 GND 8-lead MSOP SDA SCL WP VCC A0 GND 8-pad DFN SOT23-5 1 5 SDA GND SCL WP VCC Bottom view

2K bits (256 X 8) / 4K bits (512 X 8) / 8K bits (1024 X 8) / 16K bits (2048 X 8) Two-wire Serial EEPROM .002.. Block Diagram SDA SCL WP VCC GND START STOP LOGIC SERIAL CONTROL LOGIC DEVICE ADDRESS COMPARATOR DATA WORD ADDRESS COUNTER LOAD COMP LOAD INC Y DECODER HIGH VOLTAGE PUMP/TIMING EN DATA RECOVERY EEPROM SERIAL MUX X DECODER DOUT/ACKNOWLEDGEDIN DOUT V 1 . 3 K24C02C/K24C04/K24C08C/K24C16B Spring 2011

2K bits (256 X 8) / 4K bits (512 X 8) / 8K bits (1024 X 8) / 16K bits (2048 X 8) Two-wire Serial EEPROM Pin Descriptions DEVICE/P AGE ADDRESSES (A2, A1 and A0): The A2, A1 and A0 pins are device address inputs that are hard wired for the K24C02C. Eight 2K devices may be addressed on a single bus system (device addressing is discussed in detail under the Device Addressing section). The K24C04 uses the A2 and A1 inputs for hard wire addressing and a total of four 4K devices may be addressed on a single bus system. The A0 pin is a no connect and can be connected to ground. The K24C08C only uses the A2 input for hardwire addressing and a total of two 8K devices may be addressed on a single bus system. The A0 and A1 pins are no connects and can be connected to ground. The K24C16B does not use the device address pins, which limits the number of devices on a single bus to one. The A0, A1, and A2 pins are no connects and can be connected to ground. SERIAL DATA (SDA): The SDA pin is bi-directional for serial data transfer . This pin is open-drain driven and may be wire-ORed with any number of other open-drain or open- collector devices. SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device. WRITE PROTECT (WP): The K24C02C/K24C04/K24C08C/K24C16B has a W rite Protect pin that provides hardware data protection. The Write Protect pin allows normal read/write operations when connected to ground (GND). When the Write Protect pin is connected to VCC, the write protection feature is enabled and operates as shown in the following Memory Organization K24C02C, 2K SERIAL EEPR OM: Internally organized with 32 pages of 8 bytes each, the 2K requires an 8-bit data word address for random word addressing. K24C04, 4K SERIAL EEPR OM: Internally organized with 32 pages of 16 bytes each, the 4K requires a 9-bit data word address for random word addressing. K24C08C, 8K SERIAL EEPR OM: Internally organized with 64 pages of 16 bytes each, the 8K requires a 10-bit data word address for random word addressing. K24C16B, 16K SERIAL EEPR OM: Internally organized with 128 pages of 16 bytes each, the 16K requires an 11-bit data word address for random word addressing. ?Table 2: Write Protect WP Pin Status Part of the Array Protected K24C16B Full (16K) Array K24C08C Full (8K) Array K24C04 Full (4K) Array K24C02C Full (2K) Array Normal Read / Write Operations At VCC At GND K24C02C/K24C04/K24C08C/K24C16B

CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external devi ce. Data on the SDA pin may change onl y during SCL low time period s (see to Figure 1 on page 4). Data change s during SCL high period s will indica te a st art or stop condi tion as defined belo w. START CONDITION: A high- to-low tran sition of SDA with SCL high is a start condi tion whi ch must precede any other command (see to Figure 2 on page 4). STOP CONDITION: A low- to-high tran sition of SDA with SCL high is a stop condi tion . Aft er a read sequence , the stop command will pla ce the EEP ROM in a st andb y power mode (see Figure 2 on page 4). ACKNOWLEDGE: All addre sses and data word s are seriall y tran smitted to and from the EEP ROM in 8-bi t word s. The EEP ROM send s a "0" t o acknowledge that it has received each word . This happen s during the nin th clock cycle . STANDBY MODE: The K24C02C/K24C04/K24C08C/K24C16B features a low-power standby mode whi ch is enabled: upon(a) power-up and (b) after the receip t of t he STOP bit and the comple tion of any internal opera tion s MEMORY RESET: Aft er an interrup tion in pro tocol, power loss or system rese t, any two-wire par t can be reset by following these steps : 1. Cloc k up to 9 cycles . 2. Loo k f or SDA high in each cy cle while SCL is high . 3. Crea te a st art c ondi tion . ?Figure 1: Data Validity ?Figure 2: Start and Stop Definition SDA SCL START STOP SDA SCL DATA CHANGE DATA STABLE DATA STABLE K24C02C/K24C04/K24C08C/K24C16B Two-wire Serial EEPROM 2K bits (256 X 8) / 4K bits (512 X 8) / 8K bits (1024 X 8) / 16K bits (2048 X 8)

2K bits (256 X 8) / 4K bits (512 X 8) / 8K bits (1024 X 8) / 16K bits (2048 X 8 ) Two-wire Serial EEPROM ?Figure 3: Output Acknowledge Device Addressing The 2K, 4K, 8K and 16K EEPROM devices all require an 8-bit device address word following a start condition to enable the chip for a read or write operation (see to Figure 4 on page 7). The device address word consists of a mandatory "1", "0" sequence for the first four most significant bits as shown. This is common to all the Serial EEPROM devices. The next 3 bits are the A2, A1 and A0 device address bits for the 2K EEPROM. These 3 bits must compare to their corresponding hardwired input pins. The 4K EEPROM only uses the A2 and A1 device address bits with the third bit being a memory page address bit. The two device address bits must compare to their corresponding hardwired input pins. The A0 pin is no connect. The 8K EEPROM only uses the A2 device address bit with the next 2 bits being for memory page addressing. The A2 bit must compare to its corresponding hard-wired input pin. The A1 and A0 pins are no connect. The 16K does not use any device address bits but instead the 3 bits are used for memory page addressing. These page addressing bits on the 4K, 8K and 16K devices should be considered the most significant bits of the data word address which follows. The A0, A1 and A2 pins are no connect. The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if this bit is high and a write operation is initiated if this bit is low . Upon a compare of the device address, the EEPROM will output a "0". If a compare is not made, the chip will return to a standby state. SCL DATA IN DATA OUT 8 9 ACKNOWLEDGE START K24C02C/K24C04/K24C08C/K24C16B

2K bits (256 X 8) / 4K bits (512 X 8) / 8K bits (1024 X 8) / 16K bits (2048 X 8 ) Two-wire Serial EEPROM Write Operations BYTE WRITE: A writ e operat ion requires an 8-bit dat a word address following the device address word and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a "0" and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a "0" and the addressing device, such as a microcontroller , must terminate the write sequence with a stop condition. At this time the EEPROM enters an internally timed write cycle, tWR, to the nonvolatile memory . All inputs are disabled during this write cycle and the EEPROM will not respond until the write is complete (see Figure 5 on page 7). PAGE WRITE: The 2K EEPROM is capable of an 8-byte page write, and the 4K, 8K and 16K devices are capable of 16-byte page writes. A page write is initiated the same as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcontroller can transmit up to seven (2K) or fifteen (4K, 8K, 16K) more data words. The EEPROM will respond with a "0" after each data word received. The microcontroller must terminate the page write sequence with a stop condition (see Figure 6 on page 7). The data word address lower three (2K) or four (4K, 8K, 16K) bits are internally incremented following the receipt of each data word. The higher data word address bits are not incremented, retaining the memory page row location. When the word address, internally generated, reaches the page boundary , the following byte is placed at the beginning of the same page. If more than eight (2K) or sixteen (4K, 8K, 16K) data words are transmitted to the EEPROM, the data word address will "roll over" and previous data will be overwritten. ACKNO WLEDGE POLLING: Once the internally timed write cycle has started and the EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a start condition followed by the device address word. The read/write bit is representative of the operation desired. Only if the internal write cycle has completed will the EEPROM respond with a "0", allowing the read or write sequence to continue. Read Operations Read operations are initiated the same way as write operations with the exception that the read/write select bit in the device address word is set to "1". There are three read operations: current address read, random address read and sequential read. CURRENT ADDRESS READ: The internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. This address stays valid between operations as long as the chip power is maintained. The address "roll over" during read is from the last byte of the last memory page to the first byte of the first page. The address "roll over" during write is from the last byte of the current page to the first byte of the same page. Once the device address with the read/write select bit set to "1" is clocked in and acknowledged by the EEPROM, the current address data word is serially clocked out. The microcontroller does not respond with an input "0" but does generate a following stop condition (see Figure 7 on page 8). K24C02C/K24C04/K24C08C/K24C16B

2K bits (256 X 8) / 4K bits (512 X 8) / 8K bits (1024 X 8) / 16K bits (2048 X 8) Two-wire Serial EEPROM Read Operations RANDOM READ: A random read requires a "dummy" byte write sequence to load in the data word address. Once the device address word and data word address are clocked in and acknowledged by the EEPROM, the microcontroller must generate another start condition. The microcontroller now initiates a current address read by sending a device address with the read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the data word. The microcontroller does not respond with a "0" but does generate a following stop condition (see Figure 8 on page 8). SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a random address read. After the microcontroller receives a data word, it responds with an acknowledge. As long as the EEPROM receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. When the memory address limit is reached, the data word address will "roll over" and the sequential read will continue. The sequential read operation is terminated when the microcontroller does not respond with a "0" but does generate a following stop condition (see Figure 9 on page 8). ?Figure 4: Device Address ?Figure 5: Byte Write ?Figure 6: Page Write SDA LINE S T A R T M S B DEVICE ADDRESS L S B R W A C K M S B L S B A C K DATA A C K S T O P WORD ADDRESS W R I T E SDA LINE S T A R T M S B DEVICE ADDRESS L S B R W A C K M S B L S B A C K DATA ( n ) A C K WORD ADDRESS A C K DATA ( n+1 ) A C K S T O PDATA ( n+x ) W R I T E 2K 1 0 1 0 A2 A1 A0 R/W MSB LSB 4K 1 0 1 0 A2 A1 P0 R/W 8K 1 0 1 0 A2 P1 P0 R/W 16K 1 0 1 0 P2 P1 P0 R/W K24C02C/K24C04/K24C08C/K24C16B

2K bits (256 X 8) / 4K bits (512 X 8) / 8K bits (1024 X 8) / 16K bits (2048 X 8 ) Two-wire Serial EEPROM ?Figure 7: Current Address Read ?Figure 8: Random Read ?Figure 9: Sequential Read SDA LINE S T A R T M S B DEVICE ADDRESS L S B R W A C K N O A C K S T O P R E A D DATA SDA LINE S T A R T M S B DEVICE ADDRESS L S B R W A C K M S B L S B A C K WORD ADDRESS W R I T E S T A R T M S B DEVICE ADDRESS L S B R W A C K N O A C K S T O P R E A D DATA DUMMY WRITE DEVICE ADDRESS R W A C K DATA( n ) A C K A C K DATA( n+1 ) DATA( n+2 ) R E A D SDA LINE A C K N O A C K S T O PDATA( n+x ) K24C02C/K24C04/K24C08C/K24C16B

2K bits (256 X 8) / 4K bits (512 X 8) / 8K bits (1024 X 8) / 16K bits (2048 X 8 ) Two-wire Serial EEPROM ?Absolute Maximum Stress Ratings

Electrical Characteristics

?Comments Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. ?Applicable over recommended operating range from: TA = -40  C to +85  C, VCC = +1.8V to +5.5V (unless otherwise noted) Parameter Supply Voltage Supply Current VCC = 5.0V Supply Current VCC = 5.0V Standby Current 5.5 1.0 3.0 1.0 Max. READ at 100 kHz WRITE at 100 kHz VIN = VCC or GND Condition 1.8 Min. VCC ICC1 ICC2 ISB Symbol 0.4 2.0 Typ. V mA mA Unit A Input Leakage Current Output Leakage Current Input Low Level Output Low Level VCC =1.8V Output Low Level VCC =5.0V Input High Level Output Low Level VCC =3.0V 3.0 3.0 VCC x 0.3 0.2 0.4 VCC + 0.3 0.4 VIN = VCC or GND VOUT = VCC or GND IOL = 0.15 mA IOL = 3.0 mA IOL = 2.1 mA -0.3 VCC x 0.7 ILI ILO VIL VOL1 VOL3 VIH VOL2 0.05 V V V V V A A Pin Capacitance ?Applicable over recommended operating range from TA = 25  C, f = 1.0 MHz, VCC = +1.8V Parameter Input/Output Capacitance (SDA) Input Capacitance (A0, A1, A2, Max. VIN = 0V Condition Min. CI/O CIN Symbol Typ. pF pF Unit SCL) VI/O = 0V K24C02C/K24C04/K24C08C/K24C16B

2K bits (256 X 8) / 4K bits (512 X 8) / 8K bits (1024 X 8) / 16K bits (2048 X 8) Two-wire Serial EEPROM ?Applicable over recommended operating range from TA = -40 C to +85 C, VCC = +1.8V to +5.5V, CL = 1 TTL Gate and 100 pF (unless otherwise noted) Note Parameter Clock Frequency, SCL Clock Pulse Width Low Clock Pulse Width High Start Hold Time Clock Low to Data Out Valid Noise Suppression Time Time the bus must be free before a new transmission can start Start Setup Time Data In Hold Time Data In Setup Time Data Out Hold Time Write Cycle Time(for 04/16B) Inputs Fall Time(1) Inputs Rise Time(1) Stop Setup Time fSCL tLOW tHIGH tHD.STA tAA tI tBUF tSU.STA tHD.DAT tSU.DAT tDH tWR1 1.2 0.6 0.6 0.05 1.2 0.6 100 0.6 3.3 400 0.9 300 0.3 0.6 0.4 0.25 0.05 0.5 0.25 100 0.25 3.3 1000 0.55 100 0.3 kHz ns ns ms nstF tR tSU.STO Max. Units Min. Symbol Typ. 1.8-volt Max.Min. Typ. 5.0-volt s s s s s s s s s 1. This parameter is characterized and is not 100% tested. 2. AC measurement conditions: RL (connects to VCC): 1.3 k (2.5V, 5V), 10 k (1.8V) Input pulse voltages: 0.3 VCC to 0.7 VCC Input rise and fall time: 50 ns Input and output timing reference voltages: 0.5 VCC The value of RL should be concerned according to the actual loading on the user's system. ns 5.0V, 25 C, Byte Mode 1M - - - - - Write CyclesEndurance Write Cycle Time(for 02C/08C) tWR2 - 1.5 5 - 1.5 5 ms K24C02C/K24C04/K24C08C/K24C16B

2K bits (256 X 8) / 4K bits (512 X 8) / 8K bits (1024 X 8) / 16K bits (2048 X 8) Two-wire Serial EEPROM .011..011. Bus Timing ÿFigure 10: SCL: Serial Clock, SDA: Serial Data I/O Write Cycle Timing ÿFigure 11: SCL: Serial Clock, SDA: Serial Data I/O Note 1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle. SCL SDA_IN SDA_OUT tF tLOW tSU.STA tHD.STA tAA tDH tBUF tSU.STO tR tHD.DAT tSU.DAT tHIGH tLOW 8th BIT SCL SDA ACK STOP CONDITION START CONDITION tWR (1) V 1 . 3 K24C02C/K24C04/K24C08C/K24C16B Spring 2011

2K bits (256 X 8) / 4K bits (512 X 8) / 8K bits (1024 X 8) / 16K bits (2048 X 8 ) Two-wire Serial EEPROM 8-lead PDIP package diagram K24C02C/K24C04/K24C08C/K24C16B COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN MAX N e BB L b eA eB eC c A 3.60 4.00 A1 0.51 - A2 3.10 3.50 A3 1.50 1.70 b 0.44 0.53 b1 0.43 0.48 B 1.52 BSC c 0.25 0.31 c1 0.24 0.26 D 9.05 9.45 E1 6.15 6.55 e 2.54 BSC eA 7.62 BSC eB 7.62 9.50 eC 0 0.94 L 3.00 - Top View Side View End View D b c1 c Base Metal With Plating Section B-B

2K bits (256 X 8) / 4K bits (512 X 8) / 8K bits (1024 X 8) / 16K bits (2048 X 8 ) Two-wire Serial EEPROM 8-lead SOP package diagram K24C02C/K24C04/K24C08C/K24C16B COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN MAX A1 0.10 0.25 A 1.35 1.75 b 0.31 0.51 C 0.17 0.25 D 4.70 5.10 E1 3.80 4.00 E 5.79 6.20 e 1.27 BSC L θ 0.40 1.27 0° 8° Side View Top View End View e B D A N E C L θ

2K bits (256 X 8) / 4K bits (512 X 8) / 8K bits (1024 X 8) / 16K bits (2048 X 8 ) Two-wire Serial EEPROM 8-lead TSSOP package diagram K24C02C/K24C04/K24C08C/K24C16B COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN MAX D 2.80 3.20 6.20 6.60E E1 4.20 4.60 A – 1.20 A2 0.80 1.15 b 0.19 0.30 e 0.65 BSC L 0.45 0.75 θ

1.00 BSC

A Lθ D 123 N b E e 0° 8°

2K bits (256 X 8) / 4K bits (512 X 8) / 8K bits (1024 X 8) / 16K bits (2048 X 8 ) Two-wire Serial EEPROM 8-lead MSOP package diagram K24C02C/K24C04/K24C08C/K24C16B COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN MAX A1 0.05 0.15 A - 1.10 A2 0.75 0.95 A3 0.30 0.40 b 0.29 0.38 b1 0.28 0.33 c 0.15 0.20 0.14 0.16c1 D E 2.90 3.10 E1 2.90 3.10 e 0.65 BSC L 0.40 0.70 L1 0.95 BSC θ 0° 8° 4.70 5.10 Side View Top View End View e b D A N E C L θ b c1 c Base Metal With Plating Section B-B BB

2K bits (256 X 8) / 4K bits (512 X 8) / 8K bits (1024 X 8) / 16K bits (2048 X 8 ) Two-wire Serial EEPROM 8-pad DFN package diagram K24C02C/K24C04/K24C08C/K24C16B COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN MAX b 0.18 0.30 c 0.18 0.25 A 0.70 0.80 A1 - 0.05 D 1.90 2.10 D2 1.50 REF e 0.50 BSC

1.50 BSC

1.60 BSC

E 2.90 3.10 L 0.30 0.50 h 0.20 0.30 A1D 1 2 E A b h L e Nd c Top View End View Bottom View Side View h

2K bits (256 X 8) / 4K bits (512 X 8) / 8K bits (1024 X 8) / 16K bits (2048 X 8 ) Two-wire Serial EEPROM 5-lead SOT23 package diagram K24C02C/K24C04/K24C08C/K24C16B 5 4 L End View A b e D Side View 3 θ1 Top View E COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN MAX A 1.05 1.30 A1 0 0.10 A2 1.00 1.20 A3 0.55 0.75 0.30 0.50 0.33 0.38 0.10 0.21 0.14 2.60 3.00 1.40 0.16 1.80

0.95 BSC

0.30 0.60 0° 8° b c E 2.72 3.12D L e θ BB b c1 c Base Metal With Plating Section B-B

2K bits (256 X 8) / 4K bits (512 X 8) / 8K bits (1024 X 8) / 16K bits (2048 X 8) Two-wire Serial EEPROM

Ordering Information

1.Prefix 2.Series Name 24: Two-wire (I2C) Interface 3.EEPROM Density C02 = 2K bits C04 = 4K bits C08 = 8K bits C16 = 16K bits 4.Design Option Version code 5.Package Type D = PDIP S = SOP T = TSSOP M = MSOP 6.Temperature Range 7.Pack Type T = Tube R = Tape & Reel 8.Plating Technology Blank = Standard SnPb plating G = RoHS compliant 9.Operating Voltage A = 1.8 to 5.5 V   K 24 XXX X - X X X X X 1 2 3 4 5 6 7 8 9 Code Number Part Number Product Datasheet Change Notice 1.0 Package type update Initial version Dec., 2006 Version Content Date Design version & Package type update Datasheet Revision History K24C02C/K24C04/K24C08C/K24C16B N = DFN O = SOT I = Industry (-40 C to 85 C) S = Green, level 1 X = Green, level 3 1.2 1.3 Dec., 2008 Jan., 2011 Available package types Model K24C02C K24C04 √ √K24C08C K24C16B PDIP SOP TSSOP MSOP DFN SOT23

2K bits (256 X 8) / 4K bits (512 X 8) / 8K bits (1024 X 8) / 16K bits (2048 X 8) Two-wire Serial EEPROM Disclaimers The information in this publication has been carefully checked and is believed to be entirely accurate at the time of publication. HUAJIE assumes no responsibility , however , for possible errors or omissions, or for any consequences resulting from the use of the information contained herein. HUAJIE reserves the right to make changes in its products or product specifications with the intent to improve function or design at any time and without notice and is not required to update this documentation to reflect such changes. This publication does not convey to a purchaser of semiconductor devices described herein any license under the patent rights of HUAJIE or others. HUAJIE makes no warranty , representation, or guarantee regarding the suitability of its products for any particular purpose, nor does HUAJIE assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liabili ty, including with out limitation any consequential or incidental damages. " Typ. " parameters can and do vary in different applications. All operating parameters, including " Typ. " must be validated for each customer application by the customer's technical experts. HUAJIE products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , for other applications intended to support or sustain life, or for any other application in which the failure of the HUAJIE product could create a situation where personal injury or death may occur . Should the Buyer purchase or use a HUAJIE product for any such unintended or unauthorized application, the Buyer shall indemnify and hold HUAJIE and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, expenses, and reasonable attorney fees arising out of, either directly or indirectly , any claim of personal injury or death that may be associated with such unintended or unauthorized use, even if such claim alleges that HUAJIE was negligent regarding the design or manufacture of said product. K24C Series (I2C Bus) Serial EEPROM Data Sheet, Revision 1.3

2011 HUAJIE

All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electric or mechanical, by photocopying, recording, or otherwise, without the prior written consent of HUAJIE. K24C02C/K24C04/K24C08C/K24C16B