2SK2461 NEC | Alldatasheet
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Technical content
MOS FIELD EFFECT TRANSISTOR
DESCRIPTION
The 2SK2461 is N-Channel MOS Field Effect Transistor de- signed for high speed switching applications.
FEATURES
- Low On-Resistance RDS(on)1 = 80 m Ω MAX. (@ V GS = 10 V, I D = 10 A) RDS(on)2 = 0.1 Ω MAX. (@ V GS = 4 V, I D = 10 A)
- Low Ciss C iss = 1400 pF TYP.
- Built-in G-S Gate Protection Diodes
- High Avalanche Capability Ratings ABSOLUTE MAXIMUM RATINGS (T A = 25 ˚C) Drain to Source Voltage V DSS 100 V Gate to Source Voltage V GSS ±20 V Drain Current (DC) I D(DC) ±20 A Drain Current (pulse) * ID(pulse) ±80 A Total Power Dissipation (T c = 25 ˚C) P T1 35 W Total Power Dissipation (T A = 25 ˚C) P T2 2.0 W Channel Temperature T ch 150 ˚C Storage Temperature T stg –55 to +150 ˚C Single Avalanche Current IAS 20 A Single Avalanche Energy EAS 40 mJ * PW ≤ 10 µs, Duty Cycle ≤ 1 % ** Starting T ch = 25 ˚C, RG = 25 Ω , VGS = 20 V → 0 2SK2461 SWITCHING N-CHANNEL POWER MOS FET INDUSTRIAL USE © 1995 DATA SHEET Document No. TC-2529 (O. D. No. TC-8078) Date Published April 1995 P Printed in Japan Body Diode Source Drain Gate Gate Protection Diode MP-45F (ISOLATED TO-220) 10.0 ±0.3 3.2 ±0.2 4.5 ±0.2 2.7 ±0.2 2.5 ±0.1 0.65 ±0.11.5 ±0.2 2.54 1.3 ±0.2 2.54 0.7 ±0.1 4 ±0.2 15.0 ±0.3 12.0 ±0.2 3 ±0.1 123 1. Gate 2. Drain 3. Source 13.5MIN. PACKAGE DIMENSIONS (in millimeters)
ELECTRICAL CHARACTERISTICS (T A = 25 ˚C) CHARACTERISTIC SYMBOL MIN. TYP. MAX. TEST CONDITIONS Drain to Source On-Resistance RDS(on)1 58 80 VGS = 10 V, I D = 10 A Drain to Source On-Resistance RDS(on)2 70 100 VGS = 4 V, I D = 10 A Gate to Source Cutoff Voltage VGS(off) 1.0 1.7 2.0 VDS = 10 V, I D = 1 mA Forward Transfer Admittance | yfs | 12 19 VDS = 10 V, I D = 10 A Drain Leakage Current IDSS 10 VDS = 100 V, V GS = 0 Gate to Source Leakage Current IGSS ±10 VGS = ±20 V, V DS = 0 Input Capacitance Ciss 1400 VDS = 10 V Output Capacitance Coss 470 VGS = 0 Reverse Transfer Capacitance Crss 150 f = 1 MHz Turn-On Delay Time td(on) 21 ID = 10 A Rise Time tr 110 VGS(on) = 10 V Turn-Off Delay Time td(off) 140 VDD = 50 V Fall Time tf 110 RG = 10 Ω Total Gate Charge QG 51 ID = 20 A Gate to Source Charge QGS 4.9 VDD = 80 V Gate to Drain Charge QGD 15 VGS = 10 V Body Diode Forward Voltage VF(S-D) 1.1 IF = 20 A, V GS = 0 Reverse Recovery Time trr 170 IF = 20 A, V GS = 0 Reverse Recovery Charge Q rr 770 di/dt = 100 A/ µs Test Circuit 3 Gate Charge VGS = 20 → 0 V PG. RG = 25 Ω 50 Ω D.U.T. L VDD Test Circuit 1 Avalanche Capability PG. RG = 10 Ω D.U.T. RL VDD Test Circuit 2 Switching Time RG PG. IG = 2 mA 50 Ω D.U.T. RL VDD ID VDD IAS VDS BVDSS Starting Tch VGS t = 1 s Duty Cycle ≤ 1 % VGS Wave Form ID Wave Form VGS ID 10 % 10 % 90 % 90 % 90 % 10 % VGS (on) ID ton toff td (on) tr td (off) tft µ UNIT mΩ mΩ V S µA µA pF pF pF ns ns ns ns nC nC nC V ns nC The application circuits and their parameters are for references only and are not intended for use in actual design-in's.
TYPICAL CHARACTERISTICS (T A = 25 ˚C) FORWARD BIAS SAFE OPERATING AREA VDS - Drain to Source Voltage - V ID - Drain Current - A DRAIN CURRENT vs. DRAIN TO SOURCE VOLTAGE VDS - Drain to Source Voltage - V ID - Drain Current - A FORWARD TRANSFER CHARACTERISTICS VGS - Gate to Source Voltage - V ID - Drain Current - A DERATING FACTOR OF FORWARD BIAS SAFE OPERATING AREA TC - Case Temperature - ˚C dT - Percentage of Rated Power - % TOTAL POWER DISSIPATION vs. CASE TEMPERATURE TC - Case Temperature - ˚C PT - Total Power Dissipation - W 0 200 20 40 60 80 100 120 140 160 100 40 60 80 100 120 140 160 0.1 100 10 100 1000 TC = 25 ˚C Single Pulse 0 4 6 8 51 0 1 5 100
1000 Pulsed
ID(pulse) 1 ms PW=10 s Power Dissipation Limited RDS(on) Limited (at V GS = 10 V) Pulsed VGS = 4 V VGS = 6 VVGS = 10 V DC 200 ms ID(DC) VDS = 10 V 100 s 10 ms TA = –25 ˚C 25 ˚C 125 ˚C µµ
TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH PW - Pulse Width - s rth(t) - Transient Thermal Resistance - ˚C/W FORWARD TRANSFER ADMITTANCE vs. DRAIN CURRENT ID - Drain Current - A | yfs | - Forward Transfer Admittance - S DRAIN TO SOURCE ON-STATE RESISTANCE vs. GATE TO SOURCE VOLTAGE VGS - Gate to Source Voltage - V RDS(on) - Drain to Source On-State Resistance - mΩ 0 10 DRAIN TO SOURCE ON-STATE RESISTANCE vs. DRAIN CURRENT GATE TO SOURCE CUTOFF VOLTAGE vs. CHANNEL TEMPERATURE Tch - Channel Temperature - ˚C VGS(off) - Gate to Source Cutoff Voltage - V ID - Drain Current - A RDS(on) - Drain to Source On-State Resistance - mΩ 0.001 0.01 0.1 100 1 000 1 m 10 m 100 m 1 10 100 1 000 10 100 VDS=10 V Pulsed 0.1 1 100 1000 10 100 120 20 30 Pulsed 10 100 Pulsed Single Pulse 120 0.5 VDS = 10 V ID = 1 mA 1.0 1.5 2.0 –50 0 50 100 150 160 Rth(ch-a) = 62.5 ˚C/W Rth(ch-c) = 3.57 ˚C/W TA =–25 ˚C 25 ˚C 75 ˚C 125 ˚C ID = 8.0 A VGS = 10 V 100 140 VGS = 4 V µµ
DRAIN TO SOURCE ON-STATE RESISTANCE vs. CHANNEL TEMPERATURE Tch - Channel Temperature - ˚C RDS(on) - Drain to Source On-State Resistance - mΩ SOURCE TO DRAIN DIODE FORWARD VOLTAGE VSD - Source to Drain Voltage - V ISD - Diode Forward Current - A CAPACITANCE vs. DRAIN TO SOURCE VOLTAGE VDS - Drain to Source Voltage - V Ciss, Coss, Crss - Capacitance - pF SWITCHING CHARACTERISTICS ID - Drain Current - A td(on), tr, td(off), tf - Switching Time - ns 1.0 0.1 –50 120 0 50 100 150 ID = 10 A 100 1000 1.0 Pulsed 100 1 000 10 000 10 100 1 000 VGS = 0 f = 1 MHz 100 1 000 1.0 10 100 VGS - Gate to Source Voltage - V REVERSE RECOVERY TIME vs. DRAIN CURRENT ID - Drain Current - A trr - Reverse Recovery time - ns di/dt = 50 A/ s VGS = 0 0.1 100 1 000 10 000 1.0 10 100 2.0 3.0 160 VDD = 50 V VGS =10 V RG =10 Ω DYNAMIC INPUT/OUTPUT CHARACTERISTICS Qg - Gate Charge - nC VDS - Drain to Source Voltage - V 0 20 40 60 80 80 V DD = 80 V ID = 20 A VGS = 4 V VGS = 10 V 4 V VGS = 0 Crss Coss Ciss tr td(on) tf td(off) VGSVDS µ
SINGLE AVALANCHE ENERGY vs. INDUCTIVE LOAD L - Inductive Load - H IAS - Single Avalanche Energy - mJ SINGLE AVALANCHE ENERGY DERATING FACTOR Starting Tch - Starting Channel Temperature - ˚C Energy Derating Factor - % 1.0 100 100 1 m 10 m VDD = 50 V VGS = 20 V → 0 RG = 25 Ω 120 160 50 75 100 125 150 175 VDD = 50 V RG = 25 Ω VGS = 20 V → 0 IAS ≤ 20 A 100 140 EAS = 40 mJ IAS = 20 A 10 µµ
Document Name Document No. NEC semiconductor device reliability/quality control system. TEI-1202 Quality grade on NEC semiconductor devices. IEI-1209 Semiconductor device mounting technology manual. IEI-1207 Semiconductor device package manual. IEI-1213 Guide to quality assurance for semiconductor devices. MEI-1202 Semiconductor selection guide. MF-1134 Power MOS FET features and application switching power supply. TEA-1034 Application circuits using Power MOS FET. TEA-1035 Safe operating area of Power MOS FET. TEA-1037 The diode connected between the gate and source of the transistor serves as a protector against ESD. When this device is actually used, an additional protection circuit is externally required if a voltage exceeding the rated voltage may be applied to this device.
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