K11P80M50SF4

Freescale Semiconductor...

K11 Sub-Family Data Sheet

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Document overview

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PDF pages: 54

Technical content

Features

Operating Characteristics – Voltage range: 1.71 to 3.6 V Flash write voltage range: 1.71 to 3.6 V – Temperature range (ambient): -40 to 105°C
Performance – Up to 50 MHz ARM Cortex-M4 core with DSP instructions delivering 1.25 Dhrystone MIPS per MHz
Memories and memory interfaces – Up to 512 KB of program flash for devices without FlexNVM. – Up to 256 KB program flash for devices with FlexNVM. – 64 KB FlexNVM on FlexMemory devices – 4 KB FlexRAM on FlexMemory devices – Up to 64 KB RAM – Serial programming interface (EzPort)
Clocks – 3 to 32 MHz crystal oscillator – 32 kHz crystal oscillator – Multi-purpose clock generator
System peripherals – Multiple low-power modes to provide power optimization based on application requirements – External watchdog monitor – Software watchdog – Low-leakage wakeup unit
Security and integrity modules – Hardware CRC module to support fast cyclic redundancy checks Tamper detect and secure storage – Hardware random-number generator – Hardware encryption supporting DES, 3DES, AES, MD5, SHA-1, and SHA-256 algorithms – 128-bit unique identification (ID) number per chip
Human-machine interface – General-purpose input/output
Analog modules – 16-bit SAR ADC – Two analog comparators (CMP) containing a 6-bit DAC and programmable reference input
Timers – Programmable delay block – Two 2-channel general purpose timers, one with quadrature decoder functionality – Periodic interrupt timers – 16-bit low-power timer – Carrier modulator transmitter – Real-time clock
Communication interfaces – Two SPI modules – Two I2C modules – Four UART modules – I2S module Freescale Semiconductor Document Number: K11P80M50SF4 Data Sheet: Advance Information Rev. 3, 08/2012 This document contains information on a new product. Specifications and information herein are subject to change without notice. © 2012–2013 Freescale Semiconductor, Inc.

3.6 Relationship between ratings and operating

6.8.1 DSPI switching specifications (limited voltage

6.8.2 DSPI switching specifications (full voltage range).42

6.8.5 Normal Run, Wait and Stop mode performance

6.8.6 VLPR, VLPW, and VLPS mode performance

K11 Sub-Family Data Sheet Data Sheet, Rev. 3, 08/2012. 2 Freescale Semiconductor, Inc.

1 Ordering parts

1.1 Determining valid orderable parts

Valid orderable part numbers are provided on the web. To determine the orderable part numbers for this device, go to www.freescale.com and perform a part number search for the following device numbers: PK11 and MK11 .

2 Part identification

2.1 Description

Part numbers for the chip have fields that identify the specific part. You can use the values of these fields to determine the specific part you have received.

2.2 Format

Part numbers for this device have the following format: Q K## A M FFF R T PP CC N

2.3 Fields

This table lists the possible values for each field in the part number (not all combinations are valid): Field Description Values Q Qualification status • M = Fully qualified, general market flow

P = Prequalification K## Kinetis family • K11 A Key attribute • D = Cortex-M4 w/ DSP
F = Cortex-M4 w/ DSP and FPU M Flash memory type • N = Program flash only
X = Program flash and FlexMemory Table continues on the next page... Ordering parts K11 Sub-Family Data Sheet Data Sheet, Rev. 3, 08/2012. Freescale Semiconductor, Inc. 3

FFF Program flash memory size • 32 = 32 KB

64 = 64 KB
128 = 128 KB
256 = 256 KB
512 = 512 KB
1M0 = 1 MB R Silicon revision • Z = Initial
(Blank) = Main
A = Revision after main T Temperature range (°C) • V = –40 to 105
C = –40 to 85
FT = 48 QFN (7 mm x 7 mm)
LF = 48 LQFP (7 mm x 7 mm)
LH = 64 LQFP (10 mm x 10 mm)
MP = 64 MAPBGA (5 mm x 5 mm)
LK = 80 LQFP (12 mm x 12 mm)
LL = 100 LQFP (14 mm x 14 mm)
MC = 121 MAPBGA (8 mm x 8 mm)
LQ = 144 LQFP (20 mm x 20 mm)
MD = 144 MAPBGA (13 mm x 13 mm)
MJ = 256 MAPBGA (17 mm x 17 mm) CC Maximum CPU frequency (MHz) • 5 = 50 MHz
7 = 72 MHz
10 = 100 MHz
12 = 120 MHz
15 = 150 MHz N Packaging type • R = Tape and reel
(Blank) = Trays

2.4 Example

This is an example part number: MK11DX128VLK5

3 Terminology and guidelines

3.1 Definition: Operating requirement

An operating requirement is a specified value or range of values for a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useful life of the chip. Terminology and guidelines K11 Sub-Family Data Sheet Data Sheet, Rev. 3, 08/2012. 4 Freescale Semiconductor, Inc.

3.1.1 Example

This is an example of an operating requirement, which you must meet for the accompanying operating behaviors to be guaranteed: Symbol Description Min. Max. Unit VDD 1.0 V core supply voltage 0.9 1.1 V

3.2 Definition: Operating behavior

An operating behavior is a specified value or range of values for a technical characteristic that are guaranteed during operation if you meet the operating requirements and any other specified conditions.

3.2.1 Example

This is an example of an operating behavior, which is guaranteed if you meet the accompanying operating requirements: Symbol Description Min. Max. Unit IWP Digital I/O weak pullup/ pulldown current 10 130 µA

3.3 Definition: Attribute

An attribute is a specified value or range of values for a technical characteristic that are guaranteed, regardless of whether you meet the operating requirements.

3.3.1 Example

This is an example of an attribute: Symbol Description Min. Max. Unit CIN_D Input capacitance: digital pins — 7 pF Terminology and guidelines K11 Sub-Family Data Sheet Data Sheet, Rev. 3, 08/2012. Freescale Semiconductor, Inc. 5

3.4 Definition: Rating

A rating is a minimum or maximum value of a technical characteristic that, if exceeded, may cause permanent chip failure:

Operating ratings apply during operation of the chip.
Handling ratings apply when the chip is not powered.

3.4.1 Example

This is an example of an operating rating: Symbol Description Min. Max. Unit VDD 1.0 V core supply voltage –0.3 1.2 V

3.5 Result of exceeding a rating

Failures in time (ppm) The likelihood of permanent chip failure increases rapidly as soon as a characteristic begins to exceed one of its operating ratings. Terminology and guidelines K11 Sub-Family Data Sheet Data Sheet, Rev. 3, 08/2012. 6 Freescale Semiconductor, Inc.

3.6 Relationship between ratings and operating requirements

No permanent failure - Correct operation Normal operating rangeFatal range Expected permanent failure Fatal range Expected permanent failure Operating rating (max.)Operating requirement (max.)Operating requirement (min.)Operating rating (min.) Operating (power on) Degraded operating range Degraded operating range No permanent failure Handling rangeFatal range Expected permanent failure Fatal range Expected permanent failure Handling rating (max.)Handling rating (min.) Handling (power off) - No permanent failure - Possible decreased life - Possible incorrect operation - No permanent failure - Possible decreased life - Possible incorrect operation

3.7 Guidelines for ratings and operating requirements

Follow these guidelines for ratings and operating requirements:

Never exceed any of the chip’s ratings.
During normal operation, don’t exceed any of the chip’s operating requirements.
If you must exceed an operating requirement at times other than during normal operation (for example, during power sequencing), limit the duration as much as possible.

3.8 Definition: Typical value

A typical value is a specified value for a technical characteristic that:

Lies within the range of values specified by the operating behavior
Given the typical manufacturing process, is representative of that characteristic during operation when you meet the typical-value conditions or other specified conditions Typical values are provided as design guidelines and are neither tested nor guaranteed. Terminology and guidelines K11 Sub-Family Data Sheet Data Sheet, Rev. 3, 08/2012. Freescale Semiconductor, Inc. 7

3.8.1 Example 1

This is an example of an operating behavior that includes a typical value: Symbol Description Min. Typ. Max. Unit IWP Digital I/O weak pullup/pulldown current 10 70 130 µA

3.8.2 Example 2

This is an example of a chart that shows typical values for various voltage and temperature conditions: 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 150 °C 105 °C 25 °C –40 °C VDD (V) I (μA)DD_STOP TJ

3.9 Typical value conditions

Typical values assume you meet the following conditions (or other conditions as specified): Symbol Description Value Unit TA Ambient temperature 25 °C VDD 3.3 V supply voltage 3.3 V Terminology and guidelines K11 Sub-Family Data Sheet Data Sheet, Rev. 3, 08/2012. 8 Freescale Semiconductor, Inc.

4 Ratings

4.1 Thermal handling ratings

Symbol Description Min. Max. Unit Notes TSTG Storage temperature –55 150 °C 1 TSDR Solder temperature, lead-free — 260 °C 2 1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life. 2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices.

4.2 Moisture handling ratings

Symbol Description Min. Max. Unit Notes MSL Moisture sensitivity level — 3 — 1 1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices.

4.3 ESD handling ratings

Symbol Description Min. Max. Unit Notes VHBM Electrostatic discharge voltage, human body model -2000 +2000 V 1 VCDM Electrostatic discharge voltage, charged-device model -500 +500 V 2 ILAT Latch-up current at ambient temperature of 105°C -100 +100 mA 1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM). 2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.

4.4 Voltage and current operating ratings

Symbol Description Min. Max. Unit VDD Digital supply voltage –0.3 3.8 V Table continues on the next page... Ratings K11 Sub-Family Data Sheet Data Sheet, Rev. 3, 08/2012. Freescale Semiconductor, Inc. 9

Analog pins are defined as pins that do not have an associated general purpose I/O port function.

5 General

5.1 AC electrical characteristics

Figure 1. Input signal measurement reference

have C L=30pF loads,
are configured for fast slew rate (PORTx_PCRn[SRE]=0), and
are configured for high drive strength (PORTx_PCRn[DSE]=1) 2. input pins
have their passive filter disabled (PORTx_PCRn[PFE]=0)

5.2 Nonswitching electrical specifications

K11 Sub-Family Data Sheet Data Sheet, Rev. 3, 08/2012. 10 Freescale Semiconductor, Inc.

5.2.1 Voltage and current operating requirements

Table 1. Voltage and current operating requirements

2.7 V ≤ V DD ≤ 3.6 V
1.7 V ≤ V DD ≤ 2.7 V 0.7 × VDD 0.75 × VDD V V VIL Input low voltage
2.7 V ≤ V DD ≤ 3.6 V
1.7 V ≤ V DD ≤ 2.7 V 0.35 × VDD 0.3 × VDD V V VHYS Input hysteresis 0.06 × VDD — V IICIO I/O pin DC injection current — single pin
V IN < VSS-0.3V (Negative current injection)
V IN > VDD+0.3V (Positive current injection) mA IICcont Contiguous pin DC injection current —regional limit, includes sum of negative injection currents or sum of positive injection currents of 16 contiguous pins
Negative current injection
Positive current injection -25 +25 mA VRAM VDD voltage required to retain RAM 1.2 — V VRFVBAT VBAT voltage required to retain the VBAT register file VPOR_VBAT — V 1. All analog pins are internally clamped to VSS and VDD through ESD protection diodes. If VIN is greater than VAIO_MIN (=VSS-0.3V) and VIN is less than VAIO_MAX(=VDD+0.3V) is observed, then there is no need to provide current limiting resistors at the pads. If these limits cannot be observed then a current limiting resistor is required. The negative DC injection current limiting resistor is calculated as R=(VAIO_MIN-VIN)/|IIC|. The positive injection current limiting resistor is calcualted as R=(VIN-VAIO_MAX)/|IIC|. Select the larger of these two calculated resistances.

5.2.2 LVD and POR operating requirements

Table 2. V DD supply LVD and POR operating requirements Table continues on the next page... K11 Sub-Family Data Sheet Data Sheet, Rev. 3, 08/2012.

Table 2. V DD supply LVD and POR operating requirements (continued)

Level 1 falling (LVWV=00)
Level 2 falling (LVWV=01)
Level 3 falling (LVWV=10)
Level 4 falling (LVWV=11) 2.62 2.72 2.82 2.92 2.70 2.80 2.90 3.00 2.78 2.88 2.98 3.08 V V V V VHYSH Low-voltage inhibit reset/recover hysteresis — high range — ±80 — mV VLVDL Falling low-voltage detect threshold — low range (LVDV=00) 1.54 1.60 1.66 V VLVW1L VLVW2L VLVW3L VLVW4L Low-voltage warning thresholds — low range
Level 1 falling (LVWV=00)
Level 2 falling (LVWV=01)
Level 3 falling (LVWV=10)
Level 4 falling (LVWV=11) 1.74 1.84 1.94 2.04 1.80 1.90 2.00 2.10 1.86 1.96 2.06 2.16 V V V V VHYSL Low-voltage inhibit reset/recover hysteresis — low range — ±60 — mV VBG Bandgap voltage reference 0.97 1.00 1.03 V tLPO Internal low power oscillator period — factory trimmed 900 1000 1100 μs 1. Rising thresholds are falling threshold + hysteresis voltage

Table 3. VBAT power operating requirements

5.2.3 Voltage and current operating behaviors

Table 4. Voltage and current operating behaviors

2.7 V ≤ V DD ≤ 3.6 V, IOH = - 9 mA
1.71 V ≤ V DD ≤ 2.7 V, IOH = -3 mA VDD – 0.5 VDD – 0.5 V V Output high voltage — low drive strength
2.7 V ≤ V DD ≤ 3.6 V, IOH = -2 mA
1.71 V ≤ V DD ≤ 2.7 V, IOH = -0.6 mA VDD – 0.5 VDD – 0.5 V V IOHT Output high current total for all ports — 100 mA Table continues on the next page... General K11 Sub-Family Data Sheet Data Sheet, Rev. 3, 08/2012. 12 Freescale Semiconductor, Inc.

Table 4. Voltage and current operating behaviors (continued)

2.7 V ≤ V DD ≤ 3.6 V, IOL = 9 mA
1.71 V ≤ V DD ≤ 2.7 V, IOL = 3 mA 0.5 0.5 V V Output low voltage — low drive strength
2.7 V ≤ V DD ≤ 3.6 V, IOL = 2 mA
1.71 V ≤ V DD ≤ 2.7 V, IOL = 0.6 mA 0.5 0.5 V V IOLT Output low current total for all ports — 100 mA IIN Input leakage current (per pin)
@ full temperature range
@ 25 °C 1.0 0.1 μA μA IOZ Hi-Z (off-state) leakage current (per pin) — 1 μA IOZ Total Hi-Z (off-state) leakage current (all input pins) — 4 μA RPU Internal pullup resistors 22 50 kΩ 2 RPD Internal pulldown resistors 22 50 kΩ 3 1. Tested by ganged leakage method 2. Measured at Vinput = VSS 3. Measured at Vinput = VDD

5.2.4 Power mode transition operating behaviors

CPU and system clocks = 50 MHz
Bus clock = 50 MHz
Flash clock = 25 MHz

Table 5. Power mode transition operating behaviors across the operating temperature range of the chip.

VLLS0 → RUN — 130 μs
VLLS1 → RUN — 130 μs
VLLS2 → RUN — 70 μs Table continues on the next page... General K11 Sub-Family Data Sheet Data Sheet, Rev. 3, 08/2012. Freescale Semiconductor, Inc. 13

Table 5. Power mode transition operating behaviors (continued)

VLLS3 → RUN — 70 μs
LLS → RUN — 6 μs
VLPS → RUN — 5.2 μs
STOP → RUN — 5.2 μs

5.2.5 Power consumption operating behaviors

Table 6. Power consumption operating behaviors

@ 1.8V
@ 3.0V 12.98 12.93 13.8 mA mA IDD_RUN Run mode current — all peripheral clocks enabled, code executing from flash
@ 1.8V
@ 3.0V
@ 25°C
@ 125°C 17.04 17.01 18.21 19.3 18.9 mA mA mA 3, 4 IDD_WAIT Wait mode high frequency current at 3.0 V — all peripheral clocks disabled — 7.95 9.5 mA 2 IDD_WAIT Wait mode reduced frequency current at 3.0 V — all peripheral clocks disabled — 5.88 7.4 mA 5 IDD_STOP Stop mode current at 3.0 V — 320 436 μA IDD_VLPR Very-low-power run mode current at 3.0 V — all peripheral clocks disabled — 867 — μA 6 IDD_VLPR Very-low-power run mode current at 3.0 V — all peripheral clocks enabled — 1.1 — mA 7 IDD_VLPW Very-low-power wait mode current at 3.0 V — 509 — μA 8 IDD_VLPS Very-low-power stop mode current at 3.0 V — 7.33 24.2 μA IDD_LLS Low leakage stop mode current at 3.0 V
@ –40 to 25°C
@ 50°C
@ 70°C
@ 105°C — 3.14 6.48 13.85 55.53 4.8 μA Table continues on the next page... General K11 Sub-Family Data Sheet Data Sheet, Rev. 3, 08/2012. 14 Freescale Semiconductor, Inc.

Table 6. Power consumption operating behaviors (continued)

@ –40 to 25°C
@ 50°C
@ 70°C
@ 105°C — 2.19 4.35 8.92 35.33 3.4 μA IDD_VLLS2 Very low-leakage stop mode 2 current at 3.0 V
@ –40 to 25°C
@ 50°C
@ 70°C
@ 105°C — 1.77 2.81 5.20 19.88 3.1 μA IDD_VLLS1 Very low-leakage stop mode 1 current at 3.0 V
@ –40 to 25°C
@ 50°C
@ 70°C
@ 105°C — 1.03 1.92 4.03 17.43 1.8 μA IDD_VLLS0 Very low-leakage stop mode 0 current at 3.0 V with POR detect circuit enabled
@ –40 to 25°C
@ 50°C
@ 70°C
@ 105°C — 543 nA 1.36 3.39 16.52 1.1 μA IDD_VLLS0 Very low-leakage stop mode 0 current at 3.0 V with POR detect circuit disabled
@ –40 to 25°C
@ 50°C
@ 70°C
@ 105°C — 359 nA 1.03 2.87 15.20 950nA μA IDD_VBAT Average current when CPU is not accessing RTC registers at 3.0 V
@ –40 to 25°C
@ 50°C
@ 70°C
@ 105°C — 0.91 1.1 1.5 4.3 1.1 1.35 1.85 5.7 μA 9 1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See each module's specification for its supply current. 2. 50MHz core and system clock, 25MHz bus clock, and 25MHz flash clock . MCG configured for FEI mode. All peripheral clocks disabled. 3. 50MHz core and system clock, 25MHz bus clock, and 25MHz flash clock. MCG configured for FEI mode. All peripheral clocks enabled, and peripherals are in active operation. 4. Max values are measured with CPU executing DSP instructions 5. 25MHz core and system clock, 25MHz bus clock, and 12.5MHz flash clock. MCG configured for FEI mode. 6. 2 MHz core, system, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. All peripheral clocks disabled. Code executing from flash. 7. 2 MHz core, system, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. All peripheral clocks enabled but peripherals are not in active operation. Code executing from flash. 8. 2 MHz core, system, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. All peripheral clocks disabled. 9. Includes 32kHz oscillator current and RTC operation. General K11 Sub-Family Data Sheet Data Sheet, Rev. 3, 08/2012. Freescale Semiconductor, Inc. 15

5.2.5.1 Diagram: Typical IDD_RUN operating behavior

MCG in FBE mode
No GPIOs toggled
Code execution from flash with cache enabled
For the ALLOFF curve, all peripheral clocks are disabled except FTFL

Figure 2. Run mode supply current vs. core frequency K11 Sub-Family Data Sheet Data Sheet, Rev. 3, 08/2012. 16 Freescale Semiconductor, Inc.

Figure 3. VLPR mode supply current vs. core frequency

5.2.6 EMC radiated emissions operating behaviors

Table 7. EMC radiated emissions operating behaviors 1

This data was collected on a MK20DN128VLH5 64pin LQFP device.
Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions, 150

measured orientations in each frequency range. K11 Sub-Family Data Sheet Data Sheet, Rev. 3, 08/2012.

Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and Wideband

5.2.7 Designing with radiated emissions in mind

Perform a keyword search for “EMC design.”

5.2.8 Capacitance attributes

Table 8. Capacitance attributes

5.3 Switching specifications

5.3.1 Device clock specifications

Table 9. Device clock specifications K11 Sub-Family Data Sheet Data Sheet, Rev. 3, 08/2012. 18 Freescale Semiconductor, Inc.

The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for any

5.3.2 General switching specifications

Table 10. General switching specifications

Slew disabled
1.71 ≤ V DD ≤ 2.7V
Slew enabled
1.71 ≤ V DD ≤ 2.7V ns ns ns ns Port rise and fall time (low drive strength)
Slew disabled
1.71 ≤ V DD ≤ 2.7V
Slew enabled
1.71 ≤ V DD ≤ 2.7V ns ns ns ns 1. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or may not be recognized. In Stop, VLPS, LLS, and VLLSx modes, the synchronizer is bypassed so shorter pulses can be recognized in that case. 2. The greater synchronous and asynchronous timing must be met. 3. This is the minimum pulse width that is guaranteed to be recognized as a pin interrupt request in Stop, VLPS, LLS, and VLLSx modes. 4. 75pF load 5. 15pF load General K11 Sub-Family Data Sheet Data Sheet, Rev. 3, 08/2012. Freescale Semiconductor, Inc. 19

5.4 Thermal specifications

5.4.1 Thermal operating requirements

Table 11. Thermal operating requirements

5.4.2 Thermal attributes

Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site

K11 Sub-Family Data Sheet Data Sheet, Rev. 3, 08/2012. 20 Freescale Semiconductor, Inc.

Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental

JESD51-3 specification. For the MAPBGA, the board meets the JESD51-9 specification.

Determined according to JEDEC Standard JESD51-6, Integrated Circuits Thermal Test Method Environmental

Conditions—Forced Convection (Moving Air) with the board horizontal.

Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental

Conditions—Junction-to-Board. Board temperature is measured on the top surface of the board near the package.

Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate

between the top of the package and the cold plate.

Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental

Conditions—Natural Convection (Still Air).

6 Peripheral operating requirements and behaviors

6.1 Core modules

6.1.1 JTAG electricals

Table 12. JTAG limited voltage range electricals

Boundary Scan
JTAG and CJTAG
Serial Wire Debug MHz J2 TCLK cycle period 1/J1 — ns J3 TCLK clock pulse width
Boundary Scan
JTAG and CJTAG
Serial Wire Debug ns ns ns J4 TCLK rise and fall times — 3 ns J5 Boundary scan input data setup time to TCLK rise 20 — ns J6 Boundary scan input data hold time after TCLK rise 0 — ns J7 TCLK low to boundary scan output data valid — 25 ns J8 TCLK low to boundary scan output high-Z — 25 ns J9 TMS, TDI input data setup time to TCLK rise 8 — ns J10 TMS, TDI input data hold time after TCLK rise 1 — ns J11 TCLK low to TDO data valid — 17 ns J12 TCLK low to TDO high-Z — 17 ns J13 TRST assert time 100 — ns J14 TRST setup time (negation) to TCLK high 8 — ns Peripheral operating requirements and behaviors K11 Sub-Family Data Sheet Data Sheet, Rev. 3, 08/2012. Freescale Semiconductor, Inc. 21

Table 13. JTAG full voltage range electricals

Boundary Scan
JTAG and CJTAG
Serial Wire Debug MHz J2 TCLK cycle period 1/J1 — ns J3 TCLK clock pulse width
Boundary Scan
JTAG and CJTAG
Serial Wire Debug 12.5 ns ns ns J4 TCLK rise and fall times — 3 ns J5 Boundary scan input data setup time to TCLK rise 20 — ns J6 Boundary scan input data hold time after TCLK rise 0 — ns J7 TCLK low to boundary scan output data valid — 25 ns J8 TCLK low to boundary scan output high-Z — 25 ns J9 TMS, TDI input data setup time to TCLK rise 8 — ns J10 TMS, TDI input data hold time after TCLK rise 1.4 — ns J11 TCLK low to TDO data valid — 22.1 ns J12 TCLK low to TDO high-Z — 22.1 ns J13 TRST assert time 100 — ns J14 TRST setup time (negation) to TCLK high 8 — ns J3 J3 J4 J4 TCLK (input)

Figure 4. Test clock input timing K11 Sub-Family Data Sheet Data Sheet, Rev. 3, 08/2012. 22 Freescale Semiconductor, Inc.

Figure 7. TRST timing

6.2 System modules

There are no specifications necessary for the device's system modules.

6.3 Clock modules

6.3.1 MCG specifications

Table 14. MCG specifications Table continues on the next page... K11 Sub-Family Data Sheet Data Sheet, Rev. 3, 08/2012. 24 Freescale Semiconductor, Inc.

Table 14. MCG specifications (continued)

f VCO = 48 MHz
f VCO = 98 MHz 180 150 ps tfll_acquire FLL target frequency acquisition time — — 1 ms 6 PLL fvco VCO operating frequency 48.0 — 100 MHz Ipll PLL operating current
PLL @ 96 MHz (f osc_hi_1 = 8 MHz, fpll_ref =

2 MHz, VDIV multiplier = 48)

PLL @ 48 MHz (f osc_hi_1 = 8 MHz, fpll_ref =

2 MHz, VDIV multiplier = 24)

f vco = 48 MHz
f vco = 100 MHz 120 ps ps Jacc_pll PLL accumulated jitter over 1µs (RMS)
f vco = 48 MHz
f vco = 100 MHz 1350 600 ps ps Dlock Lock entry frequency tolerance ± 1.49 — ± 2.98 % Dunl Lock exit frequency tolerance ± 4.47 — ± 5.97 % Table continues on the next page... Peripheral operating requirements and behaviors K11 Sub-Family Data Sheet Data Sheet, Rev. 3, 08/2012. Freescale Semiconductor, Inc. 25

This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock
These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0.
The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency deviation

(Δfdco_t) over voltage and temperature should be considered.

These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1.
The resulting clock frequency must not exceed the maximum specified clock frequency of the device.
This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed,

FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.

Excludes any oscillator currents that are also consuming power while PLL is in operation.
This specification was obtained using a Freescale developed PCB. PLL jitter is dependent on the noise characteristics of

each PCB and results will vary.

This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled

6.3.2 Oscillator electrical specifications

This section provides the electrical characteristics of the module.

6.3.2.1 Oscillator DC electrical specifications

Table 15. Oscillator DC electrical specifications

32 kHz
4 MHz
8 MHz (RANGE=01)
16 MHz
24 MHz
32 MHz 500 200 300 950 1.2 1.5 nA μA μA μA mA mA Table continues on the next page... Peripheral operating requirements and behaviors K11 Sub-Family Data Sheet Data Sheet, Rev. 3, 08/2012. 26 Freescale Semiconductor, Inc.

Table 15. Oscillator DC electrical specifications (continued)

32 kHz
4 MHz
8 MHz (RANGE=01)
16 MHz
24 MHz
32 MHz 400 500 2.5 μA μA μA mA mA mA Cx EXTAL load capacitance — — — 2, 3 Cy XTAL load capacitance — — — 2, 3 RF Feedback resistor — low-frequency, low-power mode (HGO=0) — — — MΩ 2, 4 Feedback resistor — low-frequency, high-gain mode (HGO=1) — 10 — MΩ Feedback resistor — high-frequency, low-power mode (HGO=0) — — — MΩ Feedback resistor — high-frequency, high-gain mode (HGO=1) — 1 — MΩ RS Series resistor — low-frequency, low-power mode (HGO=0) — — — kΩ Series resistor — low-frequency, high-gain mode (HGO=1) — 200 — kΩ Series resistor — high-frequency, low-power mode (HGO=0) — — — kΩ Series resistor — high-frequency, high-gain mode (HGO=1) kΩ Vpp5 Peak-to-peak amplitude of oscillation (oscillator mode) — low-frequency, low-power mode (HGO=0) — 0.6 — V Peak-to-peak amplitude of oscillation (oscillator mode) — low-frequency, high-gain mode (HGO=1) — VDD — V Peak-to-peak amplitude of oscillation (oscillator mode) — high-frequency, low-power mode (HGO=0) — 0.6 — V Peak-to-peak amplitude of oscillation (oscillator mode) — high-frequency, high-gain mode (HGO=1) — VDD — V 1. VDD=3.3 V, Temperature =25 °C 2. See crystal or resonator manufacturer's recommendation 3. Cx,Cy can be provided by using either the integrated capacitors or by using external components. 4. When low power mode is selected, RF is integrated and must not be attached externally. 5. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any other devices. Peripheral operating requirements and behaviors K11 Sub-Family Data Sheet Data Sheet, Rev. 3, 08/2012. Freescale Semiconductor, Inc. 27

6.3.2.2 Oscillator frequency specifications

Table 16. Oscillator frequency specifications

Other frequency limits may apply when external clock is being used as a reference for the FLL or PLL.
When transitioning from FBE to FEI mode, restrict the frequency of the input clock so that, when it is divided by FRDIV, it

remains within the limits of the DCO input clock frequency.

Proper PC board layout procedures must be followed to achieve specifications.
Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S register

This section describes the module electrical characteristics. Table 17. 32kHz oscillator DC electrical specifications

When a crystal is being used with the 32 kHz oscillator, the EXTAL32 and XTAL32 pins should only be connected to

required oscillator components and must not be connected to any other devices. K11 Sub-Family Data Sheet Data Sheet, Rev. 3, 08/2012. 28 Freescale Semiconductor, Inc.

Table 18. 32kHz oscillator frequency specifications

Proper PC board layout procedures must be followed to achieve specifications.
This specification is for an externally supplied clock driven to EXTAL32 and does not apply to any other clock input. The

oscillator remains enabled and XTAL32 must be left unconnected.

The parameter specified is a peak-to-peak value and VIH and VIL specifications do not apply. The voltage of the applied

clock must be within the range of VSS to VBAT.

6.4 Memories and memory interfaces

6.4.1 Flash electrical specifications

This section describes the electrical characteristics of the flash memory module.

6.4.1.1 Flash timing specifications — program and erase

active and do not include command overhead. Table 19. NVM program/erase timing specifications

Maximum time based on expectations at cycling end-of-life.

K11 Sub-Family Data Sheet Data Sheet, Rev. 3, 08/2012.

6.4.1.2 Flash timing specifications — commands

Table 20. Flash command timing specifications

64 KB program flash
256 KB program flash 0.9 1.7 ms ms tpgmchk Program Check execution time — — 45 μs 1 trdrsrc Read Resource execution time — — 30 μs 1 tpgm4 Program Longword execution time — 65 145 μs tersblk64k tersblk256k Erase Flash Block execution time
64 KB program flash
256 KB program flash 122 580 985 ms ms tersscr Erase Flash Sector execution time — 14 114 ms 2 tpgmsec512 tpgmsec1k tpgmsec2k Program Section execution time
512 B flash
1 KB flash
2 KB flash 2.4 4.7 9.3 ms ms ms trd1all Read 1s All Blocks execution time — — 1.8 ms trdonce Read Once execution time — — 25 μs 1 tpgmonce Program Once execution time — 65 — μs tersall Erase All Blocks execution time — 250 2000 ms 2 tvfykey Verify Backdoor Access Key execution time — — 30 μs 1 tswapx01 tswapx02 tswapx04 tswapx08 Swap Control execution time
control code 0x01
control code 0x02
control code 0x04
control code 0x08 200 150 150 μs μs μs μs tpgmpart64k Program Partition for EEPROM execution time
64 KB FlexNVM 138 ms tsetramff tsetram32k tsetram64k Set FlexRAM Function execution time:
Control Code 0xFF
32 KB EEPROM backup
64 KB EEPROM backup 0.8 μs ms Byte-write to FlexRAM for EEPROM operation teewr8bers Byte-write to erased FlexRAM location execution time — 175 260 μs 3 Table continues on the next page... Peripheral operating requirements and behaviors K11 Sub-Family Data Sheet Data Sheet, Rev. 3, 08/2012. 30 Freescale Semiconductor, Inc.

Table 20. Flash command timing specifications (continued)

32 KB EEPROM backup
64 KB EEPROM backup
128 KB EEPROM backup 385 475 650 1800 2000 2400 μs μs μs Word-write to FlexRAM for EEPROM operation teewr16bers Word-write to erased FlexRAM location execution time — 175 260 μs teewr16b32k teewr16b64k teewr16b128k Word-write to FlexRAM execution time:
32 KB EEPROM backup
64 KB EEPROM backup
128 KB EEPROM backup 385 475 650 1800 2000 2400 μs μs μs Longword-write to FlexRAM for EEPROM operation teewr32bers Longword-write to erased FlexRAM location execution time — 360 540 μs teewr32b32k teewr32b64k teewr32b128k Longword-write to FlexRAM execution time:
32 KB EEPROM backup
64 KB EEPROM backup
128 KB EEPROM backup 630 810 1200 2050 2250 2675 μs μs μs 1. Assumes 25MHz flash clock frequency. 2. Maximum times for erase parameters based on expectations at cycling end-of-life. 3. For byte-writes to an erased FlexRAM location, the aligned word containing the byte must be erased.

6.4.1.3 Flash high voltage current behaviors

Table 21. Flash high voltage current behaviors

6.4.1.4 Reliability specifications

Table 22. NVM reliability specifications Table continues on the next page... K11 Sub-Family Data Sheet Data Sheet, Rev. 3, 08/2012.

Table 22. NVM reliability specifications (continued)

EEPROM backup to FlexRAM ratio = 16
EEPROM backup to FlexRAM ratio = 128
EEPROM backup to FlexRAM ratio = 512
EEPROM backup to FlexRAM ratio = 4096 35 K 315 K 1.27 M 10 M 175 K 1.6 M 6.4 M 50 M writes writes writes writes 1. Typical data retention values are based on measured response accelerated at high temperature and derated to a constant 25°C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in Engineering Bulletin EB619. 2. Cycling endurance represents number of program/erase cycles at -40°C ≤ Tj ≤ °C. 3. Write endurance represents the number of writes to each FlexRAM location at -40°C ≤Tj ≤ °C influenced by the cycling endurance of the FlexNVM (same value as data flash) and the allocated EEPROM backup per subsystem. Minimum and typical values assume all byte-writes to FlexRAM.

6.4.2 EzPort Switching Specifications

Table 23. EzPort switching specifications K11 Sub-Family Data Sheet Data Sheet, Rev. 3, 08/2012. 32 Freescale Semiconductor, Inc.

Figure 8. EzPort Timing Diagram

6.5 Security and integrity modules

6.6 Analog

6.6.1 ADC electrical specifications

differential pins ADCx_DP0, ADCx_DM0. Table 24. 16-bit ADC operating conditions

1.13 VDDA VDDA V

Table continues on the next page... K11 Sub-Family Data Sheet Data Sheet, Rev. 3, 08/2012.

Table 24. 16-bit ADC operating conditions (continued)

8-/10-/12-bit modes pF RADIN Input resistance — 2 5 kΩ RAS Analog source resistance 13-/12-bit modes fADCK < 4 MHz kΩ fADCK ADC conversion clock frequency ≤ 13-bit mode 1.0 — 18.0 MHz 4 fADCK ADC conversion clock frequency 16-bit mode 2.0 — 12.0 MHz 4 Crate ADC conversion rate ≤ 13 bit modes No ADC hardware averaging Continuous conversions enabled, subsequent conversion time 20.000 818.330 Ksps Crate ADC conversion rate 16-bit mode No ADC hardware averaging Continuous conversions enabled, subsequent conversion time 37.037 461.467 Ksps 1. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 2. DC potential difference. 3. This resistance is external to MCU. The analog source resistance must be kept as low as possible to achieve the best results. The results in this data sheet were derived from a system which has < 8 Ω analog source resistance. The RAS/CAS time constant should be kept to < 1ns. 4. To use the maximum ADC conversion clock frequency, the ADHSC bit must be set and the ADLPC bit must be clear. 5. For guidelines and examples of conversion rate calculation, download the ADC calculator tool: http://cache.freescale.com/ files/soft_dev_tools/software/app_software/converters/ADC_CALCULATOR_CNV.zip?fpsp=1 Peripheral operating requirements and behaviors K11 Sub-Family Data Sheet Data Sheet, Rev. 3, 08/2012. 34 Freescale Semiconductor, Inc.

Figure 9. ADC input impedance equivalency diagram Table 25. 16-bit ADC characteristics (V REFH = VDDA, VREFL = VSSA)

ADLPC = 1, ADHSC = 0
ADLPC = 1, ADHSC = 1
ADLPC = 0, ADHSC = 0
ADLPC = 0, ADHSC = 1 1.2 2.4 3.0 4.4 2.4 4.0 5.2 6.2 3.9 6.1 7.3 9.5 MHz MHz MHz MHz tADACK = 1/ fADACK Sample Time See Reference Manual chapter for sample times TUE Total unadjusted error
12-bit modes
<12-bit modes ±1.4 ±6.8 ±2.1 LSB4 5 DNL Differential non- linearity
12-bit modes
<12-bit modes ±0.7 ±0.2 -1.1 to +1.9 -0.3 to 0.5 LSB4 5 INL Integral non- linearity
12-bit modes
<12-bit modes ±1.0 ±0.5 -2.7 to +1.9 -0.7 to +0.5 LSB4 5 EFS Full-scale error • 12-bit modes
<12-bit modes -1.4 -5.4 -1.8 LSB4 VADIN = VDDA Table continues on the next page... Peripheral operating requirements and behaviors K11 Sub-Family Data Sheet Data Sheet, Rev. 3, 08/2012. Freescale Semiconductor, Inc. 35

Table 25. 16-bit ADC characteristics (V REFH = VDDA, VREFL = VSSA) (continued)

16-bit modes
≤13-bit modes -1 to 0 ±0.5 LSB4 ENOB Effective number of bits 16-bit differential mode
Avg = 32
Avg = 4 16-bit single-ended mode
Avg = 32
Avg = 4 12.8 11.9 12.2 11.4 14.5 13.8 13.9 13.1 bits bits bits bits SINAD Signal-to-noise plus distortion See ENOB 6.02 × ENOB + 1.76 dB THD Total harmonic distortion 16-bit differential mode
Avg = 32 16-bit single-ended mode
Avg = 32 –94 -85 dB dB SFDR Spurious free dynamic range 16-bit differential mode
Avg = 32 16-bit single-ended mode
Avg = 32 dB dB EIL Input leakage error IIn × RAS mV IIn = leakage current (refer to the MCU's voltage and current operating ratings) Temp sensor slope Across the full temperature range of the device — 1.715 — mV/°C VTEMP25 Temp sensor voltage 25 °C — 719 — mV 1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA 2. Typical values assume VDDA = 3.0 V, Temp = 25°C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and the ADLPC bit (low power). For lowest power operation the ADLPC bit must be set, the HSC bit must be clear with 1 MHz ADC conversion clock speed. 4. 1 LSB = (VREFH - VREFL)/2N 5. ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11) 6. Input data is 100 Hz sine wave. ADC conversion clock < 12 MHz. 7. Input data is 1 kHz sine wave. ADC conversion clock < 12 MHz. Peripheral operating requirements and behaviors K11 Sub-Family Data Sheet Data Sheet, Rev. 3, 08/2012. 36 Freescale Semiconductor, Inc.

6.6.2 CMP and 6-bit DAC electrical specifications

Table 26. Comparator and 6-bit DAC electrical specifications

CR0[HYSTCTR] = 00
CR0[HYSTCTR] = 01
CR0[HYSTCTR] = 10
CR0[HYSTCTR] = 11 mV mV mV mV VCMPOh Output high VDD – 0.5 — — V VCMPOl Output low — — 0.5 V tDHS Propagation delay, high-speed mode (EN=1, PMODE=1) 20 50 200 ns tDLS Propagation delay, low-speed mode (EN=1, PMODE=0) 80 250 600 ns Analog comparator initialization delay2 — — 40 μs IDAC6b 6-bit DAC current adder (enabled) — 7 — μA INL 6-bit DAC integral non-linearity –0.5 — 0.5 LSB3 DNL 6-bit DAC differential non-linearity –0.3 — 0.3 LSB 1. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD-0.6V. 2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to DACEN, VRSEL, PSEL, MSEL, VOSEL) and the comparator output settling to a stable level. 3. 1 LSB = Vreference/64 Peripheral operating requirements and behaviors K11 Sub-Family Data Sheet Data Sheet, Rev. 3, 08/2012. 38 Freescale Semiconductor, Inc.

Figure 12. Typical hysteresis vs. Vin level (VDD=3.3V, PMODE=0) K11 Sub-Family Data Sheet Data Sheet, Rev. 3, 08/2012.

Figure 13. Typical hysteresis vs. Vin level (VDD=3.3V, PMODE=1)

6.7 Timers

See General switching specifications.

6.8 Communication interfaces

K11 Sub-Family Data Sheet Data Sheet, Rev. 3, 08/2012. 40 Freescale Semiconductor, Inc.

6.8.1 DSPI switching specifications (limited voltage range)

used for communicating with slower peripheral devices. Table 27. Master mode DSPI timing (limited voltage range)

The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].

Figure 14. DSPI classic SPI timing — master mode Table 28. Slave mode DSPI timing (limited voltage range) Table continues on the next page... K11 Sub-Family Data Sheet Data Sheet, Rev. 3, 08/2012.

Table 28. Slave mode DSPI timing (limited voltage range) (continued) Figure 15. DSPI classic SPI timing — slave mode

6.8.2 DSPI switching specifications (full voltage range)

used for communicating with slower peripheral devices. Table 29. Master mode DSPI timing (full voltage range) Table continues on the next page... K11 Sub-Family Data Sheet Data Sheet, Rev. 3, 08/2012. 42 Freescale Semiconductor, Inc.

Table 29. Master mode DSPI timing (full voltage range) (continued)

The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage

range the maximum frequency of operation is reduced.

The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].

Figure 16. DSPI classic SPI timing — master mode Table 30. Slave mode DSPI timing (full voltage range) K11 Sub-Family Data Sheet Data Sheet, Rev. 3, 08/2012.

Figure 17. DSPI classic SPI timing — slave mode

6.8.3 I2C switching specifications

See General switching specifications.

6.8.4 UART switching specifications

See General switching specifications.

6.8.5 Normal Run, Wait and Stop mode performance over the full

device in Normal Run, Wait and Stop modes. Table 31. I2S/SAI master mode timing Table continues on the next page... K11 Sub-Family Data Sheet Data Sheet, Rev. 3, 08/2012. 44 Freescale Semiconductor, Inc.

Table 31. I2S/SAI master mode timing (continued) Figure 18. I2S/SAI timing — master modes Table 32. I2S/SAI slave mode timing

Applies to first bit in each frame and only if the TCR4[FSE] bit is clear

K11 Sub-Family Data Sheet Data Sheet, Rev. 3, 08/2012.

Figure 19. I2S/SAI timing — slave modes

6.8.6 VLPR, VLPW, and VLPS mode performance over the full

device in VLPR, VLPW, and VLPS modes. Table 33. I2S/SAI master mode timing in VLPR, VLPW, and VLPS modes K11 Sub-Family Data Sheet Data Sheet, Rev. 3, 08/2012. 46 Freescale Semiconductor, Inc.

Figure 20. I2S/SAI timing — master modes Table 34. I2S/SAI slave mode timing in VLPR, VLPW, and VLPS modes (full

Applies to first bit in each frame and only if the TCR4[FSE] bit is clear

K11 Sub-Family Data Sheet Data Sheet, Rev. 3, 08/2012.

Figure 21. I2S/SAI timing — slave modes

7 Dimensions

7.1 Obtaining package dimensions

Package dimensions are provided in package drawings.

8 Pinout

8.1 K11 Signal Multiplexing and Pin Assignments

for selecting which ALT functionality is available on each pin.

The analog input signals ADC0_SE10, ADC0_SE11, ADC0_DP1, and ADC0_DM1 are available only for K11, Dimensions K11 Sub-Family Data Sheet Data Sheet, Rev. 3, 08/2012. 48 Freescale Semiconductor, Inc.

K12, K21, and K22 devices and are not present on K10 and K20 devices.

The TRACE signals on PTE0, PTE1, PTE2, PTE3, and PTE4 are available only for K11, K12, K21, and K22 devices and are not present on K10 and K20 devices.
If the VBAT pin is not used, the VBAT pin should be left floating. Do not connect VBAT pin to VSS.
The FTM_CLKIN signals on PTB16 and PTB17 are available only for K11, K12, K21, and K22 devices and are not present on K10 and K20 devices. For K11D devices this signal is on ALT7, and for K11F devices, this signal is on ALT4.
Ball A10, which is PTE19 on K11D and K21D devices, is not available on K11F and K21F devices. LQFP Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort

1 ADC0_SE10ADC0_SE10PTE0 SPI1_PCS1UART1_TX TRACE_CLKOUTI2C1_SDA RTC_CLKOUT

2 ADC0_SE11ADC0_SE11PTE1/

LLWU_P0 SPI1_SOUTUART1_RX TRACE_D3I2C1_SCL SPI1_SIN

3 ADC0_DP1 ADC0_DP1 PTE2/

LLWU_P1 SPI1_SCK UART1_CTS_b TRACE_D2

4 ADC0_DM1ADC0_DM1PTE3 SPI1_SIN UART1_RTS_b TRACE_D1 SPI1_SOUT

5 DISABLED PTE4/

LLWU_P2 SPI1_PCS0UART3_TX TRACE_D0

6 DISABLED PTE5 SPI1_PCS2UART3_RX

7 VDD VDD

8 VSS VSS

9 ADC0_SE4aADC0_SE4aPTE16 SPI0_PCS0UART2_TX FTM_CLKIN0 FTM0_FLT3

10 ADC0_SE5aADC0_SE5aPTE17 SPI0_SCK UART2_RXFTM_CLKIN1 LPTMR0_ALT3

11 ADC0_SE6aADC0_SE6aPTE18 SPI0_SOUTUART2_CTS_bI2C0_SDA

12 ADC0_SE7aADC0_SE7aPTE19 SPI0_SIN UART2_RTS_bI2C0_SCL

13 ADC0_DP0 ADC0_DP0

14 ADC0_DM0ADC0_DM0

15 ADC0_DP3 ADC0_DP3

16 ADC0_DM3ADC0_DM3

17 VDDA VDDA

20 VSSA VSSA

21 TAMPER0/

RTC_WAKEUP_ B TAMPER0/ RTC_WAKEUP_ B

22 TAMPER1 TAMPER1

K11 Sub-Family Data Sheet Data Sheet, Rev. 3, 08/2012. Freescale Semiconductor, Inc. 49

Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort

23 XTAL32 XTAL32

24 EXTAL32 EXTAL32

25 VBAT VBAT

26 JTAG_TCLK/

SWD_CLK/ EZP_CLK PTA0 UART0_CTS_b/ UART0_COL_b FTM0_CH5 JTAG_TCLK/ SWD_CLK EZP_CLK

27 JTAG_TDI/

EZP_DI PTA1 UART0_RXFTM0_CH6 JTAG_TDI EZP_DI

28 JTAG_TDO/

TRACE_SWO/ EZP_DO PTA2 UART0_TX FTM0_CH7 JTAG_TDO/ TRACE_SWO EZP_DO

29 JTAG_TMS/

SWD_DIO PTA3 UART0_RTS_bFTM0_CH0 JTAG_TMS/ SWD_DIO

30 NMI_b/

EZP_CS_b PTA4/ LLWU_P3 FTM0_CH1 NMI_b EZP_CS_b

31 DISABLED PTA5 FTM0_CH2 I2S0_TX_BCLKJTAG_TRST_b

32 DISABLED PTA12 FTM1_CH0 I2S0_TXD0 FTM1_QD_PHA

33 DISABLED PTA13/

LLWU_P4 FTM1_CH1 I2S0_TX_FSFTM1_QD_PHB

34 DISABLED PTA14 SPI0_PCS0UART0_TX I2S0_RX_BCLKI2S0_TXD1

35 DISABLED PTA15 SPI0_SCK UART0_RX I2S0_RXD0

36 DISABLED PTA16 SPI0_SOUTUART0_CTS_b/

UART0_COL_b I2S0_RX_FSI2S0_RXD1

37 DISABLED PTA17 SPI0_SIN UART0_RTS_b I2S0_MCLK

38 VDD VDD

39 VSS VSS

40 EXTAL0 EXTAL0 PTA18 FTM0_FLT2FTM_CLKIN0

41 XTAL0 XTAL0 PTA19 FTM1_FLT0FTM_CLKIN1 LPTMR0_ALT1

42 RESET_b RESET_b

43 ADC0_SE8 ADC0_SE8 PTB0/

LLWU_P5 I2C0_SCL FTM1_CH0 FTM1_QD_PHA

44 ADC0_SE9 ADC0_SE9 PTB1 I2C0_SDA FTM1_CH1 FTM1_QD_PHB

45 ADC0_SE12ADC0_SE12PTB2 I2C0_SCL UART0_RTS_b FTM0_FLT3

46 ADC0_SE13ADC0_SE13PTB3 I2C0_SDA UART0_CTS_b/

UART0_COL_b FTM0_FLT0

47 DISABLED PTB10 SPI1_PCS0UART3_RX FTM0_FLT1

48 DISABLED PTB11 SPI1_SCK UART3_TX FTM0_FLT2

49 DISABLED PTB12 UART3_RTS_bFTM1_CH0 FTM0_CH4 FTM1_QD_PHA

50 DISABLED PTB13 UART3_CTS_bFTM1_CH1 FTM0_CH5 FTM1_QD_PHB

51 DISABLED PTB16 SPI1_SOUTUART0_RX EWM_IN FTM_CLKIN0

52 DISABLED PTB17 SPI1_SIN UART0_TX EWM_OUT_bFTM_CLKIN1

53 DISABLED PTB18 FTM2_CH0 I2S0_TX_BCLK FTM2_QD_PHA

54 DISABLED PTB19 FTM2_CH1 I2S0_TX_FS FTM2_QD_PHB

55 ADC0_SE14ADC0_SE14PTC0 SPI0_PCS4PDB0_EXTRG I2S0_TXD1

K11 Sub-Family Data Sheet Data Sheet, Rev. 3, 08/2012. 50 Freescale Semiconductor, Inc.

Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort

56 ADC0_SE15ADC0_SE15PTC1/

LLWU_P6 SPI0_PCS3UART1_RTS_bFTM0_CH0 I2S0_TXD0

57 ADC0_SE4b/

CMP1_IN0 ADC0_SE4b/ CMP1_IN0 PTC2 SPI0_PCS2UART1_CTS_bFTM0_CH1 I2S0_TX_FS

58 CMP1_IN1 CMP1_IN1 PTC3/

LLWU_P7 SPI0_PCS1UART1_RXFTM0_CH2 I2S0_TX_BCLK

59 VSS VSS

60 VDD VDD

61 DISABLED PTC4/

LLWU_P8 SPI0_PCS0UART1_TX FTM0_CH3 CMP1_OUT

62 DISABLED PTC5/

LLWU_P9 SPI0_SCK LPTMR0_ALT2I2S0_RXD0 CMP0_OUTFTM0_CH2

63 CMP0_IN0 CMP0_IN0 PTC6/

LLWU_P10 SPI0_SOUTPDB0_EXTRGI2S0_RX_BCLK I2S0_MCLK

64 CMP0_IN1 CMP0_IN1 PTC7 SPI0_SIN I2S0_RX_FS

65 CMP0_IN2 CMP0_IN2 PTC8 I2S0_MCLK

66 CMP0_IN3 CMP0_IN3 PTC9 I2S0_RX_BCLK FTM2_FLT0

67 DISABLED PTC10 I2C1_SCL I2S0_RX_FS

68 DISABLED PTC11/

LLWU_P11 I2C1_SDA I2S0_RXD1

69 DISABLED PTC12

70 DISABLED PTC13

71 DISABLED PTC16 UART3_RX

72 DISABLED PTC17 UART3_TX

73 DISABLED PTD0/

LLWU_P12 SPI0_PCS0UART2_RTS_b

74 ADC0_SE5bADC0_SE5bPTD1 SPI0_SCK UART2_CTS_b

75 DISABLED PTD2/

LLWU_P13 SPI0_SOUTUART2_RXI2C0_SCL

76 DISABLED PTD3 SPI0_SIN UART2_TX I2C0_SDA

77 ADC0_SE21ADC0_SE21PTD4/

LLWU_P14 SPI0_PCS1UART0_RTS_bFTM0_CH4 EWM_IN

78 ADC0_SE6bADC0_SE6bPTD5 SPI0_PCS2UART0_CTS_b/

UART0_COL_b FTM0_CH5 EWM_OUT_b

79 ADC0_SE7bADC0_SE7bPTD6/

LLWU_P15 SPI0_PCS3UART0_RXFTM0_CH6 FTM0_FLT0

80 ADC0_SE22ADC0_SE22PTD7 CMT_IRO UART0_TX FTM0_CH7 FTM0_FLT1

8.2 K11 Pinouts

The below figure shows the pinout diagram for the devices supported by this document. Many signals may be multiplexed onto a single pin. To determine what signals can be used on which pin, see the previous section. Pinout K11 Sub-Family Data Sheet Data Sheet, Rev. 3, 08/2012. Freescale Semiconductor, Inc. 51

ADC0_DM3 ADC0_DP3 ADC0_DM0 ADC0_DP0 PTE19 PTE18 PTE17 PTE16 VSS VDD PTE5 PTE4/LLWU_P2 PTE3 PTE2/LLWU_P1 PTE1/LLWU_P0 PTE0 PTD7 PTD6/LLWU_P15 PTD5 PTD4/LLWU_P14 PTD3 PTD2/LLWU_P13 PTD1 PTD0/LLWU_P12 PTC17 PTC16 PTC13 PTC12 PTC11/LLWU_P11 PTC10 PTC9 PTC8 PTC7 PTC6/LLWU_P10 PTC5/LLWU_P9 PTC4/LLWU_P8 VDD VSS PTC3/LLWU_P7 PTC2 PTC1/LLWU_P6 PTC0 PTB19 PTB18 PTB17 PTB16 PTB13 PTB12 PTB11 PTB10 PTB3 PTB2 PTB1 PTB0/LLWU_P5 RESET_b PTA19 PTA18 VSS VDD PTA17 PTA16 PTA15 PTA14 PTA13/LLWU_P4 PTA12 PTA5 PTA4/LLWU_P3 PTA3 PTA2 PTA1 PTA0 VBAT EXTAL32 XTAL32 TAMPER1 TAMPER0/RTC_WAKEUP_B Figure 22. K11 80 LQFP Pinout Diagram

9 Revision History

The following table provides a revision history for this document.

Revision History

K11 Sub-Family Data Sheet Data Sheet, Rev. 3, 08/2012. 52 Freescale Semiconductor, Inc.

Table 35. Revision History 1 6/2012 Alpha customer release. IDD_VLLS1, IDD_VLLS0, and IDD_VBAT from nA to μA. 2 7/2012 • Updated section "Power consumption operating behaviors".

Updated section "Flash timing specifications — program and erase".
Updated section "Flash timing specifications — commands".
Removed the 32K ratio from "Write endurance" in section "Reliability specifications".
Updated IDDstby maximum value in section "VREG electrical specifications".
Added the charts in section "Diagram: Typical IDD_RUN operating behavior". 3 8/2012 • Updated section "Power consumption operating behaviors".
Updated section "EMC radiated emissions operating behaviors".
Updated section "MCG specifications".
Added applicable notes in section "Signal Multiplexing and Pin Assignments".

K11 Sub-Family Data Sheet Data Sheet, Rev. 3, 08/2012. Freescale Semiconductor, Inc. 53

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Product Information

K11P80M50SF4 specifications and overview.

Summary

K11 Sub-Family Data Sheet

Description

K11 Sub-Family Data Sheet

Source title K11P80M50SF4 Datasheet(PDF) - Freescale Semiconductor, Inc

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