K10P144M100SF2_11 FREESCALE | Alldatasheet
Document overview
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Technical content
Features
- Operating Characteristics – Voltage range: 1.71 to 3.6 V Flash write voltage range: 1.71 to 3.6 V – Temperature range (ambient): -40 to 105°C
- Performance – Up to 100 MHz ARM Cortex-M4 core with DSP instructions delivering 1.25 Dhrystone MIPS per MHz
- Memories and memory interfaces – Up to 512 KB program flash memory on non- FlexMemory devices – Up to 256 KB program flash memory on FlexMemory devices – Up to 256 KB FlexNVM on FlexMemory devices – 4 KB FlexRAM on FlexMemory devices – Up to 128 KB RAM – Serial programming interface (EzPort) – FlexBus external bus interface
- Clocks – 3 to 32 MHz crystal oscillator – 32 kHz crystal oscillator – Multi-purpose clock generator
- System peripherals – 10 low-power modes to provide power optimization based on application requirements – Memory protection unit with multi-master protection – 16-channel DMA controller, supporting up to 64 request sources – External watchdog monitor – Software watchdog – Low-leakage wakeup unit
- Security and integrity modules – Hardware CRC module to support fast cyclic redundancy checks 128-bit unique identification (ID) number per chip
- Human-machine interface – Low-power hardware touch sensor interface (TSI) – General-purpose input/output
- Analog modules – Two 16-bit SAR ADCs – Programmable gain amplifier (up to x64) integrated into each ADC – Two 12-bit DACs – Three analog comparators (CMP) containing a 6-bit DAC and programmable reference input – Voltage reference
- Timers – Programmable delay block – Eight-channel motor control/general purpose/PWM timer – Two 2-channel quadrature decoder/general purpose timers – Periodic interrupt timers – 16-bit low-power timer – Carrier modulator transmitter – Real-time clock
- Communication interfaces – Two Controller Area Network (CAN) modules – Three SPI modules – Two I2C modules – Six UART modules – Secure Digital host controller (SDHC) – I2S module Freescale Semiconductor Document Number: K10P144M100SF2 Data Sheet: Product Preview Rev. 4, 3/2011 This document contains information on a product under development. Freescale reserves the right to change or discontinue this product without notice. © 2010–2011 Freescale Semiconductor, Inc. Preliminary
K10 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. 2 Preliminary Freescale Semiconductor, Inc.
3.6 Relationship between ratings and operating
6.8.2 DSPI switching specifications (low-speed mode)..53
6.8.3 DSPI switching specifications (high-speed mode) 54
K10 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Preliminary 3
1 Ordering parts
1.1 Determining valid orderable parts
Valid orderable part numbers are provided on the web. To determine the orderable part numbers for this device, go to http://www.freescale.com and perform a part number search for the following device numbers: PK10 and MK10.
2 Part identification
2.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the values of these fields to determine the specific part you have received.
2.2 Format
Part numbers for this device have the following format: Q K## M FFF T PP CCC N
2.3 Fields
This table lists the possible values for each field in the part number (not all combinations are valid): Field Description Values Q Qualification status • M = Fully qualified, general market flow
- P = Prequalification K## Kinetis family • K10 M Flash memory type • N = Program flash only
- X = Program flash and FlexMemory Table continues on the next page... Ordering parts K10 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. 4 Preliminary Freescale Semiconductor, Inc.
FFF Program flash memory size • 32 = 32 KB
- 64 = 64 KB
- 128 = 128 KB
- 256 = 256 KB
- 512 = 512 KB
- 1M0 = 1 MB T Temperature range (°C) • V = –40 to 105
- C = –40 to 85
- FT = 48 QFN (7 mm x 7 mm)
- LF = 48 LQFP (7 mm x 7 mm)
- EX = 64 QFN (9 mm x 9 mm)
- LH = 64 LQFP (10 mm x 10 mm)
- LK = 80 LQFP (12 mm x 12 mm)
- MB = 81 MAPBGA (8 mm x 8 mm)
- LL = 100 LQFP (14 mm x 14 mm)
- MC = 121 MAPBGA (8 mm x 8 mm)
- LQ = 144 LQFP (20 mm x 20 mm)
- MD = 144 MAPBGA (13 mm x 13 mm)
- MF = 196 MAPBGA (15 mm x 15 mm)
- MJ = 256 MAPBGA (17 mm x 17 mm) CCC Maximum CPU frequency (MHz) • 50 = 50 MHz
- 72 = 72 MHz
- 100 = 100 MHz
- 120 = 120 MHz
- 150 = 150 MHz N Packaging type • R = Tape and reel
- (Blank) = Trays
2.4 Example
This is an example part number: MK10N512VMD100
3 Terminology and guidelines
3.1 Definition: Operating requirement
An operating requirement is a specified value or range of values for a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useful life of the chip. Terminology and guidelines K10 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Preliminary 5
3.1.1 Example
This is an example of an operating requirement, which you must meet for the accompanying operating behaviors to be guaranteed: Symbol Description Min. Max. Unit VDD 1.0 V core supply voltage 0.9 1.1 V
3.2 Definition: Operating behavior
An operating behavior is a specified value or range of values for a technical characteristic that are guaranteed during operation if you meet the operating requirements and any other specified conditions.
3.2.1 Example
This is an example of an operating behavior, which is guaranteed if you meet the accompanying operating requirements: Symbol Description Min. Max. Unit IWP Digital I/O weak pullup/ pulldown current 10 130 µA
3.3 Definition: Attribute
An attribute is a specified value or range of values for a technical characteristic that are guaranteed, regardless of whether you meet the operating requirements.
3.3.1 Example
This is an example of an attribute: Symbol Description Min. Max. Unit CIN_D Input capacitance: digital pins — 7 pF Terminology and guidelines K10 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. 6 Preliminary Freescale Semiconductor, Inc.
3.4 Definition: Rating
A rating is a minimum or maximum value of a technical characteristic that, if exceeded, may cause permanent chip failure:
- Operating ratings apply during operation of the chip.
- Handling ratings apply when the chip is not powered.
3.4.1 Example
This is an example of an operating rating: Symbol Description Min. Max. Unit VDD 1.0 V core supply voltage –0.3 1.2 V
3.5 Result of exceeding a rating
Failures in time (ppm) The likelihood of permanent chip failure increases rapidly as soon as a characteristic begins to exceed one of its operating ratings. Terminology and guidelines K10 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Preliminary 7
3.6 Relationship between ratings and operating requirements
- No permanent failure - Correct operation Normal operating range Limited operating range - No permanent failure - Possible decreased life - Possible incorrect operation Fatal range - Probable permanent failure Limited operating range - No permanent failure - Possible decreased life - Possible incorrect operation Handling range - No permanent failure Fatal range - Probable permanent failure Operating or handling rating (max.)Operating requirement (max.)Operating requirement (min.)Operating or handling rating (min.)
3.7 Guidelines for ratings and operating requirements
Follow these guidelines for ratings and operating requirements:
- Never exceed any of the chip’s ratings.
- During normal operation, don’t exceed any of the chip’s operating requirements.
- If you must exceed an operating requirement at times other than during normal operation (for example, during power sequencing), limit the duration as much as possible.
3.8 Definition: Typical value
A typical value is a specified value for a technical characteristic that:
- Lies within the range of values specified by the operating behavior
- Given the typical manufacturing process, is representative of that characteristic during operation when you meet the typical-value conditions or other specified conditions Typical values are provided as design guidelines and are neither tested nor guaranteed.
3.8.1 Example 1
This is an example of an operating behavior that includes a typical value: Terminology and guidelines K10 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. 8 Preliminary Freescale Semiconductor, Inc.
Symbol Description Min. Typ. Max. Unit IWP Digital I/O weak pullup/pulldown current 10 70 130 µA
3.8.2 Example 2
This is an example of a chart that shows typical values for various voltage and temperature conditions: 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 150 °C 105 °C 25 °C –40 °C VDD (V) I (μA)DD_STOP TJ
3.9 Typical value conditions
Typical values assume you meet the following conditions (or other conditions as specified): Symbol Description Value Unit TA Ambient temperature 25 °C VDD 3.3 V supply voltage 3.3 V
4 Ratings
K10 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Preliminary 9
4.1 Thermal handling ratings
Symbol Description Min. Max. Unit Notes TSTG Storage temperature –55 150 °C 1 TSDR Solder temperature, lead-free — 260 °C 2 Solder temperature, leaded — 245 1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life. 2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices.
4.2 Moisture handling ratings
Symbol Description Min. Max. Unit Notes MSL Moisture sensitivity level — 3 — 1 1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices.
4.3 ESD handling ratings
Symbol Description Min. Max. Unit Notes VHBM Electrostatic discharge voltage, human body model -2000 +2000 V 1 VCDM Electrostatic discharge voltage, charged-device model -500 +500 V 2 ILAT Latch-up current at ambient temperature of 85°C -100 +100 mA 1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM). 2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
4.4 Voltage and current operating ratings
Symbol Description Min. Max. Unit VDD Digital supply voltage –0.3 3.8 V IDD Digital supply current — 185 mA VDIO Digital input voltage (except RESET, EXTAL, and XTAL) –0.3 5.5 V Table continues on the next page... Ratings K10 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. 10 Preliminary Freescale Semiconductor, Inc.
5 General
5.1 Nonswitching electrical specifications
5.1.1 Voltage and current operating requirements
Table 1. Voltage and current operating requirements
- 2.7 V ≤ V DD ≤ 3.6 V
- 1.7 V ≤ V DD ≤ 2.7 V 0.7 × VDD 0.75 × VDD V V VIL Input low voltage
- 2.7 V ≤ V DD ≤ 3.6 V
- 1.7 V ≤ V DD ≤ 2.7 V 0.35 × VDD 0.3 × VDD V V VHYS Input hysteresis 0.06 × VDD — V IIC DC injection current — single pin
- V IN < VSS –0.2 mA DC injection current — total MCU limit, includes sum of all stressed pins
- V IN < VSS mA VRAM VDD voltage required to retain RAM 1.2 — V VRFVBAT VBAT voltage required to retain the VBAT register file TBD — V General K10 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Preliminary 11
- All functional non-supply pins are internally clamped to VSS, and induce an injection current when VIN is less than VSS. The
limited to the value specified.
5.1.2 LVD and POR operating requirements
Table 2. V DD supply LVD and POR operating requirements
- Level 1 falling (LVWV=00)
- Level 2 falling (LVWV=01)
- Level 3 falling (LVWV=10)
- Level 4 falling (LVWV=11) TBD TBD TBD TBD 2.70 2.80 2.90 3.00 TBD TBD TBD TBD V V V V VHYSH Low-voltage inhibit reset/recover hysteresis — high range 60 mV VLVDL Falling low-voltage detect threshold — low range (LVDV=00) TBD 1.60 TBD V VLVW1L VLVW2L VLVW3L VLVW4L Low-voltage warning thresholds — low range
- Level 1 falling (LVWV=00)
- Level 2 falling (LVWV=01)
- Level 3 falling (LVWV=10)
- Level 4 falling (LVWV=11) TBD TBD TBD TBD 1.80 1.90 2.00 2.10 TBD TBD TBD TBD V V V V VHYSL Low-voltage inhibit reset/recover hysteresis — low range 40 mV VBG Bandgap voltage reference TBD 1.00 TBD V tLPO Internal low power oscillator period factory trimmed TBD 1000 TBD μs 1. Rising thresholds are falling threshold + hysteresis voltage
Table 3. VBAT power operating requirements K10 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. 12 Preliminary Freescale Semiconductor, Inc.
5.1.3 Voltage and current operating behaviors
Table 4. Voltage and current operating behaviors
- 2.7 V ≤ V DD ≤ 3.6 V, IOH = -10mA
- 1.71 V ≤ V DD ≤ 2.7 V, IOH = -3mA VDD – 0.5 VDD – 0.5 V V Output high voltage — low drive strength
- 2.7 V ≤ V DD ≤ 3.6 V, IOH = -2mA
- 1.71 V ≤ V DD ≤ 2.7 V, IOH = -0.6mA VDD – 0.5 VDD – 0.5 V V IOHT Output high current total for all ports — 100 mA VOL Output low voltage — high drive strength
- 2.7 V ≤ V DD ≤ 3.6 V, IOL = 10mA
- 1.71 V ≤ V DD ≤ 2.7 V, IOL = 3mA 0.5 0.5 V V Output low voltage — low drive strength
- 2.7 V ≤ V DD ≤ 3.6 V, IOL = 2mA
- 1.71 V ≤ V DD ≤ 2.7 V, IOL = 0.6mA 0.5 0.5 V V IOLT Output low current total for all ports — 100 mA IIN Input leakage current (per pin) — 1 μA 1 IOZ Hi-Z (off-state) leakage current (per pin) — 1 μA RPU Internal pullup resistors 30 50 kΩ 2 RPD Internal pulldown resistors 30 50 kΩ 3 1. Measured at VDD=3.6V 2. Measured at VDD supply voltage = VDD min and Vinput = VSS 3. Measured at VDD supply voltage = VDD min and Vinput = VDD
5.1.4 Power mode transition operating behaviors
- CPU and system clocks = 100 MHz
- Bus and FlexBus clocks = 50 MHz
- Flash clock = 25 MHz General K10 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Preliminary 13
Table 5. Power mode transition operating behaviors across the operating temperature range of the chip.
- RUN → VLLS1
- VLLS1 → RUN 4.1 123.8 μs μs RUN → VLLS2 → RUN
- RUN → VLLS2
- VLLS2 → RUN 4.1 49.3 μs μs RUN → VLLS3 → RUN
- RUN → VLLS3
- VLLS3 → RUN 4.1 49.2 μs μs RUN → LLS → RUN
- RUN → LLS
- LLS → RUN 4.1 5.9 μs μs RUN → STOP → RUN
- RUN → STOP
- STOP → RUN 4.1 4.2 μs μs RUN → VLPS → RUN
- RUN → VLPS
- VLPS → RUN 4.1 5.8 μs μs 1. Normal boot (FTFL_OPT[LPBOOT]=1)
5.1.5 Power consumption operating behaviors
Table 6. Power consumption operating behaviors
- @ 1.8V
- @ 3.0V TBD TBD mA mA Table continues on the next page... General K10 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. 14 Preliminary Freescale Semiconductor, Inc.
Table 6. Power consumption operating behaviors (continued)
- @ 1.8V
- @ 3.0V TBD TBD mA mA IDD_RUN_M AX Run mode current — all peripheral clocks enabled and peripherals active, code executing from flash
- @ 1.8V
- @ 3.0V TBD TBD mA mA IDD_WAIT Wait mode high frequency current at 3.0 V — all peripheral clocks disabled — 35 TBD mA 2 IDD_WAIT Wait mode reduced frequency current at 3.0 V — all peripheral clocks disabled — 15 TBD mA 5 IDD_STOP Stop mode current at 3.0 V — 0.4 TBD mA IDD_VLPR Very-low-power run mode current at 3.0 V — all peripheral clocks disabled — 1.25 TBD mA 6 IDD_VLPR Very-low-power run mode current at 3.0 V — all peripheral clocks enabled — TBD TBD mA 7 IDD_VLPW Very-low-power wait mode current at 3.0 V — 1.05 TBD mA 8 IDD_VLPS Very-low-power stop mode current at 3.0 V — 50 TBD μA IDD_LLS Low leakage stop mode current at 3.0 V — 12 TBD μA IDD_VLLS3 Very low-leakage stop mode 3 current at 3.0 V
- 128KB RAM devices
- 64KB RAM devices
- 32KB RAM devices TBD TBD TBD μA μA μA IDD_VLLS2 Very low-leakage stop mode 2 current at 3.0 V — 4 TBD μA IDD_VLLS1 Very low-leakage stop mode 1 current at 3.0 V — 2 TBD μA IDD_VBAT Average current when CPU is not accessing RTC registers at 3.0 V — 550 TBD nA 9 1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See each module's specification for its supply current. 2. 100MHz core and system clock, 50MHz bus and FlexBus clock, and 25MHz flash clock . MCG configured for FEI mode. All peripheral clocks disabled. 3. 100MHz core and system clock, 50MHz bus and FlexBus clock, and 25MHz flash clock. MCG configured for FEI mode. All peripheral clocks enabled, but peripherals are not in active operation. 4. 100MHz core and system clock, 50MHz bus and FlexBus clock, and 25MHz flash clock. MCG configured for FEI mode. All peripheral clocks enabled, and peripherals are in active operation. 5. 25MHz core and system clock, 25MHz bus clock, and 12.5MHz FlexBus and flash clock. MCG configured for FEI mode. 6. 2 MHz core, system, FlexBus, and bus clock and 1MHz flash clock. MCG configured for fast IRCLK mode. All peripheral clocks disabled. Code executing from flash. 7. 2 MHz core, system, FlexBus, and bus clock and 1MHz flash clock. MCG configured for fast IRCLK mode. All peripheral clocks enabled but peripherals are not in active operation. Code executing from flash. General K10 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Preliminary 15
- 2 MHz core, system, FlexBus, and bus clock and 1MHz flash clock. MCG configured for fast IRCLK mode. All peripheral
- Includes 32kHz oscillator current and RTC operation.
5.1.5.1 Diagram: Typical IDD_RUN operating behavior
- MCG in FEI mode (39.0625 kHz IRC), except for 1 MHz core (FBE)
- All peripheral clocks disabled except FTFL
- LVD disabled
- No GPIOs toggled
- Code execution from flash
Figure 1. Run mode supply current vs. core frequency — all peripheral clocks disabled
- MCG in FEI mode (39.0625 kHz IRC), except for 1 MHz core (FBE)
- All peripheral clocks enabled but peripherals are not in active operation General K10 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. 16 Preliminary Freescale Semiconductor, Inc.
- LVD disabled
- No GPIOs toggled
- Code execution from flash
Figure 2. Run mode supply current vs. core frequency — all peripheral clocks enabled
5.1.6 EMC radiated emissions operating behaviors
Table 7. EMC radiated emissions operating behaviors K10 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
- Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions, 150
Wideband TEM (GTEM) Cell Method.
- Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and Wideband
Circuits—TEM/Wideband TEM (GTEM) Cell Method.
5.1.7 Designing with radiated emissions in mind
- Go to http://www.freescale.com.
- Perform a keyword search for “EMC design.”
5.1.8 Capacitance attributes
Table 8. Capacitance attributes
5.2 Switching specifications
5.2.1 Device clock specifications
Table continues on the next page... K10 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. 18 Preliminary Freescale Semiconductor, Inc.
5.2.2 General switching specifications
- Slew disabled
- Slew enabled ns ns Port rise and fall time (low drive strength)
- Slew disabled
- Slew enabled ns ns 1. The greater synchronous and asynchronous timing must be met. 2. This is the shortest pulse that is guaranteed to be recognized. 3. 75pF load 4. 15pF load
5.3 Thermal specifications
5.3.1 Thermal operating requirements
Table 9. Thermal operating requirements K10 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
5.3.2 Thermal attributes
- Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Environmental Conditions—Forced Convection (Moving Air).
6 Peripheral operating requirements and behaviors
- have C L=30pF loads,
- are configured for fast slew rate (PORTx_PCRn[SRE]=0), and
- are configured for high drive strength (PORTx_PCRn[DSE]=1) 2. input pins
- have their passive filter disabled (PORTx_PCRn[PFE]=0)
6.1 Core modules
6.1.1 Debug trace timing specifications
Table 10. Debug trace operating behaviors Table continues on the next page... K10 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. 20 Preliminary Freescale Semiconductor, Inc.
Table 10. Debug trace operating behaviors (continued) Figure 3. TRACE_CLKOUT specifications Figure 4. Trace data specifications
6.1.2 JTAG electricals
Table 11. JTAG limited voltage range electricals
- Boundary Scan
- JTAG and CJTAG
- Serial Wire Debug MHz J2 TCLK cycle period 1/J1 — ns Table continues on the next page... Peripheral operating requirements and behaviors K10 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Preliminary 21
Table 11. JTAG limited voltage range electricals (continued)
- Boundary Scan
- JTAG and CJTAG
- Serial Wire Debug ns J4 TCLK rise and fall times — 3 ns J5 Boundary scan input data setup time to TCLK rise 20 — ns J6 Boundary scan input data hold time after TCLK rise 0 — ns J7 TCLK low to boundary scan output data valid — 25 ns J8 TCLK low to boundary scan output high-Z — 25 ns J9 TMS, TDI input data setup time to TCLK rise 8 — ns J10 TMS, TDI input data hold time after TCLK rise 1 — ns J11 TCLK low to TDO data valid — 17 ns J12 TCLK low to TDO high-Z — 17 ns J13 TRST assert time 100 — ns J14 TRST setup time (negation) to TCLK high 8 — ns
Table 12. JTAG full voltage range electricals
- Boundary Scan
- JTAG and CJTAG
- Serial Wire Debug MHz J2 TCLK cycle period 1/J1 — ns J3 TCLK clock pulse width
- Boundary Scan
- JTAG and CJTAG
- Serial Wire Debug 12.5 ns J4 TCLK rise and fall times — 3 ns J5 Boundary scan input data setup time to TCLK rise 20 — ns J6 Boundary scan input data hold time after TCLK rise 0 — ns J7 TCLK low to boundary scan output data valid — 25 ns J8 TCLK low to boundary scan output high-Z — 25 ns J9 TMS, TDI input data setup time to TCLK rise 8 — ns Table continues on the next page... Peripheral operating requirements and behaviors K10 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. 22 Preliminary Freescale Semiconductor, Inc.
Figure 7. Test Access Port timing Figure 8. TRST timing
6.2 System modules
There are no specifications necessary for the device's system modules.
6.3 Clock modules
K10 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. 24 Preliminary Freescale Semiconductor, Inc.
6.3.1 MCG specifications
Table 13. MCG specifications Table continues on the next page... K10 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Table 13. MCG specifications (continued)
- PLL @ 96 MHz (f osc_hi_1=8MHz, fpll_ref=2MHz, VDIV multiplier=48) — 950 — µA 8 fpll_ref PLL reference frequency range 2.0 — 4.0 MHz Jcyc_pll PLL period jitter — 400 — ps 9, 10 Jacc_pll PLL accumulated jitter over 1µs window — TBD — ps 9, 10 Dlock Lock entry frequency tolerance ± 1.49 — ± 2.98 % Dunl Lock exit frequency tolerance ± 4.47 — ± 5.97 % tpll_lock Lock detector detection time — — 0.15 + 1075(1/ fpll_ref) ms 11 1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock mode). 2. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0. 3. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency deviation (Δfdco_t) over voltage and temperature should be considered. 4. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1. 5. The resulting clock frequency must not exceed the maximum specified clock frequency of the device. 6. This specification was obtained at TBD frequency. 7. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed, DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running. 8. Excludes any oscillator currents that are also consuming power while PLL is in operation. 9. This specification was obtained using a Freescale developed PCB. PLL jitter is dependent on the noise characteristics of each PCB and results will vary. 10. This specification was obtained at internal frequency of TBD. 11. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled (BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes it is already running. Peripheral operating requirements and behaviors K10 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. 26 Preliminary Freescale Semiconductor, Inc.
6.3.2 Oscillator electrical specifications
This section provides the electrical characteristics of the module.
6.3.2.1 Oscillator DC electrical specifications
Table 14. Oscillator DC electrical specifications
- 32 kHz
- 4 MHz
- 8 MHz
- 16 MHz
- 24 MHz
- 32 MHz 500 200 300 700 1.2 1.5 nA μA μA μA mA mA IDDOSC Supply current — high gain mode (HGO=1)
- 32 kHz
- 4 MHz
- 8 MHz
- 16 MHz
- 24 MHz
- 32 MHz 400 800 1.5 μA μA μA mA mA mA Cx EXTAL load capacitance — — — 2, 3 Cy XTAL load capacitance — — — 2, 3 RF Feedback resistor — low-frequency, low-power mode (HGO=0) — — — MΩ 2, 4 Feedback resistor — low-frequency, high-gain mode (HGO=1) — 10 — MΩ Feedback resistor — high-frequency, low-power mode (HGO=0) — — — MΩ Feedback resistor — high-frequency, high-gain mode (HGO=1) — 1 — MΩ Table continues on the next page... Peripheral operating requirements and behaviors K10 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Preliminary 27
Table 14. Oscillator DC electrical specifications (continued)
- VDD=3.3 V, Temperature =25 °C
- See crystal or resonator manufacturer's recommendation
- Cx,Cy can be provided by using either the integrated capacitors or by using external components.
- When low power mode is selected, RF is integrated and must not be attached externally.
- The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any
6.3.2.2 Oscillator frequency specifications
Table 15. Oscillator frequency specifications Table continues on the next page... K10 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. 28 Preliminary Freescale Semiconductor, Inc.
Table 15. Oscillator frequency specifications (continued)
- Other frequency limits may apply when external clock is being used as a reference for the FLL or PLL
- Proper PC board layout procedures must be followed to achieve specifications.
- Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S register
This section describes the module electrical characteristics. Table 16. 32kHz oscillator DC electrical specifications Table 17. 32kHz oscillator frequency specifications
- Proper PC board layout procedures must be followed to achieve specifications.
6.4 Memories and memory interfaces
K10 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
6.4.1 Flash (FTFL) electrical specifications
This section describes the electrical characteristics of the FTFL module.
6.4.1.1 Flash timing specifications — program and erase
active and do not include command overhead. Table 18. NVM program/erase timing specifications
- Maximum time based on expectations at cycling end-of-life.
6.4.1.2 Flash timing specifications — commands
Table 19. Flash command timing specifications
- 256 KB data flash 1.4 ms trd1sec2k Read 1s Section execution time (flash sector) — — 40 μs 1 tpgmchk Program Check execution time — — 35 μs 1 trdrsrc Read Resource execution time — — 35 μs 1 tpgm4 Program Longword execution time — 50 TBD μs tersblk256k Erase Flash Block execution time
- 256 KB data flash 160 800 ms tersscr Erase Flash Sector execution time — 20 100 ms 2 tpgmsec512 tpgmsec1k tpgmsec2k Program Section execution time
- 512 B flash
- 1 KB flash
- 2 KB flash TBD TBD TBD TBD TBD TBD ms ms ms trd1all Read 1s All Blocks execution time — — 2.8 ms trdonce Read Once execution time — — 35 μs 1 tpgmonce Program Once execution time — 50 TBD μs Table continues on the next page... Peripheral operating requirements and behaviors K10 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. 30 Preliminary Freescale Semiconductor, Inc.
Table 19. Flash command timing specifications (continued)
- 256 KB FlexNVM 175 TBD ms tsetram32k tsetram256k Set FlexRAM Function execution time:
- 32 KB EEPROM backup
- 256 KB EEPROM backup TBD TBD TBD TBD ms ms Byte-write to FlexRAM for EEPROM operation teewr8bers Byte-write to erased FlexRAM location execution time — 100 TBD μs 3 teewr8b32k teewr8b64k teewr8b128k teewr8b256k Byte-write to FlexRAM execution time:
- 32 KB EEPROM backup
- 64 KB EEPROM backup
- 128 KB EEPROM backup
- 256 KB EEPROM backup TBD TBD TBD TBD TBD 1.5 TBD 2.5 ms ms ms ms Word-write to FlexRAM for EEPROM operation teewr16bers Word-write to erased FlexRAM location execution time — 100 TBD μs teewr16b32k teewr16b64k teewr16b128k teewr16b256k Word-write to FlexRAM execution time:
- 32 KB EEPROM backup
- 64 KB EEPROM backup
- 128 KB EEPROM backup
- 256 KB EEPROM backup TBD TBD TBD TBD TBD 1.5 TBD 2.5 ms ms ms ms Longword-write to FlexRAM for EEPROM operation teewr32bers Longword-write to erased FlexRAM location execution time — 200 TBD μs teewr32b32k teewr32b64k teewr32b128k teewr32b256k Longword-write to FlexRAM execution time:
- 32 KB EEPROM backup
- 64 KB EEPROM backup
- 128 KB EEPROM backup
- 256 KB EEPROM backup TBD TBD TBD TBD TBD 2.7 TBD 3.7 ms ms ms ms 1. Assumes 25MHz flash clock frequency. 2. Maximum times for erase parameters based on expectations at cycling end-of-life. 3. For byte-writes to an erased FlexRAM location, the aligned word containing the byte must be erased. Peripheral operating requirements and behaviors K10 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Preliminary 31
6.4.1.3 Flash (FTFL) current and power specfications
Table 20. Flash (FTFL) current and power specfications
6.4.1.4 Reliability specifications
Table 21. NVM reliability specifications
- EEPROM backup to FlexRAM ratio = 16
- EEPROM backup to FlexRAM ratio = 128
- EEPROM backup to FlexRAM ratio = 512
- EEPROM backup to FlexRAM ratio = 4096
- EEPROM backup to FlexRAM ratio = 32,768 35 K 315 K 1.27 M 10 M 80 M TBD TBD TBD TBD TBD writes writes writes writes writes 1. Typical data retention values are based on intrinsic capability of the technology measured at high temperature derated to 25°C. For additional information on how Freescale defines typical data retention, please refer to Engineering Bulletin EB618. 2. Data retention is based on Tjavg = 55°C (temperature profile over the lifetime of the application). 3. Cycling endurance represents number of program/erase cycles at -40°C ≤ Tj ≤ 125°C. 4. Write endurance represents the number of writes to each FlexRAM location at -40°C ≤Tj ≤ 125°C influenced by the cycling endurance of the FlexNVM (same value as data flash) and the allocated EEPROM backup per subsystem. Minimum value assumes all byte-writes to FlexRAM. Peripheral operating requirements and behaviors K10 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. 32 Preliminary Freescale Semiconductor, Inc.
6.4.1.5 Write endurance to FlexRAM for EEPROM
When the FlexNVM partition code is not set to full data flash, the EEPROM data set size can be set to any of several non-zero values. The bytes not assigned to data flash via the FlexNVM partition code are used by the FTFL to obtain an effective endurance increase for the EEPROM data. The built-in EEPROM record management system raises the number of program/erase cycles that can be attained prior to device wear-out by cycling the EEPROM data through a larger EEPROM NVM storage space. While different partitions of the FlexNVM are available, the intention is that a single choice for the FlexNVM partition code and EEPROM data set size is used throughout the entire lifetime of a given application. The EEPROM endurance equation and graph shown below assume that only one configuration is ever used. Writes_subsystem = × Write_efficiency × nEEPROM – 2 × EEESPLIT × EEESIZEEEESPLIT × EEESIZEnvmcycd where
- Writes_subsystem — minimum number of writes to each FlexRAM location for subsystem (each subsystem can have different endurance)
- EEPROM — allocated FlexNVM for each EEPROM subsystem based on DEPART; entered with Program Partition command
- EEESPLIT — FlexRAM split factor for subsystem; entered with the Program Partition command
- EEESIZE — allocated FlexRAM based on DEPART; entered with Program Partition command
- Write_efficiency —
- 0.25 for 8-bit writes to FlexRAM
- 0.50 for 16-bit or 32-bit writes to FlexRAM
- n nvmcycd — data flash cycling endurance Peripheral operating requirements and behaviors K10 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Preliminary 33
Figure 9. EEPROM backup writes to FlexRAM
6.4.2 EzPort Switching Specifications
Table 22. EzPort switching specifications K10 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. 34 Preliminary Freescale Semiconductor, Inc.
Figure 10. EzPort Timing Diagram
6.4.3 Flexbus Switching Specifications
the same as the internal system bus frequency or an integer divider of that frequency. Table 23. Flexbus switching specifications
- Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0], FB_ALE,
- Specification is valid for all FB_AD[31:0] and FB_TA.
K10 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Figure 11. FlexBus read timing diagram K10 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. 36 Preliminary Freescale Semiconductor, Inc.
Figure 12. FlexBus write timing diagram
6.5 Security and integrity modules
There are no specifications necessary for the device's security and integrity modules.
6.6 Analog
K10 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
6.6.1 ADC electrical specifications
Table 24. 16-bit ADC operating conditions
1.13 VDDA VDDA V
- 16 bit modes
- 8/10/12 bit modes pF RADIN Input resistance — 2 5 kΩ RAS Analog source resistance 13/12 bit modes fADCK < 4MHz kΩ fADCK ADC conversion clock frequency ≤13 bit modes 1.0 18.0 MHz fADCK ADC conversion clock frequency 16 bit modes 2.0 12.0 MHz Table continues on the next page... Peripheral operating requirements and behaviors K10 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. 38 Preliminary Freescale Semiconductor, Inc.
Table 24. 16-bit ADC operating conditions (continued)
- Typical values assume VDDA = 3.0 V, Temp = 25°C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
- This resistance is external to MCU. The analog source resistance should be kept as low as possible in order to achieve the
CAS time constant should be kept to <1ns.
- In order to use the maximum ADC conversion clock frequency ADHSC bit should be set and the ADLPC should be clear.
- In order to use the maximum ADC conversion clock frequency ADHSC bit should be set and the ADLPC should be clear.
- For guidelines and examples of conversion rate calculation please download the ADC calculator tool http://
- For guidelines and examples of conversion rate calculation please download the ADC calculator tool http://
K10 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Figure 13. ADC input impedance equivalency diagram Table 25. 16-bit ADC characteristics (V REFH = VDDA, VREFL = VSSA)
- ADLPC=1, ADHSC=0
- ADLPC=1, ADHSC=1
- ADLPC=0, ADHSC=0
- ADLPC=0, ADHSC=1 2.4 4.0 5.2 6.2 MHz MHz MHz MHz tADACK = 1/ fADACK Sample Time See Reference Manual chapter for sample times Conversion Time The ADC calculator tool can be used to determine ADC conversion times for different ADC configurations: http://cache.freescale.com/files/soft_dev_tools/software/app_software/ converters/ADC_CALCULATOR_CNV.zip?fpsp=1 TUE Total unadjusted error
- ≤13 bit modes
- <12 bit modes ±0.8 ±0.5 ±TBD LSB4 ADC conversion clock <12MHz, Max hardware averaging (AVGE = %1, AVGS = %11) Table continues on the next page... Peripheral operating requirements and behaviors K10 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. 40 Preliminary Freescale Semiconductor, Inc.
Table 25. 16-bit ADC characteristics (V REFH = VDDA, VREFL = VSSA) (continued)
- ≤13 bit modes
- <12 bit modes ±0.7 ±0.2 ±TBD ±0.5 LSB4 ADC conversion clock <12MHz, Max hardware averaging (AVGE = %1, AVGS = %11) INL Integral non- linearity
- ≤13 bit modes
- <12 bit modes ±1.0 ±0.5 ±TBD ±TBD LSB4 Max averaging EFS Full-scale error • ≤13 bit modes
- <12 bit modes ±0.4 ±1.0 ±TBD ±TBD LSB4 VADIN = VDDA EQ Quantization error
- 16 bit modes
- ≤13 bit modes -1 to 0 ±0.5 LSB4 ENOB Effective number of bits 16 bit differential mode
- Avg=32
- Avg=1 16 bit single-ended mode
- Avg=32
- Avg=1 TBD TBD TBD TBD 13.6 13.2 TBD TBD TBD TBD TBD TBD bits bits bits bits SINAD Signal-to-noise plus distortion See ENOB 6.02 × ENOB + 1.76 dB THD Total harmonic distortion 16 bit differential mode
- Avg=32 16 bit single-ended mode
- Avg=32 -94 TBD TBD TBD dB dB SFDR Spurious free dynamic range 16 bit differential mode
- Avg=32 16 bit single-ended mode
- Avg=32 TBD TBD TBD dB dB Table continues on the next page... Peripheral operating requirements and behaviors K10 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Preliminary 41
Table 26. 16-bit ADC with PGA operating conditions (continued)
- Typical values assume VDDA = 3.0 V, Temp = 25°C, fADCK = 6 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
- ADC must be configured to use the internal voltage reference (VREFOUT)
- PGA reference connected to the VREFOUT pin. If the user wishes to drive VREFOUT with a voltage other than the output
of the VREF module, the VREF module must be disabled.
- For single ended configurations the input impedence of the driven input is 1/2.
- The analog source resistance (RAS), external to MCU, should be kept as minimum as possible. Increased RAS causes drop
in PGA gain without affecting other performances. This is not dependent on ADC clock frequency.
- The minimum sampling time is dependent on input signal frequency and ADC mode of operation. A minimum of 1.25µs
Table 27. 16-bit ADC with PGA characteristics
- PGAG=1
- PGAG=2
- PGAG=3
- PGAG=4
- PGAG=5
- PGAG=6 TBD TBD TBD TBD TBD TBD TBD 0.98 1.99 3.97 7.95 15.8 31.4 61.2 TBD TBD TBD TBD TBD TBD TBD RAS < 100Ω BW Input signal bandwidth
- 16-bit modes
- < 16-bit modes kHz kHz PSRR Power supply rejection ration Gain=1 TBD TBD — dB VDDA= 3V ±100mV, fVDDA= 50Hz, 60Hz Table continues on the next page... Peripheral operating requirements and behaviors K10 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Preliminary 43
Table 27. 16-bit ADC with PGA characteristics (continued)
- Gain=1
- Gain=64 TBD TBD TBD TBD dB dB VCM= 500mVpp, fVCM= 50Hz, 100Hz VOFS Input offset voltage — 0.2 TBD mV Gain=1, ADC Averaging=32 TGSW Gain switching settling time — — 10 µs 5 dG/dT Gain drift over temperature
- Gain=1
- Gain=64 TBD TBD TBD TBD ppm/°C ppm/°C 0 to 50°C dVOFS/dT Offset drift over temperature Gain=1 — TBD TBD ppm/°C 0 to 50°C, ADC Averaging=32 dG/dVDDA Gain drift over supply voltage
- Gain=1
- Gain=64 TBD TBD TBD TBD %/V %/V VDDA from 1.71 to 3.6V EIL Input leakage error All modes IIn × RAS mV IIn = leakage current (refer to the MCU's voltage and current operating ratings) VPP,DIFF Maximum differential input signal swing where VX = VREFPGA × 0.583 V 6 SNR Signal-to-noise ratio
- Gain=1
- Gain=64 TBD TBD 83.0 57.5 dB dB 16-bit differential mode, Average=32 THD Total harmonic distortion
- Gain=1
- Gain=64 TBD TBD 89.4 90.0 dB dB 16-bit differential mode, Average=32, fin=500Hz SFDR Spurious free dynamic range
- Gain=1
- Gain=64 TBD TBD 90.9 77.0 dB dB 16-bit differential mode, Average=32, fin=500Hz Table continues on the next page... Peripheral operating requirements and behaviors K10 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. 44 Preliminary Freescale Semiconductor, Inc.
- Gain=1, Average=4
- Gain=1, Average=8
- Gain=64, Average=4
- Gain=64, Average=8
- Gain=1, Average=32
- Gain=2, Average=32
- Gain=4, Average=32
- Gain=8, Average=32
- Gain=16, Average=32
- Gain=32, Average=32
- Gain=64, Average=32 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 12.3 12.7 8.4 8.7 13.3 13.1 12.5 11.8 11.1 10.2 9.3 bits bits bits bits bits bits bits bits bits bits bits 16-bit differential mode, fin=500Hz SINAD Signal-to-noise plus distortion ratio See ENOB 6.02 × ENOB + 1.76 dB 1. Typical values assume VDDA =3.0V, Temp=25°C, fADCK=6MHz unless otherwise stated. 2. Between IN+ and IN-. The PGA draws a DC current from the input terminals. The magnitude of the DC current is a strong function if input common mode voltage (VCM) and the PGA gain. 3. This is the input leakage current of the module in addition to the PAD leakage current. 4. Gain = 2PGAG 5. When the PGA gain is changed, it takes some time to settle the output for the ADC to work properly. During a gain switching, a few ADC outputs should be discarded (minimum two data samples, may be more depending on ADC sampling rate and time of the switching). 6. Limit the input signal swing so that the PGA does not saturate during operation. Input signal swing is dependent on the PGA reference voltage and gain setting.
6.6.2 CMP and 6-bit DAC electrical specifications
Table 28. Comparator and 6-bit DAC electrical specifications Table continues on the next page... K10 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Table 28. Comparator and 6-bit DAC electrical specifications (continued)
- CR0[HYSTCTR] = 00
- CR0[HYSTCTR] = 01
- CR0[HYSTCTR] = 10
- CR0[HYSTCTR] = 11 mV mV mV mV VCMPOh Output high VDD – 0.5 — — V VCMPOl Output low — — 0.5 V tDHS Propagation delay, high-speed mode (EN=1, PMODE=1) 20 50 200 ns tDLS Propagation delay, low-speed mode (EN=1, PMODE=0) 120 250 600 ns Analog comparator initialization delay2 — — TBD ns IDAC6b 6-bit DAC current adder (enabled) — 7 — μA INL 6-bit DAC integral non-linearity –0.5 — 0.5 LSB3 DNL 6-bit DAC differential non-linearity –0.3 — 0.3 LSB 1. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD-0.6V. 2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to DACEN, VRSEL, PSEL, MSEL, VOSEL) and the comparator output settling to a stable level. 3. 1 LSB = Vreference/64 Peripheral operating requirements and behaviors K10 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. 46 Preliminary Freescale Semiconductor, Inc.
Figure 16. Typical hysteresis vs. Vin level (VDD=3.3V, PMODE=0) K10 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Figure 17. Typical hysteresis vs. Vin level (VDD=3.3V, PMODE=1) Table 29. 12-bit DAC operating requirements
- The DAC reference can be selected to be VDDA or the voltage output of the VREF module (VREFO)
- A small load capacitance (47 pF) can improve the bandwidth performance of the DAC
K10 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. 48 Preliminary Freescale Semiconductor, Inc.
Table 30. 12-bit DAC operating behaviors
1 TBD — μs 1
- High power (SP HP)
- Low power (SP LP) 1.2 0.05 1.7 0.12 V/μs CT Channel to channel cross talk — — -80 dB BW 3dB bandwidth
- High power (SP HP)
- Low power (SP LP) 550 kHz 1. Settling within ±1 LSB 2. The INL is measured for 0+100mV to VDACR−100 mV 3. The DNL is measured for 0+100 mV to VDACR−100 mV 4. The DNL is measured for 0+100mV to VDACR−100 mV with VDDA > 2.4V Peripheral operating requirements and behaviors K10 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Preliminary 49
- Calculated by a best fit curve from VSS+100 mV to VREF−100 mV
Figure 18. Typical INL error vs. digital code K10 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. 50 Preliminary Freescale Semiconductor, Inc.
Figure 19. Offset at half scale vs. temperature
6.6.4 Voltage reference electrical specifications
Table 31. VREF full-range operating requirements Table 32. VREF full-range operating behaviors Table continues on the next page... K10 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Table 32. VREF full-range operating behaviors (continued) Table 33. VREF limited-range operating requirements Table 34. VREF limited-range operating behaviors Figure 20. Typical output vs.temperature Figure 21. Typical output vs. VDD
6.7 Timers
See General switching specifications.
6.8 Communication interfaces
K10 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. 52 Preliminary Freescale Semiconductor, Inc.
6.8.1 CAN switching specifications
See General switching specifications.
6.8.2 DSPI switching specifications (low-speed mode)
used for communicating with slower peripheral devices. Table 35. Master mode DSPI timing (low-speed mode)
- The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage
range the maximum frequency of operation is reduced. Figure 22. DSPI classic SPI timing — master mode K10 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Table 36. Slave mode DSPI timing (low-speed mode) Figure 23. DSPI classic SPI timing — slave mode
6.8.3 DSPI switching specifications (high-speed mode)
used for communicating with slower peripheral devices. Table 37. Master mode DSPI timing (high-speed mode) Table continues on the next page... K10 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. 54 Preliminary Freescale Semiconductor, Inc.
Table 37. Master mode DSPI timing (high-speed mode) (continued) Figure 24. DSPI classic SPI timing — master mode Table 38. Slave mode DSPI timing (high-speed mode) K10 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Figure 25. DSPI classic SPI timing — slave mode
6.8.4 I2C switching specifications
See General switching specifications.
6.8.5 UART switching specifications
See General switching specifications.
6.8.6 SDHC specifications
appropriately to arrive at timing specs/constraints for the physical interface. Table 39. SDHC switching specifications Table continues on the next page... K10 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. 56 Preliminary Freescale Semiconductor, Inc.
Figure 26. SDHC timing
6.8.7 I2S switching specifications
(I2S_FS) shown in the figures below. Table 40. I2S master mode timing Table continues on the next page... K10 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Table 40. I2S master mode timing (continued) Figure 27. I2S timing — master mode Table 41. I2S slave mode timing Table continues on the next page... K10 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. 58 Preliminary Freescale Semiconductor, Inc.
Table 41. I2S slave mode timing (continued) Figure 28. I2S timing — slave modes
6.9 Human-machine interfaces (HMI)
6.9.1 TSI electrical specifications
Table 42. TSI electrical specifications Table continues on the next page... K10 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Table 42. TSI electrical specifications (continued)
- The TSI module is functional with capacitance values outside this range. However, optimal performance is not guaranteed.
- The programmable current source value is generated by multiplying the SCANC[REFCHRG] value and the base current.
- Measured with a 5 pF electrode, reference oscillator frequency of 10 MHz, PS = 128, NSCN = 8; Iext = 16.
- Measured with a 20 pF electrode, reference oscillator frequency of 10 MHz, PS = 128, NSCN = 2; Iext = 16.
- Measured with a 20 pF electrode, reference oscillator frequency of 10 MHz, PS = 16, NSCN = 3; Iext = 16.
- Measured with a 20 pF electrode, reference oscillator frequency of ~5 MHz (IREF = 5 μA, REFCHRG = 4), PS = 128,
- Typical value depends on the configuration used.
- Time to do one complete measurement of the electrode. Sensitivity resolution of 0.0133 pF, PS = 0, NSCN = 0, 1
electrode, DELVOL = 2, EXTCHRG = 15.
7 Dimensions
7.1 Obtaining package dimensions
Package dimensions are provided in package drawings.
8 Pinout
K10 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. 60 Preliminary Freescale Semiconductor, Inc.
8.1 K10 Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these pins on the devices supported by this document. The Port Control Module is responsible for selecting which ALT functionality is available on each pin. 144 LQF P 144 MAP BGA Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort — L5 NC NC NC — M5 NC NC NC — A10 NC NC NC — B10 NC NC NC — C10 NC NC NC
1 D3 PTE0 ADC1_SE4
a ADC1_SE4 a PTE0 SPI1_PCS1UART1_TXSDHC0_D1 I2C1_SDA
2 D2 PTE1 ADC1_SE5
a ADC1_SE5 a PTE1 SPI1_SOUTUART1_RXSDHC0_D0 I2C1_SCL
3 D1 PTE2 ADC1_SE6
a ADC1_SE6 a PTE2 SPI1_SCKUART1_CT S_b SDHC0_DC LK
4 E4 PTE3 ADC1_SE7
a ADC1_SE7 a PTE3 SPI1_SIN UART1_RT S_b SDHC0_CM D
5 E5 VDD VDD VDD
6 F6 VSS VSS VSS
7 E3 PTE4 DISABLED PTE4 SPI1_PCS0UART3_TXSDHC0_D3
8 E2 PTE5 DISABLED PTE5 SPI1_PCS2UART3_RXSDHC0_D2
9 E1 PTE6 DISABLED PTE6 SPI1_PCS3UART3_CT
S_b I2S0_MCLK I2S0_CLKIN
10 F4 PTE7 DISABLED PTE7 UART3_RT
S_b I2S0_RXD
11 F3 PTE8 DISABLED PTE8 UART5_TXI2S0_RX_F
S
12 F2 PTE9 DISABLED PTE9 UART5_RXI2S0_RX_B
13 F1 PTE10 DISABLED PTE10 UART5_CT
S_b I2S0_TXD
14 G4 PTE11 DISABLED PTE11 UART5_RT
S_b I2S0_TX_F S
15 G3 PTE12 DISABLED PTE12 I2S0_TX_B
16 E6 VDD VDD VDD
17 F7 VSS VSS VSS
18 H1 PTE16 ADC0_SE4
a ADC0_SE4 a PTE16 SPI0_PCS0UART2_TXFTM_CLKIN FTM0_FLT3
19 H2 PTE17 ADC0_SE5
a ADC0_SE5 a PTE17 SPI0_SCKUART2_RXFTM_CLKIN LPT00_ALT
20 G1 PTE18 ADC0_SE6
a ADC0_SE6 a PTE18 SPI0_SOUTUART2_CT S_b I2C0_SDA Pinout K10 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Preliminary 61
P 144 MAP BGA Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort
21 G2 PTE19 ADC0_SE7
a ADC0_SE7 a PTE19 SPI0_SIN UART2_RT S_b I2C0_SCL
22 H3 VSS VSS VSS
23 J1 ADC0_DP1ADC0_DP1ADC0_DP1
24 J2 ADC0_DM1ADC0_DM1ADC0_DM1
25 K1 ADC1_DP1ADC1_DP1ADC1_DP1
26 K2 ADC1_DM1ADC1_DM1ADC1_DM1
27 L1 PGA0_DP/
ADC0_DP0/ ADC1_DP3 PGA0_DP/ ADC0_DP0/ ADC1_DP3 PGA0_DP/ ADC0_DP0/ ADC1_DP3
28 L2 PGA0_DM/
ADC0_DM0/ ADC1_DM3 PGA0_DM/ ADC0_DM0/ ADC1_DM3 PGA0_DM/ ADC0_DM0/ ADC1_DM3
29 M1 PGA1_DP/
ADC1_DP0/ ADC0_DP3 PGA1_DP/ ADC1_DP0/ ADC0_DP3 PGA1_DP/ ADC1_DP0/ ADC0_DP3
30 M2 PGA1_DM/
ADC1_DM0/ ADC0_DM3 PGA1_DM/ ADC1_DM0/ ADC0_DM3 PGA1_DM/ ADC1_DM0/ ADC0_DM3
31 H5 VDDA VDDA VDDA
32 G5 VREFH VREFH VREFH
33 G6 VREFL VREFL VREFL
34 H6 VSSA VSSA VSSA
35 K3 ADC1_SE1
CMP2_IN2/ ADC0_SE2 ADC1_SE1 CMP2_IN2/ ADC0_SE2 ADC1_SE1 CMP2_IN2/ ADC0_SE2
36 J3 ADC0_SE1
CMP1_IN2/ ADC0_SE2 ADC0_SE1 CMP1_IN2/ ADC0_SE2 ADC0_SE1 CMP1_IN2/ ADC0_SE2
37 M3 VREF_OUT/
CMP1_IN5/ CMP0_IN5/ ADC1_SE1 VREF_OUTVREF_OUT/ CMP1_IN5/ CMP0_IN5/ ADC1_SE1
38 L3 DAC0_OUT/
CMP1_IN3/ ADC0_SE2 DAC0_OUTDAC0_OUT/ CMP1_IN3/ ADC0_SE2
39 L4 DAC1_OUT/
CMP2_IN3/ ADC1_SE2 DAC1_OUTDAC1_OUT/ CMP2_IN3/ ADC1_SE2
40 M7 XTAL32 XTAL32 XTAL32
41 M6 EXTAL32 EXTAL32 EXTAL32
K10 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. 62 Preliminary Freescale Semiconductor, Inc.
P 144 MAP BGA Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort
42 L6 VBAT VBAT VBAT
43 — VDD VDD VDD 44 — VSS VSS VSS
45 M4 PTE24 ADC0_SE1
ADC0_SE1 PTE24 CAN1_TX UART4_TX EWM_OUT
46 K5 PTE25 ADC0_SE1
ADC0_SE1 PTE25 CAN1_RXUART4_RX EWM_IN
47 K4 PTE26 DISABLED PTE26 UART4_CT
S_b RTC_CLKO UT
48 J4 PTE27 DISABLED PTE27 UART4_RT
S_b
49 H4 PTE28 DISABLED PTE28
50 J5 PTA0 JTAG_TCL
SWD_CLK/ EZP_CLK TSI0_CH1PTA0 UART0_CT S_b FTM0_CH5 JTAG_TCL SWD_CLK EZP_CLK
51 J6 PTA1 JTAG_TDI/
EZP_DI TSI0_CH2PTA1 UART0_RXFTM0_CH6 JTAG_TDIEZP_DI
52 K6 PTA2 JTAG_TDO/
TRACE_SW O/EZP_DO TSI0_CH3PTA2 UART0_TXFTM0_CH7 JTAG_TDO/ TRACE_SW O EZP_DO
53 K7 PTA3 JTAG_TMS/
SWD_DIO TSI0_CH4PTA3 UART0_RT S_b FTM0_CH0 JTAG_TMS/ SWD_DIO
54 L7 PTA4 NMI_b/
EZP_CS_b TSI0_CH5PTA4 FTM0_CH1 NMI_b EZP_CS_b
55 M8 PTA5 DISABLED PTA5 FTM0_CH2 CMP2_OUTI2S0_RX_B
JTAG_TRS T
56 E7 VDD VDD VDD
57 G7 VSS VSS VSS
58 J7 PTA6 DISABLED PTA6 FTM0_CH3 TRACE_CL
59 J8 PTA7 ADC0_SE1
ADC0_SE1 PTA7 FTM0_CH4 TRACE_D3
60 K8 PTA8 ADC0_SE1
ADC0_SE1 PTA8 FTM1_CH0 FTM1_QD_ PHA TRACE_D2
61 L8 PTA9 DISABLED PTA9 FTM1_CH1 FTM1_QD_
TRACE_D1
62 M9 PTA10 DISABLED PTA10 FTM2_CH0 FTM2_QD_
TRACE_D0
63 L9 PTA11 DISABLED PTA11 FTM2_CH1 FTM2_QD_
64 K9 PTA12 CMP2_IN0CMP2_IN0PTA12 CAN0_TX FTM1_CH0 I2S0_TXDFTM1_QD_
65 J9 PTA13 CMP2_IN1CMP2_IN1PTA13 CAN0_RXFTM1_CH1 I2S0_TX_F
S FTM1_QD_ PHB
66 L10 PTA14 DISABLED PTA14 SPI0_PCS0UART0_TX I2S0_TX_B
K10 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Preliminary 63
P 144 MAP BGA Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort
67 L11 PTA15 DISABLED PTA15 SPI0_SCKUART0_RX I2S0_RXD
68 K10 PTA16 DISABLED PTA16 SPI0_SOUTUART0_CT
S_b I2S0_RX_F S
69 K11 PTA17 ADC1_SE1
ADC1_SE1 PTA17 SPI0_SIN UART0_RT S_b I2S0_MCLKI2S0_CLKIN
70 E8 VDD VDD VDD
71 G8 VSS VSS VSS
72 M12 PTA18 EXTAL EXTAL PTA18 FTM0_FLT2FTM_CLKIN
73 M11 PTA19 XTAL XTAL PTA19 FTM1_FLT0FTM_CLKIN
LPT0_ALT1
74 L12 RESET_b RESET_b RESET_b
75 K12 PTA24 DISABLED PTA24 FB_A29
76 J12 PTA25 DISABLED PTA25 FB_A28
77 J11 PTA26 DISABLED PTA26 FB_A27
78 J10 PTA27 DISABLED PTA27 FB_A26
79 H12 PTA28 DISABLED PTA28 FB_A25
80 H11 PTA29 DISABLED PTA29 FB_A24
81 H10 PTB0 /
ADC0_SE8/ ADC1_SE8/ TSI0_CH0 ADC0_SE8/ ADC1_SE8/ TSI0_CH0 PTB0 I2C0_SCLFTM1_CH0 FTM1_QD_ PHA
82 H9 PTB1 /
ADC0_SE9/ ADC1_SE9/ TSI0_CH6 ADC0_SE9/ ADC1_SE9/ TSI0_CH6 PTB1 I2C0_SDAFTM1_CH1 FTM1_QD_ PHB
83 G12 PTB2 /
ADC0_SE1 2/TSI0_CH7 ADC0_SE1 2/TSI0_CH7 PTB2 I2C0_SCLUART0_RT S_b FTM0_FLT3
84 G11 PTB3 /
ADC0_SE1 3/TSI0_CH8 ADC0_SE1 3/TSI0_CH8 PTB3 I2C0_SDAUART0_CT S_b FTM0_FLT0
85 G10 PTB4 /
ADC1_SE1 ADC1_SE1 PTB4 FTM1_FLT0
86 G9 PTB5 /
ADC1_SE1 ADC1_SE1 PTB5 FTM2_FLT0
87 F12 PTB6 /
ADC1_SE1 ADC1_SE1 PTB6 FB_AD23
88 F11 PTB7 /
ADC1_SE1 ADC1_SE1 PTB7 FB_AD22
89 F10 PTB8 PTB8 UART3_RT
S_b FB_AD21 Pinout K10 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. 64 Preliminary Freescale Semiconductor, Inc.
P 144 MAP BGA Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort
90 F9 PTB9 PTB9 SPI1_PCS1UART3_CT
S_b FB_AD20
91 E12 PTB10 /
ADC1_SE1 ADC1_SE1 PTB10 SPI1_PCS0UART3_RX FB_AD19 FTM0_FLT1
92 E11 PTB11 /
ADC1_SE1 ADC1_SE1 PTB11 SPI1_SCKUART3_TX FB_AD18 FTM0_FLT2
93 H7 VSS VSS VSS
94 F5 VDD VDD VDD
95 E10 PTB16 /TSI0_CH9/TSI0_CH9PTB16 SPI1_SOUTUART0_RX FB_AD17 EWM_IN
96 E9 PTB17 /TSI0_CH10/TSI0_CH10PTB17 SPI1_SIN UART0_TX FB_AD16 EWM_OUT
97 D12 PTB18 /TSI0_CH11/TSI0_CH11PTB18 CAN0_TX FTM2_CH0I2S0_TX_B
FB_AD15 FTM2_QD_ PHA
98 D11 PTB19 /TSI0_CH12/TSI0_CH12PTB19 CAN0_RXFTM2_CH1I2S0_TX_F
S FB_OE_b FTM2_QD_ PHB
99 D10 PTB20 PTB20 SPI2_PCS0 FB_AD31 CMP0_OUT
100 D9 PTB21 PTB21 SPI2_SCK FB_AD30 CMP1_OUT
101 C12 PTB22 PTB22 SPI2_SOUT FB_AD29 CMP2_OUT
102 C11 PTB23 PTB23 SPI2_SIN SPI0_PCS5 FB_AD28
103 B12 PTC0 /
ADC0_SE1 TSI0_CH13 ADC0_SE1 TSI0_CH13 PTC0 SPI0_PCS4PDB0_EXT RG I2S0_TXDFB_AD14
104 B11 PTC1 /
ADC0_SE1 TSI0_CH14 ADC0_SE1 TSI0_CH14 PTC1 SPI0_PCS3UART1_RT S_b FTM0_CH0FB_AD13
105 A12 PTC2 /
ADC0_SE4 CMP1_IN0/ TSI0_CH15 ADC0_SE4 CMP1_IN0/ TSI0_CH15 PTC2 SPI0_PCS2UART1_CT S_b FTM0_CH1FB_AD12
106 A11 PTC3 /CMP1_IN1/CMP1_IN1PTC3 SPI0_PCS1UART1_RXFTM0_CH2FB_CLKOU
T
107 H8 VSS VSS VSS
108 — VDD VDD VDD
109 A9 PTC4 PTC4 SPI0_PCS0UART1_TXFTM0_CH3FB_AD11 CMP1_OUT
110 D8 PTC5 PTC5 SPI0_SCK LPT0_ALT2FB_AD10 CMP0_OUT
111 C8 PTC6 /CMP0_IN0/CMP0_IN0PTC6 SPI0_SOUTPDB0_EXT
FB_AD9
112 B8 PTC7 /CMP0_IN1/CMP0_IN1PTC7 SPI0_SIN FB_AD8
113 A8 PTC8 /
ADC1_SE4 CMP0_IN2 ADC1_SE4 CMP0_IN2 PTC8 I2S0_MCLKI2S0_CLKINFB_AD7 Pinout K10 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Preliminary 65
P 144 MAP BGA Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort
114 D7 PTC9 /
ADC1_SE5 CMP0_IN3 ADC1_SE5 CMP0_IN3 PTC9 I2S0_RX_B CLK FB_AD6 FTM2_FLT0
115 C7 PTC10 /
ADC1_SE6 CMP0_IN4 ADC1_SE6 CMP0_IN4 PTC10 I2C1_SCL I2S0_RX_F S FB_AD5
116 B7 PTC11 /
ADC1_SE7 b ADC1_SE7 b PTC11 I2C1_SDA I2S0_RXDFB_RW_b
117 A7 PTC12 PTC12 UART4_RT
S_b FB_AD27
118 D6 PTC13 PTC13 UART4_CT
S_b FB_AD26
119 C6 PTC14 PTC14 UART4_RX FB_AD25
120 B6 PTC15 PTC15 UART4_TX FB_AD24
121 — VSS VSS VSS 122 — VDD VDD VDD
123 A6 PTC16 PTC16 CAN1_RXUART3_RX FB_CS5_b/
FB_TSIZ1/ FB_BE23_1 6_BLS15_8
124 D5 PTC17 PTC17 CAN1_TX UART3_TX FB_CS4_b/
FB_TSIZ0/ FB_BE31_2 4_BLS7_0_ b
125 C5 PTC18 PTC18 UART3_RT
S_b FB_TBST_b /FB_CS2_b/ FB_BE15_8 _BLS23_16
126 B5 PTC19 PTC19 UART3_CT
S_b FB_CS3_b/ FB_BE7_0_ BLS31_24_ b FB_TA_b
127 A5 PTD0 PTD0 SPI0_PCS0UART2_RT
S_b FB_ALE/ FB_CS1_b/ FB_TS_b
128 D4 PTD1 /
ADC0_SE5 b ADC0_SE5 b PTD1 SPI0_SCKUART2_CT S_b FB_CS0_b
129 C4 PTD2 PTD2 SPI0_SOUTUART2_RX FB_AD4
130 B4 PTD3 PTD3 SPI0_SIN UART2_TX FB_AD3
131 A4 PTD4 PTD4 SPI0_PCS1UART0_RT
S_b FTM0_CH4FB_AD2 EWM_IN Pinout K10 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. 66 Preliminary Freescale Semiconductor, Inc.
P 144 MAP BGA Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort
132 A3 PTD5 /
ADC0_SE6 b ADC0_SE6 b PTD5 SPI0_PCS2UART0_CT S_b FTM0_CH5FB_AD1 EWM_OUT
133 A2 PTD6 /
ADC0_SE7 b ADC0_SE7 b PTD6 SPI0_PCS3UART0_RXFTM0_CH6FB_AD0 FTM0_FLT0
134 M10 VSS VSS VSS
135 F8 VDD VDD VDD
136 A1 PTD7 PTD7 CMT_IRO UART0_TXFTM0_CH7 FTM0_FLT1
137 C9 PTD8 DISABLED PTD8 I2C0_SCLUART5_RX FB_A16
138 B9 PTD9 DISABLED PTD9 I2C0_SDAUART5_TX FB_A17
139 B3 PTD10 DISABLED PTD10 UART5_RT
S_b FB_A18
140 B2 PTD11 DISABLED PTD11 SPI2_PCS0UART5_CT
S_b SDHC0_CL KIN FB_A19
141 B1 PTD12 DISABLED PTD12 SPI2_SCK SDHC0_D4 FB_A20
142 C3 PTD13 DISABLED PTD13 SPI2_SOUT SDHC0_D5 FB_A21
143 C2 PTD14 DISABLED PTD14 SPI2_SIN SDHC0_D6 FB_A22
144 C1 PTD15 DISABLED PTD15 SPI2_PCS1 SDHC0_D7 FB_A23
8.2 K10 Pinouts
The below figure shows the pinout diagram for the devices supported by this document. Many signals may be multiplexed onto a single pin. To determine what signals can be used on which pin, see the previous section. Pinout K10 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Preliminary 67
108 VDD
116 PTC11
124 PTC17
132 PTD5
140 PTD11
Figure 29. K10 144 LQFP Pinout Diagram K10 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. 68 Preliminary Freescale Semiconductor, Inc.
A B C D E F G H J A B C D E F G H J KK LL MM PTA18 PTC8 PTC4 NC PTC3 PTC2 PTA1 PTA6 PTA0 PTE27 ADC0_SE16/ CMP1_IN2/ ADC0_SE21 ADC1_SE16/ CMP2_IN2/ ADC0_SE22 PTE26 PTE25 PTA2 PTA3 PTA8 PTA7 VSS VSS VSSA VDDA PTE28 VSS PTE17 ADC0_DM1 ADC1_DM1 PGA0_DM/ ADC0_DM0/ ADC1_DM3 DAC0_OUT/ CMP1_IN3/ ADC0_SE23 DAC1_OUT/ CMP2_IN3/ ADC1_SE23 NC VBAT PTA4 PTA9 PTA11 PTA12 PTA13 PTB1 PTA27 PTB0 PTB4 PTB5 VSS VSS VREFL VREFH PTE11 PTE12 PTE19 PTE18 PTE16 ADC0_DP1 ADC1_DP1 PGA0_DP/ ADC0_DP0/ ADC1_DP3 PGA1_DP/ ADC1_DP0/ ADC0_DP3 PGA1_DM/ ADC1_DM0/ ADC0_DM3 VREF_OUT/ CMP1_IN5/ CMP0_IN5/ ADC1_SE18 PTE24 NC EXTAL32 XTAL32 PTA5 PTA10 VSS PTA16 PTA14 PTB3 PTA29 PTA26 PTA17 PTA15 PTA19 RESET_b PTA24 PTA25 PTA28 PTB2 PTB6 PTB7 PTB8 PTB9 VDD VDD PTB17 PTB16 PTB10 PTB11 PTB19 PTB18 PTB22 PTB23 NC PTB20 PTB21 PTC5 PTD8 PTC6 PTC7 PTD9 NC PTC1 PTC0 VSS VSS VDD VDD PTC13 PTC9 PTC11 PTC10 PTC19 PTC15 PTC14 PTC18 PTD2 PTD3 PTD10 PTD13 PTE0 PTD1 PTC17 VDD VDD PTE7 PTE3 PTE4 PTE8 PTE9 PTE10 PTE6 PTE5 PTE1 PTE2 PTD15 PTD14 PTD11 PTD12 PTC12 PTC16 PTD0 PTD4 PTD5 PTD6 PTD7 Figure 30. K10 144 MAPBGA Pinout Diagram
9 Revision History
The following table provides a revision history for this document. Table 43. Revision History Table continues on the next page...
Revision History
K10 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Preliminary 69
Table 43. Revision History (continued) K10 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. 70 Preliminary Freescale Semiconductor, Inc.
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