K10P104M100SF2 FREESCALE | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 60
Technical content
Features
- Operating Characteristics – Voltage range: 1.71 to 3.6 V – Flash write voltage range: 1.71 to 3.6 V – Temperature range (ambient): -40 to 105°C
- Performance – Up to 100 MHz ARM Cortex-M4 core with DSP instructions delivering 1.25 Dhrystone MIPS per MHz
- Memories and memory interfaces Up to 512 KB program flash memory on non- FlexMemory devices – Up to 128 KB RAM – Serial programming interface (EzPort) – FlexBus external bus interface
- Clocks – 1 to 32 MHz crystal oscillator – 32 kHz crystal oscillator – Multi-purpose clock generator
- System peripherals – 10 low-power modes to provide power optimization based on application requirements – Memory protection unit with multi-master protection – 16-channel DMA controller, supporting up to 64 request sources – External watchdog monitor – Software watchdog – Low-leakage wakeup unit
- Security and integrity modules – Hardware CRC module to support fast cyclic redundancy checks – Hardware random-number generator – 128-bit unique identification (ID) number per chip
- Human-machine interface – Low-power hardware touch sensor interface (TSI) – General-purpose input/output
- Analog modules – 16-bit SAR ADC with PGA (x64) – 12-bit DAC Analog comparator (CMP) containing a 6-bit DAC and programmable reference input – Voltage reference
- Timers – Programmable delay block – Eight-channel motor control/general purpose/PWM timers – Two-channel quadrature decoder/general purpose timers – Periodic interrupt timers – 16-bit low-power timer – Carrier modulator transmitter – Real-time clock
- Communication interfaces – Controller Area Network (CAN) module – SPI modules – I2C modules – UART modules – Secure Digital host controller (SDHC) – I2S Freescale Semiconductor Document Number: K10P104M100SF2 Data Sheet: Product Preview Rev. 1, 11/2010 This document contains information on a product under development. Freescale reserves the right to change or discontinue this product without notice. © 2010–2010 Freescale Semiconductor, Inc. Preliminary Preliminary
3.6 Relationship between ratings and operating
5.1.5.1 Diagram: Typical IDD_RUN operating
6.3.2.1 Oscillator DC Electrical Specifications 25
6.3.3.1 32kHz Oscillator DC Electrical 6.3.3.2 32kHz Oscillator Frequency
6.4.1.1 Flash Timing Parameters — Program
6.4.1.2 Flash Timing Parameters —
6.4.1.3 Flash (FTFL) Current and Power
6.6.1.3 16-bit ADC with PGA operating K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010. 2 Preliminary Freescale Semiconductor, Inc. Preliminary
6.8.1 DSPI Switching Specifications for Low-speed
6.8.2 DSPI Switching Specifications (High-speed
K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010. Freescale Semiconductor, Inc. Preliminary 3 Preliminary
1 Ordering parts
1.1 Determining valid orderable parts
Valid orderable part numbers are provided on the web. To determine the orderable part numbers for this device, go to www.freescale.com and perform a part number search for the following device numbers: PK10 and MK10.
2 Part identification
2.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the values of these fields to determine the specific part you have received.
2.2 Format
Part numbers for this device have the following format: Q K## M FFF T PP CCC N
2.3 Fields
This table lists the possible values for each field in the part number (not all combinations are valid): Field Description Values Q Qualification status • M = Fully qualified, general market flow
- P = Prequalification K## Kinetis family • K10 M Flash memory type • N = Program flash only
- X = Program flash and FlexMemory Table continues on the next page... Ordering parts K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010. 4 Preliminary Freescale Semiconductor, Inc. Preliminary
FFF Program flash memory size • 32 = 32 KB
- 64 = 64 KB
- 128 = 128 KB 256 = 256 KB
- 512 = 512 KB
- 1M0 = 1 MB T Temperature range (°C) • V = –40 to 105
- FT = 48 QFN (7 mm x 7 mm)
- LF = 48 LQFP (7 mm x 7 mm) FX = 64 QFN (9 mm x 9 mm)
- LH = 64 LQFP (10 mm x 10 mm)
- LK = 80 LQFP (12 mm x 12 mm)
- MB = 81 MAPBGA (8 mm x 8 mm)
- LL = 100 LQFP (14 mm x 14 mm)
- ML = 104 MAPBGA (8 mm x 8 mm)
- LQ = 144 LQFP (20 mm x 20 mm)
- MD = 144 MAPBGA (13 mm x 13 mm)
- MF = 196 MAPBGA (15 mm x 15 mm)
- MJ = 256 MAPBGA (17 mm x 17 mm) CCC Maximum CPU frequency (MHz) • 50 = 50 MHz
- 72 = 72 MHz
- 100 = 100 MHz 120 = 120 MHz
- 150 = 150 MHz N Packaging type • R = Tape and reel
- (Blank) = Trays
2.4 Example
This is an example part number: MK10N512VMD100
3 Terminology and guidelines
3.1 Definition: Operating requirement
An operating requirement is a specified value or range of values for a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useful life of the chip. Terminology and guidelines K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010. Freescale Semiconductor, Inc. Preliminary 5 Preliminary
3.1.1 Example
This is an example of an operating requirement, which you must meet for the accompanying operating behaviors to be guaranteed: Symbol Description Min. Max. Unit VDD 1.0 V core supply volt‐ age 0.9 1.1 V
3.2 Definition: Operating behavior
An operating behavior is a specified value or range of values for a technical characteristic that are guaranteed during operation if you meet the operating requirements and any other specified conditions.
3.2.1 Example
This is an example of an operating behavior, which is guaranteed if you meet the accompanying operating requirements: Symbol Description Min. Max. Unit IWP Digital I/O weak pullup/ pulldown current 10 130 µA
3.3 Definition: Attribute
An attribute is a specified value or range of values for a technical characteristic that are guaranteed, regardless of whether you meet the operating requirements.
3.3.1 Example
This is an example of an attribute: Symbol Description Min. Max. Unit CIN_D Input capacitance: digi‐ tal pins — 7 pF Terminology and guidelines K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010. 6 Preliminary Freescale Semiconductor, Inc. Preliminary
3.4 Definition: Rating
A rating is a minimum or maximum value of a technical characteristic that, if exceeded, may cause permanent chip failure:
- Operating ratings apply during operation of the chip.
- Handling ratings apply when the chip is not powered.
3.4.1 Example
This is an example of an operating rating: Symbol Description Min. Max. Unit VDD 1.0 V core supply volt‐ age –0.3 1.2 V
3.5 Result of exceeding a rating
Failures in time (ppm) The likelihood of permanent chip failure increases rapidly as soon as a characteristic begins to exceed one of its operating ratings. Terminology and guidelines K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010. Freescale Semiconductor, Inc. Preliminary 7 Preliminary
3.6 Relationship between ratings and operating requirements
- No permanent failure - Correct operation Normal operating range Limited operating range - No permanent failure - Possible decreased life - Possible incorrect operation Fatal range - Probable permanent failure Limited operating range - No permanent failure - Possible decreased life - Possible incorrect operation Handling range - No permanent failure Fatal range - Probable permanent failure Operating or handling rating (max.)Operating requirement (max.)Operating requirement (min.)Operating or handling rating (min.)
3.7 Guidelines for ratings and operating requirements
Follow these guidelines for ratings and operating requirements:
- Never exceed any of the chip’s ratings.
- During normal operation, don’t exceed any of the chip’s operating requirements. If you must exceed an operating requirement at times other than during normal operation (for example, during power sequencing), limit the duration as much as possible.
3.8 Definition: Typical value
A typical value is a specified value for a technical characteristic that:
- Lies within the range of values specified by the operating behavior
- Given the typical manufacturing process, is representative of that characteristic during operation when you meet the typical-value conditions or other specified conditions Typical values are provided as design guidelines and are neither tested nor guaranteed. 3.8.1 Example 1 This is an example of an operating behavior that includes a typical value: Symbol Description Min. Typ. Max. Unit IWP Digital I/O weak pullup/pulldown current 10 70 130 µA Terminology and guidelines K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010. 8 Preliminary Freescale Semiconductor, Inc. Preliminary
3.8.2 Example 2
This is an example of a chart that shows typical values for various voltage and temperature conditions: 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 150 °C 105 °C 25 °C –40 °C VDD (V) I (μA)DD_STOP TJ
3.9 Typical Value Conditions
Typical values assume you meet the following conditions (or other conditions as specified): Symbol Description Value Unit TA Ambient temperature 25 °C VDD 3.3 V supply voltage 3.3 V
4 Ratings
K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010. Freescale Semiconductor, Inc. Preliminary 9 Preliminary
4.1 Thermal handling ratings
Symbol Description Min. Max. Unit Notes TSTG Storage temperature –55 150 °C 1 TSDR Solder temperature, lead-free — 260 °C 2 Solder temperature, leaded — 245 1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life. 2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices.
4.2 Moisture handling ratings
Symbol Description Min. Max. Unit Notes MSL Moisture sensitivity level — 3 — 1 1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices.
4.3 ESD handling ratings
Symbol Description Min. Max. Unit Notes VHBM Electrostatic discharge voltage, human body model -2000 +2000 V 1 VCDM Electrostatic discharge voltage, charged-device model -500 +500 V 2 ILAT Latch-up current at ambient temperature of 85°C -100 +100 mA 1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM). 2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
4.4 Voltage and current operating ratings
Symbol Description Min. Max. Unit VDD Digital supply voltage –0.3 3.8 V IDD Digital supply current — 185 mA VDIO Digital input voltage (except RESET, EXTAL, and XTAL) –0.3 5.5 V VAIO Analog, RESET, EXTAL, and XTAL input voltage –0.3 VDD + 0.3 V Table continues on the next page... Ratings K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010. 10 Preliminary Freescale Semiconductor, Inc. Preliminary
- The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See
each module's specification for its supply current.
5 General
5.1 Nonswitching electrical specifications
5.1.1 Voltage and Current Operating Requirements
Table 1. Voltage and current operating requirements
- 2.7 V ≤ V DD ≤ 3.6 V
- 1.7 V ≤ VDD ≤ 2.7 V 0.7 × VDD 0.75 × VDD V V VIL Input low voltage
- 2.7 V ≤ V DD ≤ 3.6 V
- 1.7 V ≤ VDD ≤ 2.7 V 0.35 × VDD 0.3 × VDD V V VHYS Input hysteresis 0.06 × VDD — V Table continues on the next page... General K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010. Freescale Semiconductor, Inc. Preliminary 11 Preliminary
Table 1. Voltage and current operating requirements (continued)
- V IN > VDD
- V IN < VSS –0.2 mA mA DC injection current — total MCU limit, includes sum of all stressed pins
- VIN > VDD
- VIN < VSS mA mA 1. All functional non-supply pins are internally clamped to VSS and VDD. Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values. Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result in external power supply going out of regulation. Ensure external VDD load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if clock rate is very low (which would reduce overall power consumption).
5.1.2 LVD and POR operating requirements
Table 2. LVD and POR operating requirements
- Level 1 falling (LVWV=00)
- Level 2 falling (LVWV=01) Level 3 falling (LVWV=10)
- Level 4 falling (LVWV=11) TBD TBD TBD TBD 2.70 2.80 2.90 3.00 TBD TBD TBD TBD V V V V VHYS Low-voltage inhibit reset/recover hysteresis — high range 60 mV VLVDL Falling low-voltage detect threshold — low range (LVDV=00) TBD TBD TBD V VLVW1 VLVW2 VLVW3 VLVW4 Low-voltage warning thresholds — low range
- Level 1 falling (LVWV=00)
- Level 2 falling (LVWV=01) Level 3 falling (LVWV=10)
- Level 4 falling (LVWV=11) TBD TBD TBD TBD 1.80 1.90 2.00 2.10 TBD TBD TBD TBD V V V V Table continues on the next page... General K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010. 12 Preliminary Freescale Semiconductor, Inc. Preliminary
Table 2. LVD and POR operating requirements (continued)
- Rising thresholds are falling threshold + V HYS
5.1.3 Voltage and current operating behaviors
Table 3. Voltage and current operating behaviors
- 2.7 V ≤ V DD ≤ 3.6 V, IOH = -10mA
- 1.71 V ≤ VDD ≤ 2.7 V, IOH = -3mA VDD – 0.5 VDD – 0.5 V V Output high voltage — low drive strength
- 2.7 V ≤ V DD ≤ 3.6 V, IOH = -2mA
- 1.71 V ≤ VDD ≤ 2.7 V, IOH = -0.6mA VDD – 0.5 VDD – 0.5 V V IOHT Output high current total for all ports — 100 mA VOL Output low voltage — high drive strength
- 2.7 V ≤ V DD ≤ 3.6 V, IOL = 10mA
- 1.71 V ≤ VDD ≤ 2.7 V, IOL = 3mA 0.5 0.5 V V Output low voltage — low drive strength
- 2.7 V ≤ V DD ≤ 3.6 V, IOL = 2mA
- 1.71 V ≤ VDD ≤ 2.7 V, IOL = 0.6mA 0.5 0.5 V V IOLT Output low current total for all ports — 100 mA IIN Input leakage current (per pin) — 1 μA IOZ Hi-Z (off-state) leakage current (per pin) — 1 μA RPU and RPD Internal weak pullup and pulldown resistors 30 50 kΩ 1 1. Measured at V IL max and VDD min General K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010. Freescale Semiconductor, Inc. Preliminary 13 Preliminary
5.1.4 Power mode transition operating behaviors
- CPU and system clocks = 100MHz
- Bus and FlexBus clocks = 50 MHz Flash clock = 25 MHz
Table 4. Power mode transition operating behaviors across the operating temperature range of the chip.
- RUN → VLLS1
- VLLS1 → RUN 4.1 123.8 μs μs RUN → VLLS2 → RUN
- RUN → VLLS2
- VLLS2 → RUN 4.1 49.3 μs μs RUN → VLLS3 → RUN
- RUN → VLLS3
- VLLS3 → RUN 4.1 49.2 μs μs RUN → LLS → RUN
- RUN → LLS
- LLS → RUN 4.1 5.9 μs μs RUN → STOP → RUN
- RUN → STOP
- STOP → RUN 4.1 4.2 μs μs RUN → VLPS → RUN
- RUN → VLPS
- VLPS → RUN 4.1 5.8 μs μs 1. Normal boot (FTFL_OPT[LPBOOT]=1) General K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010. 14 Preliminary Freescale Semiconductor, Inc. Preliminary
5.1.5 Power consumption operating behaviors
Table 5. Power consumption operating behaviors
- @ 1.8V
- @ 3.0V TBD TBD mA mA IDD_RUN Run mode current — all peripheral clocks ena‐ bled, code executing from flash
- @ 1.8V
- @ 3.0V TBD TBD mA mA IDD_RUN_M AX Run mode current — all peripheral clocks ena‐ bled and peripherals active, code executing from flash
- @ 1.8V
- @ 3.0V TBD TBD mA mA IDD_WAIT Wait mode current at 3.0 V — all peripheral clocks disabled — 15 TBD mA 4 IDD_STOP Stop mode current at 3.0 V — 1.4 TBD mA IDD_VLPR Very-low-power run mode current at 3.0 V — all peripheral clocks disabled — 1.25 TBD mA 5 IDD_VLPR Very-low-power run mode current at 3.0 V — all peripheral clocks enabled — TBD TBD mA 6 IDD_VLPW Very-low-power wait mode current at 3.0 V — 1.05 TBD mA 7 IDD_VLPS Very-low-power stop mode current at 3.0 V — 30 TBD μA IDD_LLS Low leakage stop mode current at 3.0 V — 12 TBD μA IDD_VLLS3 Very low-leakage stop mode 3 current at 3.0 V
- 128KB RAM devices TBD μA IDD_VLLS2 Very low-leakage stop mode 2 current at 3.0 V — 4 TBD μA IDD_VLLS1 Very low-leakage stop mode 1 current at 3.0 V — 2 TBD μA IDD_VBAT Average current when CPU is not accessing RTC registers at 3.0 V — 550 TBD nA 1. 100MHz core and system clock, 50MHz bus and FlexBus clock, and 25MHz flash clock . MCG configured for FEI mode. All peripheral clocks disabled. 2. 100MHz core and system clock, 50MHz bus and FlexBus clock, and 25MHz flash clock. MCG configured for FEI mode. All peripheral clocks enabled, but peripherals are not in active operation. 3. 100MHz core and system clock, 50MHz bus and FlexBus clock, and 25MHz flash clock. MCG configured for FEI mode. All peripheral clocks enabled, and peripherals are in active operation. 4. 25MHz core and system clock, 25MHz bus clock, and 12.5MHz FlexBus and flash clock. MCG configured for FEI mode. 5. 2 MHz core, system, FlexBus, and bus clock and 1MHz flash clock. MCG configured for fast IRCLK mode. All peripheral clocks disabled. Code executing from flash. 6. 2 MHz core, system, FlexBus, and bus clock and 1MHz flash clock. MCG configured for fast IRCLK mode. All peripheral clocks enabled but peripherals are not in active operation. Code executing from flash. General K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010. Freescale Semiconductor, Inc. Preliminary 15 Preliminary
- 2 MHz core, system, FlexBus, and bus clock and 1MHz flash clock. MCG configured for fast IRCLK mode. All peripheral
5.1.5.1 Diagram: Typical IDD_RUN operating behavior
- MCG in FEI mode (39.0625 kHz IRC), except for 1 MHz core (FBE)
- All peripheral clocks disabled except FTFL LVD disabled
- No GPIOs toggled
- Code execution from flash
Figure 1. Run mode supply current vs. core frequency — all peripheral clocks disabled
- MCG in FEI mode (39.0625 kHz IRC), except for 1 MHz core (FBE)
- All peripheral clocks enabled but peripherals are not in active operation LVD disabled
- No GPIOs toggled
- Code execution from flash General K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010. 16 Preliminary Freescale Semiconductor, Inc. Preliminary
Figure 2. Run mode supply current vs. core frequency — all peripheral clocks enabled
5.1.6 EMC radiated emissions operating behaviors
Table 6. EMC radiated emissions operating behaviors
- Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions, 150
Wideband TEM (GTEM) Cell Method.
- Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and Wideband
Circuits—TEM/Wideband TEM (GTEM) Cell Method. K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
5.1.7 Designing with radiated emissions in mind
- To find application notes that provide guidance on designing your system to
5.1.8 Capacitance attributes
Table 7. Capacitance attributes
5.2 Switching electrical specifications
Table 8. Device clock specifications
5.3 Thermal specifications
K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010. 18 Preliminary Freescale Semiconductor, Inc.
5.3.1 Thermal operating requirements
Table 9. Thermal operating requirements
5.3.2 Thermal attributes
6 Peripheral operating requirements and behaviors
6.1 Core modules
- Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Environmental Conditions—Forced Convection (Moving Air).
- Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental Conditions
- Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate
the top of the package and the cold plate.
- Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air). K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
6.1.1 Debug trace timing specifications
Table 10. Debug trace operating behaviors Figure 3. TRACE_CLKOUT specifications Figure 4. Trace data specifications
6.1.2 JTAG electricals
Table 11. JTAG electricals
- JTAG and CJTAG
- Serial Wire Debug MHz J2 TCLK cycle period 1/J1 — ns Table continues on the next page... Peripheral operating requirements and behaviors K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010. 20 Preliminary Freescale Semiconductor, Inc. Preliminary
Table 11. JTAG electricals (continued)
- JTAG and CJTAG
- Serial Wire Debug ns J4 TCLK rise and fall times — 3 ns J5 Boundary scan input data setup time to TCLK rise 20 — ns J6 Boundary scan input data hold time after TCLK rise 0 — ns J7 TCLK low to boundary scan output data valid — 30 ns J8 TCLK low to boundary scan output high-Z — 30 ns J9 TMS, TDI input data setup time to TCLK rise 16 — ns J10 TMS, TDI input data hold time after TCLK rise 1 — ns J11 TCLK low to TDO data valid — 4 ns J12 TCLK low to TDO high-Z — 4 ns J13 TRST assert time 100 — ns J14 TRST setup time (negation) to TCLK high 8 — ns J3 J3 J4 J4 TCLK (input)
Figure 5. Test clock input timing K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Figure 8. TRST timing
6.2 System modules
There are no specifications necessary for the device's system modules.
6.3 Clock modules
6.3.1 MCG Specifications
Table 12. MCG specifications Table continues on the next page... K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Table 12. MCG specifications (continued)
- The resulting system clock frequencies should not exceed their maximum specified values.
K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010. 24 Preliminary Freescale Semiconductor, Inc.
- This specification includes the 2% precision of the internal reference frequency (slow clock).
- The resulting clock frequency must not exceed the maximum specified clock frequency of the device.
- This specification was obtained at TBD frequency.
- This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed,
FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.
- This specification was obtained using a Freescale developed PCB. PLL jitter is dependent on the noise characteristics of
each PCB and results will vary.
- This specification was obtained at internal frequency of TBD.
- This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled
6.3.2 Oscillator Electrical Characteristics
This section provides the electrical characteristics of the module.
6.3.2.1 Oscillator DC Electrical Specifications
Table 13. Oscillator DC electrical specifications, (V SSOSC= 0 VDC) (TA = TL to TH)
- 32 kHz
- 1 MHz
4 MHz
- 8 MHz
- 16 MHz
- 24 MHz
- 32 MHz 500 100 200 300 700 1.2 1.5 nA μA μA μA μA mA mA IDDOSC Supply current — high gain mode
- 32 kHz
- 1 MHz
- 8 MHz
- 16 MHz
- 24 MHz
- 32 MHz 200 400 800 1.5 μA μA μA μA mA mA mA Cx EXTAL load capacitance — — — 2, 3 Cy XTAL load capacitance — — — 2 , 3 Table continues on the next page... Peripheral operating requirements and behaviors K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010. Freescale Semiconductor, Inc. Preliminary 25 Preliminary
- 1 MHz resonator
- 2 MHz resonator
4 MHz resonator
- 8 MHz resonator
- 16 MHz resonator
- 20 MHz resonator
- 32 MHz resonator 6.6 3.3 kΩ kΩ kΩ kΩ kΩ kΩ kΩ Vpp Peak-to-peak amplitude of oscillation (oscillator mode) — low-frequency, low-power mode — 0.6 — V Peak-to-peak amplitude of oscillation (oscillator mode) — low-frequency, high-gain mode 0.75 × VDD33OSC VDD33OSC — V Peak-to-peak amplitude of oscillation (oscillator mode) — high-frequency, low-power mode — 0.6 — V Peak-to-peak amplitude of oscillation (oscillator mode) — high-frequency, high-gain mode 0.75 × VDD33OSC VDD33OSC — V 1. V DD33OSC=3.3 V, Temperature =27 °C, Cx/Cy=20 pF 2. See crystal or resonator manufacturer's recommendation 3. R F and Cx,Cy are integrated in low-frequency, low-power mode and must not be attached externally Peripheral operating requirements and behaviors K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010. 26 Preliminary Freescale Semiconductor, Inc. Preliminary
6.3.2.2 Oscillator frequency specifications
Table 14. Oscillator frequency specifications, (V DD33OSC = VDD33OSC (min) to
- This parameter is characterized before qualification rather than 100% tested.
- Proper PC board layout procedures must be followed to achieve specifications.
- Crystal start up time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S
This section describes the module electrical characteristics. Table 15. 32kHz Oscillator Module DC Electrical Specifications (V SSOSC= 0 VDC) K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Table 16. 32kHz oscillator frequency specifications (V DD33OSC = VDD33OSC (min)
- This parameter is characterized before qualification rather than 100% tested.
- Proper PC board layout procedures must be followed to achieve specifications.
6.4 Memories and memory interfaces
6.4.1 Flash (FTFL) Electrical Characteristics
This section describes the electrical characteristics of the FTFL module.
6.4.1.1 Flash Timing Parameters — Program and Erase
active and do not include command overhead. Table 17. NVM program/erase timing characteristics
- Maximum time based on expectations at cycling end-of-life.
6.4.1.2 Flash Timing Parameters — Commands
Table 18. Flash command timing characteristics Table continues on the next page... K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010. 28 Preliminary Freescale Semiconductor, Inc.
Table 18. Flash command timing characteristics (continued)
- Assumes 25MHz flash clock frequency.
- Maximum times for erase parameters based on expectations at cycling end-of-life.
6.4.1.3 Flash (FTFL) Current and Power Parameters
Table 19. Flash (FTFL) current and power parameters
6.4.1.4 Reliability Characteristics
Table 20. NVM reliability characteristics
- Typical data retention values are based on intrinsic capability of the technology measured at high temperature derated to
- Data retention is based on T javg = 55°C (temperature profile over the lifetime of the application).
- Cycling endurance represents number of program/erase cycles at -40°C ≤ T j ≤ 125°C
K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
6.4.2 EzPort Switching Specifications
Table 21. EzPort switching specifications Figure 9. EzPort Timing Diagram
6.4.3 Flexbus Switching Specifications
the same as the internal system bus frequency or an integer divider of that frequency. K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010. 30 Preliminary Freescale Semiconductor, Inc.
Table 22. Flexbus switching specifications
- Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0], and FB_TS.
- Specification is valid for all FB_AD[31:0] and FB_TA.
Figure 10. FlexBus read timing diagram K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Figure 11. FlexBus write timing diagram
6.5 Security and integrity modules
There are no specifications necessary for the device's security and integrity modules.
6.6 Analog
6.6.1 ADC electrical specifications
K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010. 32 Preliminary Freescale Semiconductor, Inc.
differential/12-bit single-ended accuracy specifications. Table 23. 16-bit ADC operating conditions
1.13 VDDA VDDA V
- 16 bit modes
- 8/10/12 bit modes pF RADIN Input resistance — 2 5 kΩ Table continues on the next page... Peripheral operating requirements and behaviors K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010. Freescale Semiconductor, Inc. Preliminary 33 Preliminary
Table 23. 16-bit ADC operating conditions (continued)
- f ADCK > 8MHz
- f ADCK = 4–8MHz fADCK < 4MHz 13/12 bit modes
- f ADCK > 16MHz
- f ADCK > 8MHz
- f ADCK = 4–8MHz
- f ADCK < 4MHz 11/10 bit modes
- f ADCK > 8MHz
- f ADCK = 4–8MHz
- f ADCK < 4MHz 9/8 bit modes
- f ADCK > 8MHz
- f ADCK < 8MHz 0.5 0.5 kΩ kΩ kΩ kΩ kΩ kΩ kΩ kΩ kΩ kΩ kΩ kΩ External to MCU Assumes ADLSMP=0 fADCK ADC conversion clock frequency ADLPC=0, ADHSC=1
- 16 bit modes
- ≤13 bit modes ADLPC=0, ADHSC=0 16 bit modes
- ≤13 bit modes ADLPC=1, ADHSC=1
- 16 bit modes
- ≤13 bit modes ADLPC=1, ADHSC=0
- 16 bit modes
- ≤13 bit modes 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 TBD TBD 8.0 12.0 5.0 8.0 2.5 5.0 MHz MHz MHz MHz MHz MHz MHz MHz 1. Typical values assume V DDA = 3.0 V, Temp = 25°C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 2. DC potential difference. Peripheral operating requirements and behaviors K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010. 34 Preliminary Freescale Semiconductor, Inc. Preliminary
Figure 12. ADC input impedance equivalency diagram Table 24. 16-bit ADC characteristics (V REFH = VDDA, VREFL = VSSA)
- ADLPC=1, ADHSC=1
- ADLPC=0, ADHSC=0 ADLPC=0, ADHSC=1 215 340 470 610 μA μA μA μA ADLSMP= ADCO=1 Supply current • Stop, reset, module off — 0.01 0.8 μA fADACK ADC asynchro‐ nous clock source
- ADLPC=1, ADHSC=0
- ADLPC=1, ADHSC=1
- ADLPC=0, ADHSC=0 ADLPC=0, ADHSC=1 TBD TBD TBD TBD 2.4 4.0 5.2 6.2 TBD TBD TBD TBD MHz MHz MHz MHz tADACK = 1/ fADACK Sample Time See Reference Manual chapter for sample times Conversion Time See Reference Manual chapter for conversion times Table continues on the next page... Peripheral operating requirements and behaviors K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010. Freescale Semiconductor, Inc. Preliminary 35 Preliminary
Table 24. 16-bit ADC characteristics (V REFH = VDDA, VREFL = VSSA) (continued)
- 16 bit differential
- 16 bit single-ended
- 13 bit differential 12 bit single-ended
- 11 bit differential
- 10 bit single-ended
- 9 bit differential
- 8 bit single-ended ±14.0 ±13.0 ±1.5 ±TBD ±0.8 ±TBD ±0.5 ±0.5 ±TBD ±TBD ±TBD ±TBD ±TBD ±TBD ±1.0 ±1.0 LSB3 Max hard‐ ware aver‐ aging (AVGE = %1, AVGS = %11) DNL Differential non- linearity
- 16 bit differential
- 16 bit single-ended
- 13 bit differential 12 bit single-ended
- 11 bit differential
- 10 bit single-ended
- 9 bit differential
- 8 bit single-ended ±2.5 ±2.5 ±0.7 ±0.7 ±0.5 ±TBD ±0.2 ±0.2 ±TBD ±TBD ±TBD ±TBD ±TBD ±TBD ±0.5 ±0.5 LSB3 Max hard‐ ware aver‐ aging (AVGE = %1, AVGS = %11) INL Integral non-line‐ arity
- 16 bit differential
- 16 bit single-ended
- 13 bit differential 12 bit single-ended
- 11 bit differential
- 10 bit single-ended
- 9 bit differential
- 8 bit single-ended -6 to +2.5 -2 to +12 ±1.0 ±1.0 ±0.5 ±0.5 ±0.3 ±0.3 ±TBD ±TBD ±TBD ±TBD ±0.5 ±0.5 LSB3 Max aver‐ aging EZS Zero-scale error • 16 bit differential
- 16 bit single-ended
- 13 bit differential 12 bit single-ended
- 11 bit differential
- 10 bit single-ended
- 9 bit differential
- 8 bit single-ended ±4.0 ±4.0 ±0.7 ±0.7 ±0.4 ±0.4 ±0.2 ±0.2 ±TBD ±TBD ±TBD ±TBD ±0.5 ±0.5 LSB3 VADIN = VSSA Table continues on the next page... Peripheral operating requirements and behaviors K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010. 36 Preliminary Freescale Semiconductor, Inc. Preliminary
- 16 bit single-ended
- 13 bit differential 12 bit single-ended
- 11 bit differential
- 10 bit single-ended
- 9 bit differential
- 8 bit single-ended 0 to +10 0 to +14 ±1.0 ±TBD ±0.4 ±0.4 ±0.2 ±0.2 ±TBD ±TBD ±TBD ±TBD ±0.5 ±0.5 LSB3 VADIN = VDDA EQ Quantization er‐ ror
- 16 bit modes
- ≤13 bit modes -1 to 0 ±0.5 LSB3 ENOB Effective number of bits 16 bit differential mode
- Avg=32
- Avg=16 Avg=8
- Avg=4
- Avg=1 16 bit single-ended mode
- Avg=32
- Avg=16
- Avg=8
- Avg=4
- Avg=1 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 13.6 TBD 14.1 TBD 13.2 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD bits bits bits bits bits bits bits bits bits bits SINAD Signal-to-noise plus distortion See ENOB 6.02 × ENOB + 1.76 dB THD Total harmonic distortion 16 bit differential mode
- Avg=32 16 bit single-ended mode
- Avg=32 -94 TBD TBD TBD dB dB SFDR Spurious free dy‐ namic range 16 bit differential mode
- Avg=32 16 bit single-ended mode
- Avg=32 TBD TBD TBD dB dB Table continues on the next page... Peripheral operating requirements and behaviors K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010. Freescale Semiconductor, Inc. Preliminary 37 Preliminary
- –40°C to 25°C
- 25°C to 105°C TBD TBD mV/°C mV/°C VTEMP25 Temp sensor voltage 25°C — TBD — mV 1. All accuracy numbers assume the ADC is calibrated with V REFH = VDDA 2. Typical values assume V DDA = 3.0 V, Temp = 25°C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 3. 1 LSB = (VREFH - VREFL)/2N 4. Input data is 1 kHz sine wave. 6.6.1.3 16-bit ADC with PGA operating conditions
Table 25. 16-bit ADC with PGA operating conditions
- Typical values assume V DDA = 3.0 V, Temp = 25°C, fADCK = 6 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
- ADC must be configured to use the internal voltage reference (VREFOUT)
- PGA reference connected to the VREFOUT pin. If the user wishes to drive VREFOUT with a voltage other than the output
of the VREF module, the VREF module must be disabled. K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010. 38 Preliminary Freescale Semiconductor, Inc.
- The analog source resistance (R AS), external to MCU, should be kept as minimum as possible. Increased RAS causes drop
in PGA gain without affecting other performances. This is not dependent on ADC clock frequency.
- The minimum sampling time is dependent on input signal frequency and ADC mode of operation. A minimum of 1.25µs
Table 26. 16-bit ADC with PGA characteristics
- PGAG=1
- PGAG=2 PGAG=3
- PGAG=4
- PGAG=5
- PGAG=6 TBD TBD TBD TBD TBD TBD TBD 3.9 TBD TBD 29.9 TBD TBD TBD TBD TBD TBD TBD TBD dB dB dB dB dB dB dB RAS < 100Ω GA Gain error — — ±0.5 dB RAS < 100Ω BW Input signal band‐ width
- 16-bit modes
- < 16-bit modes kHz kHz PSRR Power supply re‐ jection ration Gain=1 TBD TBD — dB VDDA= 3V ±100mV, fVDDA= 50Hz, 60Hz CMRR Common mode rejection ratio
- Gain=1
- Gain=64 TBD TBD TBD TBD dB dB VCM= 500mVpp, fVCM= 50Hz, 100Hz VOFS Input offset volt‐ age — 0.2 TBD mV Gain=1, ADC Averaging=32 TGSW Gain switching settling time — TBD 10 µs 3 dG/dT Gain drift over temperature
- Gain=1
- Gain=64 TBD TBD TBD TBD ppm/°C ppm/°C 0 to 50°C dVOFS/dT Offset drift over temperature Gain=1 — TBD TBD ppm/°C 0 to 50°C, ADC Averaging=32 dG/dVDDA Gain drift over supply voltage
- Gain=1
- Gain=64 TBD TBD TBD TBD %/V %/V VDDA from 1.71 to 3.6V Table continues on the next page... Peripheral operating requirements and behaviors K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010. Freescale Semiconductor, Inc. Preliminary 39 Preliminary
Table 26. 16-bit ADC with PGA characteristics (continued)
- Gain=1
- Gain=64 TBD TBD 8.3 57.7 dB dB Average=32 THD Total harmonic distortion
- Gain=1
- Gain=64 TBD TBD 87.3 85.3 dB dB Average=32, fin=100Hz SFDR Spurious free dy‐ namic range
- Gain=1
- Gain=64 TBD TBD 92.42 92.54 dB dB Average=32, fin=100Hz ENOB Effective number of bits
- Gain=1, Average=4
- Gain=1, Average=8
- Gain=64, Average=4 Gain=64, Average=8
- Gain=1, Average=32
- Gain=2, Average=32
- Gain=4, Average=32
- Gain=8, Average=32
- Gain=16, Average=32
- Gain=32, Average=32
- Gain=64, Average=32 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 12.3 12.7 8.4 8.7 13.4 13.1 12.6 11.8 11.1 10.2 9.3 bits bits bits bits bits bits bits bits bits bits bits SINAD Signal-to-noise plus distortion ra‐ tio See ENOB 6.02 × ENOB + 1.76 dB 1. Typical values assume V DDA =3.0V, Temp=25°C, fADCK=6MHz unless otherwise stated. 2. Gain = 2PGAGx 3. When the PGA gain is changed, it takes some time to settle the output for the ADC to work properly. During a gain switching, a few ADC outputs should be discarded (minimum two data samples, may be more depending on ADC sampling rate and time of the switching). 4. Limit the input signal swing so that the PGA does not saturate during operation. Input signal swing is dependent on the PGA reference voltage and gain setting. Peripheral operating requirements and behaviors K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010. 40 Preliminary Freescale Semiconductor, Inc. Preliminary
6.6.2 CMP and 6-bit DAC electrical specifications
Table 27. Comparator and 6-bit DAC electrical specifications
- HYSTCTR = 00
- HYSTCTR = 01 HYSTCTR = 10
- HYSTCTR = 11 mV mV mV mV VCMPOh Output high VDD – 0.5 — — V VCMPOl Output low — — 0.5 V tDHS Propagation delay, high-speed mode (EN=1, PMODE=1) 20 50 120 ns tDLS Propagation delay, low-speed mode (EN=1, PMODE=1) 120 250 420 ns Analog comparator initialization delay — — TBD ns IDAC6b 6-bit DAC current adder (enabled) — — 8 μA INL 6-bit DAC integral non-Llnearity –0.5 — 0.5 LSB1 DNL 6-bit DAC differential non-linearity –0.3 — 0.3 LSB 1. 1 LSB = V reference/64 6.6.3 12-bit DAC electrical characteristics 6.6.3.1 12-bit DAC operating requirements
Table 28. 12-bit DAC operating requirements Table continues on the next page... K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Table 28. 12-bit DAC operating requirements (continued)
- The DAC reference can be selected to be VDDA or the voltage output of the VREF module (VREFO)
- A small load capacitance (47 pF) can improve the bandwidth performance of the DAC
Table 29. 12-bit DAC operating behaviors
1 TBD — μs 1
Table continues on the next page... K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010. 42 Preliminary Freescale Semiconductor, Inc.
Table 29. 12-bit DAC operating behaviors (continued)
- High power (SP HP)
- Low power (SP LP) 1.2 0.05 1.7 0.12 V/μs CT Channel to channel cross talk — — -80 dB BW 3dB bandwidth
- High power (SPHP)
- Low power (SPLP) 550 kHz 1. Settling within ±1 LSB 2. The INL is measured for 0+100mV to VDACR−100 mV 3. The DNL is measured for 0+100 mV to V DACR−100 mV 4. The DNL is measured for 0+100mV to V DACR−100 mV with VDDA > 2.4V 5. Calculated by a best fit curve from V SS+100 mV to VREF−100 mV
Figure 13. Typical INL error vs. digital code K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Figure 14. Offset at half scale vs. temperature
6.6.4 Voltage Reference Electrical Specifications
Table 30. VREF full-range operating requirements Table 31. VREF full-range operating behaviors Table continues on the next page... K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010. 44 Preliminary Freescale Semiconductor, Inc.
Table 31. VREF full-range operating behaviors (continued) Table 32. VREF limited-range operating requirements Table 33. VREF limited-range operating behaviors Figure 15. Typical output vs.temperature Figure 16. Typical output vs. VDD
6.7 Timers
See General Switching Specifications.
6.8 Communication interfaces
K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
6.8.1 DSPI Switching Specifications for Low-speed Operation
used for communicating with slower peripheral devices. Table 34. Master Mode DSPI Timing (Low-speed mode)
- The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage
range the maximum frequency of operation is reduced. Figure 17. DSPI Classic SPI Timing — Master Mode Table 35. Slave Mode DSPI Timing (Low-speed Mode) Table continues on the next page... K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010. 46 Preliminary Freescale Semiconductor, Inc.
Table 35. Slave Mode DSPI Timing (Low-speed Mode) (continued) Figure 18. DSPI Classic SPI Timing — Slave Mode
6.8.2 DSPI Switching Specifications (High-speed mode)
used for communicating with slower peripheral devices. Table 36. Master Mode DSPI Timing (High-speed mode) Table continues on the next page... K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Table 36. Master Mode DSPI Timing (High-speed mode) (continued) Figure 19. DSPI Classic SPI Timing — Master Mode Table 37. Slave Mode DSPI Timing (High-speed mode) K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010. 48 Preliminary Freescale Semiconductor, Inc.
Figure 20. DSPI Classic SPI Timing — Slave Mode
6.8.3 SDHC Specifications
appropriately to arrive at timing specs/constraints for the physical interface. Table 38. SDHC switching specifications K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Figure 21. SDHC timing
6.8.4 I2S Switching Specifications
(I2S_FS) shown in the figures below. Table 39. I2S master mode timing K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010. 50 Preliminary Freescale Semiconductor, Inc.
6.9 Human-machine interfaces (HMI)
6.9.1 General Switching Specifications
FlexCAN, CMT, and I2C signals. Table 41. General switching specifications
- Slew disabled
- Slew enabled ns ns Port rise and fall time (low drive strength)
- Slew disabled
- Slew enabled ns ns 1. The greater synchronous and asynchronous timing must be met. 2. This is the shortest pulse that is guaranteed to be recognized. 3. 75pF load 4. 15pF load
6.9.2 TSI Electrical Specifications
Table 42. Touch Sensing Input module specifications Table continues on the next page... K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010. 52 Preliminary Freescale Semiconductor, Inc.
Table 42. Touch Sensing Input module specifications (continued)
- The TSI module is functional with capacitance values outside of this range. However, optimal performance is not
- The programmable current source value is generated by multiplying the SCANC[REFCHRG] value and the base current
- The programmable current source value is generated by multiplying the SCANC[EXTCHRG] value and the base current
- Measured with a 5pF electrode, reference oscillator frequency of 10MHz, PS = 128, NCSC = 8; Iext = 16
- Measured with a 20pF electrode, reference oscillator frequency of 10MHz, PS = 128, NCSC = 2; Iext = 16
- Measured with a 20pF electrode, reference oscillator frequency of 10MHz, PS = 16, NCSC = 3; Iext = 16
- 1pF electrode capacitance with 4.96ms scan time
- Time that takes to do one complete measurement of the electrode. Sensitivity resolution of 0.0133pF
7 Dimensions
7.1 Obtaining package dimensions
Package dimensions are provided in package drawings. K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
8 Pinout
8.1 K10 Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these pins on the devices supported by this document. The Port Control Module is responsible for selecting which ALT functionality is available on each pin. 100 QFP Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort
1 ADC1_SE4a ADC1_SE4a PTE0 SPI1_PCS1 UART1_TX SDHC0_D1 I2C1_SDA
2 ADC1_SE5a ADC1_SE5a PTE1 SPI1_SOUT UART1_RX SDHC0_D0 I2C1_SCL
3 ADC1_SE6a ADC1_SE6a PTE2 SPI1_SCK UART1_CTS_
b SDHC0_DCLK
4 ADC1_SE7a ADC1_SE7a PTE3 SPI1_SIN UART1_RTS_
b SDHC0_CMD
5 DISABLED PTE4 SPI1_PCS0 UART3_TX SDHC0_D3
6 DISABLED PTE5 SPI1_PCS2 UART3_RX SDHC0_D2
7 DISABLED PTE6 SPI1_PCS3 UART3_CTS_
b I2S0_MCLK I2S0_CLKIN
8 VDD VDD
9 VSS VSS
10 ADC0_SE4a ADC0_SE4a PTE16 SPI0_PCS0 UART2_TX FTM_CLKIN0 FTM0_FLT3
11 ADC0_SE5a ADC0_SE5a PTE17 SPI0_SCK UART2_RX FTM_CLKIN1 LPT00_ALT3
12 ADC0_SE6a ADC0_SE6a PTE18 SPI0_SOUT UART2_CTS_
b I2C0_SDA
13 ADC0_SE7a ADC0_SE7a PTE19 SPI0_SIN UART2_RTS_
b I2C0_SCL
14 ADC0_DP1 ADC0_DP1
15 ADC0_DM1 ADC0_DM1
16 ADC1_DP1 ADC1_DP1
17 ADC1_DM1 ADC1_DM1
18 PGA0_DP/
ADC0_DP0/ ADC1_DP3 PGA0_DP/ ADC0_DP0/ ADC1_DP3
19 PGA0_DM/
ADC0_DM0/ ADC1_DM3 PGA0_DM/ ADC0_DM0/ ADC1_DM3
20 PGA1_DP/
ADC1_DP0/ ADC0_DP3 PGA1_DP/ ADC1_DP0/ ADC0_DP3
21 PGA1_DM/
ADC1_DM0/ ADC0_DM3 PGA1_DM/ ADC1_DM0/ ADC0_DM3 Pinout K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010. 54 Preliminary Freescale Semiconductor, Inc. Preliminary
Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort
22 VDDA VDDA
23 VREFH VREFH
24 VREFL VREFL
25 VSSA VSSA
26 VREF_OUT VREF_OUT
27 DAC0_OUT DAC0_OUT
28 XTAL32 XTAL32
29 EXTAL32 EXTAL32
30 VBAT VBAT
31 ADC0_SE17 ADC0_SE17 PTE24 CAN1_TX UART4_TX EWM_OUT_b
32 ADC0_SE18 ADC0_SE18 PTE25 CAN1_RX UART4_RX EWM_IN
33 DISABLED PTE26 UART4_CTS_
b RTC_CLKOUT
34 JTAG_TCLK/
SWD_CLK/ EZP_CLK TSI0_CH1 PTA0 UART0_CTS_ b FTM0_CH5 JTAG_TCLK/ SWD_CLK EZP_CLK
35 JTAG_TDI/
EZP_DI TSI0_CH2 PTA1 UART0_RX FTM0_CH6 JTAG_TDI EZP_DI
36 JTAG_TDO/
TRACE_SWO/ EZP_DO TSI0_CH3 PTA2 UART0_TX FTM0_CH7 JTAG_TDO/ TRACE_SWO EZP_DO
37 JTAG_TMS/
SWD_DIO TSI0_CH4 PTA3 UART0_RTS_ b FTM0_CH0 JTAG_TMS/ SWD_DIO
38 NMI_b/
EZP_CS_b TSI0_CH5 PTA4 FTM0_CH1 NMI_b EZP_CS_b
39 JTAG_TRST PTA5 FTM0_CH2 CMP2_OUT I2S0_RX_BCL
K JTAG_TRST
40 VDD VDD
41 VSS VSS
42 CMP2_IN0 CMP2_IN0 PTA12 CAN0_TX FTM1_CH0 I2S0_TXD FTM1_QD_PH
A
43 CMP2_IN1 CMP2_IN1 PTA13 CAN0_RX FTM1_CH1 I2S0_TX_FS FTM1_QD_PH
B
44 DISABLED PTA14 SPI0_PCS0 UART0_TX I2S0_TX_BCL
K
45 DISABLED PTA15 SPI0_SCK UART0_RX I2S0_RXD
46 DISABLED PTA16 SPI0_SOUT UART0_CTS_
b I2S0_RX_FS
47 ADC1_SE17 ADC1_SE17 PTA17 SPI0_SIN UART0_RTS_
b I2S0_MCLK I2S0_CLKIN
48 VDD VDD
49 VSS VSS
50 EXTAL EXTAL PTA18 FTM0_FLT2 FTM_CLKIN0
51 XTAL XTAL PTA19 FTM1_FLT0 FTM_CLKIN1 LPT0_ALT1
52 RESET_b RESET_b
K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010. Freescale Semiconductor, Inc. Preliminary 55 Preliminary
Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort
53 ADC0_SE8/
ADC1_SE8/ TSI0_CH0 ADC0_SE8/ ADC1_SE8/ TSI0_CH0 PTB0 I2C0_SCL FTM1_CH0 FTM1_QD_PH A
54 ADC0_SE9/
ADC1_SE9/ TSI0_CH6 ADC0_SE9/ ADC1_SE9/ TSI0_CH6 PTB1 I2C0_SDA FTM1_CH1 FTM1_QD_PH B
55 ADC0_SE12/
TSI0_CH7 ADC0_SE12/ TSI0_CH7 PTB2 I2C0_SCL UART0_RTS_ b FTM0_FLT3
56 ADC0_SE13/
TSI0_CH8 ADC0_SE13/ TSI0_CH8 PTB3 I2C0_SDA UART0_CTS_ b FTM0_FLT0
57 DISABLED PTB9 SPI1_PCS1 UART3_CTS_
b FB_AD20
58 ADC1_SE14 ADC1_SE14 PTB10 SPI1_PCS0 UART3_RX FB_AD19 FTM0_FLT1
59 ADC1_SE15 ADC1_SE15 PTB11 SPI1_SCK UART3_TX FB_AD18 FTM0_FLT2
60 VSS VSS
61 VDD VDD
62 TSI0_CH9 TSI0_CH9 PTB16 SPI1_SOUT UART0_RX FB_AD17 EWM_IN
63 TSI0_CH10 TSI0_CH10 PTB17 SPI1_SIN UART0_TX FB_AD16 EWM_OUT_b
64 TSI0_CH11 TSI0_CH11 PTB18 CAN0_TX FTM2_CH0 I2S0_TX_BCL
K FB_AD15 FTM2_QD_PH A
65 TSI0_CH12 TSI0_CH12 PTB19 CAN0_RX FTM2_CH1 I2S0_TX_FS FB_OE_b FTM2_QD_PH
B
66 DISABLED PTB20 SPI2_PCS0 FB_AD31 CMP0_OUT
67 DISABLED PTB21 SPI2_SCK FB_AD30 CMP1_OUT
68 DISABLED PTB22 SPI2_SOUT FB_AD29 CMP2_OUT
69 DISABLED PTB23 SPI2_SIN SPI0_PCS5 FB_AD28
70 ADC0_SE14/
TSI0_CH13 ADC0_SE14/ TSI0_CH13 PTC0 SPI0_PCS4 PDB0_EXTRG I2S0_TXD FB_AD14
71 ADC0_SE15/
TSI0_CH14 ADC0_SE15/ TSI0_CH14 PTC1 SPI0_PCS3 UART1_RTS_ b FTM0_CH0 FB_AD13
72 ADC0_SE4b/
CMP1_IN0/ TSI0_CH15 ADC0_SE4b/ CMP1_IN0/ TSI0_CH15 PTC2 SPI0_PCS2 UART1_CTS_ b FTM0_CH1 FB_AD12
73 CMP1_IN1 CMP1_IN1 PTC3 SPI0_PCS1 UART1_RX FTM0_CH2 FB_CLKOUT
74 VSS VSS
75 VDD VDD
76 DISABLED PTC4 SPI0_PCS0 UART1_TX FTM0_CH3 FB_AD11 CMP1_OUT
77 DISABLED PTC5 SPI0_SCK LPT0_ALT2 FB_AD10 CMP0_OUT
78 CMP0_IN0 CMP0_IN0 PTC6 SPI0_SOUT PDB0_EXTRG FB_AD9
79 CMP0_IN1 CMP0_IN1 PTC7 SPI0_SIN FB_AD8
80 ADC1_SE4b/
CMP0_IN2 ADC1_SE4b/ CMP0_IN2 PTC8 I2S0_MCLK I2S0_CLKIN FB_AD7
81 ADC1_SE5b/
CMP0_IN3 ADC1_SE5b/ CMP0_IN3 PTC9 I2S0_RX_BCL K FB_AD6 FTM2_FLT0
82 ADC1_SE6b/
CMP0_IN4 ADC1_SE6b/ CMP0_IN4 PTC10 I2C1_SCL I2S0_RX_FS FB_AD5 Pinout K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010. 56 Preliminary Freescale Semiconductor, Inc. Preliminary
Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort
83 ADC1_SE7b ADC1_SE7b PTC11 I2C1_SDA I2S0_RXD FB_RW_b
84 DISABLED PTC12 UART4_RTS_
b FB_AD27
85 DISABLED PTC13 UART4_CTS_
b FB_AD26
86 DISABLED PTC14 UART4_RX FB_AD25
87 DISABLED PTC15 UART4_TX FB_AD24
88 VSS VSS
89 VDD VDD
90 DISABLED PTC16 CAN1_RX UART3_RX FB_CS5_b/
FB_TSIZ1/ FB_BE23_16_ BLS15_8_b
91 DISABLED PTC17 CAN1_TX UART3_TX FB_CS4_b/
FB_TSIZ0/ FB_BE31_24_ BLS7_0_b
92 DISABLED PTC18 UART3_RTS_
b FB_TBST_b/ FB_CS2_b/ FB_BE15_8_B LS23_16_b
93 DISABLED PTD0 SPI0_PCS0 UART2_RTS_
b FB_ALE/ FB_CS1_b/ FB_TS_b
94 ADC0_SE5b ADC0_SE5b PTD1 SPI0_SCK UART2_CTS_
b FB_CS0_b
95 DISABLED PTD2 SPI0_SOUT UART2_RX FB_AD4
96 DISABLED PTD3 SPI0_SIN UART2_TX FB_AD3
97 DISABLED PTD4 SPI0_PCS1 UART0_RTS_
b FTM0_CH4 FB_AD2 EWM_IN
98 ADC0_SE6b ADC0_SE6b PTD5 SPI0_PCS2 UART0_CTS_
b FTM0_CH5 FB_AD1 EWM_OUT_b
99 ADC0_SE7b ADC0_SE7b PTD6 SPI0_PCS3 UART0_RX FTM0_CH6 FB_AD0 FTM0_FLT0
100 DISABLED PTD7 CMT_IRO UART0_TX FTM0_CH7 FTM0_FLT1
8.2 K10 Pinouts
The below figure shows the pinout diagram for the devices supported by this document. Many signals may be multiplexed onto a single pin. To determine what signals can be used on which pin, see the previous section. Pinout K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010. Freescale Semiconductor, Inc. Preliminary 57 Preliminary
PGA1_DP/ADC1_DP0/ADC0_DP3 PGA0_DM/ADC0_DM0/ADC1_DM3 PGA0_DP/ADC0_DP0/ADC1_DP3 ADC1_DM1 ADC1_DP1 ADC0_DM1 ADC0_DP1 PTE19 PTE18 PTE17 PTE16 VSS VDD PTE6 PTE5 PTE4 PTE3 PTE2 PTE1 PTE0 VDD VSS PTC3 PTC2 PTC1 PTC0 PTB23 PTB22 PTB21 PTB20 PTB19 PTB18 PTB17 PTB16 VDD VSS PTB11 PTB10 PTB9 PTB3 PTB2 PTB1 PTB0 RESET_b PTA19 VSSA VREFL VREFH VDDA PGA1_DM/ADC1_DM0/ADC0_DM3 PTD6 PTC7 PTC6 PTC5 PTC450 PTA18 VSS VDD PTA17 PTA16 PTA15 PTA14 PTA13 PTA12 VSS VDD PTA5 PTA4 PTA3 PTA2 PTA1 PTA0 PTE26 PTE25 PTE24 VBAT EXTAL32 XTAL32 DAC0_OUT VREF_OUT
98 PTD5
97 PTD4
96 PTD3
95 PTD2
94 PTD1
93 PTD0
92 PTC18
91 PTC17
90 PTC16
89 VDD
88 VSS
80 PTC8
83 PTC11
84 PTC12
85 PTC13
86 PTC14
87 PTC15
100 PTD7
Figure 24. K10 100 LQFP Pinout Diagram
9 Revision History
The following table provides a revision history for this document.
Revision History
K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010. 58 Preliminary Freescale Semiconductor, Inc. Preliminary
Table 43. Revision History K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010. Freescale Semiconductor, Inc. Preliminary 59 Preliminary
How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. Technical Information Center, EL516
2100 East Elliot Road
Tempe, Arizona 85284 1-800-521-6274 or +1-480-768-2130 www.freescale.com/support Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7
81829 Muenchen, Germany
+44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) www.freescale.com/support Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo 153-0064 Japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com Asia/Pacific: Freescale Semiconductor China Ltd. Exchange Building 23F No. 118 Jianguo Road Chaoyang District Beijing 100022 China +86 10 5879 8000 support.asia@freescale.com Freescale Semiconductor Literature Distribution Center P .O. Box 5405 Denver, Colorado 80217 1-800-441-2447 or +1-303-675-2140 Fax: +1-303-675-2150 LDCForFreescaleSemiconductor@hibbertgroup.com Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”, must be validated for each customer application by customer’s technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. ARM is the registered trademark of ARM Limited. ARM Cortex-M4 is the trademark of ARM Limited. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2010. All rights reserved. K10P104M100SF2 Rev. 1 Preliminary