JLC1562B ONSEMI | Alldatasheet
Document overview
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- PDF pages: 10
Technical content
Features
- Pb−Free Packages are Available*
- Low Power Dissipation
- I2C−Bus Format (2−Wire Type; SDA, SCL) Data Transfer
- 6−bit DAC
- Bus Address Selectable (3−bit)
- Address Input Pins are Pulled Up to VDD with Internal Resistor
- I/O Pins are Open Drain Outputs
- 5 Comparators at Inputs
- Inputs Protected from External Bus Currents in Power Down Mode 125 VDAC SCL SDA VDD VSS
Figure 1. Pin Assignment Reference Manual, SOLDERRM/D.
ORDERING INFORMATION
JLC1562BN PDIP−16 500 / Unit PAK JLC1562BF EIAJ−16 (Pb−Free)
50 Units / Rail
JLC1562BFEL EIAJ−16 (Pb−Free)
2000 Units / Reel
http://onsemi.com †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. JLC1562BNG PDIP−16 (Pb−Free) 500 / Unit PAK
Figure 2. Block Diagram and selects 1/2 VDD for Comparator “B” threshold.
8 Bit
6 Bit
5 Bit
3 Bit
80 V DD
16 X R65
http://onsemi.com ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ MAXIMUM RATINGS (Referenced to GND) ÎÎÎÎÎ ÎÎÎÎÎ Symbol ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Parameter ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ Value ÎÎÎ ÎÎÎ Unit ÎÎÎÎÎ ÎÎÎÎÎ Vdd ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ DC Supply Voltage ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ –0.5 to +7.0 ÎÎÎ ÎÎÎ V ÎÎÎÎÎ ÎÎÎÎÎ Vin ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ DC Input Voltage ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ –0.5 to Vdd +0.5 ÎÎÎ ÎÎÎ V ÎÎÎÎÎ ÎÎÎÎÎ Vout ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ DC Output Voltage ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ –0.5 to Vdd +0.5 ÎÎÎ ÎÎÎ V ÎÎÎÎÎ ÎÎÎÎÎ I ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ DC Input/Output Current (per Pin) ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ mA ÎÎÎÎÎ ÎÎÎÎÎ IDD ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ DC Supply Current (VDD and GND Pins) ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ mA ÎÎÎÎÎ ÎÎÎÎÎ Tstg ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Storage Temperature Range ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ –65 to +150 ÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ TL ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Lead Temperature, 1 mm from Case for 10 Seconds ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ 300 ÎÎÎ ÎÎÎ Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. RECOMMENDED OPERATING CONDITIONS ÎÎÎÎÎ ÎÎÎÎÎ Symbol ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Parameter ÎÎÎÎ ÎÎÎÎ Min ÎÎÎÎ ÎÎÎÎ Max ÎÎÎ ÎÎÎ Unit ÎÎÎÎÎ ÎÎÎÎÎ Vdd ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ DC Supply Voltage ÎÎÎÎ ÎÎÎÎ 4.2 ÎÎÎÎ ÎÎÎÎ 6.0 ÎÎÎ ÎÎÎ V ÎÎÎÎÎ ÎÎÎÎÎ Vin, Vout ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ DC Input Voltage ÎÎÎÎ ÎÎÎÎ 0.0 ÎÎÎÎ ÎÎÎÎ Vdd ÎÎÎ ÎÎÎ V ÎÎÎÎÎ ÎÎÎÎÎ TA ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Operating Temperature ÎÎÎÎ ÎÎÎÎ –40 ÎÎÎÎ ÎÎÎÎ +85 ÎÎÎ ÎÎÎ DC CHARACTERISTICS (Referenced to Vss) Guaranteed Limit Symbol Parameter Min Max Unit VIH Maximum Input Voltage, “H” 0.7 Vdd − V VIL Maximum Input Voltage, “L” − 0.3 Vdd V VOL Maximum Output Voltage, “L” (Iout = 4mA) − 0.3 V Iin Maximum Input Leakage Current (Vin = Vdd or Vss, SCL pin only) − ± 1.0 A Ioz Maximum Output Hi−Z Leakage Current (Output = High Impedance; Vout = Vdd) − ± 5.0 A C in Maximum Input Capacitance (Input Pin) − 10 pF C out Maximum Output Capacitance (Output Pin) − 15 pF C i/o Maximum I/O Capacitance (I/O Pin) − 15 pF VICR Comparator Common Mode Input Voltage Range 0 Vdd −1.5 V ICC Maximum Quiescent Supply Current (per Package) − 5.0 mA COMPARATOR AC CHARACTERISTICS Guaranteed Limit Symbol Parameter Test Conditions Min Typ Max Unit tPD Maximum Propagation Delay Vref = 1.5 V, 10mV overdrive − 1.0 − S Vref = 1.5 V, 100mV overdrive − 0.2 − S
http://onsemi.com DA COMPARATOR CHARACTERISTICS Guaranteed Limit Symbol Parameter Min Typ Max Unit DNL DAC Referential NON−Linearity ±1/4 LSB eFS DAC Full Scale Error ±1 LSB eZC DAC Zero Scale Error ±1 LSB TIMING CHARACTERISTICS Guaranteed Limit Symbol Parameter Min Max Unit fCL SCL CLOCK Frequency 0 100 kHz tBUF BUS Free Time (Between “STOP” and “START”) 4.7 − s tHD:STA HOLD Time for “START” 4.0 − s tLOW HOLD Time at SCL CLOCK LOW 4.7 − s tHIGH HOLD Time at SCL CLOCK HI 4.0 − s tHD:DAT DATA HOLD Time 0 − s tSU:DAT DATA SETUP Time 250 − ns tR Rise Time (SDA and SCL) − 1000 ns tF Fall Time (SDA and SCL) − 300 ns tSU:STO SETUP Time for “STOP” 4.0 − s SDA SCL tBUF tLOW tR tF tHD:STA tHD:DAT tHIGH tSU:DAT tSU:STO
http://onsemi.com SDA SCL 1.) WRITE MODE (A) 2.) WRITE MODE (B) 3.) READ MODE (A) 4.) READ MODE (B) SDA SCL P0 − P7 I/O Expander (Slave Device) The JLC1562B Supports the following types of Bus Cycles SACKWrite Data (2)SACKWrite Data (1)SACKSlave Address & R/W PS SACKWrite Data (1)SACKSlave Address & R/W PS MACKRead DataSACKSlave Address & R/W PS Read Data (2)MACKRead Data (1)SACKSlave Address & R/WS MACK Read Data (3) MACK P S = START Condition SACK = Slave Acknowledgement MACK = Master Acknowledgement P = STOP Condition Micro Controller (Master Device) MODE READ WRITE SDA I/O Expander Master Device Slave Device I/O Port Receiver Transmitter Transmitter Receiver Input Output READ / WRITE MODES
http://onsemi.com ACKS 0 1 1 1 A2 A1 A0 1 ACK P D7 D6 D5 D4 D3 D2 D1 D0 ACKS 0 1 1 1 A2 A1 A0 0 ACK P D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0 <<READ MODE>> <<WRITE MODE>> Slave Address Read Data I/O Expander Device Address (Pins A0 − A2) 1 : READ ADDRESS A6 A5 A4 A3 0 1 1 1 is hard wired as A0 − A2 R/W A3 − A6 Slave Address Output of Comparator “A”. (Vth = 1/2 VDD ) Output of Comparator “B”. (Vth = 1/2 VDD OR V DAC ) READ LATCH Bit Controls when Data Will Be Latched. D5 − D7 D0 − D4 Read Data Slave Address Write Data (1) Write Data (2) I/O Expander Device Address (Pins A0 − A2) 0 : WRITE ADDRESS A6 A5 A4 A3 0 1 1 1 is hard wired as A0 − A2 R/W A3 − A6 Slave Address Device Pins P0 to P7 Output Bits.D0 − D7Write Data (1) READ LATCH CONTROLD7Write Data (2) Latch Control of Signals C0 − C4 in the Device BLOCK DIAGRAM COMPARATOR “B” V ref Control BitD6 0 : Data is latched at the ACK after a READ COMMAND. 1 : Data is latched when Comparator “B” switches from 0 to 1. (switch point is controlled by Vth.) 1 : Data is reset at the ACK after a READ COMMAND. DAC Input BitsD0 − D5 0:V ref 40 1:V ref V DAC READ WRITE DATA FORMAT
http://onsemi.com A0xxx1110S 9876543219 876543219 87654321 A A P DATA (I) valid DATA (II) valid <<WRITE MODE>> SCL SDA Write_buffer Latch Pulse I/O Port (P0 − P7) DAC Latch Pulse DAC Latch WRITE COMMAND DATA (I) DATA (II) A1xxx1110S 9876543219 87654321 A P DATA (I) <<READ MODE>> (READ LATCH = 0) SCL SDA PISO Load Pulse Comp_out (C0 − C4) Comp_out (C5 − C7) READ COMMAND DATA (I) + (II) DATA (II) A1xxx1110S 987654321 987654329 87654321 DATA (I) <<READ MODE>> (READ LATCH = 1) SCL SDA LATCH Reset Comp._out Latched Data PISO Load Pulse WRITE DATA (II) READ COMMAND DATA (I) PA1 PA DAC Latch D7 (READ LATCH Bit)
http://onsemi.com PACKAGE DIMENSIONS PDIP−16 N SUFFIX CASE 648−08 ISSUE T NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. −A− B F C S H G D J L M 16 PL SEATING 916 K PLANE−T− MAM0.25 (0.010) T DIM MIN MAX MIN MAX MILLIMETERSINCHES A 0.740 0.770 18.80 19.55 B 0.250 0.270 6.35 6.85 C 0.145 0.175 3.69 4.44 D 0.015 0.021 0.39 0.53 F 0.040 0.70 1.02 1.77 G 0.100 BSC 2.54 BSC H 0.050 BSC 1.27 BSC J 0.008 0.015 0.21 0.38 K 0.110 0.130 2.80 3.30 L 0.295 0.305 7.50 7.74 M 0 10 0 10 S 0.020 0.040 0.51 1.01
http://onsemi.com PACKAGE DIMENSIONS EIAJ−16 F SUFFIX CASE 966−01 ISSUE O H E A 1 DIM MIN MAX MIN MAX INCHES --- 2.05 --- 0.081 MILLIMETERS 0.05 0.20 0.002 0.008 0.35 0.50 0.014 0.020 0.18 0.27 0.007 0.011 9.90 10.50 0.390 0.413 5.10 5.45 0.201 0.215 1.27 BSC 0.050 BSC 7.40 8.20 0.291 0.323 0.50 0.85 0.020 0.033 1.10 1.50 0.043 0.059 0.70 0.90 0.028 0.035 --- 0.78 --- 0.031 A HE LE 10 0 10 LE Q 1 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). M L DETAIL P VIEW P c A b e 16 9 D Z E A b c D E e L M Z
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