JL555SGA

LM555JAN TI1 | Alldatasheet

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Technical content

Literature Number: SNOSAQ8B

September 27, 2010 Timer General Description The LM555 is a highly stable device for generating accurate time delays or oscillation. Additional terminals are provided for triggering or resetting if desired. In the time delay mode of operation, the time is precisely controlled by one external re- sistor and capacitor. For astable operation as an oscillator, the free running frequency and duty cycle are accurately con- trolled with two external resistors and one capacitor. The circuit may be triggered and reset on falling waveforms, and the output circuit can source or sink up to 200mA or drive TTL circuits.

Features

■ Direct replacement for SE555/NE555 ■ Timing from microseconds through hours ■ Operates in both astable and monostable modes ■ Adjustable duty cycle ■ Output can source or sink 200 mA ■ Output and supply TTL compatible ■ Temperature stability better than 0.005% per °C ■ Normally on and normally off output

Applications

■ Precision timing ■ Pulse generation ■ Sequential timing ■ Time delay generation ■ Pulse width modulation ■ Pulse position modulation ■ Linear ramp generator

Ordering Information

NS Part Number JAN Part Number NS Package Number Package Description JL555SPA JM38510/10901SPA J08A 8LD Ceramic Dip JL555SGA JM38510/10901SGA H08A 8LD Metal Can Connection Diagrams Dual-In-Line Package 20153703 Top View Metal Can Package 20153733 Top View © 2010 National Semiconductor Corporation 201537 www.national.com

201537 Version 3 Revision 1 Print Date/Time: 2010/10/01 00:30:58

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Absolute Maximum Ratings (Note 1) Supply Voltage +18V Discharge Current +200mA Output Sink Current +200mA Output Source Current −200mA Power Dissipation (Note 2) Metal Can 300mW @ +125°C CERDIP 370mW @ +125°C Operating Temperature Range −55°C ≤ TA ≤ +125°C Maximum Junction Temperature (TJmax) +175°C Storage Temperature Range −65°C ≤ TA ≤ +150°C Soldering Information (Soldering 10 Seconds) 300°C Thermal Resistance θJA CERDIP Still Air 123°C/W CERDIP 500LF / Min Air Flow 69°C/W Metal Can Still Air 171°C/W Metal Can 500LF / Min Air Flow 92°C/W θJC CERDIP 18°C/W Metal Can 41°C/W ESD Tolerance (Note 3) 1KV Recommended Operating Conditions Supply Voltage Range +4.5V to +16VDC Quality Conformance Inspection Mil-Std-883, Method 5005 - Group A Subgroup Description Temp °C

1 Static tests at 25

2 Static tests at 125

3 Static tests at -55

4 Dynamic tests at 25

5 Dynamic tests at 125

6 Dynamic tests at -55

7 Functional tests at 25

8A Functional tests at 125 8B Functional tests at -55

9 Switching tests at 25

10 Switching tests at 125

11 Switching tests at -55

12 Settling time at 25

13 Settling time at 125

14 Settling time at -55

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Electrical Characteristics

Symbol Parameter Conditions Notes Min Max Unit Sub- groups ICC Power Supply Current VCC = 4.5V 5.0 mA 1, 2, 3 VCC = 16.5V 20 mA 1, 2, 3 VTrig Trigger Voltage VCC = 4.5V 1.3 1.8 V 1 1.3 2.1 V 2 1.15 1.8 V 3 VCC = 16.5V 5.2 5.8 V 1 5.2 6.1 V 2 5.0 5.8 V 3 ITrig Trigger Current VCC = 16.5V -5.0 µA 1, 2, 3 VTh Threshold Voltage VCC = 4.5V 2.7 3.3 V 1 2.6 3.4 V 2, 3 VCC = 16.5V 10.7 11.3 V 1 10.6 11.4 V 2, 3 ITh Threshold Current VCC = 16.5V 250 nA 1, 2 2,500 nA 3 VOL Logical "0" Output Voltage VCC = 4.5V, ISink = 5mA 0.25 V 1

0.35 V 2, 3

VCC = 4.5V, ISink = 50mA 2.2 V 1, 2

2.6 V 3

VCC = 16.5V, ISink = 10mA 0.15 V 1, 3

0.25 V 2

VCC = 16.5V, ISink = 50mA 0.5 V 1, 3

0.7 V 2

VCC = 16.5V, ISink = 100mA 2.2 V 1

2.8 V 2, 3

VOH Logical "1" Output Voltage VCC = 4.5V, ISource = -100mA 2.6 V 1, 2

2.2 V 3

VCC = 16.5V, ISource = -100mA 14.6 V 1, 2

14 V 3

ICEX Discharge Transistor Leakage Current VCC = 16.5V 100 nA 1, 3 3,000 nA 2 VSat Discharge Transistor Saturation Voltage VCC = 16.5V 0.8 V 1, 3

1.0 V 2

VR Reset Voltage VCC = 16.5V (Note 4), (Note 5) 0.1 1.3 V 1, 2, 3 IR Reset Current VCC = 16.5V -1.6 mA 1, 2, 3 AC Parameters Symbol Parameter Conditions Notes Min Max Unit Sub- groups tPLH Propagation Delay Time VCC = 4.5V 800 nS 9, 11 900 nS 10 VCC = 16.5V 800 nS 9, 11 900 nS 10 www.national.com 4

Symbol Parameter Conditions Notes Min Max Unit Sub- groups tPHL Propagation Delay Time VCC = 4.5V 12 µS 9, 10, 11 VCC = 16.5V 12 µS 9, 10, 11 tTLH Transition Time VCC = 4.5V 300 nS 9, 10, 11 VCC = 16.5V 300 nS 9, 10, 11 tTHL Transition Time VCC = 4.5V 300 nS 9, 10, 11 VCC = 16.5V 300 nS 9, 10, 11 tDOH Time Delay Output High RT = 1KΩ VCC = 4.5V 106.7 113.3 µS 9, 10, 11 VCC = 16.5V 106.7 113.3 µS 9, 10, 11 Time Delay Output High RT = 100KΩ VCC = 4.5V 10.67 11.33 mS 9, 10, 11 VCC = 16.5V 10.67 11.33 mS 9, 10, 11 ΔtD / ΔVCC Drift In Time Delay ΔVCC = 12, VCC = 4.5V to 16.5V (Note 6) -220 220 nS/V 9 ΔtD / ΔT Temperature Coefficient of Time Delay VCC = 16.5V -11 11 nS/°C 10, 11 tCh Capacitor Charge Time RT = 1KΩ VCC = 4.5V 120 156 µS 9, 10, 11 VCC = 16.5V 120 156 µS 9, 10, 11 Capacitor Charge Time RT = 100KΩ VCC = 4.5V 11.3 15 mS 9, 10, 11 VCC = 16.5V 11.3 15 mS 9, 10, 11 tDis Capacitor Discharge Time RT = 1KΩ VCC = 4.5V 57.5 80 µS 9, 10, 11 VCC = 16.5V 57.5 80 µS 9, 10, 11 Capacitor Discharge Time RT = 100KΩ VCC = 4.5V 5.4 7.7 mS 9, 10, 11 VCC = 16.5V 5.4 7.7 mS 9, 10, 11 ΔtCh / ΔVCC Drift In Capacitor Charge Time ΔVCC = 12, VCC = 4.5V to 16.5V -820 820 nS/V 9 ΔtCh / ΔT Temperature Coefficient Capacitor Charge Time VCC = 16.5V (Note 6) -68 68 nS/°C 10, 11 tRes Reset Time VCC = 16.5V 1.5 µS 9, 11 2.0 µS 10 DC Drift Parameters Delta calculations performed on JAN S devices at Group B, Subgroup 5, only. Symbol Parameter Conditions Notes Min Max Unit Sub- groups VTrig Trigger Voltage VCC = 16.5V -0.05 0.05 V 1 VTh Threshold Voltage VCC = 16.5V -0.05 0.05 V 1 VOL Logical "0" Output Voltage VCC = 16.5V, ISink = 10mA -0.05 0.05 V 1 ICEX Discharge Transistor Leakage Current VCC = 16.5V -50 50 nA 1 Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Note 2: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax (maximum junction temperature), θJA (package junction to ambient thermal resistance), and TA (ambient temperature). The maximum allowable power dissipation at any temperature is PDmax = (TJmax - TA)/ θJA or the number given in the Absolute Maximum Ratings, whichever is lower. Note 3: Human body model, 1.5KΩ in series with 100pF. Note 4: Parameter tested go-no-go, only. Note 5: Datalog reading of 0.7V will reflect the Reset Voltage levels passing and a reading of 0.5V or 1.5V reflects the Reset voltage levels failing the low level or high level respectfully. Note 6: Calculated parameter. 5 www.national.com

Typical Performance Characteristics Minimum Pulse Width Required for Triggering 20153704 Supply Current vs. Supply Voltage 20153719 High Output Voltage vs. Output Source Current 20153720 Low Output Voltage vs. Output Sink Current 20153721 Low Output Voltage vs. Output Sink Current 20153722 Low Output Voltage vs. Output Sink Current 20153723 www.national.com 6

Output Propagation Delay vs. Voltage Level of Trigger Pulse 20153724 Output Propagation Delay vs. Voltage Level of Trigger Pulse 20153725 Discharge Transistor (Pin 7) Voltage vs. Sink Current 20153726 Discharge Transistor (Pin 7) Voltage vs. Sink Current 20153727 7 www.national.com

FIGURE 1. Monostable VCC = 5V Top Trace: Input 5V/Div. TIME = 0.1 ms/DIV. Middle Trace: Output 5V/Div. RA = 9.1kΩ Bottom Trace: Capacitor Voltage 2V/Div. FIGURE 2. Monostable Waveforms state until a trigger pulse is again applied. high before the end of timing cycle. FIGURE 3. Time Delay connected) it will trigger itself and free run as a multivibrator. by the ratio of these two resistors. FIGURE 4. Astable quency are independent of the supply voltage.

VCC = 5V Top Trace: Output 5V/Div. TIME = 20μs/DIV. Bottom Trace: Capacitor Voltage 1V/Div. FIGURE 5. Astable Waveforms FIGURE 6. Free Running Frequency shows the waveforms generated in a divide by three circuit. VCC = 5V Top Trace: Input 4V/Div. TIME = 20μs/DIV. Middle Trace: Output 2V/Div. RA = 9.1kΩ Bottom Trace: Capacitor 2V/Div. FIGURE 7. Frequency Divider the circuit, and in Figure 9 are some waveform examples. FIGURE 8. Pulse Width Modulator VCC = 5V Top Trace: Modulation 1V/Div. TIME = 0.2 ms/DIV. Bottom Trace: Output Voltage 2V/Div. FIGURE 9. Pulse Width Modulator

erated for a triangle wave modulation signal. FIGURE 10. Pulse Position Modulator VCC = 5V Top Trace: Modulation Input 1V/Div. TIME = 0.1 ms/DIV. Bottom Trace: Output 2V/Div. FIGURE 11. Pulse Position Modulator Figure 13 shows waveforms generated by the linear ramp. VCC = 5V Top Trace: Input 3V/Div. TIME = 20μs/DIV. Middle Trace: Output 5V/Div. R1 = 47kΩ Bottom Trace: Capacitor Voltage 1V/Div. FIGURE 13. Linear Ramp

FIGURE 14. 50% Duty Cycle Oscillator to 1/3 VCC and trigger the lower comparator. allel with 1μF electrolytic. monostable pulse width to 10μs minimum. pulse width must be 0.3μs, typical.

Revision History

Date Released Revision Section Changes 08/04/05 A New Release to corporate format 1 MDS datasheet converted into corporate format. MJLM555-X Rev 1A0 to be archived 07/25/06 B Applications Information, page 8 Correct a typo in the paragraph after figure 1 (change the word internal to interval) to reflect same change made to Commercial data sheet. Revision A will be Archived. 09/27/2010 C Obsolete Data Sheet End Of Life on Product/NSID Sept. 1998 www.national.com 12

Physical Dimensions inches (millimeters) unless otherwise noted 8LD Ceramic Dip Package (J) 13 www.national.com

8LD Metal Can Package (H) www.national.com 14

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201537 Version 3 Revision 1 Print Date/Time: 2010/10/01 00:30:59

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