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LF198JAN Monolithic Sample-and-Hold Circuits Literature Number: SNOSAJ2
Monolithic Sample-and-Hold Circuits General Description The LF198 is a monolithic sample-and-hold circuit which utilizes BI-FET technology to obtain ultra-high dc accuracy with fast acquisition of signal and low droop rate. Operating as a unity gain follower, dc gain accuracy is 0.002% typical and acquisition time is as low as 6 µs to 0.01%. A bipolar input stage is used to achieve low offset voltage and wide bandwidth. Input offset adjust is accomplished with a single pin, and does not degrade input offset drift. The wide band- width allows the LF198 to be included inside the feedback loop of 1 MHz op amps without having stability problems. Input impedance of 10 10Ω allows high source impedances to be used without degrading accuracy. P-channel junction FET’s are combined with bipolar devices in the output amplifier to give droop rates as low as 5 mV/min w i t ha1µ F hold capacitor. The JFET’s have much lower noise than MOS devices used in previous designs and do not exhibit high temperature instabilities. The overall design guarantees no feed-through from input to output in the hold mode, even for input signals equal to the supply voltages.
Features
n Operates from ±5V to ±18V supplies n Less than 10 µs acquisition time n TTL, PMOS, CMOS compatible logic input n 0.5 mV typical hold step at C h = 0.01 µF n Low input offset n 0.002% gain accuracy n Low output noise in hold mode n Input characteristics do not change during hold mode n High supply rejection ratio in sample or hold n Wide bandwidth n Space Qualified Logic inputs on the LF198 are fully differential with low input current, allowing direct connection to TTL, PMOS, and CMOS. Differential threshold is 1.4V. The LF198 will operate from ±5V to ±18V supplies.
Ordering Information
NSC Part Number JAN Part Number NSC Package Number Package Description JL198BGA JM38510/12501BGA H08C 8LD Metal Can JL198SGA JM38510/12501SGA H08C 8LD Metal Can Connection Diagrams Metal Can Package 20128114 See NS Package Number H08C February 2005 LF198JAN Monolithic Sample-and-Hold Circuits © 2005 National Semiconductor Corporation DS201281 www.national.com
Typical Connection and Performance Curve Acquisition Time 20128132 20128116 Functional Diagram 20128101 LF198JAN www.national.com 2
Absolute Maximum Ratings(Note 1) Supply Voltage ±18V Power Dissipation (Package Limitation) (Note 2) 500 mW Operating Ambient Temperature Range −55˚C ≤T A ≤ +125˚C Storage Temperature Range −65˚C to +150˚C Maximum Junction Temperature (T Jmax) +150˚C Input Voltage Equal to Supply Voltage Logic To Logic Reference Differential Voltage (Note 3) +7V, −30V Output Short Circuit Duration Indefinite Hold Capacitor Short Circuit Duration 10 sec Lead Temperature (Soldering, 10 sec.) 300˚C Thermal Resistance θ JA Metal Can (Still Air @ 0.5W) 160˚C/W Metal Can (500 LF/Min Air Flow @ 0.5W) 84˚C/W θJC Metal Can 48˚C/W ESD Tolerance (Note 7) 500V Quality Conformance Inspection Mil-Std-883, Method 5005 — Group A Subgroup Description Temperature (˚C)
1 Static tests at +25˚C
2 Static tests at +125˚C
3 Static tests at −55˚C
4 Dynamic tests at +25˚C
5 Dynamic tests at +125˚C
6 Dynamic tests at −55˚C
7 Functional tests at +25˚C
8A Functional tests at +125˚C 8B Functional tests at −55˚C
9 Switching tests at +25˚C
10 Switching tests at +125˚C
11 Switching tests at −55˚C
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Electrical Characteristics
Symbol Parameter Conditions Notes Min Max Unit Sub- groups VIO Input Offset Voltage +VCC = 3.5V, -VCC = -26.5V, VCM = 11.5V -3.0 3.0 mV 1 -5.0 5.0 mV 2, 3 +VCC = 26.5V, -VCC = -3.5V, VCM = -11.5V -3.0 3.0 mV 1 -5.0 5.0 mV 2, 3 +VCC = 15V, -VCC = -15V, VCM =0 V -3.0 3.0 mV 1 -5.0 5.0 mV 2, 3 +VCC = 7V, -VCC = -3V, VCM =2 V -3.0 3.0 mV 1 -5.0 5.0 mV 2, 3 +VCC = 3V, -VCC = -7V, VCM = -2V -3.0 3.0 mV 1 -5.0 5.0 mV 2, 3 IIB Input Bias Current +VCC = 3.5V, -VCC = -26.5V, VCM = 11.5V -1.0 25 nA 1 -25 75 nA 2, 3 +VCC = 26.5V, -VCC = -3.5V,VCM = -11.5V -1.0 25 nA 1 -25 75 nA 2, 3 +VCC = 15V, -VCC = -15V, VCM =0 V -1 25 nA 1 -25 75 nA 2, 3 +VCC = 7V, -VCC = -3V, VCM =2 V -1 25 nA 1 -25 75 nA 2, 3 +VCC = 3V, -VCC = -7V, VCM = -2V -1.0 25 nA 1 -25 75 nA 2, 3 ZI Input Impedance +V CC = 3.5V to 26.6V, -VCC = -26.5V to -3.5V, VCM = 11.5V to -11.5V
2.0 G Ω 1
1.0 G Ω 2, 3
VIO Adj+ Input Offset Voltage Adjustment +V CC = 15V, -VCC = -15V, VCM =0 V 6.0 mV 1, 2, 3 VIO Adj- Input Offset Voltage Adjustment +V CC = 15V, -VCC = -15V, VCM =0 V -6.0 mV 1, 2, 3 PSRR+ Power Supply Rejection Ratio -V CC = -18V, +VCC = 18V to 12V 80 dB 1, 2, 3 PSRR- Power Supply Rejection Ratio +V CC = 18V, -VCC = -12V to -18V 80 dB 1, 2, 3 ICC Supply Current +VCC = 15V, -VCC = -15V, VCM =0 V 1.0 5.5 mA 1,2 1.0 6.5 mA 3 AE Gain Error +V CC = 3.5V to 26.5V, -VCC = -26.5V to -3.5V, VCM = -11.5V to 11.5V -0.005 0.005 % 1 -0.02 0.02 % 2, 3 +VCC =3 Vt o7 V , -VCC = -7V to -3V, VCM = -2V to 2V -0.02 0.02 % 1 -0.04 0.04 % 2, 3 RSC Series Charge Resistance +V CC = 15V, -VCC = -15V, VCM =0 V 75 400 Ω 1, 2, 3 IIH (a) Logical 1 Input Current +V CC = 8.5V, -VCC = -21.5V 0 10 µA 1, 2, 3 IIH (b) Logical 1 Input Current +V CC = 8.5V, -VCC = -21.5V 0 10 µA 1, 2, 3 IIL (a) Logical 0 Input Current +V CC = 21.5V, -VCC = -8.5V -1.0 1.0 µA 1, 2, 3 IIL (b) Logical 0 Input Current +V CC = 21.5V, -VCC = -8.5V -1.0 1.0 µA 1, 2, 3 IOS+ Output Short Circuit Current +V CC = 15V, -VCC = -15V, VCM =0 V -25 mA 1, 2, 3 LF198JAN www.national.com 4
Electrical Characteristics (Continued) DC Parameters (Continued) Symbol Parameter Conditions Notes Min Max Unit Sub- groups IOS- Output Short Circuit Current +V CC = 15V, -VCC = -15V, VCM =0 V 25 mA 1, 2, 3 ICH+ Hold Capacitor Charge Current +VCC = 15V, -VCC = -15V, VCM =0 V -3.0 mA 1 -2.0 mA 2, 3 ICH- Hold Capacitor Charge Current +VCC = 15V, -VCC = -15V, VCM =0 V 3.0 mA 1 2.0 mA 2, 3 VTh(H) Differential Logic Threshold +V CC = 15V, -VCC = -15V, VCM =0 V Logic = 2.0V, Logic Ref = 2.0V 1.0 mA 1, 2, 3 VTh(L) Differential Logic Threshold +V CC = 15V, -VCC = -15V, VCM =0 V Logic = 0.8V, Logic Ref = 2.0V -10 10 µA 1, 2, 3 IHL+ Hold Mode Leakage Current +VCC = 3.5V, -VCC = -26.5V, VCM = -11.5V (Note 5) -0.100 0.100 nA 1 -50 50 nA 2 IHL- Hold Mode Leakage Current +VCC = 26.5V, -V CC = -3.5V, VCM = 11.5V (Note 5) -0.100 0.100 nA 1 -50 50 nA 2 ZO Output Impedance +V CC = 15V, -VCC = -15V, VCM =0 V 2.0 Ω 1, 2, 3 VHS (HOLD) Step Voltage +VCC = 3.5V, -V CC = -26.5V, VCM = 11.5V (Note 4) -2.0 2.0 mV 1 -5.0 5.0 mV 2, 3 +VCC = 26.5V, -V CC = -3.5V, VCM = -11.5V (Note 4) -2.0 2.0 mV 1 -5.0 5.0 mV 2, 3 FRR Feedthrough Rejection Ratio +VCC = 15V, -VCC = -15V, VCM = 0V, VI = 0V to 11.5V 86 dB 1 80 dB 2, 3 +VCC = 15V, -VCC = -15V, VCM = 0V, VI = 11.5V to 0V 86 dB 1 80 dB 2, 3 +VCC = 15V, -VCC = -15V, VCM = 0V, VI = 0V to -11.5V 86 dB 1 80 dB 2, 3 +VCC = 15V, -VCC = -15V, VCM = 0V, VI = -11.5V to 0V 86 dB 1 80 dB 2, 3 AC/DC Parameters Symbol Parameter Conditions Notes Min Max Unit Sub- groups Delta VIO / Delta T Input Offset Voltage Temp Sensitivity -20 20 µV/˚C 8A, 8B TAQ Aquisition Time +V CC = 15V, -VCC = -15V 25 µS 7 TAP Aperture Time +V CC = 15V, -VCC = -15V 300 nS 7 TS Settling Time +V CC = 15V, -VCC = -15V 1.5 µS 7 FRR AC Feedthrough Rejection Ratio +V CC = 15V, -VCC = -15V, VI = 20Vpp 86 dB 7 TRTS Transient Response (settling time) +VCC = 3.5V, -VCC = -26.5V, VI = 100mV pulse 2.5 µS 7 +VCC = 26.5V, -VCC = -3.5V, VI = 100mV pulse 2.5 µS 7 LF198JAN www.national.com5
AC/DC Parameters (Continued) Symbol Parameter Conditions Notes Min Max Unit Sub- groups TROS Transient Response (overshoot) +VCC = 3.5V, -VCC = -26.5V, VI = 100mV pulse 40 % 7 +VCC = 26.5V, -VCC = -3.5V, VI = 100mV pulse 40 % 7 enH Noise +V CC = 15V, -VCC = -15V 10 mV RMS 7 enS Noise +V CC = 15V, -VCC = -15V 10 mV RMS 7 DC Parameters: Drift Values Delta calculations performed on S-Level devices at group B, subgroup 5 ONLY. Symbol Parameters Conditions Notes Min Max Unit Sub- groups VIO Input Offset Voltage +V CC = 15V, -VCC = -15V, VCM =0 V -0.5 0.5 mV 1 IIB Input Bias Current +V CC = 15V, -VCC = -15V, VCM =0 V -2.5 2.5 nA 1 Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device i s functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characterist ics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the lis ted test conditions Note 2: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, θJA, and the ambient temperature, TA. The maximum allowable power dissipation at any temperature is P D =( TJMAX −T A)/θJA, or the number given in the Absolute Maximum Ratings, whichever is lower. . Note 3: Although the differential voltage may not exceed the limits given, the common-mode voltage on the logic pins may be equal to the supply voltages withou t causing damage to the circuit. For proper logic operation, however, one of the logic pins must always be at least 2V below the positive supply and 3V abov e the negative supply. Note 4: Hold step is sensitive to stray capacitive coupling between input logic signals and the hold capacitor. 1 pF, for instance, will create an additional 0.5 mV step with a 5V logic swing and a 0.01µF hold capacitor. Magnitude of the hold step is inversely proportional to hold capacitor value. Note 5: Leakage current is measured at a junction temperature of 25˚C. The effects of junction temperature rise due to power dissipation or elevated ambient can be calculated by doubling the 25˚C value for each 11˚C increase in chip temperature. Leakage is guaranteed over full input signal range. Note 6: See Definition of Terms Note 7: Human body model, 100pF discharged through 1.5K Ω Typical Performance Characteristics Aperture Time (Note 6) Dielectric Absorption Error in Hold Capacitor 20128117 20128118 LF198JAN www.national.com 6
Typical Performance Characteristics (Continued) Dynamic Sampling Error (Note 6) Output Droop Rate 20128119 20128120 Hold Step (Note 6) “Hold” Settling Time (Note 6) 20128121 20128122 Leakage Current into Hold Capacitor Phase and Gain (Input to Output, Small Signal) 20128123 20128124 LF198JAN www.national.com7
Typical Performance Characteristics (Continued) Gain Error Power Supply Rejection 20128125 20128126 Output Short Circuit Current Output Noise 20128127 20128128 Note 8: See Definition Input Bias Current Feedthrough Rejection Ratio (Hold Mode) 20128129 20128130 LF198JAN www.national.com 8
Typical Performance Characteristics (Continued) Hold Step vs Input Voltage Output Transient at Start of Sample Mode 20128131 20128112 Output Transient at Start of Hold Mode 20128113 Logic Input Configurations TTL & CMOS 3V ≤ V LOGIC (Hi State) ≤ 7V 20128133 Threshold = 1.4V 20128134 Threshold = 1.4V*Select for 2.8V at pin 8 LF198JAN www.national.com9
Logic Input Configurations (Continued) CMOS 7V ≤ VLOGIC (Hi State) ≤ 15V 20128135 Threshold = 0.6 (V +) + 1.4V 20128136 Threshold = 0.6 (V +) − 1.4V Op Amp Drive 20128137 Threshold ≈ +4V 20128138 Threshold = −4V Application Hints HOLD CAPACITOR Hold step, acquisition time, and droop rate are the major trade-offs in the selection of a hold capacitor value. Size and cost may also become important for larger values. Use of the curves included with this data sheet should be helpful in selecting a reasonable value of capacitance. Keep in mind that for fast repetition rates or tracking fast signals, the capacitor drive currents may cause a significant temperature rise in the LF198. A significant source of error in an accurate sample and hold circuit is dielectric absorption in the hold capacitor. A mylar cap, for instance, may “sag back” up to 0.2% after a quick change in voltage. A long sample time is required before the circuit can be put back into the hold mode with this type of capacitor. Dielectrics with very low hysteresis are polysty- rene, polypropylene, and Teflon. Other types such as mica and polycarbonate are not nearly as good. The advantage of polypropylene over polystyrene is that it extends the maxi- mum ambient temperature from 85˚C to 100˚C. Most ce- ramic capacitors are unusable with > 1% hysteresis. Ce- ramic “NPO” or “COG” capacitors are now available for 125˚C operation and also have low dielectric absorption. For more exact data, see the curve Dielectric Absorption Error. The hysteresis numbers on the curve are final values, taken after full relaxation. The hysteresis error can be significantly reduced if the output of the LF198 is digitized quickly after the hold mode is initiated. The hysteresis relaxation time constant in polypropylene, for instance, is 10 — 50 ms. If A-to-D conversion can be made within 1 ms, hysteresis error will be reduced by a factor of ten. DC AND AC ZEROING DC zeroing is accomplished by connecting the offset adjust pin to the wiper o fa1k Ω potentiometer which has one end tied to V + and the other end tied through a resistor to ground. The resistor should be selected to give ≈0.6 mA through the 1k potentiometer. AC zeroing (hold step zeroing) can be obtained by adding an inverter with the adjustment pot tied input to output. A 10 pF capacitor from the wiper to the hold capacitor will give ±4m V hold step adjustment with a 0.01 µF hold capacitor and 5V logic supply. For larger logic swings, a smaller capacitor < 10 pF) may be used. LOGIC RISE TIME For proper operation, logic signals into the LF198 must have a minimum dV/dt of 1.0 V/µs. Slower signals will cause excessive hold step. If a R/C network is used in front of the LF198JAN www.national.com 10
Application Hints (Continued) logic input for signal delay, calculate the slope of the wave- form at the threshold point to ensure that it is at least 1.0 V/µs. SAMPLING DYNAMIC SIGNALS Sample error to moving input signals probably causes more confusion among sample-and-hold users than any other pa- rameter. The primary reason for this is that many users make the assumption that the sample and hold amplifier is truly locked on to the input signal while in the sample mode. In actuality, there are finite phase delays through the circuit creating an input-output differential for fast moving signals. In addition, although the output may have settled, the hold capacitor has an additional lag due to the 300 Ω series resistor on the chip. This means that at the moment the “hold” command arrives, the hold capacitor voltage may be somewhat different than the actual analog input. The effect of these delays is opposite to the effect created by delays in the logic which switches the circuit from sample to hold. For example, consider an analog input of 20 Vp-p at 10 kHz. Maximum dV/dt is 0.6 V/µs. With no analog phase delay and 100 ns logic delay, one could expect up to (0.1 µs) (0.6V/µs) = 60 mVerror if the “hold” signal arrived near maximum dV/dt of the input. A positive-going input would give a +60 mV error. Now assume a 1 MHz (3 dB) bandwidth for the overall analog loop. This generates a phase delay of 160 ns. If the hold capacitor sees this exact delay, then error due to analog delay will be (0.16 µs) (0.6 V/µs) = −96 mV. Total output error is +60 mV (digital) −96 mV (analog) for a total of −36 mV. To add to the confusion, analog delay is proportioned to hold capacitor value while digital delay remains constant. A family of curves (dynamic sampling error) is included to help esti- mate errors. A curve labeled Aperture Time has been included for sam- pling conditions where the input is steady during the sam- pling period, but may experience a sudden change nearly coincident with the “hold” command. This curve is based on a 1 mV error fed into the output. A second curve, Hold Settling Time indicates the time re- quired for the output to settle to 1 mV after the “hold” command. DIGITAL FEEDTHROUGH Fast rise time logic signals can cause hold errors by feeding externally into the analog input at the same time the amplifier is put into the hold mode. To minimize this problem, board layout should keep logic lines as far as possible from the analog input and the C h pin. Grounded guarding traces may also be used around the input line, especially if it is driven from a high impedance source. Reducing high amplitude logic signals to 2.5V will also help. Guarding Technique 20128105 Use 10-pin layout. Guard around Chis tied to output. LF198JAN www.national.com11
X1000 Sample & Hold Sample and Difference Circuit (Output Follows Input inHold Mode) 20128139 *For lower gains, the LM108 must be frequency compensated 20128140 VOUT =V B + ∆VIN(HOLD MODE) Ramp Generator with Variable Reset Level Integrator with Programmable Reset Level 20128142 20128143 LF198JAN www.national.com 12
Typical Applications (Continued) Output Holds at Average of Sampled Input Increased Slew Current 20128146 20128147 Reset Stabilized Amplifier (Gain of 1000) Fast Acquisition, Low Droop Sample & Hold 20128149 20128150 LF198JAN www.national.com13
Typical Applications (Continued) Synchronous Correlator for Recovering Signals Below Noise Level 2–Channel Switch 20128152 20128153 AB ZIN 1010Ω 47 kΩ BW . 1 MHz . 400 kHz Crosstalk −90 dB −90 dB @ 1 kHz Offset ≤ 6m V ≤ 75 mV DC & AC Zeroing Staircase Generator 20128159 20128155 *Select for step height 50k → ≅ 1V Step LF198JAN www.national.com 14
Typical Applications (Continued) Differential Hold Capacitor Hysteresis Compensation 20128157 20128156 **Adjust for amplitude Definition of Terms Hold Step:The voltage step at the output of the sample and hold when switching from sample mode to hold mode with a steady (dc) analog input voltage. Logic swing is 5V. Acquisition Time:The time required to acquire a new ana- log input voltage with an output step of 10V. Note that acquisition time is not just the time required for the output to settle, but also includes the time required for all internal nodes to settle so that the output assumes the proper value when switched to the hold mode. Gain Error: The ratio of output voltage swing to input volt- age swing in the sample mode expressed as a per cent difference. Hold Settling Time: The time required for the output to settle within 1 mV of final value after the “hold” logic com- mand. Dynamic Sampling Error: The error introduced into the held output due to a changing analog input at the time the hold command is given. Error is expressed in mV with a given hold capacitor value and input slew rate. Note that this error term occurs even for long sample times. Aperture Time: The delay required between “Hold” com- mand and an input analog transition, so that the transition does not affect the held output. LF198JAN www.national.com15
Revision Section Originator Changes 02/25/05 A New release, Corporate format L. Lytle 1 MDS converted to corp. datasheet format. MJLF198–X Rev 2B0 MDS to be archived. LF198JAN www.national.com 16
Physical Dimensions inches (millimeters) unless otherwise noted Metal Can Package (H) National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. For the most current product information visit us at www.national.com. LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. BANNED SUBSTANCE COMPLIANCE National Semiconductor manufactures products and uses packing materials that meet the provisions of the Customer Products Stewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification (CSP-9-111S2) and contain no ‘‘Banned Substances’’ as defined in CSP-9-111S2. National Semiconductor Americas Customer Support Center Email: new.feedback@nsc.com Tel: 1-800-272-9959 National Semiconductor Europe Customer Support Center Fax: +49 (0) 180-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 National Semiconductor Asia Pacific Customer Support Center Email: ap.support@nsc.com National Semiconductor Japan Customer Support Center Fax: 81-3-5639-7507 Email: jpn.feedback@nsc.com Tel: 81-3-5639-7560 www.national.com LF198JAN Monolithic Sample-and-Hold Circuits
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