LM193JAN NSC | Alldatasheet
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Technical content
Features
— Voltage range: 5.0VDC to 36VDC — Single or dual supplies: ±2.5VDC to ±18VDC n Very low supply current drain (0.4 mA) — independent of supply voltage n Low input biasing current: 25 nA typ n Low input offset current: ±3 nA typ n Maximum offset voltage +5mV Max @ 25˚C n Input common-mode voltage range includes ground n Differential input voltage range equal to the power supply voltage n Low output saturation voltage,: 250 mV at 4 mA typ n Output voltage compatible with TTL, DTL, ECL, MOS and CMOS logic systems
Ordering Information
Non-Inverting Comparator with Hysteresis 20143238 20143209 May 2005 LM193JAN Low Power Low Offset Voltage Dual Comparators © 2005 National Semiconductor Corporation DS201432 www.national.com
Schematic and Connection Diagrams 20143202 Metal Can Package 20143203 Dual-In-Line Package 20143201 LM193JAN www.national.com
Absolute Maximum Ratings (Note 1) Supply Voltage, V+ 36VDC or ±18VDC Differential Input Voltage (Note 5) 36V Output Voltage 36V Input Voltage −0.3VDC to +36VDC Input Current (VIN< −0.3VDC) (Note 4) 50 mA Power Dissipation (Note 2), CERDIP 400 mW @ TA = 125˚C Metal Can 330 mW @ TA = 125˚C Maximum Junction Temperature (TJmax 175˚C Output Short-Circuit to Ground (Note 3) Continuous Operating Temperature Range Storage Temperature Range Thermal Resistance θJA Metal Can (Still Air) 174˚C/W Metal Can (500LF/Min Air flow) 99˚C/W CERDIP (Still Air) 146˚C/W CERDIP (500LF/Min Air flow) 85˚C/W θJC Metal Can 44˚C/W CERDIP 33˚C/W Lead Temperature (Soldering, 10 seconds) 260˚C ESD Tolerance (Note 6) 500V Quality Conformance Inspection Mil-Std-883, Method 5005 - Group A Subgroup
Description
Temp˚C Static tests at Static tests at 125 Static tests at -55 Dynamic tests at Dynamic tests at 125 Dynamic tests at -55 Functional tests at Functional tests at 125 Functional tests at -55 Switching tests at Switching tests at 125 Switching tests at -55 Settling time at Settling time at 125 Settling time at -55 LM193JAN www.national.com
+VCC = 30V, -VCC = 0V, VO = 15V -5.0 5.0 mV -7.0 7.0 mV 2, 3 +VCC = 2V, -VCC = -28V, VO = -13V -5.0 5.0 mV -7.0 7.0 mV 2, 3 +VCC = 5V, -VCC = 0V, VO = 1.4V -5.0 5.0 mV -7.0 7.0 mV 2, 3 +VCC = 2V, -VCC = -3V, VO = -1.6V -5.0 5.0 mV -7.0 7.0 mV 2, 3 IIO Input offset Current +VCC = 30V, -VCC = 0V, VO = 15V, RS = 20KΩ (Note 7) -25 nA 1, 2 (Note 7) -75 nA +VCC = 2V, -VCC = -28V, VO = -13V, RS = 20KΩ (Note 7) -25 nA 1, 2 (Note 7) -75 nA +VCC = 5V, -VCC = 0V, VO = 1.4V, RS = 20KΩ (Note 7) -25 nA 1, 2 (Note 7) -75 nA +VCC = 2V, -VCC = -3V, VO = -1.6V, RS = 20KΩ (Note 7) -25 nA 1, 2 (Note 7) -75 nA ±IIB Input Bias Current +VCC = 30V, -VCC = 0V, VO = 15V, RS = 20KΩ (Note 7) -100 +0.1 nA 1, 2 (Note 7) -200 +0.1 nA +VCC = 2V, -VCC = -28V, VO = -13V, RS = 20KΩ (Note 7) -100 +0.1 nA 1, 2 (Note 7) -200 +0.1 nA +VCC = 5V, -VCC = 0V, VO = 1.4V, RS = 20KΩ (Note 7) -100 +0.1 nA 1, 2 (Note 7) -200 +0.1 nA +VCC = 2V, -VCC = -3V, VO = -1.6V, RS = 20KΩ (Note 7) -100 +0.1 nA 1, 2 (Note 7) -200 +0.1 nA CMRR Input Voltage Common Mode Rejection 2V ≤+VCC ≤30V, -28V ≤-VCC ≤0V, -13V ≤VO ≤15V dB 1, 2, 3 2V ≤+VCC ≤5V, -3V ≤-VCC ≤0V, -1.6V ≤VO ≤1.4V dB 1, 2, 3 ICEX Output Leakage Current +VCC = 30V, -VCC = 0V, VO = +30V 1.0 µA 1, 2, 3 +IIL Input Leakage Current +VCC = 36V, -VCC = 0V, +VI = 34V, -VI = 0V -500 500 nA 1, 2, 3 -IIL Input Leakage Current +VCC = 36V, -VCC = 0V, +VI = 0V, -VI = 34V -500 500 nA 1, 2, 3 VOL Logical "0" Output Voltage +VCC = 4.5V, -VCC = 0V, IO = 4mA 0.4 V 0.7 V 2, 3 +VCC = 4.5V, -VCC = 0V, IO = 8mA 1.5 V 2.0 V 2, 3 ICC Power Supply Current +VCC = 5V, -VCC = 0V, VID = 15mV 2.0 mA 1, 2 3.0 mA +VCC = 30V, -VCC = 0V, VID = 15mV 3.0 mA 1, 2 4.0 mA ∆IO / ∆T Temperature Coefficient of Input Offset Voltage 25˚C ≤TA ≤+125˚C (Note 9) -25 µV/˚C -55˚C ≤TA ≤25˚C (Note 9) -25 µV/˚C LM193JAN www.national.com
(Continued) DC Parameters (Continued) Symbol Parameter Conditions Notes Min Max Unit Sub- groups ∆IIO / ∆T Temperature Coefficient of Input Offset Current 25˚C ≤TA ≤+125˚C (Note 9) -300 300 pA/˚C -55˚C ≤TA ≤25˚C (Note 9) -400 400 pA/˚C AVS Open Loop Voltage Gain +VCC = 15V, -VCC = 0V, RL = 15KΩ, 1V ≤VO ≤11V (Note 8) V/mV (Note 8) V/mV 5, 6 VLat Voltage Latch (Logical "1" Input) +VCC = 5V, -VCC = 0V, VI = 10V, IO = 4mA 0.4 V AC Parameters The following conditions apply, unless otherwise specified. +VCC = 5V, −VCC = 0V Symbol Parameter Conditions Notes Min Max Unit Sub- groups tRLH Response Time VI = 100mV, RL = 5.1KΩ, VOD = 5mV 5.0 µS 7, 8B 7.0 µS VI = 100mV, RL = 5.1KΩ, VOD = 50mV 0.8 µS 7, 8B 1.2 µS tRHL Response Time VI = 100mV, RL = 5.1KΩ, VOD = 5mV 2.5 µS 7, 8B 3.0 µS VI = 100mV, RL = 5.1KΩ, VOD = 50mV 0.8 µS 7, 8B 1.0 µS CS Channel Separation +VCC = 20V, -VCC = -10V, A to B dB +VCC = 20V, -VCC = -10V, B to A dB Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Note 2: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax (maximum junction temperature), θJA (package junction to ambient thermal resistance), and TA (ambient temperature). The maximum allowable power dissipation at any temperature is PDmax = (TJmax - TA)/θJA or the number given in the Absolute Maximum Ratings, whichever is lower. Note 3: Short circuits from the output to V+ can cause excessive heating and eventual destruction. When considering short circuits to ground, the maximum output current is approximately 20 mA independent of the magnitude of V+. Note 4: This input current will only exist when the voltage at any of the input leads is driven negative. It is due to the collector-base junction of the input PNP transistors becoming forward biased and thereby acting as input diode clamps. In addition to this diode action, there is also lateral NPN parasitic transistor action on the IC chip. This transistor action can cause the output voltages of the comparators to go to the V+ voltage level (or to ground for a large overdrive) for the time duration that an input is driven negative. This is not destructive and normal output states will re-establish when the input voltage, which was negative, again returns to a value greater than −0.3VDC. Note 5: Positive excursions of input voltage may exceed the power supply level. As long as the other voltage remains within the common-mode range, the comparator will provide a proper output state. The low input voltage state must not be less than −0.3V (or 0.3V below the magnitude of the negative power supply, if used). Note 6: Human body model, 1.5KΩin series with 100pF. Note 7: S/S RS = 20KΩ, tested with RS = 100KΩfor better resolution Note 8: K in datalog is equivalent to V/mV. Note 9: Calculated parameter for ∆VIO / ∆T and ∆IIO / ∆T. LM193JAN www.national.com
Typical Performance Characteristics Supply Current Input Current 20143225 20143226 Output Saturation Voltage Response Time for Various Input Overdrives—Negative Transition 20143227 20143228 Response Time for Various Input Overdrives—Positive Transition 20143229 LM193JAN www.national.com
The LM193 series are high gain, wide bandwidth devices which, like most comparators, can easily oscillate if the output lead is inadvertently allowed to capacitively couple to the inputs via stray capacitance. This shows up only during the output voltage transition intervals as the comparator change states. Power supply bypassing is not required to solve this problem. Standard PC board layout is helpful as it reduces stray input-output coupling. Reducing the input re- sistors to < 10 kΩreduces the feedback signal levels and finally, adding even a small amount (1.0 to 10 mV) of positive feedback (hysteresis) causes such a rapid transition that oscillations due to stray feedback are not possible. Simply socketing the IC and attaching resistors to the pins will cause input-output oscillations during the small transition intervals unless hysteresis is used. If the input signal is a pulse waveform, with relatively fast rise and fall times, hysteresis is not required. All input pins of any unused comparators should be tied to the negative supply. The bias network of the LM193 series establishes a drain current which is independent of the magnitude of the power supply voltage over the range of from 2.0 VDC to 30 VDC. It is usually unnecessary to use a bypass capacitor across the power supply line. The differential input voltage may be larger than V+ without damaging the device (Note 5). Protection should be provided to prevent the input voltages from going negative more than −0.3 VDC (at 25˚C). An input clamp diode can be used as shown in the applications section. The output of the LM193 series is the uncommitted collector of a grounded-emitter NPN output transistor. Many collectors can be tied together to provide an output OR’ing function. An output pull-up resistor can be connected to any available power supply voltage within the permitted supply voltage range and there is no restriction on this voltage due to the magnitude of the voltage which is applied to the V+ terminal of the LM193 package. The output can also be used as a simple SPST switch to ground (when a pull-up resistor is not used). The amount of current which the output device can sink is limited by the drive available (which is independent of V+) and the β of this device. When the maximum current limit is reached (approximately 16mA), the output transistor will come out of saturation and the output voltage will rise very rapidly. The output saturation voltage is limited by the ap- proximately 60ΩrSAT of the output transistor. The low offset voltage of the output transistor (1.0mV) allows the output to clamp essentially to ground level for small load currents. Typical Applications (V+=5.0 VDC) Basic Comparator Driving CMOS Driving TTL 20143235 20143236 20143237 Squarewave Oscillator Pulse Generator Crystal Controlled Oscillator 20143238 20143239 * For large ratios of R1/R2, D1 can be omitted. 20143240 LM193JAN www.national.com
Typical Applications (V+=5.0 VDC) (Continued) Two-Decade High Frequency VCO 20143241 V* = +30 VDC +250 mVDC ≤VC ≤+50 VDC 700Hz ≤fo ≤100kHz Basic Comparator Non-Inverting Comparator with Hysteresis 20143206 20143209 Inverting Comparator with Hysteresis Output Strobing 20143210 20143211 LM193JAN www.national.com
Typical Applications (V+=5.0 VDC) (Continued) AND Gate OR Gate 20143212 20143213 Large Fan-in AND Gate Limit Comparator 20143214 20143215 Comparing Input Voltages of Opposite Polarity ORing the Outputs 20143216 20143217 LM193JAN www.national.com
Typical Applications (V+=5.0 VDC) (Continued) Zero Crossing Detector (Single Power Supply) One-Shot Multivibrator 20143221 20143222 Bi-Stable Multivibrator One-Shot Multivibrator with Input Lock Out 20143224 20143223 Zero Crossing Detector Comparator With a Negative Reference 20143243 20143244 LM193JAN www.national.com
Typical Applications (V+=5.0 VDC) (Continued) Time Delay Generator 20143207 Split-Supply Applications (V+=+15 VDC and V−=−15 VDC) MOS Clock Driver 20143242 LM193JAN www.national.com
A New Release. Corporate format L. Lytle 1 MDS datasheets converted into one Corp. datasheet format. DC Drift table was deleted due to no JANS product offerings. MJLM193-X Rev 1A1 MDS will be archived. LM193JAN www.national.com
inches (millimeters) unless otherwise noted Metal Can Package (H) Ceramic Dual-In-Line Package LM193JAN www.national.com
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