LM193JAN_14 TI1 | Alldatasheet

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www.ti.com SNOSAN2A –MAY 2005–REVISED MARCH 2013 LM193JANLowPowerLowOffsetVoltageDualComparators Check forSamples: LM193JAN 1FEATURES DESCRIPTION The LM193 series consistsof two independent 2• Wide Supply precisionvoltagecomparatorswithan offsetvoltage– VoltageRange: 5.0VDC to36VDC specificationas low as 2.0 mV max for two – Singleor Dual Supplies:±2.5VDC to±18VDC comparators which were designed specificallyto operatefroma singlepower supplyovera widerange• Very Low Supply CurrentDrain(0.4mA) — of voltages.Operationfrom splitpower suppliesisIndependentofSupply Voltage alsopossibleand thelow power supplycurrentdrain• Low InputBiasingCurrent:25 nA typ isindependentofthemagnitudeofthepower supply

  • Low InputOffsetCurrent:±3 nA typ voltage.These comparators also have a unique characteristicinthattheinputcommon-mode voltage• Maximum OffsetVoltage+5mV Max @ 25°C range includesground,even thoughoperatedfrom a• InputCommon-Mode VoltageRange Includes singlepower supplyvoltage.Ground Applicationareas includelimitcomparators,simple• DifferentialInputVoltageRange Equal tothe analogto digitalconverters;pulse,squarewave andPower Supply Voltage timedelaygenerators;wide range VCO; MOS clock
  • Low Output SaturationVoltage,:250 mV at4 timers;multivibratorsand high voltagedigitallogic mA typ gates.The LM193 serieswas designed to directly interfacewithTTL and CMOS. When operatedfrom• Output VoltageCompatible withTTL, DTL, both plus and minus power supplies,the LM193ECL, MOS and CMOS Logic Systems serieswilldirectlyinterfacewithMOS logicwhere theirlow power drainis a distinctadvantage overADVANTAGES standardcomparators.
  • High PrecisionComparators
  • Reduced VOS DriftOver Temperature
  • EliminatesNeed forDual Supplies
  • Allows Sensing Near Ground
  • Compatible withallForms ofLogic
  • Power DrainSuitableforBatteryOperation Squarewave Oscillator Non-InvertingComparator withHysteresis Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2Alltrademarksarethepropertyoftheirrespectiveowners. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2005–2013,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

SNOSAN2A –MAY 2005–REVISED MARCH 2013 www.ti.com Schematic and Connection Diagrams Figure1. TO-99 Figure2. CDIP Package These deviceshave limitedbuilt-inESD protection.The leadsshouldbe shortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamage totheMOS gates.

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www.ti.com SNOSAN2A –MAY 2005–REVISED MARCH 2013 AbsoluteMaximum Ratings(1) SupplyVoltage,V+ 36VDC or±18VDC DifferentialInputVoltage(2) 36V OutputVoltage 36V InputVoltage −0.3VDC to+36VDC InputCurrent(VIN< −0.3VDC )(3) 50 mA CDIP 400 mW @ TA = 125°C Power Dissipation(4) TO-99 330 mW @ TA = 125°C Maximum JunctionTemperature(TJmax ) 175°C OutputShort-CircuittoGround(5) Continuous OperatingTemperatureRange −55°C ≤ TA ≤ +125°C StorageTemperatureRange −65°C ≤ TA ≤ +150°C TO-99 MetalCan (StillAir) 174°C/W MetalCan (500LF/MinAirflow) 99°C/W θJA CDIP CERDIP (StillAir) 146°C/W ThermalResistance CERDIP (500LF/MinAirflow) 85°C/W TO-99 44°C/W θJC CDIP 33°C/W Lead Temperature(Soldering,10 seconds) 260°C ESD Tolerance(6) 500V (1) AbsoluteMaximum Ratingsindicatelimitsbeyond whichdamage tothedevicemay occur.OperatingRatingsindicateconditionsfor whichthedeviceisfunctional,butdo notensurespecificperformancelimits.Forensuredspecificationsand testconditions,see the ElectricalCharacteristics.The ensuredspecificationsapplyonlyforthetestconditionslisted.Some performancecharacteristicsmay degradewhen thedeviceisnotoperatedunderthelistedtestconditions. (2) Positiveexcursionsofinputvoltagemay exceed thepower supplylevel.As longas theothervoltageremainswithinthecommon-mode range,thecomparatorwillprovidea properoutputstate.The lowinputvoltagestatemust notbe lessthan−0.3V(or0.3Vbelowthe magnitudeofthenegativepower supply,ifused). (3) Thisinputcurrentwillonlyexistwhen thevoltageatany oftheinputleadsisdrivennegative.Itisdue tothecollector-basejunctionof theinputPNP transistorsbecoming forwardbiasedand therebyactingas inputdiodeclamps.Inadditiontothisdiodeaction,thereis alsolateralNPN parasitictransistoractionon theIC chip.Thistransistoractioncan cause theoutputvoltagesofthecomparatorstogo totheV+ voltagelevel(ortogroundfora largeoverdrive)forthetimedurationthatan inputisdrivennegative.Thisisnotdestructive and normaloutputstateswillre-establishwhen theinputvoltage,whichwas negative,againreturnstoa valuegreaterthan−0.3VDC . (4) The maximum power dissipationmust be deratedatelevatedtemperaturesand isdictatedby TJmax (maximum junctiontemperature), θJA (packagejunctiontoambientthermalresistance),and TA (ambienttemperature).The maximum allowablepower dissipationatany temperatureisPDmax = (TJmax -TA)/θJA orthenumber givenintheAbsoluteMaximum Ratings,whicheverislower. (5) ShortcircuitsfromtheoutputtoV+ can cause excessiveheatingand eventualdestruction.When consideringshortcircuitstoground, themaximum outputcurrentisapproximately20 mA independentofthemagnitudeofV+. (6) Human body model,1.5KΩ inserieswith100pF. Copyright© 2005–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:LM193JAN

SNOSAN2A –MAY 2005–REVISED MARCH 2013 www.ti.com QualityConformance Inspection Mil-Std-883,Method 5005 -Group A Subgroup Description Temp °C

1 Statictestsat 25

2 Statictestsat 125

3 Statictestsat -55

4 Dynamic testsat 25

5 Dynamic testsat 125

6 Dynamic testsat -55

7 Functionaltestsat 25

9 Switchingtestsat 25

10 Switchingtestsat 125

11 Switchingtestsat -55

12 Settlingtimeat 25

13 Settlingtimeat 125

14 Settlingtimeat -55

LM193JAN ElectricalCharacteristics DC Parameters Symbol Parameter Conditions Notes Min Max Unit Sub- groups VIO InputOffsetVoltage +VCC = 30V,-VCC = 0V, -5.0 5.0 mV 1 VO = 15V -7.0 7.0 mV 2,3 +VCC = 2V,-VCC = -28V, -5.0 5.0 mV 1 VO = -13V -7.0 7.0 mV 2,3 +VCC = 5V,-VCC = 0V, -5.0 5.0 mV 1 VO = 1.4V -7.0 7.0 mV 2,3 +VCC = 2V,-VCC = -3V, -5.0 5.0 mV 1 IIO InputoffsetCurrent +VCC = 30V,-VCC = 0V, See (1) -25 25 nA 1,2 VO = 15V,R S = 20KΩ See (1) -75 75 nA 3 +VCC = 2V,-VCC = -28V, See (1) -25 25 nA 1,2 VO = -13V,R S = 20KΩ See (1) -75 75 nA 3 +VCC = 5V,-VCC = 0V, See (1) -25 25 nA 1,2 VO = 1.4V,R S = 20KΩ See (1) -75 75 nA 3 +VCC = 2V,-VCC = -3V, See (1) -25 25 nA 1,2 VO = -1.6V,R S = 20KΩ See (1) -75 75 nA 3 ±IIB InputBiasCurrent +VCC = 30V,-VCC = 0V, See (1) -100 +0.1 nA 1,2 VO = 15V,R S = 20KΩ See (1) -200 +0.1 nA 3 +VCC = 2V,-VCC = -28V, See (1) -100 +0.1 nA 1,2 VO = -13V,R S = 20KΩ See (1) -200 +0.1 nA 3 +VCC = 5V,-VCC = 0V, See (1) -100 +0.1 nA 1,2 VO = 1.4V,R S = 20KΩ See (1) -200 +0.1 nA 3 +VCC = 2V,-VCC = -3V, See (1) -100 +0.1 nA 1,2 VO = -1.6V,R S = 20KΩ See (1) -200 +0.1 nA 3 (1) S/S R S = 20KΩ,testedwithR S = 100KΩ forbetterresolution

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www.ti.com SNOSAN2A –MAY 2005–REVISED MARCH 2013 LM193JAN ElectricalCharacteristics DC Parameters (continued) Symbol Parameter Conditions Notes Min Max Unit Sub- groups CMRR InputVoltageCommon Mode 2V ≤ +VCC ≤ 30V, Rejection -28V ≤ -VCC ≤ 0V, -13V ≤ VO ≤ 15V 76 dB 1,2,3 2V ≤ +VCC ≤ 5V, -3V ≤ -VCC ≤ 0V, -1.6V≤ VO ≤ 1.4V 70 dB 1,2,3 ICEX OutputLeakage Current +VCC = 30V,-VCC = 0V, VO = +30V 1.0 µA 1,2,3 +IIL InputLeakage Current +VCC = 36V,-VCC = 0V, +VI= 34V,-VI= 0V -500 500 nA 1,2,3 -IIL InputLeakage Current +VCC = 36V,-VCC = 0V, +VI= 0V,-VI= 34V -500 500 nA 1,2,3 VOL Logical"0"OutputVoltage +VCC = 4.5V,-VCC = 0V, 0.4 V 1 IO = 4mA 0.7 V 2,3 +VCC = 4.5V,-VCC = 0V, 1.5 V 1 IO = 8mA 2.0 V 2,3 ICC Power SupplyCurrent +VCC = 5V,-VCC = 0V, 2.0 mA 1,2 VID = 15mV 3.0 mA 3 +VCC = 30V,-VCC = 0V, 3.0 mA 1,2 VID = 15mV 4.0 mA 3 ΔIO /ΔT TemperatureCoefficientofInput 25°C ≤ TA ≤ +125°C See (2) -25 25 µV/°C 2 OffsetVoltage -55°C ≤ TA ≤ 25°C See (2) -25 25 µV/°C 3 ΔIIO /ΔT TemperatureCoefficientofInput 25°C ≤ TA ≤ +125°C See (2) -300 300 pA/°C 2 OffsetCurrent -55°C ≤ TA ≤ 25°C See (2) -400 400 pA/°C 3 AVS Open Loop VoltageGain +VCC = 15V,-VCC = 0V, See (3) 50 V/mV 4 R L = 15KΩ, 1V ≤ VO ≤ 11V See (3) 25 V/mV 5,6 VLat VoltageLatch(Logical"1"Input) +VCC = 5V,-VCC = 0V, VI= 10V,IO = 4mA 0.4 V 9 (2) CalculatedparameterforΔVIO /ΔT and ΔIIO /ΔT. (3) K indatalogisequivalenttoV/mV. AC Parameters The followingconditionsapply,unlessotherwisespecified.+VCC = 5V,−VCC = 0V Symbol Parameter Conditions Notes Min Max Unit Sub- groups tRLH Response Time VI= 100mV, R L = 5.1KΩ, 5.0 µS 7,8B VOD = 5mV 7.0 µS 8A VI= 100mV, R L = 5.1KΩ, 0.8 µS 7,8B VOD = 50mV 1.2 µS 8A tRHL Response Time VI= 100mV, R L = 5.1KΩ, 2.5 µS 7,8B VOD = 5mV 3.0 µS 8A VI= 100mV, R L = 5.1KΩ, 0.8 µS 7,8B VOD = 50mV 1.0 µS 8A CS ChannelSeparation +VCC = 20V,-VCC = -10V, A toB 80 dB 7 +VCC = 20V,-VCC = -10V, B toA 80 dB 7 Copyright© 2005–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:LM193JAN

SNOSAN2A –MAY 2005–REVISED MARCH 2013 www.ti.com TypicalPerformance Characteristics Supply Current InputCurrent Figure3. Figure4. Response Time forVariousInputOverdrives— Negative Output SaturationVoltage Transition Figure5. Figure6. Response Time forVariousInputOverdrives— PositiveTransition Figure7.

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www.ti.com SNOSAN2A –MAY 2005–REVISED MARCH 2013 APPLICATION HINTS The LM193 seriesarehighgain,wide bandwidthdeviceswhich,likemost comparators,can easilyoscillateifthe outputleadisinadvertentlyallowedtocapacitivelycoupletotheinputsviastraycapacitance.Thisshows up only duringthe outputvoltagetransitionintervalsas the comparatorchange states.Power supplybypassingisnot requiredto solvethisproblem.StandardPC board layoutishelpfulas itreducesstrayinput-outputcoupling. Reducing the inputresistorsto < 10 kΩ reducesthe feedbacksignallevelsand finally,addingeven a small amount (1.0to10 mV) ofpositivefeedback(hysteresis)causes such a rapidtransitionthatoscillationsdue to strayfeedbackare not possible.Simplysocketingthe IC and attachingresistorsto the pinswillcause input- outputoscillationsduringthe smalltransitionintervalsunlesshysteresisisused.Ifthe inputsignalisa pulse waveform,withrelativelyfastriseand falltimes,hysteresisisnotrequired. Allinputpinsofany unused comparatorsshouldbe tiedtothenegativesupply. The biasnetworkoftheLM193 seriesestablishesa draincurrentwhichisindependentofthemagnitudeofthe power supplyvoltageovertherangeoffrom2.0VDC to30 VDC . Itisusuallyunnecessarytouse a bypasscapacitoracrossthepower supplyline. The differentialinputvoltagemay be largerthan V+ withoutdamaging the device (1). Protectionshould be providedtopreventtheinputvoltagesfromgoingnegativemore than−0.3VDC (at25°C).An inputclamp diode can be used as shown intheapplicationssection. The outputoftheLM193 seriesistheuncommittedcollectorofa grounded-emitterNPN outputtransistor.Many collectorscan be tiedtogethertoprovidean outputOR'ingfunction.An outputpull-upresistorcan be connected toany availablepower supplyvoltagewithinthepermittedsupplyvoltagerangeand thereisno restrictionon this voltagedue to the magnitudeof the voltagewhich isappliedto the V+ terminalof the LM193 package.The outputcan alsobe used as a simpleSPST switchtoground(when a pull-upresistorisnotused).The amount of currentwhichtheoutputdevicecan sinkislimitedby thedriveavailable(whichisindependentofV+)and theβ ofthisdevice.When themaximum currentlimitisreached(approximately16mA), theoutputtransistorwillcome out of saturationand the outputvoltagewillriseveryrapidly.The outputsaturationvoltageislimitedby the approximately60Ω rSAT oftheoutputtransistor.The low offsetvoltageoftheoutputtransistor(1.0mV)allowsthe outputtoclamp essentiallytogroundlevelforsmallloadcurrents. (1) Positiveexcursionsofinputvoltagemay exceed thepower supplylevel.As longas theothervoltageremainswithinthecommon-mode range,thecomparatorwillprovidea properoutputstate.The lowinputvoltagestatemust notbe lessthan−0.3V(or0.3Vbelowthe magnitudeofthenegativepower supply,ifused). Copyright© 2005–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:LM193JAN

SNOSAN2A –MAY 2005–REVISED MARCH 2013 www.ti.com TypicalApplications (V+=5.0VDC ) Basic Comparator DrivingCMOS DrivingTTL Squarewave Oscillator Pulse Generator CrystalControlledOscillator *ForlargeratiosofR1/R2, D1 can be omitted. Figure8. Two-Decade High Frequency VCO V* = +30 VDC +250 mV DC ≤ VC ≤ +50 VDC 700Hz ≤ fo ≤ 100kHz Basic Comparator Non-InvertingComparator withHysteresis

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www.ti.com SNOSAN2A –MAY 2005–REVISED MARCH 2013 InvertingComparator withHysteresis Output Strobing AND Gate OR Gate Large Fan-inAND Gate LimitComparator Comparing InputVoltagesofOpposite Polarity ORing theOutputs Copyright© 2005–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:LM193JAN

SNOSAN2A –MAY 2005–REVISED MARCH 2013 www.ti.com Zero Crossing Detector(SinglePower Supply) One-Shot Multivibrator Bi-StableMultivibrator One-Shot MultivibratorwithInputLock Out Zero Crossing Detector Comparator With a NegativeReference

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www.ti.com SNOSAN2A –MAY 2005–REVISED MARCH 2013 Figure9. Time Delay Generator Split-SupplyApplications (V+=+15 VDC and V−=−15 VDC ) Figure10. MOS Clock Driver Copyright© 2005–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:LM193JAN

SNOSAN2A –MAY 2005–REVISED MARCH 2013 www.ti.com REVISION HISTORY SECTION Date Released Revision Section Originator Changes 05/09/05 A New Release.Corporateformat L.Lytle 1 MDS datasheetsconvertedintoone Corp. datasheetformat.DC Drifttablewas deleted due tono JANS productofferings.MJLM193-X Rev 1A1 MDS willbe archived. 03/26/2013 A AllSections Changed layoutofNationalData SheettoTI format

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www.ti.com 11-Apr-2013 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) Op Temp (°C) Top-Side Markings (4) Samples JL193BGA ACTIVE TO-99 LMC 8 20 TBD Call TI Call TI -55 to 125 JL193BGA JM38510/11202BGA Q ACO JM38510/11202BGA Q JM38510/11202BGA ACTIVE TO-99 LMC 8 20 TBD Call TI Call TI -55 to 125 JL193BGA JM38510/11202BGA Q ACO JM38510/11202BGA Q M38510/11202BGA ACTIVE TO-99 LMC 8 20 TBD Call TI Call TI -55 to 125 JL193BGA JM38510/11202BGA Q ACO JM38510/11202BGA Q (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.

www.ti.com 11-Apr-2013 Addendum-Page 2 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

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