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LF156JAN JFET Input Operational Amplifiers Literature Number: SNOSAQ0
JFET Input Operational Amplifiers General Description This is the first monolithic JFET input operational amplifier to incorporate well matched, high voltage JFETs on the same chip with standard bipolar transistors (BI-FET ™ Technology). This amplifier features low input bias and offset currents/low offset voltage and offset voltage drift, coupled with offset adjust which does not degrade drift or common-mode rejec- tion. The device is also designed for high slew rate, wide bandwidth, extremely fast settling time, low voltage and current noise and a low 1/ƒ noise corner.
Features
n Replace expensive hybrid and module FET op amps n Rugged JFETs allow blow-out free handling compared with MOSFET input devices n Excellent for low noise applications using either high or low source impedance — very low 1/f corner n Offset adjust does not degrade drift or common-mode rejection as in most monolithic amplifiers n New output stage allows use of large capacitive loads (5,000 pF) without stability problems n Internal compensation and large differential input voltage capability
Applications
n Precision high speed integrators n Fast D/A and A/D converters n High impedance buffers n Wideband, low noise, low drift amplifiers n Logarithmic amplifiers n Photocell amplifiers n Sample and Hold circuits Common Features n Low input bias current: 30pA n Low Input Offset Current: 3pA n High input impedance: 10 12Ω n Low input noise current: n High common-mode rejection ratio: 100 dB n Large dc voltage gain: 106 dB Uncommon Features n Extremely fast settling time to 0.01% 1.5µs n Fast slew rate 12V/µs n Wide gain bandwidth 5MHz n Low input noise voltage 12
Ordering Information
NS PART NUMBER SMD PART NUMBER NS PACKAGE NUMBER PACKAGE DISCRIPTION JL156BGA JM38510/11402 H08C 8LD Metal Can JL156SGA JM38510/11402 H08C 8LD Metal Can Connection Diagrams Metal Can Package (H) 20151114 Top View See NS Package Number H08C BI-FET™ , BI-FET II™ are trademarks of National Semiconductor Corporation. March 2006 LF156JAN JFET Input Operational Amplifiers © 2006 National Semiconductor Corporation DS201511 www.national.com
*3pF in LF357 series. Detailed Schematic 20151113 *C = 3pF in LF357 series. LF156JAN www.national.com 2
Absolute Maximum Ratings(Note 1) Supply Voltage ±22V Differential Input Voltage ±40V Input Voltage Range (Note 3) ±20V Output Short Circuit Duration (Note 4) Continuous T JMAX 175˚C Power Dissipation at T A = 25˚C (Note 2) Still Air 560 mW
500 LF/Min Air Flow 1200 mW
θJA Still Air 160˚C/W
400 LF/Min Air Flow 65˚C/W
θJC 23˚C/W Storage Temperature Range −65˚C ≤ TA ≤ +150˚C Lead Temperature (Soldering 10 sec.) 300˚C ESD tolerance (Note 5) 1200V Recommended Operating Conditions Supply voltage range ±5t o ±20 VDC Ambient temperature range −55˚C ≤ TA ≤ +125˚C Quality Conformance Inspection MIL-STD-883, Method 5005 - Group A Subgroup Description Temp ( C)
1 Static tests at +25
2 Static tests at +125
3 Static tests at -55
4 Dynamic tests at +25
5 Dynamic tests at +125
6 Dynamic tests at -55
7 Functional tests at +25
8A Functional tests at +125 8B Functional tests at -55
9 Switching tests at +25
10 Switching tests at +125
11 Switching tests at -55
12 Settling time at +25
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The following conditions apply, unless otherwise specified. DC: VCC = ±20V, VCM =0 V Symbol Parameter Conditions Notes Min Max Unit Sub- groups ICC Supply Current +V CC = 15V, -VCC = -15V 7.0 mA 1 6.0 mA 2 11 mA 3 VIO Input Offset Voltage +V CC = 5V, -VCC = -35V, VCM = 15V -5.0 5.0 mV 1 -7.0 7.0 mV 2, 3 +VCC = 35V, -VCC = -5V, VCM = -15V -5.0 5.0 mV 1 -7.0 7.0 mV 2, 3 -5.0 5.0 mV 1 -7.0 7.0 mV 2, 3 CC = 5V, -VCC = -5V -5.0 5.0 mV 1 -7.0 7.0 mV 2, 3 ±IIB Input Bias Current +V CC = 5V, -VCC = -35V, VCM = 15V -0.1 3.5 nA 1 -10 60 nA 2 +VCC = 35V, -VCC = -5V, VCM = -15V -0.1 0.1 nA 1 -10 50 nA 2 -0.1 0.1 nA 1 -10 50 nA 2 +VCC = 5V, -VCC = -25V, VCM = 10V -0.1 0.3 nA 1 -10 50 nA 2 IIO Input Offset Current -0.02 0.02 nA 1 -20 +20 nA 2 +PSRR Power Supply Rejection Ratio +V CC = 10V, -VCC = -20V 85 dB 1, 2, 3 -PSRR Power Supply Rejection Ratio +V CC = 20V, -VCC = -10V 85 dB 1, 2, 3 CMR Input Voltage Common Mode Rejection VCM = -15V to 15V 85 dB 1, 2, 3 VIO Adj (+) Adjustment for Input Offset Voltage 8.0 mV 1, 2, 3 VIO Adj (-) Adjustment for Input Offset Voltage -8.0 mV 1, 2, 3 +IOS Output Short Circuit Current (For Positive Output) +VCC = 15V, -VCC = -15V, t ≤ 25mS -50 mA 1, 2, 3 -IOS Output Short Circuit Current (For Negative Output) +VCC = 15V, -VCC = -15V, t ≤ 25mS 50 mA 1, 2, 3 ∆ VIO/∆T Temperature Coefficient of Input Offset Voltage 25˚C ≤ TA ≤ +125˚C (Note 7) -30 30 µV/˚C 2 -55˚C≤ TA ≤ 25˚C (Note 7) -30 30 µV/˚C 3 -AVS Open Loop Voltage Gain (Single Ended) VO = -15V, RL =2 KΩ (Note 6) 50 V/mV 4 (Note 6) 25 V/mV 5, 6 +AVS Open Loop Voltage Gain (Single Ended) VO = +15V, RL =2 KΩ (Note 6) 50 V/mV 4 (Note 6) 25 V/mV 5, 6 AVS Open Loop Voltage Gain (Single Ended) VCC = ±5V, VO = ±2V, RL =2 KΩ (Note 6) 10 V/mV 4, 5, 6 -VOP Output Voltage Swing V CM = 20V, RL = 10KΩ - 1 6 V 4 ,5 ,6 VCM = 20V, RL =2 KΩ - 1 5 V 4 ,5 ,6 +VOP Output Voltage Swing V CM = -20V, RL = 10KΩ 1 6 V 4 ,5 ,6 VCM = -20V, RL =2 KΩ 1 5 V 4 ,5 ,6 LF156JAN www.national.com 4
The following conditions apply, unless otherwise specified. AC: VCC = ±15V, VCM =0 V Symbol Parameter Conditions Notes Min Max Unit Sub- groups -SR Slew Rate Fall V I = 5V to -5V, A V =1 7.5 V/µS 7
5 V/µS 8A, 8B
+SR Slew Rate Rise V I = -5V to 5V, A V = 1 7.5 V/µS 7 TRTR Transient Response Rise Time R L =2 KΩ,C L= 100pF, VI = 50mV, AV =1 100 nS 7, 8A, 8B TROS Transient Response Overshoot R L =2 KΩ,C L = 100pF, VI = 50mV, AV =1 40 % 7, 8A, 8B NIBB Noise Broad Band BW = 5KHz, V CC = ±20V 10 µV RMS 7 NIPC Noise Popcorn BW = 5KHz, V CC = ±20V 40 µV PK 7 tS (+) Settling Time A V = -1 1500 nS 12 tS (-) Settling Time A V = -1 1500 nS 12 Drift Values The following conditions apply, unless otherwise specified. AC: VCC = ±20V, VCM =0 V Delta calculations performed on JAN S devices at group B, subgroup 5 only Symbol Parameter Conditions Notes Min Max Unit Sub- groups VIO Input Offset Voltage -1.0 1.0 mV 1 ±IIB Input Bias Current -0.05 0.05 nA 1 Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate condition for which the device is functional, but do not guarantee specific performance limits . For guaranteed specifications and test conditions, see the Electrical Characterist ics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the lis ted test conditions. Note 2: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax(maximum junction temperature), θJA(package junction to ambient thermal resistance), and TA (ambient temperature). The maximum allowable power dissipation at any temperature is P D=(TJmax−TA)/θJA or the number given in the Absolute Maximum Ratings, whichever is lower. Note 3: The absolute maximum negative input voltage is equal to the negative power supply voltage. Note 4: Short circuit may be to ground or either supply. Rating applies to +125˚C case temperature or +75˚C ambient temperature. Note 5: Human body model, 100pF discharged through 1.5K Ω. Note 6: Datalog Reading in K = V/mV. Note 7: Calculated parameter. LF156JAN www.national.com5
Typical DC Performance Characteristics Input Bias Current Input Bias Current 20151137 20151138 Input Bias Current Voltage Swing 20151139 20151140 Supply Current Supply Current 20151141 20151142 LF156JAN www.national.com 6
Typical DC Performance Characteristics(Continued) Negative Current Limit Positive Current Limit 20151143 20151144 Positive Common-Mode Input Voltage Limit Negative Common-Mode Input Voltage Limit 20151145 20151146 Open Loop Voltage Gain Output Voltage Swing 20151147 20151148 LF156JAN www.national.com7
Typical AC Performance Characteristics Gain Bandwidth Normalized Slew Rate 20151150 20151151 Output Impedance Output Impedance 20151152 20151153 LF156 Small Signal Pulse Response, AV =+ 1 LF156 Large Signal Puls Response, AV =+ 1 20151106 20151109 LF156JAN www.national.com 8
Typical AC Performance Characteristics(Continued) Inverter Settling Time Open Loop Frequency Response 20151156 20151157 Bode Plot Common-Mode Rejection Ratio 20151159 20151161 Power Supply Rejection Ratio 20151163 LF156JAN www.national.com9
Typical AC Performance Characteristics(Continued) Undistorted Output Voltage Swing Equivalent Input Noise Voltage 20151164 20151165 Equivalent Input Noise Voltage (Expanded Scale) 20151166 LF156JAN www.national.com 10
These are op amps with JFET input devices. These JFETs have large reverse breakdown voltages from gate to source and drain eliminating the need for clamps across the inputs. Therefore large differential input voltages can easily be ac- commodated without a large increase in input current. The maximum differential input voltage is independent of the supply voltages. However, neither of the input voltages should be allowed to exceed the negative supply as this will cause large currents to flow which can result in a destroyed unit. Exceeding the negative common-mode limit on either input will force the output to a high state, potentially causing a reversal of phase to the output. Exceeding the negative common-mode limit on both inputs will force the amplifier output to a high state. In neither case does a latch occur since raising the input back within the common-mode range again puts the input stage and thus the amplifier in a normal operating mode. Exceeding the positive common-mode limit on a single input will not change the phase of the output however, if both inputs exceed the limit, the output of the amplifier will be forced to a high state. These amplifiers will operate with the common-mode input voltage equal to the positive supply. In fact, the common- mode voltage can exceed the positive supply by approxi- mately 100 mV independent of supply voltage and over the full operating temperature range. The positive supply can therefore be used as a reference on an input as, for ex- ample, in a supply current monitor and/or limiter. Precautions should be taken to ensure that the power supply for the integrated circuit never becomes reversed in polarity or that the unit is not inadvertently installed backwards in a socket as an unlimited current surge through the resulting forward diode within the IC could cause fusing of the internal conductors and result in a destroyed unit. All of the bias currents in these amplifiers are set by FET current sources. The drain currents for the amplifiers are therefore essentially independent of supply voltage. As with most amplifiers, care should be taken with lead dress, component placement and supply decoupling in order to ensure stability. For example, resistors from the output to an input should be placed with the body close to the input to minimize “pickup” and maximize the frequency of the feed- back pole by minimizing the capacitance from the input to ground. A feedback pole is created when the feedback around any amplifier is resistive. The parallel resistance and capacitance from the input of the device (usually the inverting input) to AC ground set the frequency of the pole. In many instances the frequency of this pole is much greater than the expected 3dB frequency of the closed loop gain and consequently there is negligible effect on stability margin. However, if the feedback pole is less than approximately six times the expected 3 dB frequency a lead capacitor should be placed from the output to the input of the op amp. The value of the added capacitor should be such that the RC time constant of this capacitor and the resistance it parallels is greater than or equal to the original feedback pole time constant. Typical Circuit Connections VOS Adjustment 20151167 VOS is adjusted with a 25k potentiometer The potentiometer wiper is connected to V + For potentiometers with temperature coefficient of 100 ppm/˚C or less the additional drift with adjust is ≈ 0.5µV/ ˚C/mV of adjustment Typical overall drift: 5µV/˚C ±(0.5µV/˚C/mV of adj.) Driving Capacitive Loads 20151168 * LF15 6R=5 k Due to a unique output stage design, these amplifiers have the ability to drive large capacitive loads and still maintain stability. C L(MAX) . 0.01µF. Overshoot ≤ 20% Settling time (ts) . 5µs LF156JAN www.national.com11
Settling Time Test Circuit 20151116 Settling time is tested with the LF156 connected as unity gain inverter. FET used to isolate the probe capacitance Output = 10V step Large Signal Inverter Output, VOUT (from Settling Time Circuit) LF356 20151118 LF156JAN www.national.com 12
Typical Applications (Continued) Low Drift Adjustable Voltage Reference 20151120 All resistors and potentiometers should be wire-wound P1: drift adjust P2: VOUT adjust Fast Logarithmic Converter 20151121 Dynamic range: 100µA ≤ Ii ≤ 1mA (5 decades), |VO| = 1V/decade Transient response: 3µs for ∆Ii = 1 decade C1, C2, R2, R3: added dynamic compensation VOS adjust the LF156 to minimize quiescent error RT: Tel Labs type Q81 + 0.3%/˚C LF156JAN www.national.com13
Typical Applications (Continued) Precision Current Monitor 20151131 VO = 5 R1/R2 (V/mA of I S) R1, R2, R3: 0.1% resistors 8-Bit D/A Converter with Symmetrical Offset Binary Operation 20151132 R1, R2 should be matched within ±0.05% Full-scale response time: 3µs EO B1 B2 B3 B4 B5 B6 B7 B8 Comments +9.920 11111111 Positive Full-Scale +0.040 10000000 ( + ) Zero-Scale −0.040 01111111 ( − ) Zero-Scale −9.920 00000000 Negative Full-Scale LF156JAN www.national.com 14
Typical Applications (Continued) Wide BW Low Noise, Low Drift Amplifier 20151170 Parasitic input capacitance C1 . 3pF interacts with feedback elements and creates undesirable high frequency pole. To compensate add C2 such that: R2 C2 . R1 C1. Boosting the LF156 with a Current Amplifier 20151173 IOUT(MAX).150mA (will drive RL≥ 100Ω) No additional phase shift added by the current amplifier LF156JAN www.national.com15
Typical Applications (Continued)
3 Decades VCO
R1, R4 matched. Linearity 0.1% over 2 decades. Isolating Large Capacitive Loads 20151122 Overshoot 6% ts 10µs When driving large C L, the VOUT slew rate determined by C L and IOUT(MAX): LF156JAN www.national.com 16
Typical Applications (Continued) Low Drift Peak Detector 20151123 By adding D1 and R f,V D1=0 during hold mode. Leakage of D2 provided by feedback path through R f. Leakage of circuit is essentially I b plus capacitor leakage of Cp. Diode D3 clamps V OUT (A1) to VIN−VD3 to improve speed and to limit reverse bias of D2. Maximum input frequency should be << 1⁄2πRfCD2 where CD2 is the shunt capacitance of D2. High Impedance, Low Drift Instrumentation Amplifier 20151126 System VOS adjusted via A2 VOS adjust Trim R3 to boost up CMRR to 120 dB. Instrumentation amplifier resistor array recommended for best accuracy and lowest drift LF156JAN www.national.com17
Typical Applications (Continued) Fast Sample and Hold 20151133 Both amplifiers (A1, A2) have feedback loops individually closed with stable responses (overshoot negligible) Acquisition time TA, estimated by: LF156 develops full S r output capability for V IN ≥ 1V Addition of SW2 improves accuracy by putting the voltage drop across SW1 inside the feedback loop Overall accuracy of system determined by the accuracy of both amplifiers, A1 and A2 LF156JAN www.national.com 18
Typical Applications (Continued) High Accuracy Sample and Hold 20151127 By closing the loop through A2, the V OUT accuracy will be determined uniquely by A1. No VOS adjust required for A2. TA can be estimated by same considerations as previously but, because of the added propagation delay in the feedback loop (A2) the overshoot is not negligible. Overall system slower than fast sample and hold R1, CC: additional compensation Use LF156 for j Fast settling time j Low VOS High Q Notch Filter 20151134 2 R 1=R=1 0 M Ω 2C = C1 = 300pF Capacitors should be matched to obtain high Q fNOTCH = 120 Hz, notch = −55 dB, Q > 100 Use LF155 for j Low IB j Low supply current LF156JAN www.national.com19
Revision History
Released Revision Section Originator Changes 03/10/06 A New Released, Corporate format. R. Malone New Release, Corporate format 1 MDS data sheet converted into a Corp. data sheet format. Following MDS data sheet will be Archived MJLF156-X, Rev. 0A0. LF156JAN www.national.com 20
Physical Dimensions inches (millimeters) unless otherwise noted Metal Can Package (H) National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. For the most current product information visit us at www.national.com. LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. BANNED SUBSTANCE COMPLIANCE National Semiconductor manufactures products and uses packing materials that meet the provisions of the Customer Products Stewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification (CSP-9-111S2) and contain no ‘‘Banned Substances’’ as defined in CSP-9-111S2. Leadfree products are RoHS compliant. National Semiconductor Americas Customer Support Center Email: new.feedback@nsc.com Tel: 1-800-272-9959 National Semiconductor Europe Customer Support Center Fax: +49 (0) 180-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 National Semiconductor Asia Pacific Customer Support Center Email: ap.support@nsc.com National Semiconductor Japan Customer Support Center Fax: 81-3-5639-7507 Email: jpn.feedback@nsc.com Tel: 81-3-5639-7560 www.national.com LF156JAN JFET Input Operational Amplifiers
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