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www.ti.com SNOSAJ9A –APRIL 2005–REVISED MARCH 2013 LF147JANWideBandwidthQuadJFETInputOperationalAmplifier Check forSamples: LF147JAN 1FEATURES DESCRIPTION The LF147 isa low cost,highspeed quad JFET input 23• InternallyTrimmed OffsetVoltage:5 mV Max operationalamplifierwithan internallytrimmed input• Low InputBias Current:50 pA Typ. offsetvoltage( BI-FET™ IItechnology).The device

  • Low InputNoise Current:0.01pA/√Hz Typ. requiresa low supplycurrentand yet maintainsa largegainbandwidthproductand a fastslewrate.In• Wide Gain Bandwidth: 4 MHz Typ. addition,well matched high voltage JFET input• High Slew Rate:13 V/μs Typ. devices provide very low input bias and offset
  • Low Supply Current:7.2mA Typ. currents.The LF147 is pin compatiblewith the standardLM148. This featureallowsdesignersto• High InputImpedance: 1012Ω Typ. immediatelyupgrade the overallperformance of• Low TotalHarmonic Distortion: existingLF148 and LM124 designs.– A V = 10,R L = 10K Ω,VO = 20VP-P The LF147 may be used inapplicationssuch as high– BW = 20Hz — 20KHz ≤0.02% Typ. speed integrators,fastD/A converters,sample-and-
  • Low 1/fNoise Corner:50 Hz Typ. hold circuitsand many othercircuitsrequiringlow inputoffsetvoltage,low inputbiascurrent,highinput• FastSettlingTime to0.01%:2 μs Typ. impedance,highslew rateand wide bandwidth.The devicehas lownoiseand offsetvoltagedrift. Connection Diagram Figure1. CDIP Package Top View See Package Number J Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2BI-FETisa trademarkofTexas Instruments. 3Allothertrademarksarethepropertyoftheirrespectiveowners. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2005–2013,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

SNOSAJ9A –APRIL 2005–REVISED MARCH 2013 www.ti.com SimplifiedSchematic Figure2. ¼ Quad DetailedSchematic These deviceshave limitedbuilt-inESD protection.The leadsshouldbe shortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamage totheMOS gates.

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www.ti.com SNOSAJ9A –APRIL 2005–REVISED MARCH 2013 AbsoluteMaximum Ratings(1) SupplyVoltage ±18V DifferentialInputVoltage ±30V InputVoltageRange (2) ±15V OutputShortCircuitDuration(3) Continuous Power Dissipation(4)(5) 900 mW TJ max 150°C θJA CDIP 70°C/W OperatingTemperatureRange −55°C ≤ TA ≤ 125°C StorageTemperatureRange −65°C ≤ TA ≤ 150°C Lead Temperature(Soldering,10 sec.) 260°C ESD (6) 900V (1) AbsoluteMaximum Ratingsindicatelimitsbeyond whichdamage tothedevicemay occur.OperatingRatingsindicateconditionsfor whichthedeviceisfunctional,butdo notensurespecificperformancelimits.Forensuredspecificationsand testconditions,see the ElectricalCharacteristics.The ensuredspecificationsapplyonlyforthetestconditionslisted.Some performancecharacteristicsmay degradewhen thedeviceisnotoperatedunderthelistedtestconditions. (2) Unlessotherwisespecifiedtheabsolutemaximum negativeinputvoltageisequaltothenegativepower supplyvoltage. (3) Any oftheamplifieroutputscan be shortedtogroundindefinitely,however,more thanone shouldnotbe simultaneouslyshortedas the maximum junctiontemperaturewillbe exceeded. (4) The maximum power dissipationmust be deratedatelevatedtemperaturesand isdictatedby TJmax (maximum junctiontemperature), θJA (Packagejunctiontoambientthermalresistance),and TA (ambienttemperature).The maximum allowablepower dissipationatany temperatureisPDmax = (TJmax — TA)/θJA orthenumber givenintheAbsoluteMaximum Ratings,whicheverislower. (5) Max. Power Dissipationisdefinedby thepackage characteristics.OperatingthepartneartheMax. Power Dissipationmay cause the parttooperateoutsidespecifiedlimits. (6) Human body model,1.5kΩ inserieswith100 pF. Recommended OperatingConditions SupplyVoltageRange ±5V to±15V QualityConformance Inspection Mil-Std-883,Method 5005 -Group A Subgroup Description Temp (°C)

1 Statictestsat 25

2 Statictestsat 125

3 Statictestsat -55

4 Dynamic testsat 25

5 Dynamic testsat 125

6 Dynamic testsat -55

7 Functionaltestsat 25

9 Switchingtestsat 25

10 Switchingtestsat 125

11 Switchingtestsat -55

12 SettlingTime at 25

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SNOSAJ9A –APRIL 2005–REVISED MARCH 2013 www.ti.com LF147JAN ElectricalCharacteristicsDC Parameters The followingconditionsapply,unlessotherwisespecified:VCC = ±15V,VCM = 0V Sub-Symbol Parameter Conditions Notes Min Max Unit groups VIO InputOffsetVoltage -5.0 5.0 mV 1+VCC = 26V,-VCC = -4V, VCM = -11V -7.0 7.0 mV 2,3 -5.0 5.0 mV 1+VCC = 4V,-VCC = -26V, VCM = 11V -7.0 7.0 mV 2,3 -5.0 5.0 mV 1+VCC = 15V,-VCC = -15V, VCM = 0V -7.0 7.0 mV 2,3 -5.0 5.0 mV 1+VCC = 5V,-VCC = -5V, VCM = 0V -7.0 7.0 mV 2,3 ±IIB InputBiasCurrent -0.4 0.2 nA 1+VCC = 26V,-VCC = -4V, VCM = -11V -10 50 nA 2 -0.2 0.2 nA 1+VCC = 15V,-VCC = -15V, VCM = 0V -10 50 nA 2 -0.2 1.2 nA 1+VCC = 4V,-VCC = -26V, VCM = 11V -10 70 nA 2 IIO InputOffsetCurrent -0.1 0.1 nA 1+VCC = 15V,-VCC = -15V, VCM = 0V -20 20 nA 2 +PSRR Power SupplyRejectionRatio -VCC = -15V, 80 dB 1,2,3+VCC = 20V to10V -PSRR Power SupplyRejectionRatio +VCC = 15V, 80 dB 1,2,3-VCC = -20V to-10V CMRR InputVoltageCommon Mode ±VCC = ±4V to±26V, 80 dB 1,2,3Rejection VCM = -11V to+11V +IOS OutputShortCircuitCurrent +VCC = 15V,-VCC = -15V, -80 mA 1,2,3VCM = -10V,t≤ 25mS −IOS OutputShortCircuitCurrent +VCC = 15V,-VCC = -15V, 80 mA 1,2,3VCM = 10V,t≤ 25mS ICC SupplyCurrent 14 mA 1,2 +VCC = 15V,-VCC = -15V 16 mA 3 DeltaVIO / InputOffsetVoltageTemp. 25°C ≤ TA ≤ +125°C See (1) -30 30 µV/°C 2 DeltaT Sensitivity -55°C ≤ TA ≤ 25°C See (1) -30 30 µV/°C 3 +VOP OutputVoltageSwing +VCC = 15V,-VCC = -15V, 12 V 4,5,6R L=10KΩ,VCM = -15V +VCC = 15V,-VCC = -15V,R L=2KΩ, 10 V 4,5,6VCM = -15V -VOP OutputVoltageSwing +VCC = 15V,-VCC = -15V, -12 V 4,5,6R L=10KΩ,VCM = 15V +VCC = 15V,-VCC = -15V, -10 V 4,5,6R L = 2KΩ,VCM = 15V +AVS Open Loop VoltageGain 50 V/mV 4+VCC = 15V,-VCC = -15V, R L = 2KΩ,VO = 0 to10V 25 V/mV 5,6 −AVS Open Loop VoltageGain 50 V/mV 4+VCC = 15V,-VCC = -15V, R L = 2KΩ,VO = 0 to-10V 25 V/mV 5,6 AVS Open Loop VoltageGain +VCC = 5V,-VCC = -5V, 20 V/mV 4,5,6R L = 10KΩ,VO = ±2V (1) Calculatedparameters.

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www.ti.com SNOSAJ9A –APRIL 2005–REVISED MARCH 2013 LF147JAN ElectricalCharacteristicsAC Parameters The followingconditionsapply,unlessotherwisespecified:VCC = ±15V Sub-Symbol Parameter Conditions Notes Min Max Unit groups +SR Slew Rate 7 V/µS 7 VI= -5V to+5V

5 V/µS 8A,8B

-SR Slew Rate 7 V/µS 7 VI= +5V to-5V TR TR TransientResponse RiseTime AV=1, VI=50mV, C L= 100pF, 200 nS 7,8A,8BR L=2KΩ TR OS TransientResponse Overshoot AV=1, VI=50mV, C L= 100pF, 40 % 7,8A,8BR L=2KΩ NIBB NoiseBroadband BW = 10Hz to15KHz, R S = 0Ω 15 µVRMS 7 NIPC NoisePopcorn BW = 10Hz to15KHz, 80 µVPK 7R S = 100KΩ C S ChannelSeparation R L = 2KΩ 80 dB 7 R L = 2KΩ,VI= ±10V,A toB 80 dB 7 R L = 2KΩ,VI= ±10V,A toC 80 dB 7 R L = 2KΩ,VI= ±10V,A toD 80 dB 7 R L = 2KΩ,VI= ±10V,B toA 80 dB 7 R L = 2KΩ,VI= ±10V,B toC 80 dB 7 R L = 2KΩ,VI= ±10V,B toD 80 dB 7 R L = 2KΩ,VI= ±10V,C toA 80 dB 7 R L = 2KΩ,VI= ±10V,C toB 80 dB 7 R L = 2KΩ,VI= ±10V,C toD 80 dB 7 R L = 2KΩ,VI= ±10V,D toA 80 dB 7 R L = 2KΩ,VI= ±10V,D toB 80 dB 7 R L = 2KΩ,VI= ±10V,D toC 80 dB 7 ±tS SettlingTime 1,50AV = 1 nS 120 LF147JAN ElectricalCharacteristicsDriftValues The followingconditionsapply,unlessotherwisespecified:DC ±VCC = ±15V,VCM = 0V,“Deltacalculationsperformedon JAN S and QMLV devicesatgroupB,subgroup5 only” Sub-Symbol Parameters Conditions Notes Min Max Unit groups VIO InputOffsetVoltage +VCC = 15V,-VCC = -15V, -1.0 1.0 mV 1 VCM = 0V +IIB InputBiasCurrent +VCC = 15V,-VCC = -15V, -0.1 0.1 nA 1 VCM = 0V -IIB InputBiasCurrent +VCC = 15V,-VCC = -15V, -0.1 0.1 nA 1 VCM = 0V Copyright© 2005–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:LF147JAN

SNOSAJ9A –APRIL 2005–REVISED MARCH 2013 www.ti.com TypicalPerformance Characteristics InputBias Current InputBias Current Figure3. Figure4. PositiveCommon-Mode Supply Current InputVoltageLimit Figure5. Figure6. NegativeCommon-Mode InputVoltageLimit PositiveCurrentLimit Figure7. Figure8.

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www.ti.com SNOSAJ9A –APRIL 2005–REVISED MARCH 2013 TypicalPerformance Characteristics(continued) NegativeCurrentLimit Output VoltageSwing Figure9. Figure10. Output VoltageSwing Gain Bandwidth Figure11. Figure12. Bode Plot Slew Rate Figure13. Figure14. Copyright© 2005–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:LF147JAN

SNOSAJ9A –APRIL 2005–REVISED MARCH 2013 www.ti.com TypicalPerformance Characteristics(continued) UndistortedOutput Voltage Distortionvs Frequency Swing Figure15. Figure16. Open Loop Frequency Common-Mode Rejection Response Ratio Figure17. Figure18. Power Supply Rejection EquivalentInputNoise Ratio Voltage Figure19. Figure20.

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www.ti.com SNOSAJ9A –APRIL 2005–REVISED MARCH 2013 TypicalPerformance Characteristics(continued) Open Loop VoltageGain Output Impedance Figure21. Figure22. InverterSettlingTime Figure23. Pulse Response R L=2 kΩ,C L=10 pF Small SignalInverting Small SignalNon-Inverting Figure24. Figure25. Copyright© 2005–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:LF147JAN

SNOSAJ9A –APRIL 2005–REVISED MARCH 2013 www.ti.com Pulse Response (continued) R L=2 kΩ,C L=10 pF Large SignalInverting Large SignalNon-Inverting Figure26. Figure27. CurrentLimit(RL=100Ω) Figure28.

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www.ti.com SNOSAJ9A –APRIL 2005–REVISED MARCH 2013 APPLICATION HINTS The LF147 isan op amp withan internallytrimmed inputoffsetvoltageand JFET inputdevices(BI-FETII). These JFETs have largereversebreakdown voltagesfrom gate to sourceand draineliminatingthe need for clampsacrosstheinputs.Therefore,largedifferentialinputvoltagescan easilybe accommodated withouta large increaseininputcurrent.The maximum differentialinputvoltageisindependentofthesupplyvoltages.However, neitheroftheinputvoltagesshouldbe allowedtoexceed thenegativesupplyas thiswillcause largecurrentsto flowwhichcan resultina destroyedunit. Exceeding the negativecommon-mode limiton eitherinputwillforcethe outputto a high state,potentially causinga reversalofphase totheoutput.Exceedingthenegativecommon-mode limiton bothinputswillforce the amplifieroutputto a highstate.In neithercase does a latchoccursinceraisingthe inputback withinthe common-mode rangeagainputstheinputstageand thustheamplifierina normaloperatingmode. Exceedingthepositivecommon-mode limiton a singleinputwillnotchange thephase oftheoutput;however,if bothinputsexceed thelimit,theoutputoftheamplifierwillbe forcedtoa highstate. The amplifierswilloperatewitha common-mode inputvoltageequaltothepositivesupply;however,thegain bandwidthand slewratemay be decreasedinthiscondition.When thenegativecommon-mode voltageswings towithin3V ofthenegativesupply,an increaseininputoffsetvoltagemay occur. Each amplifierisindividuallybiasedby a zenerreferencewhichallowsnormalcircuitoperationon ±4.5V power supplies.Supplyvoltageslessthanthesemay resultinlowergainbandwidthand slewrate. The LF147 willdrivea 2 kΩ loadresistanceto±10V overthefulltemperaturerange.Iftheamplifierisforcedto driveheavierloadcurrents,however,an increaseininputoffsetvoltagemay occuron thenegativevoltageswing and finallyreachan activecurrentlimiton bothpositiveand negativeswings. Precautionsshouldbe takentoensurethatthepower supplyfortheintegratedcircuitneverbecomes reversedin polarityorthattheunitisnotinadvertentlyinstalledbackwardsina socketas an unlimitedcurrentsurgethrough theresultingforwarddiodewithintheIC couldcause fusingoftheinternalconductorsand resultina destroyed unit. As withmost amplifiers,careshouldbe takenwithleaddress,component placementand supplydecouplingin ordertoensurestability.For example,resistorsfromtheoutputtoan inputshouldbe placedwiththebody close to the inputto minimize“pick-up” and maximize the frequencyof the feedback pole by minimizingthe capacitancefromtheinputtoground. A feedbackpoleiscreatedwhen the feedbackaround any amplifierisresistive.The parallelresistanceand capacitancefromtheinputofthedevice(usuallytheinvertinginput)toAC groundsetthefrequencyofthepole. Inmany instancesthefrequencyofthispoleismuch greaterthantheexpected3 dB frequencyoftheclosed loopgainand consequentlythereisnegligibleeffecton stabilitymargin.However, ifthefeedbackpoleisless thanapproximately6 timestheexpected3 dB frequencya leadcapacitorshouldbe placedfromtheoutputtothe inputoftheop amp. The valueoftheadded capacitorshouldbe such thattheRC timeconstantofthiscapacitor and theresistanceitparallelsisgreaterthanorequaltotheoriginalfeedbackpoletimeconstant. Copyright© 2005–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:LF147JAN

SNOSAJ9A –APRIL 2005–REVISED MARCH 2013 www.ti.com TypicalApplications Figure29. DigitallySelectablePrecisionAttenuator Allresistors1% tolerance

  • Accuracyofbetterthan0.4% withstandard1% valueresistors No offsetadjustmentnecessary
  • Expandabletoany number ofstages
  • Veryhighinputimpedance VOA1 A2 A3 Attenuation 0 0 0 0 0 0 1 −1 dB 0 1 0 −2 dB 0 1 1 −3 dB 1 0 0 −4 dB 1 0 1 −5 dB 1 1 0 −6 dB 1 1 1 −7 dB

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www.ti.com SNOSAJ9A –APRIL 2005–REVISED MARCH 2013 Figure30. Long Time IntegratorwithReset,Hold and StartingThresholdAdjustment

  • VO startsfromzeroand isequaltotheintegraloftheinputvoltagewithrespecttothethresholdvoltage:
  • Outputstartswhen VIN ≥ VTH
  • SwitchS1 permitsstoppingand holdingany outputvalue
  • SwitchS2 resetssystemtozero Figure31. UniversalStateVariableFilter Forcircuitshown: fO =3 kHz,fNOTCH =9.5kHz Q=3.4 Passband gain: Highpass– 0.1 Bandpass – 1 Lowpass – 1 Notch– 10
  • fo× Q ≤ 200 kHz
  • 10V peak sinusoidaloutputswingwithoutslewlimitingto200 kHz
  • See LM148 datasheetfordesignequations Copyright© 2005–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:LF147JAN

SNOSAJ9A –APRIL 2005–REVISED MARCH 2013 www.ti.com Date Revision Section Originator Changes Released 04/18/05 A New Releaseintocorporateformat L.Lytle 1 MDS datasheetsconvertedintoone Corp. datasheetformat.MJLF147 –X rev1B1 MDS willbe archived 03/20/13 A All Changed layoutofNationalData SheettoTI format

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www.ti.com 7-Nov-2014 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples JL147BCA ACTIVE CDIP J 14 25 TBD Call TI Call TI -55 to 125 JL147BCA JM38510/11906BCA Q JM38510/11906BCX ACTIVE CDIP J 14 TBD Call TI Call TI -55 to 125 M38510/11906BCX ACTIVE CDIP J 14 TBD Call TI Call TI -55 to 125 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

www.ti.com 7-Nov-2014 Addendum-Page 2 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

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