LF147JAN TI1 | Alldatasheet
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LF147JAN Wide Bandwidth Quad JFET Input Operational Amplifier Literature Number: SNOSAJ9
Wide Bandwidth Quad JFET Input Operational Amplifier General Description The LF147 is a low cost, high speed quad JFET input operational amplifier with an internally trimmed input offset voltage (BI-FET II ™ technology). The device requires a low supply current and yet maintains a large gain bandwidth product and a fast slew rate. In addition, well matched high voltage JFET input devices provide very low input bias and offset currents. The LF147 is pin compatible with the stan- dard LM148. This feature allows designers to immediately upgrade the overall performance of existing LF148 and LM124 designs. The LF147 may be used in applications such as high speed integrators, fast D/A converters, sample-and-hold circuits and many other circuits requiring low input offset voltage, low input bias current, high input impedance, high slew rate and wide bandwidth. The device has low noise and offset voltage drift.
Features
j Internally trimmed offset voltage: 5 mV max j Low input bias current: 50 pA Typ. j Low input noise current: 0.01 pA/ √Hz Typ. j Wide gain bandwidth: 4 MHz Typ. j High slew rate: 13 V/µs Typ. j Low supply current: 7.2 mA Typ. j High input impedance: 10 12Ω Typ. j Low total harmonic distortion: AV = 10, RL = 10KΩ,V O = 20VP-P BW = 20Hz — 20KHz ≤0.02% Typ. j Low 1/f noise corner: 50 Hz Typ. j Fast settling time to 0.01%: 2 µs Typ.
Ordering Information
NS Part Number JAN Part Number NS Package Number Package Description JL147BCA JM38510/11906BCA J14A 14LD CERDIP Connection Diagram Dual-In-Line Package 20129801 Top View See NS Package Number J14A BI-FET II™ is a trademark of National Semiconductor Corporation. April 2005 LF147JAN Wide Bandwidth Quad JFET Input Operational Amplifier © 2005 National Semiconductor Corporation DS201298 www.national.com
1⁄4 Quad 20129813 Detailed Schematic 20129809 LF147JAN www.national.com 2
Absolute Maximum Ratings(Note 1) Supply Voltage ±18V Differential Input Voltage ±30V Input Voltage Range (Note 2) ±15V Output Short Circuit Duration (Note 3) Continuous Power Dissipation (Notes 4, 5) 900 mW T J max 150˚C θJA CERDIP 70˚C/W Operating Temperature Range −55˚C ≤ TA ≤ 125˚C Storage Temperature Range −65˚C ≤ TA ≤ 150˚C Lead Temperature (Soldering, 10 sec.) 260˚C ESD (Note 6) 900V Recommended Operating Conditions Supply Voltage Range ±5V to ±15V Quality Conformance Inspection Mil-Std-883, Method 5005 - Group A Subgroup Description Temp (˚C)
1 Static tests at 25
2 Static tests at 125
3 Static tests at -55
4 Dynamic tests at 25
5 Dynamic tests at 125
6 Dynamic tests at -55
7 Functional tests at 25
8A Functional tests at 125 8B Functional tests at -55
9 Switching tests at 25
10 Switching tests at 125
11 Switching tests at -55
12 Settling Time at 25
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The following conditions apply, unless otherwise specified: V CC = ±15V, VCM =0 V Symbol Parameter Conditions Notes Min Max Unit Sub- groups VIO Input Offset Voltage +VCC = 26V, -VCC = -4V, VCM = -11V -5.0 5.0 mV 1 -7.0 7.0 mV 2, 3 +VCC = 4V, -VCC = -26V, VCM = 11V -5.0 5.0 mV 1 -7.0 7.0 mV 2, 3 +VCC = 15V, -VCC = -15V, VCM =0 V -5.0 5.0 mV 1 -7.0 7.0 mV 2, 3 +VCC = 5V, -VCC = -5V, VCM =0 V -5.0 5.0 mV 1 -7.0 7.0 mV 2, 3 ±IIB Input Bias Current +VCC = 26V, -VCC = -4V, VCM = -11V -0.4 0.2 nA 1 -10 50 nA 2 +VCC = 15V, -VCC = -15V, VCM =0 V -0.2 0.2 nA 1 -10 50 nA 2 +VCC = 4V, -VCC = -26V, VCM = 11V -0.2 1.2 nA 1 -10 70 nA 2 IIO Input Offset Current +VCC = 15V, -VCC = -15V, VCM =0 V -0.1 0.1 nA 1 -20 20 nA 2 +PSRR Power Supply Rejection Ratio -V CC = -15V, +VCC = 20V to 10V 80 dB 1, 2, 3 -PSRR Power Supply Rejection Ratio +V CC = 15V, -VCC = -20V to -10V 80 dB 1, 2, 3 CMRR Input Voltage Common Mode Rejection ±VCC = ±4V to ±26V, VCM = -11V to +11V 80 dB 1, 2, 3 +IOS Output Short Circuit Current +V CC = 15V, -VCC = -15V, VCM = -10V, t ≤ 25mS -80 mA 1, 2, 3 −IOS Output Short Circuit Current +V CC = 15V, -VCC = -15V, VCM = 10V, t ≤ 25mS 80 mA 1, 2, 3 ICC Supply Current +VCC = 15V, -VCC = -15V 14 mA 1, 2 16 mA 3 Delta VIO / Delta T Input Offset Voltage Temp. Sensitivity 25˚C ≤ TA ≤ +125˚C (Note 7) -30 30 µV/˚C 2 -55˚C ≤ TA ≤ 25˚C (Note 7) -30 30 µV/˚C 3 +VOP Output Voltage Swing +V CC = 15V, -VCC = -15V, RL=10KΩ,V CM = -15V 1 2 V 4 ,5 ,6 +VCC = 15V, -VCC = -15V, RL=2KΩ,V CM = -15V 1 0 V 4 ,5 ,6 -VOP Output Voltage Swing +V CC = 15V, -VCC = -15V, RL=10KΩ,V CM = 15V - 1 2 V 4 ,5 ,6 +VCC = 15V, -VCC = -15V, RL =2 KΩ,V CM = 15V - 1 0 V 4 ,5 ,6 +AVS Open Loop Voltage Gain +VCC = 15V, -VCC = -15V, RL =2 KΩ,V O =0t o1 0 V
50 V/mV 4
25 V/mV 5, 6
−AVS Open Loop Voltage Gain +VCC = 15V, -VCC = -15V, RL =2 KΩ,V O = 0 to -10V AVS Open Loop Voltage Gain +V CC = 5V, -VCC = -5V, RL = 10KΩ,V O = ±2V 20 V/mV 4, 5, 6 LF147JAN www.national.com 4
The following conditions apply, unless otherwise specified: V CC = ±15V Symbol Parameter Conditions Notes Min Max Unit Sub- groups +SR Slew Rate VI = -5V to +5V 7 V/µS 7
5 V/µS 8A, 8B
-SR Slew Rate VI = +5V to -5V 7 V/µS 7 TRTR Transient Response Rise Time AV=1, V I=50mV, CL= 100pF, RL=2KΩ 200 nS 7, 8A, 8B TROS Transient Response Overshoot AV=1, V I=50mV, CL= 100pF, RL=2KΩ 40 % 7, 8A, 8B NIBB Noise Broadband BW = 10Hz to 15KHz, R S =0 Ω 15 µV RMS 7 NIPC Noise Popcorn BW = 10Hz to 15KHz, RS = 100KΩ 80 µV PK 7 CS Channel Separation R L =2 KΩ 80 dB 7 RL =2 KΩ,V I = ±10V, A to B 80 dB 7 RL =2 KΩ,V I = ±10V, A to C 80 dB 7 RL =2 KΩ,V I = ±10V, A to D 80 dB 7 RL =2 KΩ,V I = ±10V, B to A 80 dB 7 RL =2 KΩ,V I = ±10V, B to C 80 dB 7 RL =2 KΩ,V I = ±10V, B to D 80 dB 7 RL =2 KΩ,V I = ±10V, C to A 80 dB 7 RL =2 KΩ,V I = ±10V, C to B 80 dB 7 RL =2 KΩ,V I = ±10V, C to D 80 dB 7 RL =2 KΩ,V I = ±10V, D to A 80 dB 7 RL =2 KΩ,V I = ±10V, D to B 80 dB 7 RL =2 KΩ,V I = ±10V, D to C 80 dB 7 ±tS Settling Time A V = 1 1,500 nS 12 Drift Values The following conditions apply, unless otherwise specified: DC ±VCC = ±15V, VCM = 0V, “Delta calculations performed on JAN S and QMLV devices at group B, subgroup 5 only” Symbol Parameters Conditions Notes Min Max Unit Sub- groups VIO Input Offset Voltage +VCC = 15V, -VCC = -15V, VCM =0 V -1.0 1.0 mV 1 +IIB Input Bias Current +V CC = 15V, -VCC = -15V, VCM =0 V -0.1 0.1 nA 1 -IIB Input Bias Current +V CC = 15V, -VCC = -15V, VCM =0 V -0.1 0.1 nA 1 Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characterist ics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the lis ted test conditions. Note 2: Unless otherwise specified the absolute maximum negative input voltage is equal to the negative power supply voltage. Note 3: Any of the amplifier outputs can be shorted to ground indefinitely, however, more than one should not be simultaneously shorted as the maximum junction temperature will be exceeded. Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax (maximum junction temperature), θJA (Package junction to ambient thermal resistance), and TA (ambient temperature). The maximum allowable power dissipation at any temperature is PDmax =( TJmax —T A)/ θJA or the number given in the Absolute Maximum Ratings, whichever is lower. Note 5: Max. Power Dissipation is defined by the package characteristics. Operating the part near the Max. Power Dissipation may cause the part to operate outside guaranteed limits. Note 6: Human body model, 1.5 k Ω in series with 100 pF. Note 7: Calculated parameters. LF147JAN www.national.com5
Typical Performance Characteristics Input Bias Current Input Bias Current 20129814 20129815 Supply Current Positive Common-Mode Input Voltage Limit 20129816 20129817 Negative Common-Mode Input Voltage Limit Positive Current Limit 20129818 20129819 LF147JAN www.national.com 6
Typical Performance Characteristics (Continued) Negative Current Limit Output Voltage Swing 20129820 20129821 Output Voltage Swing Gain Bandwidth 20129822 20129823 Bode Plot Slew Rate 20129824 20129825 LF147JAN www.national.com7
Typical Performance Characteristics (Continued) Distortion vs Frequency Undistorted Output Voltage Swing 20129826 20129827 Open Loop Frequency Response Common-Mode Rejection Ratio 20129828 20129829 Power Supply Rejection Ratio Equivalent Input Noise Voltage 20129830 20129831 LF147JAN www.national.com 8
Typical Performance Characteristics (Continued) Open Loop Voltage Gain Output Impedance 20129832 20129833 Inverter Settling Time 20129834 LF147JAN www.national.com9
Pulse Response RL=2 kΩ,C L=10 pF Small Signal Inverting 20129804 Small Signal Non-Inverting 20129805 Large Signal Inverting 20129806 Large Signal Non-Inverting 20129807 Current Limit (RL=100Ω) 20129808 LF147JAN www.national.com 10
The LF147 is an op amp with an internally trimmed input offset voltage and JFET input devices (BI-FET II). These JFETs have large reverse breakdown voltages from gate to source and drain eliminating the need for clamps across the inputs. Therefore, large differential input voltages can easily be accommodated without a large increase in input current. The maximum differential input voltage is independent of the supply voltages. However, neither of the input voltages should be allowed to exceed the negative supply as this will cause large currents to flow which can result in a destroyed unit. Exceeding the negative common-mode limit on either input will force the output to a high state, potentially causing a reversal of phase to the output. Exceeding the negative common-mode limit on both inputs will force the amplifier output to a high state. In neither case does a latch occur since raising the input back within the common-mode range again puts the input stage and thus the amplifier in a normal operating mode. Exceeding the positive common-mode limit on a single input will not change the phase of the output; however, if both inputs exceed the limit, the output of the amplifier will be forced to a high state. The amplifiers will operate with a common-mode input volt- age equal to the positive supply; however, the gain band- width and slew rate may be decreased in this condition. When the negative common-mode voltage swings to within 3V of the negative supply, an increase in input offset voltage may occur. Each amplifier is individually biased by a zener reference which allows normal circuit operation on ±4.5V power sup- plies. Supply voltages less than these may result in lower gain bandwidth and slew rate. The LF147 will drivea2k Ω load resistance to ±10V over the full temperature range. If the amplifier is forced to drive heavier load currents, however, an increase in input offset voltage may occur on the negative voltage swing and finally reach an active current limit on both positive and negative swings. Precautions should be taken to ensure that the power supply for the integrated circuit never becomes reversed in polarity or that the unit is not inadvertently installed backwards in a socket as an unlimited current surge through the resulting forward diode within the IC could cause fusing of the internal conductors and result in a destroyed unit. As with most amplifiers, care should be taken with lead dress, component placement and supply decoupling in order to ensure stability. For example, resistors from the output to an input should be placed with the body close to the input to minimize “pick-up” and maximize the frequency of the feed- back pole by minimizing the capacitance from the input to ground. A feedback pole is created when the feedback around any amplifier is resistive. The parallel resistance and capacitance from the input of the device (usually the inverting input) to AC ground set the frequency of the pole. In many instances the frequency of this pole is much greater than the expected 3 dB frequency of the closed loop gain and consequently there is negligible effect on stability margin. However, if the feed- back pole is less than approximately 6 times the expected 3 dB frequency a lead capacitor should be placed from the output to the input of the op amp. The value of the added capacitor should be such that the RC time constant of this capacitor and the resistance it parallels is greater than or equal to the original feedback pole time constant. LF147JAN www.national.com11
Digitally Selectable Precision Attenuator 20129810 All resistors 1% tolerance Accuracy of better than 0.4% with standard 1% value resistors No offset adjustment necessary Expandable to any number of stages Very high input impedance A1 A2 A3 V O Attenuation 000 0 001 − 1 d B 010 − 2 d B 011 − 3 d B 100 − 4 d B 101 − 5 d B 110 − 6 d B 111 − 7 d B LF147JAN www.national.com 12
Typical Applications (Continued) Long Time Integrator with Reset, Hold and Starting Threshold Adjustment 20129811 VO starts from zero and is equal to the integral of the input voltage with respect to the threshold voltage: Output starts when V IN ≥ VTH Switch S1 permits stopping and holding any output value Switch S2 resets system to zero LF147JAN www.national.com13
Typical Applications (Continued) Universal State Variable Filter 20129812 For circuit shown: fO=3 kHz, fNOTCH=9.5 kHz Q=3.4 Passband gain: Highpass — 0.1 Bandpass — 1 Lowpass — 1 Notch — 10 foxQ≤200 kHz 10V peak sinusoidal output swing without slew limiting to 200 kHz See LM148 data sheet for design equations LF147JAN www.national.com 14
Revision Section Originator Changes 04/18/05 A New Release into corporate format L. Lytle 1 MDS datasheets converted into one Corp. datasheet format. MJLF147–X rev 1B1 MDS will be archived LF147JAN www.national.com15
Physical Dimensions inches (millimeters) unless otherwise noted Ceramic Dual-In-Line Package (J) National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. For the most current product information visit us at www.national.com. LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. BANNED SUBSTANCE COMPLIANCE National Semiconductor manufactures products and uses packing materials that meet the provisions of the Customer Products Stewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification (CSP-9-111S2) and contain no ‘‘Banned Substances’’ as defined in CSP-9-111S2. National Semiconductor Americas Customer Support Center Email: new.feedback@nsc.com Tel: 1-800-272-9959 National Semiconductor Europe Customer Support Center Fax: +49 (0) 180-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 National Semiconductor Asia Pacific Customer Support Center Email: ap.support@nsc.com National Semiconductor Japan Customer Support Center Fax: 81-3-5639-7507 Email: jpn.feedback@nsc.com Tel: 81-3-5639-7560 www.national.com LF147JAN Wide Bandwidth Quad JFET Input Operational Amplifier
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