IS-2981RH RENESAS | Alldatasheet

Document overview

  • Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
  • PDF pages: 4

Technical content

Features

  • Electrically screened to SMD # 5962-00520
  • QML qualified per MIL-PRF-38535 requirements
  • R a d i a t i o n e n v i r o n m e n t - Single event latch-up immune DI process
  • Output clamp diode, V

Applications

  • Drivers for various loads - Relays, solenoids and motors
  • Reliable replacement of discrete solutions
  • Interfacing between low-level logic and high-current loads Pin Configuration IS1-2981RH-Q, IS1-2981EH-Q (CDIP2-T18) TOP VIEW

1 OUT 1

V CC

IS-2981RH, IS-2981EH FN4869 Rev 1.00 Page 2 of 4 Jun 24, 2013

Ordering Information

(Note 3) INTERNAL MKT.NUMBER (Notes 1, 2) PART MARKING TEMP. RANGE (°C) PACKAGE (RoHS Compliant) PKG. DWG. # 5962R0052001VVC IS1-2981RH-Q Q 5962R00 52001VVC -55 to +125 18 Ld SBDIP D18.3 5962R0052002VVC IS1-2981EH-Q Q 5962R00 52002VVC -55 to +125 18 Ld SBDIP D18.3 5962R0052001QVC IS1-2981RH-8 Q 5962R00 52001QVC -55 to +125 18 Ld SBDIP D18.3 5962R0052001V9A IS0-2981RH-Q -55 to +125 Die 5962R0052002V9A IS0-2981EH-Q -55 to +125 Die D18.3 IS1-2981RH/PROTO IS1-2981RH/PROTO IS1-2981RH/PROTO -55 to +125 18 Ld SBDIP D18.3 NOTE: 1. These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. 2. For Moisture Sensitivity Level (MSL), please see device information page for IS-2981RH, IS-2981EH. For more information on MSL, please see tech brief TB363. 3. Specifications for Rad Hard QML devices are controlled by the Defense Logistics Agency Land and Maritime (DLA). The SMD numbers listed in the “Ordering Information” table on page 2 must be used when ordering.

IS-2981RH, IS-2981EH FN4869 Rev 1.00 Page 3 of 4 Jun 24, 2013 Die Characteristics DIE DIMENSIONS: 2667µm x 5131µm (105 mils x 202 mils) Thickness: 483µm ±25.4µm (19 mils ±1 mil) INTERFACE MATERIALS Glassivation Type: Nitride (Si3N4) over Silox (SiO2) Nitride Thickness: 4.0kÅ ± 1.0kÅ Silox Thickness: 12.0kÅ ±4.0kÅ Metallization Top Metal 2: Ti/AlCu Thickness: 1.6µm ±0.02µm Metal 1: Ti/AlCu Thickness: 0.8µm ±0.01µm Substrate HVTDLM, Bonded Wafer, Dielectric Isolation Backside Finish Silicon ASSEMBLY RELATED INFORMATION Substrate Potential Must be tied to GND. ADDITIONAL INFORMATION Worst Case Current Density <1.0 x 105 A/cm2 Transistor Count Metallization Mask Layout IS-2981RH, IS-2981EH 87 65 4 3 2 1 11 12 13 14 15 16 17 18 10A NOTES: 4. Pad numbers correspond to package pin functions. 5. Bond to all four pad 9 locations for V CC current sharing purposes. 6. Bond to both pad 10 locations for GND current sharing purposes. 7. Pad 10A is not used in die applications. 8. Die backside must be connected to GND.

FN4869 Rev 1.00 Page 4 of 4 Jun 24, 2013 IS-2981RH, IS-2981EH Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com For additional products, see www.intersil.com/en/products.html © Copyright Intersil Americas LLC 2000-2013. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. Ceramic Dual-In-Line Metal Seal Packages (SBDIP) NOTES: 1. Index area: A notch or a pin one identification mark shall be locat- ed adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of t he finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. Dimension Q shall be measured from the seating plane to the base plane. 6. Measure dimension S1 at all four corners. 7. Measure dimension S2 from the top of the ceramic body to the nearest metallization or lead. 8. N is the maximum number of terminal positions. 9. Braze fillets shall be concave. 10. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 11. Controlling dimension: INCH. bbb C A - BS c Q L A SEATING BASE D PLANE PLANE S S -D--A- -C- eA -B- aaa C A - BM DS Sccc C A - BM DS S D E b A e M (c) (b) SECTION A-A BASE LEAD FINISH METAL eA/2 M A D18.3 MIL-STD-1835 CDIP2-T18 (D-6, CONFIGURATION C)

18 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE

A - 0.200 - 5.08 - b 0.014 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 E 0.220 0.310 5.59 7.87 - e 0.100 BSC 2.54 BSC - eA 0.300 BSC 7.62 BSC - eA/2 0.150 BSC 3.81 BSC - L 0.125 0.200 3.18 5.08 - Q 0.015 0.070 0.38 1.78 5 S1 0.005 - 0.13 - 6 S2 0.005 - 0.13 - 7  90o 105o 90o 105o - aaa - 0.015 - 0.38 - bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - M - 0.0015 - 0.038 2 N1 8 1 8 8 Rev. 0 5/18/94