IS-1845ASRH_08 INTERSIL | Alldatasheet
Document overview
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Technical content
Features
- Electrically Screened to DSCC SMD # 5962-01509
- QML Qualified per MIL-PRF-38535 Requirements
- Radiation Environment - SEU Cross-Section at 89MeV/mg/cm 2. . . . 5 x 10-6cm2
- Undervoltage Lockout . . 8.8V Start (Typ), 8.2V Stop (Typ)
Applications
- Current-Mode Switch ing Power Supplies
- Control of High Current FET Drivers
- Motor Speed and Direction Control TM Pinouts IS7-1845ASRH (8 LD CDIP2-T8 SBDIP) TOP VIEW IS9-1845ASRH (18 LD FLATPACK) TOP VIEW NOTES: 1. Grounding the Comp pin does not inhibit the output. The output may be inhibited by applying >1.2V to the ISENSE pin. 2. This part should be operated with C t = 3.3nF and Rt = 10k timing components only. COMP VFB ISENSE RTCT VREF VCC OUT GND COMP VFB NC NC NC ISENSE RTCT NC 21 7 VREF VCC VC OUT NC GND OSCGND NC NC1 18NC Data Sheet September 25, 2008NOT RECOMMENDED FOR NEW DESIGNS RECOMMENDED REPLACEMENT PART ISL7884XARH
2 FN9001.4 September 25, 2008
Ordering Information
MKT. NUMBER TEMP. RANGE (°C) PACKAGE PKG. DWG. # 5962F0150901V9A IS0-1845ASRH-Q -50 to +125 IS0-1845ASRH/Sample IS0-1845ASRH/Sample -50 to +125 5962F0150901VPC IS7-1845ASRH-Q -50 to +125 8 Ld SBDIP D8.3 5962F0150901VPC IS7-1845ASRH-QS9000 -50 to +125 8 Ld SBDIP D8.3 5962F0150901QPC IS7-1845ASRH-8 -50 to +125 8 Ld SBDIP D8.3 5962F0150901QPC IS7-1845ASRH-8S9000 -50 to +125 8 Ld SBDIP D8.3 5962F0150901VXC IS9-1845ASRH-Q -50 to +125 18 Ld Flatpack K18.B 5962F0150901VXC IS9-1845ASRH-QS9000 -50 to +125 18 Ld Flatpack K18.B 5962F0150901QXC IS9-1845ASRH-8 -50 to +125 18 Ld Flatpack K18.B IS7-1845ASRH/Proto IS7-1845ASRH/Proto -50 to +125 8 Ld SBDIP D8.3 IS9-1845ASRH/Proto IS9-1845ASRH/Proto -50 to +125 18 Ld Flatpack K18.3 Typical Performance Curves FIGURE 1. OSCILLATOR FREQUENCY vs R t and Ct FIGURE 2. MAXIMUM DUTY CYCLE vs R t
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnishe d by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN9001.4 September 25, 2008 Die Characteristics DIE DIMENSIONS 3090µm x 4080µm (121.6 mils x 159.0 mils) Thickness: 483µm ± 25.4µm (19 mils ± 1 mil) INTERFACE MATERIALS Glassivation Type: Phosphorus Silicon Glass (PSG) Thickness: 8.0kA ± 1.0kA Top Metallization Type: AlSiCu Thickness: 16.0kA ± 2kA Substrate Radiation Hardened Silicon Gate, Dielectric Isolation Backside Finish Silicon ASSEMBLY RELATED INFORMATION Substrate Potential Unbiased (DI) ADDITIONAL INFORMATION Worst Case Current Density <2.0 x 105 A/cm2 Transistor Count 582 Metallization Mask Layout IS-1845ASRH NOTES: 3. Both the GND pads must be bonded to ground. 4. The OUT double-sized bond pad must be double bonded for current sharing purposes. 5. The OSCGND double-sized bond pad must be double bonded to ground for current sharing purposes. VFB COMP VREF VC VCCOUT GND GND OSCGND RTCT ISENSE IS-1845ASRH