IS-1825ASRH INTERSIL | Alldatasheet
Document overview
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- PDF pages: 3
Technical content
Features
- Electrically Screened to DSCC SMD # 5962-02511
- QML Qualified per MIL-PRF-38535 Requirements
- Radiation Environment
- Undervoltage Lockout
- Improved Soft-Start Function Compared with Commercial 1825A/1823A Types
- Pulse-by-Pulse Current Limiting
- Latched Overcurrent Comparator with Full Cycle Restart
- Programmable Leading Edge Blanking
Applications
- Voltage or Current-Mode Switching Power Supplies
- Control of High Current MOSFET Drivers
- Motor Speed and Direction Control Pinouts IS1-1825ASRH, ISL71823ASRHQD (CDIP2-T16 SBDIP) TOP VIEW IS9-1825ASRH, ISL71823ASRHQF (CDFP4-F20 FLATPACK) TOP VIEW INV NON-INV E/A OUT CLK/LEB RT CT SS RAMP VREF OUT B VC PGND OUT A GND ILIM/SD VCC 12 0 NC INV NON-INV E/A OUT CLK/LEB RT CT RAMP SS NC VREF VCC OUT B PGND VC VC PGND OUT A GND ILIM/SD Data Sheet September 25, 2008 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002, 2005, 2008. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
2 FN9065.3 September 25, 2008
Ordering Information
MKT. NUMBER TEMP . RANGE (°C) PACKAGE PKG DWG. # IS0-1825ASRH/SAMPLE IS0-1825ASRH/SAMPLE -50 to +125 5962F0251101V9A IS0-1825ASRH-Q -50 to +125 5962F0251101QEC IS1-1825ASRH-8 -50 to +125 16 Ld SBDIP D16.3 5962F0251101QXC IS9-1825ASRH-8 -50 to +125 20 Ld Flatpack K20.A 5962F0251101VEC IS1-1825ASRH-Q -50 to +125 16 Ld SBDIP D16.3 5962F0251101VXC IS9-1825ASRH-Q -50 to +125 20 Ld Flatpack K20.A IS1-1825ASRH/Proto IS1-1825ASRH/Proto -50 to +125 16 Ld SBDIP D16.3 IS9-1825ASRH/Proto IS9-1825ASRH/Proto -50 to +125 20 Ld Flatpack K20.A 5962F0251102QEC ISL71823ASRHQD -50 to +125 16 Ld SBDIP D16.3 5962F0251102QXC ISL71823ASRHQF -50 to +125 20 Ld Flatpack K20.A 5962F0251102VEC ISL71823ASRHVD -50 to +125 16 Ld SBDIP D16.3 5962F0251102VXC ISL71823ASRHVF -50 to +125 20 Ld Flatpack K20.A ISL71823ASRHD/Proto ISL71823ASRHD/Proto -50 to +125 16 Ld SBDIP D16.3 ISL71823ASRHF/Proto ISL71823ASRHF/Proto -50 to +125 20 Ld Flatpack K20.A Typical Performance Curves FIGURE 1. OSCILLATOR FREQUENCY vs R t and Ct FIGURE 2. MAXIMUM DUTY CYCLE vs R t
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnishe d by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN9065.3 September 25, 2008 Die Characteristics DIE DIMENSIONS: 4310µm x 5840µm (170 mils x 230 mils) Thickness: 483µm ± 25.4µm (19 mils ± 1 mil) INTERFACE MATERIALS Glassivation Type: Phosphorus Silicon Glass (PSG) Thickness: 8.0kA ± 1.0kA Top Metallization Type: AlSiCu Thickness: 16.0kA ± 2kA Substrate: Radiation Hardened Silicon Gate, Dielectric Isolation Backside Finish: Silicon ASSEMBLY RELATED INFORMATION Substrate Potential: Unbiased (DI) ADDITIONAL INFORMATION Worst Case Current Density: <2.0 x 105 A/cm2 Transistor Count: 585 Metallization Mask Layout IS-1825ASRH/ISL71823ASRH VC VC VREF INV NON-INV E/A OUT CLK/LEB CT RAMP SS ILIM/SD OGND GND OUT A PGND PGND OUT B VCC Notes: 1. Both the OGND (oscillator ground) and the GND (cont rol circuit ground) pads must be bonded to ground. These pads are both bonded to the GND pin on the packaged devices. 2. All double-sized bond pads must be double bonded for current sharing purposes. RT RT IS-1825ASRH, ISL71823ASRH