IPS4260L STMICROELECTRONICS | Alldatasheet

Document overview

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  • PDF pages: 29

Technical content

Datasheet sections

  • 1 Block diagram
  • 2 Pin description
  • 2.1 VCC
  • 2.2 PGND, SGND
  • 2.4 IN1, IN2, IN3, IN4
  • 2.5 LOAD1, LOAD2, LOAD3, LOAD4
  • 2.6 Open load in off-state
  • 2.7 FLT
  • 2.8 ILIM
  • 2.9 CoD
  • 3 Absolute maximum ratings
  • 4 Electrical characteristics
  • 5 Power stage logic
  • 6 Protection and diagnostic
  • 6.1 Undervoltage lock-out
  • 6.2 Overtemperature
  • 6.3 Current limitation and cut-off
  • 6.4 Open load in off-state
  • 6.5 GND wire break protection
  • 6.6 VCC wire break protection
  • 7 Active clamp
  • 7.1 Fast current decay with TVS between VZ and supply rail
  • 7.2 Fast current decay with TVS between VZ and PGND
  • 8.1 HTSSOP20 package information
  • 9 Packaging information
  • 9.1 HTSSOP20 packaging information
  • 10 Ordering information

Features

  • 8 V to 50 V operating voltage range
  • Four independent protected channels
  • V CC undervoltage lock-out
  • High speed operation (t r, tf < 1 μs)
  • Programmable load current limitation level by external resistor
  • Typical operating load current: 0.5 A (per channel) / 2 A (one channel)
  • Thermally independent junction overtemperature protections
  • Programmable non-dissipative short-circuit protection (cut-off) by external resistor
  • Open load (off-state) and short-to-ground activated by external pull-down resistors
  • Fast demagnetization of inductive loads with integrated catch diodes clamping turn-off transients
  • Ground and V CC wire break protection
  • V CC overvoltage protection
  • Common open load diagnostic
  • Common thermal shutdown and overload diagnostic
  • Per channel thermal shutdown diagnostic
  • Designed to meet IEC 61131-2
  • Miniaturized HTSSOP20 package Application
  • Programmable logic control
  • Industrial PC peripheral input/output
  • Numerical control machines
  • General low-side switch applications

Description

The IPS4260L is a monolithic high speed (FSW up to 250 kHz) device, which can drive four independent capacitive, resistive or inductive loads with one side connected to supply voltage. The channels can be parallelized to reduce power dissipation. When connected to Vcc rail, four integrated catch diodes clamp the turn-off transients generated by inductive loads even with huge inductance; combined with proper external TVS connected to VCC or to GND the IC allows fast decay, too. Each channel is protected against overload or short circuit event: the intervention level can be set by an external resistor on ILIM pin . Built-in thermal shutdown protects the chip against overtemperature even in case of short-circuit. If enabled, the integrated cut-off protection features a non-dissipative protection in case of overload; it limits both the output average current value and, consequently, the device overheating. Cut-off delay/restart can be programmed by external resistors on CoD pin; it can be disabled by shorting CoD to GND. Product status link IPS4260L Product label Quad low-side intelligent power switch IPS4260L Datasheet DS12305 - Rev 5 - July 2021 For further information contact your local STMicroelectronics sales office.

Two common diagnostic open drains pins (OL, for open load and FLT for cut-off and thermal shutdown) together with the four open drain on each INx pin (cut-off and thermal shutdown) feature an extensive diagnostic of the chip. IPS4260L DS12305 - Rev 5 page 2/29

1 Block diagram

Figure 1. Block diagram

2 Pin description

Figure 2. Pin connection (top view) Table 1. Pin configuration

4 IN1 Channel 1 input / cut-off and thermal shutdown diagnostic Input/output

5 IN2 Channel 2 input / cut-off and thermal shutdown diagnostic Input/output

6 IN3 Channel 3 input / cut-off and thermal shutdown diagnostic Input/output

7 IN4 Channel 4 input / cut-off and thermal shutdown diagnostic Input/output

9 OL Cumulative power stage open load or short ground common diagnostic Output open

11 CoD

12 ILIM

14 LOAD4 Power stage, channel 4 Input

15 LOAD3 Power stage, channel 3 Input

16 LOAD2 Power stage, channel 2 Input

17 LOAD1 Power stage, channel 1 Input

2.1 VCC

IC supply voltage. This pin has to be connected to the supply rail of the application.

2.2 PGND, SGND

PGND stands for power ground and it is internally connected to the source of the integrated switches. SGND stands for signal ground and it is the reference level for the logic interface. SGND and PGND pins must be shorted on the application board. In order to reduce as much as possible the switching noises from PGND to SGND, the application board has to be designed with two different ground planes for SGND and PGND. The two ground planes have to be shorted by a dedicated net. 2.3 VZ These two pins (corresponding to the cathodes of the clamp diodes) must be shorted together on the application and connected directly to supply rail or, alternatively, connected by a Zener or TVS diode to supply rail or PGND. Connecting VZ pins directly to the supply rail implies that the inductive loads are demagnetized without fast decay option: in fact the VLOADx (voltage on LOADx pin) is forced to the forward voltage of the integrated clamp diodes. The connection by a Zener or TVS allows to drive loads requiring fast current decay (fast demagnetization). For the proper selection of the external Zener or TVS, please refer to Section 7.1 Fast current decay with TVS between VZ and supply rail and Section 7.2 Fast current decay with TVS between VZ and PGND Note: Leaving VZ pins floating, the integrated output voltage clamp is activated and the fast current decay capability is limited by the heatsink capability of the IC. See EAS in Table 2. Absolute maximum ratings.

2.4 IN1, IN2, IN3, IN4

These pins drive the power stage on pins LOAD1, LOAD2, LOAD3 and LOAD4. Besides an internal weak pull-down resistor (see Iinx in Table 7. Logic inputs), each IN1, IN2, IN3, IN4, is internally wired to an open drain transistor, used for diagnostic purposes, and must be driven through a series resistor. The open drain transistor is turned-on in case of thermal shutdown or cut-off protection of the relative channel (see Section 6.2 Overtemperature and Section 6.3 Current limitation and cut-off ).

2.5 LOAD1, LOAD2, LOAD3, LOAD4

Power stage load connection pins: integrated power transistor are in low-side configuration, so the load has to be connected between LOADx pin and supply rail. The power stage channels can be paralleled.

2.6 Open load in off-state

OL pin is used for diagnostic purpose and it is internally wired to an open drain transistor. If the open load feature is enabled (see Section 6.4 Open load in off-state) the open drain transistor is activated when LOADx is in off state and the open load threshold (VOLoff) is triggered (see Table 8. Protection and diagnostic ).

2.7 FLT

This pin is used for diagnostic purpose and it is internally wired to an open drain transistor. The open drain transistor is turned on in case of junction thermal shutdown or during the cut-off protection. IPS4260L VCC DS12305 - Rev 5 page 5/29

2.8 ILIM

This pin cannot be left floating and can be used to program the limitation current value through an external resistor (RILIM) see Table 8. Protection and diagnostic. The resistor RILIM has to be connected between ILIM and SGND pins. When the IPS4260L ICs are used in the same application, their ILIM pins cannot be wired together: each IC must be connected to its own resistor ( see Section 6.3 Current limitation and cut-off )

2.9 CoD

This pin cannot be left floating and can be used to program the cut-off delay time tcoff (see Table 8. Protection and diagnostic) through an external resistor (RCoD). The resistor RCoD has to be connected between CoD and SGND pins. The cut-off function can be completely disabled by shorting CoD pin to SGND: in this condition the power stage channel remains ON in limitation condition, supplying the current to the load until the input is forced LOW or the thermal shutdown threshold is triggered (see Section 6.3 Current limitation and cut-off ) IPS4260L ILIM DS12305 - Rev 5 page 6/29

3 Absolute maximum ratings

Table 2. Absolute maximum ratings operation under these conditions is not implied. All voltages are referenced to GND. Table 3. Thermal data

4 Electrical characteristics

(8 V < VCC < 50 V; -40 °C < TJ < 125 °C, unless otherwise specified) Table 4. Supply Table 5. Output stage Table 6. Switching (VCC = 24 V; RLOAD = 24 Ω, input rise time < 0.1 μs )

Electrical characteristics

Symbol Parameter Test conditions Min. Typ. Max. Unit VFAULT VVoltage drop on FAULT pin or INx pin IFLT = 5 mA VINx = 0 V, (TJX > TJSD or cut-off event) 0.1 IINX All digital input/output pin current VIN = 5 V 70 μA Table 8. Protection and diagnostic DS12305 - Rev 5 page 10/29

5 Power stage logic

Table 9. Power stage (LOADx pin) truth table Figure 5. Application circuit (fast decay enabled by TVS between Vz and supply rail)

6 Protection and diagnostic

The IC integrates several protections to ease the design of a robust application.

6.1 Undervoltage lock-out

after VCC exceeds the turn-on threshold (VUV(on)). Turn-on and turn-off thresholds are defined in Table 4. Supply.

6.2 Overtemperature

Table 8. Protection and diagnostic). The internal fault signal is set when the channel is OFF due to thermal fault. Note that the FLT pin reports the logic OR of the four output channels faults. Figure 8. Thermal protection signalization behavior on FLT

6.3 Current limitation and cut-off

limited up to 3 A (typical). For RILIM > 120 kΩ the current is anyway limited but the linearity is not guaranteed.

increases but linearity of equation 2 is not guaranteed. current limitation condition, until the related input becomes LOW or the thermal protection threshold is triggered. Figure 9. Cut-off signalization behavior on FLT

6.4 Open load in off-state

(RPD) between LOADx and PGND ground plane.

Figure 10. Open load off-state related INx pin, the fault condition is no longer detected. channels in parallel the total Ipu becomes 80uA).

6.5 GND wire break protection

circuit or an external TVS). stages are turned off independently of the input status.

is activated by active clamp as if the input had been deactivated. case of Vz pins connected by a TVS to ground layer. Figure 11. GND wire break

6.6 VCC wire break protection

as if the input had been deactivated. Figure 12. VCC wire break

VCC wire break protection is guaranteed when VZ floats or when VZ is connected to GND by a proper TVS, while it is limited (see below) when VZ is shorted to VCC. If VZ is connected to VCC by a TVS (with clamping voltage = VCL), then VCC wire break protection is limited by the following design rule: VCL > VL+ - (VLOAD+VD+VUVLO). IPS4260L VCC wire break protection DS12305 - Rev 5 page 17/29

7 Active clamp

Figure 13. VLOAD and ILOAD in case of slow demagnetization internal heatsink capability, see EAS in Table 2. Absolute maximum ratings . Figure 14. Active clamp equivalent principle schematic.

7.1 Fast current decay with TVS between VZ and supply rail

dissipate the power due to the demagnetization currents flowing from the active channels. Figure 15. VLOAD and ILOAD in case of fast demagnetization (fast decay)

7.2 Fast current decay with TVS between VZ and PGND

8.1 HTSSOP20 package information

Figure 16. HTSSOP20 package outline Table 10. HTSSOP20 mechanical data

9 Packaging information

9.1 HTSSOP20 packaging information

Figure 17. Carrier Tape for HTSSOP20 20L

Figure 18. HTSSOP20 Shipping Tube

Table 11. Ordering information

Ordering information

DS12305 - Rev 5 page 23/29

Revision history

Table 12. Document revision history 02-Oct-2017 1 Initial release. and diagnostic, minor text updates inside the document.

Contents

DS12305 - Rev 5 page 26/29