IPS160H STMICROELECTRONICS | Alldatasheet
Document overview
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- PDF pages: 26
Technical content
Datasheet sections
- 1 Block diagram
- 2 Pin description
- 2.2 OUT
- 2.3 DIAG
- 2.4 CoD
- 2.5 GND
- 2.6 VCC
- 3 Absolute maximum ratings
- 4 Electrical characteristics
- 5 Output logic
- 6 Protection and diagnostic
- 6.1 Undervoltage lock-out
- 6.2 Overtemperature
- 6.3 Cut-off
- 6.4 Open load in off-state
- 6.5 VCC disconnection protection
- 6.6 GND disconnection protection
- 7 Active clamp
- 8 Package information
- 8.1 PowerSSO12 package information
- 9 Revision history
Features
RDS(on) IOUT VCC 0.060 Ω 2.5 A 65 V 8 V to 60 V operating voltage range Minimum output current limitation: 2.6 A Non-dissipative short-circuit protection (cut- off) Programmable cut-off delay time using external capacitor Diagnostic signalization for: open load in off- state, cut-off and junction thermal shutdown Fast demagnetization of inductive load Ground disconnection protection VCC disconnection protection Undervoltage lock-out Designed to meet IEC 61131-2 PSSO12 package
Applications
Programmable logic control Industrial PC peripheral input/output Numerical control machines SIL applications
Description
The IPS160H is a monolithic device which can drive capacitive, resistive or inductive loads with one side connected to ground; it is specifically designed to match safety integrity level (SIL) applications. Built-in thermal shutdown protects the chip against overtemperature and short-circuit. In order to minimize the power dissipation when the output is shorted, a non-dissipative short-circuit protection (cut-off) is implemented, it limits both the output average current value and, consequently, the device overheating. The DIAG common diagnostic pin reports the thermal shutdown, open load in off-state and cut-off. Cut-off delay time can be programmed by an external capacitor. Table 1: Device summary Order code Package Packing IPS160H PowerSSO12 Tube IPS160HTR PowerSSO12 Tape and reel PowerSSO12
1 Block diagram
Figure 1: Block diagram IN GND Vcc OUT CoD Undervoltage detection Vcc clamp Output clamp Current limitation cut -off Open load in off-state Junction Overtemperature Logic interface DIAG GIPG1702151307LM
2 Pin description
Figure 2: Pin connection (top view) Table 2: Pin configuration Number Name Function Type 1, 12, TAB VCC Device supply voltage Supply
2 IN Channel input Input
3 DIAG Common diagnostic pin both for thermal shutdown, cut-off and
4 CoD
Cut-off delay pin, cannot be left floating. Connected to GND by 1 kΩ resistor to disable the cut-off function. Connect to a CCoD capacitor to set the cut-off delay see Table 9: "Protection and diagnostic" Input 5, 6 NC Not connected
7 GND Device ground Ground
8, 9, 10,
11 OUT Channel power stage output Output
2.1 IN This pin drives the output stage to pin OUT. IN pin has internal weak pull-down resistors, see Table 8: "Logic inputs".
2.2 OUT
Output power transistor is in high-side configuration, with active clamp for fast demagnetization. TAB=Vcc VCC IN DIAG CoD NC NC OUT OUT OUT OUT VCC GND GIPG1702151321LM
2.3 DIAG
This pin is used for diagnostic purpose and it is internally wired to an open drain transistor. The open drain transistor is turned on in case of junction thermal shutdown, cut -off, or open load in off-state.
2.4 CoD
This pin cannot be left floating and can be used to program the cut-off delay time tcoff, seeTable 9: "Protection and diagnostic" through an external capacitor (CCoD). The cut-off function can be completely disabled connecting the CoD pin to GND through 1 kΩ resistor: in this condition the output channel remains on in limitation condition, supplying the current to the load until the input is forced LOW or the thermal shutdown threshold is triggered or tcoff time elapses.
2.5 GND
IC ground.
2.6 VCC
IC supply voltage.
3 Absolute maximum ratings
Table 3: Absolute maximum ratings Symbol Parameter Value Unit VCC Supply voltage -0.3 to 65 V VOUT Output channel voltage Vcc-Vclamp to Vcc+0.3 V IIN Input current -10 to +10 mA VIN IN voltage VCC V VCOD Output cut-off voltage pin 5.5 V ICOD Input current on cut-off pin -1 to +10 mA VDIAG Fault voltage VCC V IDIAG Fault current -5 to +10 mA ICC(1) Maximum DC reverse current flowing through the IC from GND to VCC -250 mA IOUT Output stage current Internally limited A -IOUT(1) Maximum DC reverse current flowing through the IC from OUT to VCC 5 EAS(1) Single pulse avalanche energy (TAMB = 125 °C, VCC = 24 V, lload = 1.15 H load = 24 Ohm) 800 mJ PTOT Power dissipation at TC = 25 °C(2) Internally limited W TSTG Storage temperature range -55 to 150 TJ Junction temperature -40 to 150 Notes: (1)Verifyed on application board with Rth(ja) = 49 °C/W (2)TJSD(MAX)-TC)/ Rth(JA) Absolute maximum ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. All voltages are referenced to GND. Table 4: Thermal data Symbol Parameter Value Unit Rth(JC) Thermal resistance junction-case 1 °C/W Rth(JA) Thermal resistance junction-ambient 49 Package mounted on a 2-layer application board with Cu thickness = 35 μm, total dissipation area = 1.5 cm2 connected by 6 vias.
4 Electrical characteristics
(8 V < VCC < 60 V; -40 °C < TJ < 125 °C, unless otherwise specified) Table 5: Supply Symbol Parameter Test conditions Min. Typ. Max. Unit VCC Supply voltage VUVON VUVON Undervoltage on threshold 6.9 VUVOFF Undervoltage off threshold 6.5 7.8 VUVH Undervoltage hysteresis 0.15 0.5 IS Supply current in off-state VCC = 24 V 300 μA VCC = 60 V 350 Supply current in on-state VCC = 24 V mA VCC = 60 V 1.4 ILGND GND disconnection output current VGND = VIN = VCC VOUT = 0 V 1 mA Table 6: Output stage Symbol Parameter Test conditions Min. Typ. Max. Unit RDS(on) On-state resistance VCC = 24 V IOUT =1 A @ TJ = 25 °C mΩ VCC = 24 V IOUT =1 A @ TJ = 125 °C 120 VOUT(OFF) Off-state output voltage VIN = 0 V and IOUT = 0 A 2 V IOUT(OFF) Off-state output current VCC = 24 V, VIN = 0 V, VOUT = 0 V μA VCC = 60 V, VIN = 0 V, VOUT = 0 V IOUT(OFF-min) Off-state output current VIN = 0 V, VOUT = 4 V -35 Table 7: Switching (VCC = 24 V; -40 °C < TJ < 125 °C, RLOAD = 24 Ω) Symbol Parameter Test conditions Min. Typ. Max. Unit tr Rise time IOUT = 1 A μs tf Fall time tPD(H-L) Propagation delay time off tPD(L-H) Propagation delay time on
Table 8: Logic inputs Symbol Parameter Test conditions Min. Typ. Max. Unit VIL Input low level voltage 0.8 V VIH Input high level voltage 2.2 VI(HYST) Input hysteresis voltage 0.4 IIN Input current VCC = VIN = 36 V 200 μA VCC = VIN = 60 V 550 Table 9: Protection and diagnostic Symbol Parameter Test conditions Min. Typ. Max. Unit Vclamp VCC active clamp ICC = 10 mA 65.5 68.5 71.5 V Vdemag Demagnetization voltage IOUT = 0.5 A; load =1 mH VCC-71.5 VCC-68.5 VCC-65.5 VOLoff Open load (off-state) or short to VCC detection threshold tBKT Open load blanking time 200 μs VDIAG Voltage drop on DIAG IDIAG = 4 mA 1 V IDIAG DIAG pin leakage current VCC ≤ 36 V μA
36 V ˂ VCC ≤ 60 V
VCC ≤ 32 V, RLOAD ≤ 10 mΩ 2.6 4.3 A tcoff Cut-off current delay time Programmable by the external capacitor on CoD pin. Cut-off is disabled when CoD pin is connected to GND through 1 kΩ resistor. TJ˂ TJSD 50xCCOD[nf] ± 35%(1) μs tres Output stage restart delay time TJ˂ TJSD 32xtcoff [μs]± 40% TJSD Junction temperature shutdown 150 170 190 TJHYST Junction temperature thermal hysteresis Notes: (1)The formula is guaranteed in the range 10 nF ≤ CCOD ≤ 100 nF.
5 Output logic
Table 10: Output stage truth table Operation IN OUT DIAG Normal L H L H H H Cut-off L H L L L L Overtemperature L H L L L L Open load L H H (external pull-up resistor is used) H L (external pull-up resistor is used) H UVLO X X L L X X
IPS160H Protection and diagnostic
6 Protection and diagnostic
The IC integrates several protections to ease the design of a robust application.
6.1 Undervoltage lock-out
The device turns off if the supply voltage falls below the turn-off threshold (VUV(off)). Normal operation restarts after VCC exceeds the turn-on threshold (VUV(on)). Turn-on and turn-off thresholds are defined in Table 5: "Supply".
6.2 Overtemperature
The output stage turns off when its internal junction temperature (T J) exceeds the shutdown threshold TJSD. Normal operation restarts when TJ comes back below the reset threshold (TJSD - TJHYST), see Table 9: "Protection and diagnostic". The internal fault signal is set when the channel is off due to thermal protection and it is reset when the junction triggers the reset threshold. This same behavior is reported on DIAG pin.
6.3 Cut-off
The output current of the power stage is internally limited at the fixed ILIM threshold. The IPS160H implements the cut-off feature which limits the duration of the current limitation condition. The duration of the current limitation condition (Tcoff) can be set by a capacitor (CCoD) placed between CoD and GND pins. The design rule for CCoD is: tcoff[us] +/- 35% = 50 x Ccod[nF] The drift of +/-35% is guaranteed in the range of 10 nF < Ccod < 100 nF; lower capacitance than 10 nF can be used. If ILIM threshold is triggered, the output stage remains in the current limitation condition (IOUT = ILIM) no longer than tcoff. If tcoff elapses, the output stage turns off and restarts after the tres restart time. Thermal shutdown protection has higher priority than cut-off: IC is forced off if TJSD is triggered before tcoff elapses if TJSD is triggered, IC is maintained off even after the tres has elapsed and until the TJ decreases below TJSD-TJHYST
Protection and diagnostic IPS160H Figure 5: Current limitation and cut-off The fault condition is reported on the DIAG pin. The internal cut-off flag signal is latched at output switch-off and released after the time tres, the same behavior is reported on DIAG pin. The status of the DIAG is independent on the IN pin status. If CoD pin is connected to GND through 1 kΩ resistor (cut-off feature disabled), when the output channel triggers the limitation threshold, it remains on, in current limitation condition, until the input becomes LOW or the thermal protection threshold is triggered. In case of low ambient temperature conditions (TAMB < -20 °C) and high supply voltage (VCC > 36 V) the cut-off function needs activating in order to avoid IC permanent damages. The following table reports the suggested cut-off delay for the different operating voltage. Table 11: Minimum cut-off delay for TAMB < -20 °C VCC [V] Cut-off delay [μs] Cut-off capacitance [nF] 36-48 100 2.2 48-60 50 1
6.4 Open load in off-state
The IPS160H provides the open load detection feature which detects if the load is disconnected from the OUT pin. This feature can be activated by a resistor (RPU) between OUT and VCC pins. ILIM tCOFF tres IOUT VIN t t TJ<TJSD t VDIAG tPD(L-H) tPD(H-L)
IPS160H Protection and diagnostic Figure 6: Open load off-state In case of wire break and during the OFF state (IN = low), the output voltage VOUT rises according to the the partitioning between the external pull-up resistor and the internal resistance of the IC (RI). The effect of the LED (if any) on the output pin has to be considered as well. In case of wire break and during the ON state (IN = high), the output voltage VOUT is pulled up to VCC by the low resistive integrated switch. If the load is not connected, in order to guarantee the correct open load signalization it must result: VOUT > VOLoff(max.) Referring to the circuit in figure 6: 𝑉𝑂𝑈𝑇 = 𝑉𝐶𝐶 −𝑅𝑃𝑈 ×𝐼𝑃𝑈 = 𝑉𝐶𝐶 −𝑅𝑃𝑈 ×(𝐼𝑅𝐼 +𝐼𝐿𝐸𝐷 +𝐼𝑅𝐿) therefore: 𝑅𝑃𝑈 < 𝑉𝐶𝐶(𝑚𝑖𝑛) −𝑉𝑂𝐿𝑜𝑓𝑓(𝑚𝑎𝑥) (𝑉𝑂𝐿𝑜𝑓𝑓(𝑚𝑎𝑥) 𝑅𝐼 +𝑉𝑂𝐿𝑜𝑓𝑓(𝑚𝑎𝑥) −𝑉𝐿𝐸𝐷 𝑅𝐿𝐸𝐷 If the load is connected, in order to avoid any false signalization of the open load, it must result as follows: VOUT < VOLoff(min) By taking into account the circuit in figure 6: 𝑉𝑂𝑈𝑇 = 𝑉𝐶𝐶 −𝑅𝑃𝑈 ×𝐼𝑃𝑈 = 𝑉𝐶𝐶 −𝑅𝑃𝑈 ×(𝑉𝑂𝑈𝑇 𝑅𝐼 +𝑉𝑂𝑈𝑇 −𝑉𝐿𝐸𝐷 𝑅𝐿𝐸𝐷 +𝑉𝑂𝑈𝑇 𝑅𝐿 so: 𝑅𝑃𝑈 > 𝑉𝐶𝐶(𝑚𝑎𝑥) −𝑉𝑂𝐿𝑜𝑓𝑓(𝑚𝑖𝑛) (𝑉𝑂𝐿𝑜𝑓𝑓(𝑚𝑖𝑛) 𝑅𝐼 +𝑉𝑂𝐿𝑜𝑓𝑓(𝑚𝑖𝑛) −𝑉𝐿𝐸𝐷 𝑅𝐿𝐸𝐷 +𝑉𝑂𝐿𝑜𝑓𝑓(𝑚𝑖𝑛) 𝑅𝐿 The fault condition is reported on the DIAG pin and the fault reset occurs when load is reconnected. OUT PGND SUPPLY RAIL GROUND PLANE Application board IPS160H RLOAD RPU Open load detection signal + VOLOFF VCC VCC EXPOSED PAD RLED RI
Protection and diagnostic IPS160H If the channel is switched on by IN pin, the fault condition is no longer detected. When inductive load is driven, some ringing of the output voltage may be observed at the end of the demagnetization. In fact, the load is completely demagnetized when ILOAD = 0 A and the OUT pin remains floating until next turn-on. In order to avoid a fake signalization of the open load event driving inductive loads, the open load signal is ma sked for tBKT. So, the open load is reported on the DIAG pin with a delay of tBKT and if the open load event is triggered for more than tBKT.
6.5 VCC disconnection protection
The IC is protected despite the VCC disconnection event. This event is intended as the disconnection of the VCC wire from the application board, see figure below. When this condition happens, the IC continues working normally until the voltage on the VCC pin is ≥ VUV(OFF). Once the VUVOFF is triggered, the output channel is turned off independently on the input status. In case of inductive load, if the VCC is disconnected while the output channel is still active, the IC allows the discharge of the energy still stored in the inductor through the integrated power switch. Figure 7: VCC disconnection OUT GND SUPPLY RAIL GROUND PLANE APPLICATION BOARD IPS160H VCC EXPOSED PAD ON CVCC VCC >VUVOFF DRIVING CIRCUITRY
IPS160H Protection and diagnostic
6.6 GND disconnection protection
GND disconnection is intended as the disconnection event of the application ground, see figure below. When this event happens, the IC continues working normally until the voltage between VCC and GND pins of the IC results ≥ VUVOFF. The voltage on GND pin of the IC rises up to the supply rail voltage level. In case of GND disconnection event, a current (ILGND) flows through OUT pin. Table 8: "Logic inputs" reports IOUT = ILGND for the worst case of GND disconnection event in case of output shorted to ground. Figure 8: GND disconnection OUT GND SUPPLY RAIL GROUND PLANE APPLICATION BOARD IPS160H VCC EXPOSED PAD ON CVCC VCC DRIVING CIRCUITRY LOAD
7 Active clamp
Active clamp is also known as fast demagnetization of inductive loads or fast current decay. When a high-side driver turns off an inductance, an undervoltage is detected on output. The OUT pin is pulled down to Vdemag. The conduction state is modulated by an internal circuitry in order to keep the OUT pin voltage at about Vdemag until the load energy has been dissipated. The energy is dissipated both in IC internal switch and in load resistance. Figure 9: Active clamp equivalent principle schematic OUT GND SUPPLY RAIL GROUND PLANE APPLICATION BOARD IPS160H L LOAD Clamp circuitryVCC EXPOSED PAD GIPG1802150915LM
Figure 10: Fast demag waveforms The demagnetization of inductive load causes a huge electrical and thermal stress to the IC. The curve plotted below shows the maximum demagnetization energy that the IC can support in a single demagnetization pulse with VCC = 24 V and TAMB = 125 °C. If higher demagnetization energy is required then an external free-wheeling Schottky diode has to be connected between OUT (cathode) and GND (anode) pins. Note that in this case the fast demagnetization is inhibited. ILOAD tDEMAGIOUT VIN t tON VOUT VCC VCC-VDEMAG t t ~~~
Figure 11: Typical demagnetization energy (single pulse) at VCC = 24 V and TAMB = 125 °C 500 1000 1500 2000 2500 3000 3500 4000 500 700 900 1100 1300 1500 1700 1900 2100 2300 2500 EDEMAG [mJ] ILOAD [mA]
8 Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark.
8.1 PowerSSO12 package information
Figure 12: PowerSSO12 package outline
Table 12: PowerSSO12 package mechanical data Dim. mm Min. Typ. Max. A 1.250 1.700 A1 0.000 0.100 A2 1.100 1.600 B 0.230 0.410 C 0.190 0.250 D 4.800 5000 E 3.800 4000 e 0.800 H 5800 6.200 h 0.250 0.55 L 0.400 0.1270 k 0d 8d X 1.900 2500 Y 3.600 4.200 ddd 0.100 Dimension D doesn't include mold flash protrusions or gate burrs. Mold flash protrusions or gate burrs don't exceed 0.15 mm in total both side.
Figure 13: PowerSSO12 recommended footprint
9 Revision history
Table 13: Document revision history Date Revision Changes 19-Mar-2015 1 Initial release. 04-Nov-2015 2 Minor text changes throughout the document. Added Figure 7: "VCC disconnection", Figure 10: "Fast demag waveforms" and Figure 11: "Typical demagnetization energy (single pulse) at VCC = 24 V and TAMB = 125 °C".