STIPN1M50T-H_V01 STMICROELECTRONICS | Alldatasheet
Document overview
- Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
- PDF pages: 23
Technical content
Datasheet sections
- 1 Internal schematic diagram and pin configuration
- 2 Electrical ratings
- 2.1 Absolute maximum ratings
- 2.2 Thermal data
- 3 Electrical characteristics
- 3.1 Inverter part
- 3.2 Control part
- 3.2.1 NTC thermistor
- 3.3 Waveform definitions
- 4 Shutdown function
- 5 Application circuit example
- 5.1 Guidelines
- 6 Package information
- 6.1 NDIP-26L type C package information
- 6.2 NDIP-26L packing information
Features
- IPM 1 A, 500 V, R DS(on) = 3.6 Ω, 3-phase MOSFET inverter bridge including control ICs for gate driving
- Optimized for low electromagnetic interference
- 3.3 V, 5 V, 15 V CMOS/TTL input comparators with hysteresis and pull-down/ pull-up resistors
- Undervoltage lockout
- Internal bootstrap diode
- Interlocking function
- Shutdown function
- Comparator for fault protection against overtemperature and overcurrent
- Op-amp for advanced current sensing
- Optimized pinout for easy board layout
- NTC for temperature control (UL 1434 CA 2 and 4)
- Up to ±2 kV ESD protection (HBM C = 100 pF, R = 1.5 kΩ)
Applications
- 3-phase inverters for motor drives
- Dishwashers
- Roller shutters
- Air-conditioning fans
- Draining and recirculation pumps
Description
This SLLIMM (small low-loss intelligent molded module) nano provides a compact, high-performance AC motor drive in a simple, rugged design. It is composed of six MOSFETs and three half-bridge HVICs for gate driving, providing low electromagnetic interference (EMI) characteristics with optimized switching speed. The package is optimized for thermal performance and compactness in built-in motor applications, or other low power applications where assembly space is limited. This IPM includes an operational amplifier, completely uncommitted, and a comparator that can be used to design a fast and efficient protection circuit. SLLIMM is a trademark of STMicroelectronics. Product status link STIPN1M50T-H Product summary Order code STIPN1M50T-H Marking IPN1M50T-H Package NDIP-26L Packing Tube SLLIMM-nano IPM, 3-phase inverter, 1 A, 3.6 Ω max., 500 V MOSFET STIPN1M50T-H Datasheet DS11494 - Rev 6 - January 2020 For further information contact your local STMicroelectronics sales office.
1 Internal schematic diagram and pin configuration
Figure 1. Internal schematic diagram
Table 1. Pin description
1 GND Ground
3 VCC W Low voltage power supply W phase
4 HIN W High-side logic input for W phase
5 LIN W Low-side logic input for W phase
6 OP+ Op-amp non inverting input
7 OPOUT Op-amp output
8 OP- Op-amp inverting input
9 VCC V Low voltage power supply V phase
10 HIN V High-side logic input for V phase
11 LIN V Low-side logic input for V phase
12 CIN Comparator input
13 VCC U Low voltage power supply for U phase
14 HIN U High-side logic input for U phase
15 T/SD/OD NTC thermistor terminal / shutdown logic input (active low) / open-drain (comparator output)
16 LIN U Low-side logic input for U phase
17 VBOOT U Bootstrap voltage for U phase
18 P Positive DC input
19 U, OUTU U phase output
20 NU Negative DC input for U phase
21 VBOOT V Bootstrap voltage for V phase
22 V, OUTV V phase output
23 NV Negative DC input for V phase
24 VBOOT W Bootstrap voltage for W phase
25 W, OUTW W phase output
26 NW Negative DC input for W phase
Figure 2. Pin layout (top view) (*) Dummy pin internally connected to P (positive DC input).
2 Electrical ratings
2.1 Absolute maximum ratings
Table 2. Inverter part
- Applied between HINi, LINi and GND for i = U, V, W.
- Pulse width limited by max. junction temperature.
Table 3. Control part Table 4. Total system
1000 Vrms
2.2 Thermal data
Table 5. Thermal data
3 Electrical characteristics
TJ = 25 °C unless otherwise specified.
3.1 Inverter part
Table 6. Static
- Applied between HINx, LINx and GND for x=U,V,W.
Table 7. Inductive load switching time and energy
- t ON and tOFF include the propagation delay time of the internal drive. tC(ON) and tC(OFF) are the switching time of MOSFET
itself under the internally given gate driving conditions.
- Applied between HINx, LINx and GND for x=U,V,W.
Electrical characteristics
3.2 Control part
(VCC = 15 V unless otherwise specified). Table 8. Low voltage power supply Table 9. Bootstrapped voltage Table 10. Logic inputs
Table 11. Op-amp characteristics
- The direction of input current is out of the IC.
Table 12. Sense comparator characteristics
- Equivalent values as a result of the resistances of three drivers in parallel.
Table 13. Truth table
3.2.1 NTC thermistor
Figure 5. Internal structure of SD and NTC RPD_SD: equivalent value as result of resistances of three drivers in parallel. Figure 6. Equivalent resistance (NTC//RPD_SD)
3.3 Waveform definitions
Figure 9. Dead time and interlocking waveform definitions
4 Shutdown function
The device is equipped with three half-bridge IC gate drivers and integrates a comparator for fault detection. input pin (CIN) can be connected to an external shunt resistor for current monitoring. For an effective design of the shutdown circuit, please refer to Application note AN4966. Figure 10. Shutdown timing waveforms Please refer to AN4966 for further details.
- R NTC to be considered only when the NTC is internally connected to the T/SD /OD pin.
5 Application circuit example
Figure 11. Application circuit example Application designers are free to use a different scheme according to the specifications of the device.
5.1 Guidelines
- Input signals HIN, LIN are active high logic. A 375 kΩ (typ.) pull-down resistor is built-in for each input. To avoid input signal oscillation, the wiring of each input should be as short as possible, and the use of RC filters (R1, C1) on each input signal is suggested. The filters should be with a time constant of about 100 ns and placed as close as possible to the IPM input pins.
- The use of a bypass capacitor C VCC (aluminum or tantalum) can reduce the transient circuit demand on the power supply. Also, to reduce any high-frequency switching noise distributed on the power lines, a decoupling capacitor C2 (100 to 220 nF, with low ESR and low ESL) should be placed as close as possible to the Vcc pin and in parallel with the bypass capacitor.
- The use of an RC filter (R SF, CSF) is recommended to prevent protection circuit malfunction. The time constant (RSF x CSF) should be set to 1 μs and the filter must be placed as close as possible to the CIN pin.
- The SD is an input/output pin (open-drain type if it is used as output). A built-in thermistor NTC is internally connected between the SD pin and GND. The voltage VSD-GND decreases as the temperature increases, due to the pull-up resistor RSD. In order to keep the voltage always higher than the high-level logic threshold, the pull-up resistor should be set to 1 kΩ or 2.2 kΩ for 3.3 V or 5 V MCU power supply, respectively. The capacitor CSD of the filter on SD should be fixed no higher than 3.3 nF in order to assure the SD activation time τA ≤ 500 ns. Besides, the filter should be placed as close as possible to the SD pin.
- The decoupling capacitor C 3 (from 100 to 220 nF, ceramic with low ESR and low ESL), in parallel with each Cboot, filters high-frequency disturbance. Both Cboot and C3 (if present) should be placed as close as possible to the U, V, W and Vboot pins. Bootstrap negative electrodes should be connected to U, V, W terminals directly and separated from the main output wires.
- To avoid overvoltage on the V cc pin, a Zener diode (Dz1) can be used. Similarly on the Vboot pin, a Zener diode (Dz2) can be placed in parallel with each Cboot.
- The use of the decoupling capacitor C 4 (100 to 220 nF, with low ESR and low ESL) in parallel with the electrolytic capacitor Cvdc is useful to prevent surge destruction. Both capacitors C4 and Cvdc should be placed as close as possible to the IPM (C4 has priority over Cvdc).
- By integrating an application-specific type HVIC inside the module, direct coupling to the MCU terminals without an opto-couplers is possible.
- Low-inductance shunt resistors have to be used for phase leg current sensing.
- In order to avoid malfunctions, the wiring on N pins, the shunt resistor and P WR_GND should be as short as possible.
- The connection of SGN_GND to PWR_GND on one point only (close to the shunt resistor terminal) can reduce the impact of power ground fluctuation. These guidelines ensure the specifications of the device for application designs. For further details, please refer to the relevant application note.
Table 14. Recommended operating conditions
6 Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark.
6.1 NDIP-26L type C package information
Figure 12. NDIP-26L type C package outline
Package information
DS11494 - Rev 6 page 18/23
Table 15. NDIP-26L type C mechanical data
6.2 NDIP-26L packing information
Figure 13. NDIP-26L tube (dimensions are in mm) Table 16. Shipping details
Revision history
Table 17. Document revision history 03-Feb-2016 1 Initial release. Document status promoted from preliminary to production data. Updated title and features in cover page. definition and Section 6.2: Packing information. Application circuit example and Section 5.1: Guidelines. Updated Section 6.1: NDIP-26L package information. Document status changed from preliminary to production data. Modified Table 15: "Recommended operating conditions". Modified Table 2. Inverter part, Table 5. Thermal data. Modified Section 5.1 Guidelines. Modified title, features and applications in cover page. function and Section 5.1 Guidelines.