ISL6235 INTERSIL | Alldatasheet

Document overview

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Technical content

Features

  • PWM Only Mode for Reduced Noise at Light Loads
  • Provides Five Re gulated Voltages - +5V ALWAYS - +3.3V ALWAYS -+ 5 V M a i n - +3.3V Main -+ 1 2 V
  • High Efficiency Over Wide Line and Load Range - Synchronous Buck Converters on Main Outputs
  • No Current-Sense Resistor Required - Uses MOSFET’s r DS(ON) - Optional Current-Sense Resistor for More Precision
  • Operates Directly From Battery 5.6 to 24V Input
  • Input Undervoltage Lock-Out (UVLO)
  • Excellent Dynamic Response - Voltage Feed-Forward and Current-Mode Control
  • Monitors Output Voltages
  • Synchronous Converters Operate Out of Phase
  • Separate Shut-Down Pins for Advanced Configuration and Power Interface (ACPI) Compatibility
  • 300kHz Fixed Switching Fr equency on Main Outputs
  • Thermal Shut-Down Protection

Applications

  • Mobile PCs
  • Hand-Held Portable Instruments
  • L C D P C s
  • Cable Modems
  • DSL Modems
  • S e t T o p B o x Related Literature
  • Application Note AN9915 (IPM6220)

Ordering Information

TEMP. RANGE (oC) PACKAGE PKG. NO. ISL6235CA -10 to 85 24 Ld SSOP M24.15 IPM6220EVAL1 Evaluation Board VBATT 3.3V ALWAYS BOOT2 UGATE2 VSEN2 SDWN2 PGOOD BOOT1 LGATE1 ISEN1 PHASE1 GND GATE3 SDWNALL UGATE1 PGND2 PHASE2 ISEN2 VSEN1 VSEN3 5V ALWAYS LGATE2 PGND1 SDWN1 Data Sheet June 2001NOT RECOMMENDED FOR NEW DESIGNS RECOMMENDED REPLACEMENT ISL6232 (Available Feb. 2004)

RESET (POR) SDWNALL RAMP 1RAMP 2 CLK VBATT LGATE2 VOLT- CLAMP OC 2.8V D Q Q R VCC BOOT2 UGATE2 PHASE2 LGATE2 PGND2 VCC LGDR2 HGDR2 HI LO GATE LOGIC 2 PWM ON DEADTIME SHUTOFF LGATE2 R1 = 20K VSEN2 ISEN2 - PWM LATCH 2 OC COMP2 CLK2 CLK1 SECOND EA1 REF LGATE1 VOLT- CLAMP OC LOGIC1 D Q Q R VCC BOOT1 UGATE1 PHASE1 LGATE1 PGND1 VCC LGDR1 HGDR1 HI LO GATE LOGIC 1 PWM ON DEADTIME SHUTOFF LGATE1 R1 = 20K VSEN1 ISEN1 -PWM LATCH 1 OC COMP1 SECOND SDWN2 SDWN1 REFERENCE AND SOFT START REF GND POR POR 5V-ALWAYS SDWN VSEN1VBATT SDWN 3.3V-ALWAYS LDO1 LDO2 PGOOD OUTPUT VOLTAGE MONITOR OVP2 OVP1 LOGIC2 UVFLT 200ns VCC UVFLT 2.5VOVP1 OVP2 VSEN3 GATE3 CLK1 BOOST CONTROLLER REF ISL6235

Simplified Power System Diagram Typical Application PWM1 5V MAIN LINEAR LINEAR PWM3 ISL6235 CONTROLLER CONTROLLER CONTROLLER CONTROLLER PWM2 CONTROLLER VBATT 3.3V MAIN VBATT VBATT 12V BOOST MONITORS PGOODVOLTAGE, CURRENT 3.3V ALWAYS 5V ALWAYS +VBATT µP CORE CLOCK I/O VCORE VI/O VCLOCKC8051 5V ALWAYS 3.3V ALWAYS VID CODE SDWN1 SDWN2 5V MAIN 3.3V MAIN ISL6235 IPM6210 ENABLE SDWN SDWNALL PROCESSOR ON/OFF 12V RESET PGOOD PGOOD PCM CIA ISL6235

I Absolute Maximum Ratings Thermal Information Operating Conditions Thermal Resistance (Typical, Note 1) θJA (oC/W) (SSOP - Lead Tips Only) CAUTION: Stresses above those listed in “Abs olute Maximum Ratings” may cause permanent dam age to the device. This is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. Refer to Block and Simplified Power System Diagrams, and Typical Application Schematic PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Input Quiescent Current I CC SDWN1 = SDWN2 = 5V, SDWNALL = Vin, Outputs open circuited -1 . 4 2 . 0m A Stand-by Current I CCSB SDWN1 = SDWN2 = 0V, SDWNALL = Vin, Outputs open circuited - 300 - µA Shut-down Current I CCSN SDWNALL = 0V - <1.0 - µA Input Undervoltage Lock Out UVLO Rising VBATT 4.3 4.7 5.1 V Input Undervoltage Lock Out UVLO VBATT, Hysteresis - 300 - mV OSCILLATOR PWM1,2 Oscillator Frequency F c1,2 255 300 345 kHz REFERENCE AND SOFT START Internal Reference Voltage V REF - 2.472 - V Reference Voltage Accuracy -1.0 - +1.0 % SDWN1,SDWN2 Output Current During Start-up ISS -5- µA PWM1 CONVERTER, 5V Main Output Voltage V OUT1 -5 . 0- V Undervoltage Shut-Down Level V UV1 2µs delay, % Feedback Voltage at VSNS1 Pin 70 75 80 % Current Limit Threshold I OC2 Current from ISNS1 Pin Through RSNS1 90 135 180 µA Overvoltage Threshold V OVP1 2µs delay, % Feedback Voltage at VSNS1 Pin 110 115 120 % Maximum Duty Cycle DC MAX SDWN1>4.0V - 94 - % PWM2 CONVERTER, 3.3V Main Output Voltage VOUT2 - 3.3 - V Undervoltage Shut-Down Level V UV2 2µs delay, % Feedback Voltage at VSNS2 Pin 70 75 80 % Current Limit Threshold I OC2 Current from ISNS2 Pin Through RSNS2 90 135 180 µA Overvoltage Threshold V OVP2 2µs Delay, % Feedback Voltage at VSNS2 Pin 110 115 120 % Maximum Duty Cycle DC MAX SDWN2 > 4.0V - 94 - % ISL6235

Internal Resistance to GND on VSNS2 Pin RVSNS2 - 66K - Ω PWM1 and PWM2 CONTROLLER GATE DRIVERS Upper Drive Pull-Up Resistance R 2UGPUP -5 1 2 Ω Upper Drive Pull-Down Resistance R 2UGPDN -4 1 0 Ω Lower Drive Pull-Up Resistance R 2LGPUP -69 Ω Lower Drive Pull-Down Resistance R 2LGPDN -58 Ω PWM 3 CONVERTER 12V Feedback Regulation Voltage VSEN3 - 2.472 - V 12V Feedback Regulation Voltage Input Current IVSEN3 -0 . 1 1 . 0 µA Line and Load Regulation 0.0 < IVOUT3 < 120mA, 4.9V < 5VMain < 5.1V -2 - +2 % Undervoltage Shut-Down Level V UV3 2µs Delay, % Feedback Voltage at VSNS3 Pin 70 75 80 % Overvoltage Threshold V OVP3 2µs Delay, % Feedback Voltage at VSNS3 Pin - 115 120 % PWM3 Oscillator Frequency F c3 85 100 115 kHz Maximum Duty Cycle -3 3- % PWM 3 CONTROLLER GATE DRIVERS Pull-Up Resistance R3GPUP - 8 12 Ω Pull-Down Resistance R3GPDN - 8 12 Ω 5V AND 3.3V ALWAYS Linear Regulator Accuracy PWM1, 5V Output OFF (SDWN1 = 0V); 5.6V < VBATT < 22V; 0 < Iload < 50mA -2.0 0.5 +2.0 % 5V ALWAYS Output Voltage Regulation PWM1, 5V output ON (SDWN1 = 5V); 0 < Iload < 50mA -3.3 1.0 +2.0 % Maximum Output Current Combined 5V ALWAYS and 3.3V ALWAYS 50 - - mA Current Limit Combined 5V ALWAYS and 3.3V ALWAYS 100 180 - mA 5V ALWAYS Undervoltage Shut-Down -7 5- % Bypass Switch rDS(ON) PWM1, 5V output ON (SDWN1 = 5V) - 1.3 - Ω POWER GOOD AND CONTROL FUNCTIONS Power Good Threshold for PWM1 and PWM2 Output Voltages -14 -12 -10 % PGOOD Leakage Current I PGLKG VPULLUP = 5.0V - - 1.0 µA PGOOD Voltage Low V PGOOD IPGOOD = -4mA - 0.2 0.5 V PGOOD Minimum Pulse Width T PGmin -1 0- µs SDWN1, 2- Low (Off) -0 . 8- V SDWN1, 2, - High (On) -4 . 3- V SDWNALL - High (On) -2 . 4- V SDWNALL - Low (Off) SDWNALL - 40 - mV Over-Temperature Shutdown - 150 - oC Over-Temperature Hysteresis -2 5- oC Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. Refer to Block and Simplified Power System Diagrams, and Typical Application Schematic (Continued) PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS ISL6235

Functional Pin Descriptions VBATT (Pin 1) Supplies all the power necessary to operate the chip. The IC starts to operate when the voltage on this pin exceeds 4.7V and stops operating when the voltage on this pin drops below approximately 4.5V. Also provides battery voltage to the oscillator for feed-forward rejection to input voltage variations. 3.3V ALWAYS (Pin 2) Output of 3.3V ALWAYS linear regulator. 5V ALWAYS (Pin 6) Output of 5V ALWAYS linear regulator or the +5V Main output. If the +5V Main output is enabled, it is switched internally from the VSEN1 pin to the 5V ALWAYS output. This improves efficiency and reduces the power dissipation in the controller. BOOT1, BOOT2 (Pins 24 and 3) Power is supplied to the upper MOSFET drivers of PWM1 and PWM2 converters via the BOOT pins. Connect these pins to the respective junctions of bootstrap capacitors with the cathodes of the bootstrap diodes. Anodes of the bootstrap diodes are connected to pin 6, 5V ALWAYS. UGATE1, UGATE2 (Pins 23 and 4) These pins provide the gate drive for the upper MOSFETs. Connect UGATE pins to the respective PWM converter’s upper MOSFET gate. PHASE1, PHASE2 (Pins 22 and 5) The phase nodes are the junctions of the upper MOSFET sources, output filter inductors, and lower MOSFET drains. Connect the PHASE pins directly to the respective PWM converter’s lower MOSFET drain. ISEN1, ISEN2 (Pins 21 and 9) These pins are used to monitor the voltage drop across the lower MOSFETs for current feedback and current-limit protection. For more precise current detection, these inputs can be connected to optional current sense resistors placed in series with the sources of the lower MOSFETs. LGATE1, LGATE 2 (Pins 20 and 7) These pins provide the gate drive for the lower MOSFETs. Connect the lower MOSFET gate of each converter to the corresponding pin. PGND1, PGND2 (Pins 19 and 8) These are the lower MOSFET gate drive return connection for PWM1 and PWM2 converters, respectively. Tie each lower MOSFET source directly to the corresponding pin. VSEN1, VSEN2 (Pins 18, 10) These pins are connected to the main outputs and provide the voltage feedback signal for the respective PWM controllers. The PGOOD, overvoltage protection (OVP) and undervoltage shutdown circuits use these signals to determine output voltage status and/or to initiate undervoltage shut down. The VSEN1 input is also switched internally to the 5V ALWAYS output if the +5V Main output is enabled. SDWNALL (Pin 13) This pin provides enable/disable function for all outputs. The chip is completely disabled when this pin is pulled to ground. When this pin is pulled high, the 5V ALWAYS and 3.3 ALWAYS outputs are on and the other outputs are enabled. The state of 5V Main and 3.3V Main outputs depend on the voltage on SDWN1 and SDWN2 respectively. See Table 1. SDWN1 (Pin 17) This pin provides enable/disable function and soft-start for the PWM1, 5V Main, output. The output is enabled when this pin is high and SDWNALL is also high. The 5V output is held off when the pin is pulled to the ground. SDWN2 (Pin 11) This pin provides enable/disable function and soft-start for PWM2, 3.3V Main, output. The output is enabled when this pin is high and SDWNALL is also high. The 3.3V output is held off when the pin is pulled to the ground. VSEN3 (Pin 15) This input pin is the voltage feedback signal for PWM3, the boost controller. The boost controller regulates this point to a voltage divided level of 2.472 VDC. The PGOOD, overvoltage protection (OVP) and undervoltage shutdown circuits use this signal to determine output-voltage status and/or to initiate undervoltage shut down. This pin can also be used to independently disable the PWM3 controller. Connect this pin to 5V ALWAYS if the boost converter is not populated in your design. GATE3 (Pin 16) This pin drives the gate of the boost MOSFET. PGOOD (Pin 12) PGOOD is an open drain output used to indicate the status of the PWM converters’ output voltages. This pin is pulled low when any of the outputs except PWM3 (12V) is not within -10% of respective nominal voltages, or when PWM3 (12V) is not within its undervoltage and overvoltage thresholds. GND (Pin 14) Signal ground for the IC. All voltage levels are measured with respect to this pin. ISL6235

ALWAYS, and a flexible boost converter, nominally 12V. with the maximum duty cycle limited to 33%. 3.3V Main and +5V Main outputs. saving board space and parts cost. upper MOSFET, lower MOSFET and the output inductor. the inductor current is ramping down as shown. series with the lower MOSFETs’ source. for the expected maximum operating temperature. and sampling continues as normal.

0 A, V

5V PHASE (10V/DIV.) 1µs/DIV. FIGURE 1. OUT OF PHASE OPERATION

over all operating conditions. the 5V Main, for the 12V output. disabled to prevent excessive power dissipation. outputs drop below 75% of its set point. MOSFET is turned off and the lower MOSFET is turned on. normal operation will continue. when the die temperature cools to 125oC. including ripple voltage and load transients. select the output capacitors. FIGURE 3. 12V BOOST OPERATION

the drop in output voltage allowed during the load transient. L is calculated in the Inductor Selection section. circuitry for specific decoupling requirements.

  1. They must have sufficient bulk capacitance to sustain the
  2. The ESR must be sufficiently low to meet the desired
  3. The ESR zero should be placed, in a rather large range,

to provide additional phase margin. minimum, 10µF capacitors on their outputs. Figure 4. Depending on the specifics of the input power and

in the parasitic circuit impedances. series available from AVX is surge current tested. switching frequency, 100kHz. where L is the value of the boost inductor. and thermal management considerations. device turns on and off into near zero voltage. dissipated by the ISL6235 and do not heat the MOSFETs. SW which increases the upper MOSFET switching losses. thermal-resistance specifications. FIGURE 4. INPUT RMS CURRENT VS LOAD

FIGURE 6. APPLICATIONS CIRCUIT

All Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at website www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporat ion reserves the right to make changes in circuit design and/o r specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. How- ever, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site www.intersil.com ISL6235 Shrink Small Outline Plastic Packages (SSOP) NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M -1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Inter- lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual in- dex feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “B” does not include dambar protrusion. Allowable dam- bar protrusion shall be 0.10mm (0.004 inch) total in excess of “B” dimension at maximum material condition. 10. Controlling dimension: INCHES. C onverted millimeter dimensions are not necessarily exact. α INDEX AREA E D N 123 -B- 0.17(0.007) C AM BS e -A- B M -C- A SEATING PLANE 0.10(0.004) h x 45o C H 0.25(0.010) BM M L 0.25 0.010 GAUGE PLANE M24.15

24 LEAD THIN SHRINK NARROW BODY SMALL OUTLINE

A 0.053 0.069 1.35 1.75 - A1 0.004 0.010 0.10 0.25 - B 0.008 0.012 0.20 0.30 9 C 0.007 0.010 0.18 0.25 - D 0.337 0.344 8.55 8.74 3 E 0.150 0.157 3.81 3.98 4 e 0.025 BSC 0.635 BSC - H 0.228 0.244 5.80 6.19 - h 0.0099 0.0196 0.26 0.49 5 L 0.016 0.050 0.41 1.27 6 N2 4 2 4 7 α 0o 8o 0o 8o - Rev. 0 12/00