IPM6220 RENESAS | Alldatasheet
Document overview
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Technical content
Features
- Provides Five Regulated Voltages -+ 5 V A L W A Y S - +3.3V ALWAYS -+ 5 V M a i n - +3.3V Main -+ 1 2 V
- High Efficiency Over Wide Line and Load Range - Synchronous Buck Converters on Main Outputs - Hysteretic Operation at Light Load
- No Current-Sense Resistor Required - Uses MOSFET’s r DS(ON) - Optional Current-Sense Resistor for More Precision
- Operates Directly From Battery 5.6 to 22V Input
- Input Undervoltage Lock-Out (UVLO)
- Excellent Dynamic Response - Voltage Feed-Forward and Current-Mode Control
- Monitors Output Voltages
- Synchronous Converters Operate Out of Phase
- Separate Shut-Down Pins for Advanced Configuration and Power Interface (ACPI) Compatibility
- 300kHz Fixed Switching Frequency on Main Outputs
- Thermal Shut-Down Protection
Applications
- Mobile PCs
- Hand-Held Portable Instruments Related Literature
- Application Note AN9915
Ordering Information
TEMP. RANGE (oC) PACKAGE PKG. NO. IPM6220CA 0 to 70 24 Ld SSOP M24.15 IPM6220EVAL1 Evaluation Board VBATT 3.3V ALWAYS BOOT2 UGATE2 VSEN2 SDWN2 PGOOD BOOT1 LGATE1 ISEN1 PHASE1 GND GATE3 SDWNALL UGATE1 PGND2 PHASE2 ISEN2 VSEN1 VSEN3 5V ALWAYS LGATE2 PGND1 SDWN1 NOT RECOMMENDED FOR NEW DESIGNS RECOMMENDED REPLACEMENT ISL6232 (Available Feb. 2004)
FN4903 Rev.1.00 Page 2 of 14 Dec 2000 IPM6220 Block Diagram EA2 REF POWER-ON RESET (POR) SDWNALL RAMP 1RAMP 2 CLK VBATT LGATE2 VOLT- CLAMP OC 2.8V D Q Q R VCC BOOT2 UGATE2 PHASE2 LGATE2 PGND2 VCC LGDR2 HGDR2 HI LO GATE LOGIC 2 PWM ON PWM/HYST DEADTIME SHUTOFF LGATE2 R1 = 20K VSEN2 ISEN2 - PWM LATCH 2 OC COMP2 HYST ON HYST COMP2 CLK2 CLK2 CLK1 SECOND EA1 REF LGATE1 VOLT- CLAMP OC LOGIC1 D Q Q R VCC BOOT1 UGATE1 PHASE1 LGATE1 PGND1 VCC LGDR1 HGDR1 HI LO GATE LOGIC 1 PWM ON PWM/HYST DEADTIME SHUTOFF LGATE1 R1 = 20K VSEN1 ISEN1 -PWM LATCH 1 OC COMP1 HYST ON HYST COMP1 CLK1 -PWMMD1 SECOND SDWN2 SDWN1 REFERENCE AND SOFT START REF GND POR POR 5V-ALWAYS SDWN VSEN1VBATT SDWN 3.3V-ALWAYS LDO1 LDO2 PGOOD OUTPUT VOLTAGE MONITOR OVP2 OVP1 LOGIC2 PWM MODE 1 FIGURE 1. PWMMD1 PWMMD2 PWMMD2 UVFLT 200ns VCC UVFLT 2.5VOVP1 OVP2 PWM MODE 2 VSEN3 GATE3 CLK1 BOOST CONTROLLER REF
FN4903 Rev.1.00 Page 4 of 14 Dec 2000 I Absolute Maximum Ratings Thermal Information Operating Conditions Thermal Resistance (Typical, Note 1) JA (oC/W) JC (oC/W) (SSOP - Lead Tips Only) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. Refer to Block and Simplified Power System Diagrams, and Typical Application Schematic PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Input Quiescent Current I CC SDWN1 = SDWN2 = 5V, SDWNALL = VIN, Outputs open circuited -1 . 4 2 . 0m A Stand-by Current I CCSB SDWN1 = SDWN2 = 0V, SDWNALL = VIN, Outputs open circuited - 300 A Shut-down Current I CCSN SDWNALL = 0V - <1.0 A Input Under-voltage Lock Out UVLO Rising VBATT 4.3 4.7 5.1 V Input Under-voltage Lock Out U VLO VBATT, Hysteresis 150 mV OSCILLATOR PWM1,2 Oscillator Frequency F c1,2 255 300 345 kHz REFERENCE AND SOFT START Internal Reference Voltage V REF - 2.472 - V Reference Voltage Accuracy -1.0 - +1.0 % SDWN1, SDWN2 Output Current During Start-up ISS -5- A PWM1 CONVERTER, 5V Main Output Voltage V OUT1 5 . 0 V Under-Voltage Shut-Down Level V UV1 2s delay, % Feedback Voltage at VSNS1 pin 70 75 80 % Current Limit Threshold I OC2 Current from ISNS1 Pin Through RSNS1 90 135 180 A Over-Voltage Threshold V OVP1 2s delay, % Feedback Voltage at VSNS1 pin 110 115 120 % Maximum Duty Cycle DC MAX SDWN1 > 4.0V 94 % PWM2 CONVERTER, 3.3V Main Output Voltage VOUT2 3.3 V Under-Voltage Shut-Down Level V UV2 2s delay, % Feedback Voltage at VSNS2 pin 70 75 80 % Current Limit Threshold I OC2 Current from ISNS2 Pin Through RSNS2 90 135 180 A Over-Voltage Threshold V OVP2 2s delay, % Feedback Voltage at VSNS2 pin 110 115 120 % Maximum Duty Cycle DC MAX SDWN2 > 4.0V 94 %
FN4903 Rev.1.00 Page 5 of 14 Dec 2000 Internal Resistance to GND on VSNS2 Pin R VSNS2 66K PWM1 and PWM2 CONTROLLER GATE DRIVERS Upper Drive Pull-Up Resistance R 2UGPUP -7 1 2 Upper Drive Pull-Down Resistance R 2UGPDN -4 1 0 Lower Drive Pull-Up Resistance R 2LGPUP -69 Lower Drive Pull-Down Resistance R 2LGPDN -58 PWM 3 CONVERTER 12V Feedback Regulation Voltage VSEN3 2.472 V 12V Feedback Regulation Voltage Input Current I VSEN3 0.1 1.0 A Line and Load Regulation 0.0 < IV OUT3 < 120mA, 4.9V< 5VMain <5.1V -2 +2 % Under-Voltage Shut-Down Level V UV3 2s delay, % Feedback Voltage at VSNS3 pin 70 75 80 % Over-Voltage Threshold V OVP3 2s delay, % Feedback Voltage at VSNS3 pin 115 120 % PWM3 Oscillator Frequency F c3 85 100 115 kHz Maximum Duty Cycle 33 % PWM 3 CONTROLLER GATE DRIVERS Pull-Up Resistance R3GPUP 6 12 Pull-Down Resistance R3GPDN 6 12 5V and 3.3V ALWAYS Linear Regulator Accuracy PWM1, 5V Output OFF (SDWN1 = 0V); 5.6V < VBATT < 22V; 0 < ILOAD < 50mA -2.0 0.5 +2.0 % 5V ALWAYS Output Voltage Regulation PWM1, 5V Output ON (SDWN1 = 5V); 0 < ILOAD < 50mA -3.3 1.0 +2.0 % Maximum Output Current Combined 5V ALWAYS and 3.3V ALWAYS 50 mA Current Limit Combined 5V ALWAYS and 3.3V ALWAYS 100 180 mA 5V ALWAYS Under-Voltage Shut-Down 75 % Bypass Switch rDS(ON) PWM1, 5V Output ON (SDWN1 = 5V) 1.3 POWER GOOD AND CONTROL FUNCTIONS Power Good Threshold for PWM1 and PWM2 Output Voltages -14 -12 -10 % PGOOD Leakage Current I PGLKG VPULLUP = 5.0V - - 1.0 A PGOOD Voltage Low V PGOOD IPGOOD = -4mA 0.2 0.5 V PGOOD Minimum Pulse Width T PGmin 10 s SDWN1, 2, - Low (Off) 0.8 V SDWN1, 2, - High (On) 4.3 V SDWNALL - High (On) 2.4 V SDWNALL - Low (Off) SDWNALL, Hysteresis 40 mV Over-Temperature Shutdown 150 oC Over-Temperature Hysteresis 25 oC Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. Refer to Block and Simplified Power System Diagrams, and Typical Application Schematic (Continued) PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
FN4903 Rev.1.00 Page 6 of 14 Dec 2000 Functional Pin Descriptions VBATT (Pin 1) Supplies all the power necessary to operate the chip. The IC starts to operate when the voltage on this pin exceeds 4.7V and stops operating when the voltage on this pin drops below approximately 4.5V. Also provides battery voltage to the oscillator for feed-forward rejection to input voltage variations. 3.3V ALWAYS (Pin 2) Output of 3.3V ALWAYS linear regulator. 5V ALWAYS (Pin 6) Output of 5V ALWAYS linear regulator or the +5V Main output. If the +5V Main output is enabled, it is switched internally from the VSEN1 pin to the 5V ALWAYS output. This improves efficiency and reduces the power dissipation in the controller. BOOT1, BOOT2 (Pins 24 and 3) Power is supplied to the upper MOSFET drivers of PWM1 and PWM2 converters via the BOOT pins. Connect these pins to the respective junctions of bootstrap capacitors with the cathodes of the bootstrap diodes. Anodes of the bootstrap diodes are connected to pin 6, 5V ALWAYS. UGATE1, UGATE2 (Pins 23 and 4) These pins provide the gate drive for the upper MOSFETs. Connect UGATE pins to the respective PWM converter’s upper MOSFET gate. PHASE1, PHASE2 (Pins 22 and 5) The phase nodes are the junctions of the upper MOSFET sources, output filter inductors, and lower MOSFET drains. Connect the PHASE pins directly to the respective PWM converter’s lower MOSFET drain. ISEN1, ISEN2 (Pins 21 and 9) These pins are used to monitor the voltage drop across the lower MOSFETs for current feedback and current-limit protection. For more precise current detection, these inputs can be connected to optional current sense resistors placed in series with the sources of the lower MOSFETs. LGATE1, LGATE 2 (Pins 20 and 7) These pins provide the gate drive for the lower MOSFETs. Connect the lower MOSFET gate of each converter to the corresponding pin. PGND1, PGND2 (Pins 19 and 8) These are the lower MOSFET gate drive return connection for PWM1 and PWM2 converters, respectively. Tie each lower MOSFET source directly to the corresponding pin. VSEN1, VSEN2 (Pins 18, 10) These pins are connected to the main outputs and provide the voltage feedback signal for the respective PWM controllers. The PGOOD, overvoltage protection (OVP) and undervoltage shutdown circuits use these signals to determine output- voltage status and/or to initiate undervoltage shut down. The VSEN1 input is also switched internally to the 5V ALWAYS output if the +5V Main output is enabled. SDWNALL (Pin 13) This pin provides enable/disable function for all outputs. The chip is completely disabled when this pin is pulled to ground. When this pin is pulled high, the 5V ALWAYS and 3.3 ALWAYS outputs are on and the other outputs are enabled. The state of 5V Main and 3.3V Main outputs depend on the voltage on SDWN1 and SDWN2 respectively. See Table 1. SDWN1 (Pin 17) This pin provides enable/disable function and soft-start for the PWM1, 5V Main, output. The output is enabled when this pin is high and SDWNALL is also high. The 5V output is held off when the pin is pulled to the ground. SDWN2 (Pin 11) This pin provides enable/disable function and soft-start for PWM2, 3.3V Main, output. The output is enabled when this pin is high and SDWNALL is also high. The 3.3V output is held off when the pin is pulled to the ground. VSEN3 (Pin 15) This input pin is the voltage feedback signal for PWM3, the boost controller. The boost controller regulates this point to a voltage divided level of 2.472 VDC. The PGOOD, overvoltage protection (OVP) and undervoltage shutdown circuits use this signal to determine output-voltage status and/or to initiate undervoltage shut down. This pin can also be used to independently disable the PWM3 controller. Connect this pin to 5V ALWAYS if the boost converter is not populated in your design. GATE3 (Pin 16) This pin drives the gate of the boost MOSFET. PGOOD (Pin 12) PGOOD is an open drain output used to indicate the status of the PWM converters’ output voltages. This pin is pulled low when any of the outputs except PWM3 (12V) is not within -10% of respective nominal voltages, or when PWM3 (12V) is not within its undervoltage and overvoltage thresholds. GND (Pin 14) Signal ground for the IC. All voltage levels are measured with respect to this pin. General Description The IPM6220 addresses the system electronics power needs of modern notebook and sub-notebook PCs. The IC integrates control circuits for two synchronous buck converters for 5V Main and 3.3V Main buses, two linear regulators for 3.3V ALWAYS and 5V ALWAYS, and a 12V boost converter.
the maximum duty cycle limited to 33%. current-sense technique is based on the lower MOSFET rDS(ON). inductor current becomes discontinuous. saving board space and parts cost. current is ramping down as shown. series with the lower MOSFETs’ source. the expected maximum operating temperature. input and output voltages and a low value of the inductor. the hysteretic comparator and turns off at the upper limit. dissipation associated with continuous switching.
0 A, V
5V PHASE (10V/DIV.) 1s/DIV. FIGURE 4. OUT OF PHASE OPERATION
FN4903 Rev.1.00 Page 10 of 14 Dec 2000 reduction in Ro by one-half will pull the output voltage down to 0.707 of nominal and cause an under-voltage condition. The 12V converter starts to operate at the same time as the 5V Main converter. The rising voltage on the 5V Main output and the 33% duty cycle limit provides a similar soft-start, as the 5V Main, for the 12V output. 3V ALWAYS, 5V ALWAYS Linear Regulators The 3.3V ALWAYS and 5V ALWAYS outputs are derived from the battery voltage and are the first voltages available in the notebook when power on is initiated. The 5V ALWAYS output is generated directly from the battery voltage by a linear regulator. It is used to power the system micro- controller and to internally power the chip and the gate drivers. The 3.3V ALWAYS output is generated from the 5V ALWAYS output and may be used to power the keyboard controller or other peripherals. The combined current capability of these outputs is 50mA. When the 5V Main output is greater than it’s undervoltage level, it is switched to the 5V ALWAYS output via an internal 1.3 MOSFET switch. Simultaneously, the 5V ALWAYS linear regulator is disabled to prevent excessive power dissipation. The rise time of the 5V ALWAYS is determined by the value of the output capacitance on the 5V and 3.3V ALWAYS outputs. The internal regulator is current limited to about 180mA, so the start up time is approximately: Where COUT is the sum of the capacitances on the 5V and 3.3V ALWAYS outputs. Power Good Status The IPM6220 monitors all the output voltages except for the 3.3V ALWAYS. A single power-good signal, PGOOD, is issued when soft-start is completed and all monitored outputs are within 10% of their respective set points. After the soft-start sequence is completed, undervoltage protection latches the chip off when any of the monitored outputs drop below 75% of its set point. A ‘soft-crowbar’ function is implemented for an overvoltage on the 3.3V Main or 5V Main outputs. If the output voltage goes above 115% of their nominal output level, the upper MOSFET is turned off and the lower MOSFET is turned on. This ‘soft- crowbar’ condition will be maintained until the output voltage returns to the regulation window and then normal operation will continue. This ‘soft-crowbar’ and monitoring of the output, prevents the output voltage from ringing negative as the inductor current flows in the ‘reverse’ direction through the lower MOSFET and output capacitors. Over-Temperature Protection The IC incorporates an over-temperature protection circuit that shuts all the outputs down when the die temperature exceeds 150oC. Normal operation is automatically restored when the die temperature cools to 125oC. Component Selection Guidelines Output Capacitor Selection The output capacitors for each output have unique requirements. In general, the output capacitors should be selected to meet the dynamic regulation requirements including ripple voltage and load transients. 3.3V Main and 5V Main PWM Output Capacitors Selection of the output capacitors is also dependent on the output inductor so some inductor analysis is required to select the output capacitors. One of the parameters limiting the converter’s response to a load transient is the time required for the inductor current to slew to it’s new level. Given a sufficiently fast control loop design, the IPM6220 will provide either 0% or 94% duty cycle in response to a load transient. The response time is the time interval required to slew the inductor current from an initial current value to the load current level. During this interval the difference between the inductor current and the transient current level must be supplied by the output capacitor(s). Minimizing the response time can minimize the output capacitance required. Also, if the load transient rise time is slower than the inductor response time, as in a hard drive or CD drive, this reduces the requirement on the output capacitor. The maximum capacitor value required to provide the full, rising step, transient load current during the response time of the inductor is: Where: COUT is the output capacitor(s) required, LO is the output inductor, ITRAN is the transient load current step, VIN is the input voltage, VOUT is output voltage, and VOUT is the drop in output voltage allowed during the load transient. High frequency capacitors initially supply the transient current and slow the load rate-of-change seen by the bulk capacitors. The bulk filter capacitor values are generally determined by the ESR (Equivalent Series Resistance) and voltage rating requirements as well as actual capacitance requirements. The output voltage ripple is due to the inductor ripple current and the ESR of the output capacitors as defined by: where, IL is calculated in the Inductor Selection section. High frequency decoupling capacitors should be placed as close to the power pins of the load as physically possible. Be careful not to add inductance in the circuit board wiring that could cancel the usefulness of these low inductance tC OUT COUT LO ITRAN ITRAN DVOUT VRIPPLE IL ESR=
circuitry for specific decoupling requirements. provide sequencing of the main outputs at start-up.
- They must have sufficient bulk capacitance to sustain the
- The ESR must be sufficiently low to meet the desired output
- The ESR zero should be placed, in a rather large range, to
provide additional phase margin. 10F capacitors on their outputs. voltage and 1.5 times is a conservative guideline.
- Depending on the specifics of the input power and it’s
significantly less than the combined in-phase current. the parasitic circuit impedances. series available from AVX is surge current tested. FIGURE 9. INPUT RMS CURRENT vs LOAD
FN4903 Rev.1.00 Page 12 of 14 Dec 2000 +12V Boost Converter Inductor Selection The inductor value is chosen to provide the required output power to the load. where, Vinmin is the minimum input voltage, 4.9V; Dmax = 1/3, the maximum duty cycle; Ro is the minimum load resistance; Vo is the nominal output voltage and F is the switching frequency, 100kHz. +12V Boost Converter Output Capacitor Selection The total capacitance on the 12V output should be chosen appropriately, so that the output voltage will be higher than the undervoltage limit (9V) when the 5V Main soft-start time has elapsed. This will avoid triggering of the 12V undervoltage protection. The maximum value of the boost capacitor, Comax that will charge to 9V in the soft start time, Tss, is shown below, where L is the value of the boost inductor. The output capacitor ESR and the boost inductor ripple current determines the output voltage ripple. The ripple voltage is given by: and the maximum ripple current, IL, is given by: where L is the boost inductor calculated above, 5V is the boost input voltage and 3.3 is the maximum on time for the boost MOSFET. MOSFET Considerations The logic level MOSFETs are chosen for optimum efficiency given the potentially wide input voltage range and output power requirements. Two N-channel MOSFETs are used in each of the synchronous-rectified buck converters for the PWM1 and PWM2 outputs. These MOSFETs should be selected based upon rDS(ON) , gate supply requirements, and thermal management considerations. The power dissipation includes two loss components; conduction loss and switching loss. These losses are distributed between the upper and lower MOSFETs according to duty cycle (see the following equations). The conduction losses are the main component of power dissipation for the lower MOSFETs. Only the upper MOSFET has significant switching losses, since the lower device turns on and off into near zero voltage. The equations assume linear voltage-current transitions and do not model power loss due to the reverse-recovery of the lower MOSFET’s body diode. The gate-charge losses are dissipated by the IPM6220 and do not heat the MOSFETs. However, a large gate-charge increases the switching time, t SW which increases the upper MOSFET switching losses. Ensure that both MOSFETs are within their maximum junction temperature at high ambient temperature by calculating the temperature rise according to package thermal-resistance specifications. Layout Considerations MOSFETs switch very fast and efficiently. The speed with which the current transitions from one device to another causes voltage spikes across the interconnecting impedances and parasitic circuit elements. The voltage spikes can degrade efficiency, radiate noise into the circuit, and lead to device overvoltage stress. Careful component layout and printed circuit design minimizes the voltage spikes in the converter. Consider, as an example, the turn-off transition of one of the upper PWM MOSFETs. Prior to turn-off, the upper MOSFET is carrying the full load current. During the turn-off, current stops flowing in the upper MOSFET and is picked up by the lower MOSFET. Any inductance in the switched current path generates a voltage spike during the switching interval. Careful component selection, tight layout of the critical components, and short, wide circuit traces minimize the magnitude of voltage spikes. See the placement and the printed circuit board layout details. There are two sets of critical components in a DC-DC converter using an IPM6220 controller. The switching power components are the most critical because they switch large amounts of energy, and as such, they tend to generate equally large amounts of noise. The critical small signal components are those connected to sensitive nodes or those supplying critical bias currents. Power Components Layout Considerations The power components and the controller IC should be placed first. Locate the input capacitors, especially the high-frequency ceramic decoupling capacitors, close to the power MOSFETs. Locate the output inductor and output capacitors between the MOSFETs and the load. Locate the PWM controller close to the MOSFETs. Insure the current paths from the input capacitors to the MOSFETs, to the output inductors and output capacitors are as short as possible with maximum allowable trace widths. A multi-layer printed circuit board is recommended. Dedicate one solid layer for a ground plane and make all critical component ground connections with vias to this layer. Dedicate another solid layer as a power plane and break this plane into smaller islands of common voltage levels. The power plane should support the input power and output power nodes. Use Lmax Vinmin 2 Dmax 2 Ro 2V o 2 F Comax Tss VRIPPLE IL ESR= IL PUPPER IO 2 rDS ON VOUT VIN IO VIN tSW FS PLOWER IO VIN
FN4903 Rev.1.00 Page 14 of 14 Dec 2000 IPM6220 Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com For additional products, see www.intersil.com/en/products.html © Copyright Intersil Americas LLC 2000. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. Shrink Small Outline Plastic Packages (SSOP) NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Inter- lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual in- dex feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “B” does not include dambar protrusion. Allowable dam- bar protrusion shall be 0.10mm (0.004 inch) total in excess of “B” dimension at maximum material condition. 10. Controlling dimension: INCHES. Converted millimeter dimensions are not necessarily exact. INDEX AREA E D N 123 -B- 0.17(0.007) C AM BS e -A- B M -C- A SEATING PLANE 0.10(0.004) h x 45o C H 0.25(0.010) BM M L 0.25 0.010 GAUGE PLANE M24.15
24 LEAD THIN SHRINK NARROW BODY SMALL OUTLINE
A 0.053 0.069 1.35 1.75 - A1 0.004 0.010 0.10 0.25 - B 0.008 0.012 0.20 0.30 9 C 0.007 0.010 0.18 0.25 - D 0.337 0.344 8.55 8.74 3 E 0.150 0.157 3.81 3.98 4 e 0.025 BSC 0.635 BSC - H 0.228 0.244 5.80 6.19 - h 0.0099 0.0196 0.26 0.49 5 L 0.016 0.050 0.41 1.27 6 N2 4 2 4 7 0o 8o 0o 8o - Rev. 0 12/00