IPM6210A INTERSIL | Alldatasheet
Document overview
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Technical content
Features
Provides 3 Regulated Voltages - 0.9V to 2.0V Microprocessor Core (SpeedStep TM Enabled) - 1.5V Microprocessor I/O - 2.5V Microprocessor Clock Generator High Efficiency Over Wide Load Range Not Dissipative Current-Sense Scheme - Uses MOSFET’s r DS(ON) - Optional Current-Sense Resistor for Precision Overcurrent Adaptive Dead-Time Drivers for N-Channel MOSFETs Operates from +5V, +3.3V and Battery (5.6-24V) Inputs Precision Core Voltage Control: - Remote “Kelvin” Sensing - Summing Current-Mode Control - On-Chip Mode-Compensated “Droop” for Optimum Transient Response and Lower Processor Power Dissipation TTL-Compatible 5-Bit Digital Output Voltage Selection - Wide Range - 0.925V DC to 1.3VDC in 25mV Steps, and from 1.3VDC to 2.0VDC in 50mV Steps - Programmable “On-the-Fly” VID Code Change with Customer Programmable Slew Rate and 100µsS e t t l i n g Time Power-Good Output Voltage Monitor No Negative Voltage on Outputs at Turn-Off Overvoltage, Undervoltage and Overcurrent Fault Monitors 300kHz Fixed Switching Frequency Thermal Shutdown
Applications
Mobile PCs Web Tablets Internet Appliances
Ordering Information
PART NUMBER TEMP. ( oC) PACKAGE PKG. NO. I P M 6 2 1 0 A C A - 1 0t o8 5 2 8L dS S O P M 2 8 . 1 5 I P M 6 2 1 0 A C A - T - 1 0t o8 5 2 8L dS S O P , Tape and Reel M28.15 Data Sheet August 2001
IPM6210A (SSOP) TOP VIEW Simplified Power System Diagram LGATE2 PGND2 BOOT2 UGATE2 VID1 VID0 VSEN2 V3IN VOUT3 VCC UGATE1 BOOT1 PGND1 SOFT EN VSEN1 VRET1 GND LGATE1 VID3 PHASE2 VID2 ISEN1 VIN ISEN2 VID4 PHASE1 PGOOD +VIN VOUT1VOUT2 VOUT3 IPM6210A COREI/O PWM2 LINEAR CONTROLLER REGULATOR PWM1 CONTROLLER CPU CLK +VIN 3.3V VID CODE IPM6210A
Absolute Maximum Ratings Thermal Information CC +0.3V Recommended Operating Conditions Thermal Resistance (Typical, Note 1) θJA (oC/W) (SSOP - Lead Tips Only) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operatio no ft h e device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See T ech Brief TB379 for details. Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. Refer to Figures 1, 2 and 3 PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS VCC SUPPLY Nominal Supply Current I CC GATE1, GATE2 Open - 2 2.5 mA Shutdown Supply Current I CCS -3 0- µA Battery Pin Supply Current I VIN 30 - 200 µA Battery Pin Leakage Current at Shutdown I VINSD --1 µA POWER-ON RESET Rising VCC Threshold 4.3 4.5 4.6 V Falling VCC Threshold 3.9 4.1 4.3 V OSCILLATOR Free Running Frequency 255 300 345 kHz Ramp Amplitude, peak-to-peak V BAT =1 6 V - 2 - V Ramp Offset -0 . 5- V REFERENCE, DAC AND SOFT START VID0-VID4 Input Low Voltage -- 1 . 2 V VID0-VID4 Input High Voltage 1.8 - - V VID0-VID4 Pull-up Current to VCC -1- µA DAC Voltage Accuracy -1.0 - +1.0 % Soft-Start Current During Start-Up I SS VSS = 0V...0.9V 18 25 32 µA ENABLE Enable Voltage Low V ENLOW IC Inhibited - - 1.2 V Enable Voltage High V ENHIGH IC Enabled Input has Internal Pull-up Current Source 2 µA (Typ) 2.0 - - V PWM 1 CONVERTER Output Voltage VOUT1 Defined by the current VID code (Table 1) 0.925 - 2.0 V Static Load Regulation 100mA < I VOUT1 < 15.0A -2.0 - +2.0 % IPM6210A
Undervoltage Shutdown Level V UV1 Percent of the voltage set by VID code. Disabled during dynamic VID code change. 72 75 78 % Undervoltage Shutdown Delay T DOC1 1.2 - 1.6 µs Overvoltage V OVP1 Percent of the voltage set by VID code. 112 115 120 % Overvoltage Shutdown Delay T DOV1 1.6 - 3.2 µs Overcurrent Comparator Threshold I OC1 100 135 170 µA PWM 2 CONVERTER Output Voltage VOUT2 1.5 V Load Regulation 100mA < I VOUT3 < 2.1A -2.0 - +2.0 % Undervoltage Shutdown Level V UV2 1.09 - 1.13 V Undervoltage Shutdown Delay T DOC2 1.2 - 1.6 µs Overvoltage Shutdown V OVP2 1.70 - 1.78 V Overvoltage Shutdown Delay T DOV2 1.6 - 3.2 µs Overcurrent Comparator Threshold I OC2 100 140 170 µA LINEAR REGULATOR Output Voltage VOUT3 2.5 V Load Regulation 1mA < I VOUT3 < 100mA -2.0 - 2.0 % Undervoltage Shutdown Level V UV3 1.8 - 2.0 V Current Limit I oc3 260 320 400 mA PWM CONTROLLER ERROR AMPLIFIERS DC Gain By Design - 86 - dB Gain-Bandwidth Product GBWP By Design - 2.7 - MHz Slew Rate SR By Design - 1 - V/ µs PWM 1 CONTROLLER GATE DRIVERS Upper Drive Pull-Up Resistance R 1UGPUP -68 Ω Upper Drive Pull-Down Resistance R 1UGPDN -35 Ω Lower Drive Pull-Up Resistance R 1LGPUP -68 Ω Lower Drive Pull-Down Resistance R 1LGPDN -0 . 8 1 . 5 Ω PWM 2 CONTROLLER GATE DRIVERS Upper Drive Pull-Up Resistance R 2UGPUP -1 2 2 0 Ω Upper Drive Pull-Down Resistance R 2UGPDN -6 1 0 Ω Lower Drive Pull-Up Resistance R 2LGPUP -1 0 2 0 Ω Lower Drive Pull-Down Resistance R 2LGPDN -35 Ω POWER GOOD VOUT1 Upper Threshold Percent of the voltage defined by the VID code 108 - 114 % VOUT1 Lower Threshold, Falling Edge Percent of the voltage defined by the VID code 85 - 92 % VOUT1 Lower Threshold, Rising Edge Percent of the voltage defined by the VID code 87 - 94 % VOUT2 Upper Threshold 1.63 - 1.7 V VOUT2 Lower Threshold 1.32 - 1.38 V VOUT3 Upper Threshold 2.7 - 2.9 V VOUT3 Lower Threshold 2.18 - 2.32 V PGOOD Voltage Low V PGOOD IPGOOD =- 4 m A - - 0 . 5 V PGOOD Leakage Current I PGlLKG VPULLUP = 5.0V - - 1.0 µA Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. Refer to Figures 1, 2 and 3 (Continued) PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS IPM6210A
+ - 0.9V BOOT1 VID0 VID1 VID2 VID3 DACOUT POWER-ON RESET (POR) TTL DAC REFERENCE SOFT START VID4 SOFT VSEN1 UGATE1 PHASE1 LGATE1 PGND1 VCC LGDR1 HGDR1 GATE CONTROL VRET1 ISEN1 LGATE1 LGATE1 R1 = 20K + - OC LOGIC1 HI LO GATE LOGIC 1 OC COMP1 EA1 D Q Q R VCC PWM ON PWM/HYST DEADT RAMP 1RAMP 2 CLK VBAT SHUTOFF LGATE2 + - CLAMP OC LOGIC22.8V D Q Q R VCC BOOT2 UGATE2 PHASE2 LGATE2 PGND2 VCC LGDR2 HGDR2 GATE CONTROL HI LO GATE LOGIC 2 PWM ON PWM/HYST DEADT SHUTOFF LGATE2 R1 = 20K VSEN2 ISEN2 PWM LATCH 1 FCCM FCCM PWM LATCH 2 OC COMP2 HYST ON HYST COMP1 HYST ON DAC OUT CLK1 PRE AMP HYST COMP2 CLK2 CLK2 CLK1 FFBK1 DUTY CYCLE GND PGOOD OUTPUT VOLTAGE MONITOR V3IN VOUT3 + -0.9V LINEAR REGULATOR OVP1 OVP2 OVP1 OVP2 DYNAMIC CLAMP DUTY CYCLE DYNAMIC Σ Σ LOGIC 1 MODE CONTROL PHASE1 FFBK1 LOGIC 1 MODE CONTROL FAST FEEDBACK COMP1 COMP 2 MODE CONTROL PHASE1 VCCEN IPM6210A
Functional Pin Descriptions VID0, VID1, VID2, VID3, VID4 (Pins 11, 10, 9, 8 and 7 Respectively) VID0-VID4 are the input pins to the 5-bit DAC. The states of these five pins program the internal voltage reference (DACOUT). The level of DACOUT sets the core converter output voltage (V OUT1). It also sets the core PGOOD, UVP and OVP thresholds. BOOT1, BOOT2 (Pins 25 and 3) These pins provide power to the upper MOSFET drivers of the core and I/O converters. Connect these pins to their respective junctions of the bootstrap capacitors and the cathodes of the bootstrap diodes. The anodes of the bootstrap diodes are connected to pin 28, VCC. PHASE1, PHASE2 (Pins 23 and 5) The PHASE nodes are the junction points of the upper MOSFET sources, output filter inductors, and lower MOSFET drains. Connect the PHASE pins to the respective PWM converter’s upper MOSFET source. ISEN1, ISEN2 (Pins 22 and 6) These pins are used to monitor the voltage drop across the lower MOSFETs for current feedback, output voltage droop and overcurrent protection. For precise current detection these inputs could be connected to optional current sense resistors placed in series with sources of the lower MOSFETs. To set the gain of the current sense amplifier, a resistor should be placed in series with each of these inputs. UGATE1, UGATE2 (Pins 24 and 4) These pins provide the gate drive for the upper MOSFET s. LGATE1, LGATE 2 (Pin 27 and 1) These pins provide the gate drive for the lower MOSFETs. PGND1, PGND2 (Pin 26 and 2) These are the power ground connection for the core and I/O converters, respectively. Tie each lower MOSFET source to the corresponding pin. VSEN2 (Pin 12) This pin is connected to the I/O output and provides voltage feedback to the I/O error amplifier. The PGOOD, UVP and OVP comparators use this signal. V3IN (Pin 13) This pin provides input power for the 2.5V linear regulator. The typical input voltage for that pin is 3.3V. Alternatively, 5.0V system rail can be used while efficiency will be proportionally lower. VOUT3 (Pin 14) Output of the 2.5V linear regulator. Supplies current up to 150mA. The output current on this pin is internally limited to 250mA. VSEN1, VRTN1 (Pins 17 and 16) These pins are connected to the core converter’s output voltage to provide remote sensing. The PGOOD, UVP and OVP comparators use these pins for protection. SOFT (Pin 18) Connect a capacitor from this pin to the ground. This capacitor (typically 0.1mF), along with an internal 25mA current source, sets the soft-start interval of the converter. When voltage on this pin exceeds 0.9V, the soft start is completed. After the soft-start is completed, the pin function is changed. The internal circuit regulates voltage on this pin to the value commanded by VID code. The pin now has 500mA source/sink capability that allows to set desired slew rate for upward and downward VID code changes. VIN (Pin 19) VIN provides battery voltage to the oscillator for feed-forward rejection of input voltage variations. EN (Pin 20) This pin enables IC operation when left open or pulled-up to VCC. Also, it unlatches the chip after fault when being cycled. PGOOD (Pin 21) PGOOD is an open drain output used to indicate the status of the PWM converters’ output voltages. This pin is pulled low when the core output is not within ±10% of the DACOUT reference voltage, or when any of the other outputs are not within their respective undervoltage and overvoltage thresholds. The PGOOD output is pulled low for “01111” and ‘11111’ VID code. See Table 1. GND (Pin 15) Signal ground for the IC. All voltage levels are measured with respect to this pin. VCC (Pin 28) Supplies all the power necessary to operate the chip. The IC starts to operate when the voltage on this pin exceeds 4.5V and shuts down when the voltage on this pin drops below 4.0V.
Description
The IPM6210A three-in-one power management integrated circuit provides complete power solution for modern processors for notebook and sub-notebook PCs. The IC controls operation of two synchronous buck converters and one linear regulator. The output voltage of the core converter can be adjusted in the range from 0.925V to 2.0 by changing the DAC code settings (see Table 1). The output voltage of the I/O converter is fixed to 1.5V. The internal linear regulator provides fixed 2.5V for the CPU clock generator from the system +3.3V bus. The output voltage of the core converter IPM6210A
current, the PWM mode of operation is restored. as a fraction of the VID set voltage. than 4.0V, POR disables the chip. change in the core output voltage due to a VID code change. capacitor conforming to the VID code. voltage change when the processor commands to do so. when voltage on the SOFT pin reaches 0.9V. through a TTL-compatible 5-bit digital-to-analog converter. the IC down and set PGOOD low. MOSFET during its conduction time. FIGURE 1. INITIAL STARTUP SpeedStep™ is a trademark of Intel Corporation. PowerNow!™ is a trademark of Advanced Micro Devices, Inc.
load in anticipation of the possible load current step. circuit, but the feature is rather emulated by the feedback. is illustrated by the following equation. (performance or battery optimized).
01111 N o C P U
11111 N o C P U
- 0 = Connected to GND or V
FIGURE 2. MODE-COMPENSATED DROOP
obtained from the following equation. protection circuitry (140µA). the lower gate driver high and turns the lower MOSFET on. threshold, OVP comparator is disengaged. activated, a common problem for OVP schemes with a latch. Overvoltage protection is not provided for the linear regulator. negative output voltage at shutdown, as shown in Figure 11. A rising edge on EN clears the fault latch. temperatures below 125oC through the full soft-start cycle. and maximum load currents for each controller. choose proper value of the output filter inductor. usually easy to satisfy in high frequency converters. rate (di/dt) and the magnitude of the transient load current. allowable ESR rather than actual capacitance requirements. close to the processor power pins as physically possible. FIGURE 11. SHUTDOWN WAVEFORMS
output ripple voltage and the initial voltage drop after a transient. In most cases, multiple electrolytic capacitors of small case size perform better than a single large case capacitor. MOSFET Selection and Considerations Requirements for the upper and lower MOSFETs are different in mobile applications. The reason for that is the 10:1 difference in conduction time of the lower and the upper MOSFETs driven by a difference between the input voltage which is nominally in the range from 8V to 20V, while nominal output voltage is about 1.5V. Requirements for the lower MOSFET are simpler than those to the upper one. The lower the r DS(ON) of this device, the lower the conduction losses, the higher the converter’s efficiency. Switching losses and gate drive losses are not significant because of zero-voltage switching conditions inherent for this device in the buck converter. Low reverse recovery charge of the body diode is important because it causes shoot-trough current spikes when the upper MOSFET turns on. Also, important is to verify that the lower MOSFET gate voltage does not reach threshold when high dV/dt transition occurs on the phase node. To minimize this effect, IPM6210A has a low, 0.8 Ω typical, low side driver pull-down resistance. Requirements to the upper MOSFET r DS(ON) are less stringent than to the lower MOSFET because its conduction time is significantly shorter so switching losses can dominate especially at higher input voltages. It is recommended to have equal conduction and switching losses in the upper MOSFET at the nominal input voltage and load current. Then the maximum of the converter efficiency is tuned to the operating point where it is most desired. Also, this provides the most cost effective solution. Precise calculation of power dissipation in the MOSFETs is very complex because many parameters affecting turn-on and turn-off times such as gate reverse transfer charge, gate internal resistance, body diode reverse recovery charge, package and layout impedances and their variation with the operation conditions are not available to a designer. The following equations are provided only for rough estimation of the power losses and should be accompanied by a detailed breadboard evaluation. Attention should be paid to the input voltage extremes where power dissipation in the MOSFET s is usually higher. T able 2 provides some component information for several typical applications. Layout Considerations Switching converters, even during normal operation, produce short pulses of current which could cause substantial ringing and be a source of EMI pollution if layout constrains are not observed. There are two sets of critical components in a DC-DC converter. The switching power components process large amounts of energy at high rate and though, usually appear to be a source of a noise, end a low power components responsible for bias and feedback functions, though appear to be mainly recipients of the noise. The situation with the IPM6210A control IC is even more critical as it provides control functions for two independent converters and poor layout design could lead to cross talk between the converters and result in degradation in the performance. A multi-layer printed circuit board is recommended. Dedicate one solid layer for a ground plane. Dedicate another solid layer as a power plane and break this plane into smaller island of common voltage levels. Notice all the nodes that are subjected to high dV/dt voltage swing as PHASE1,2 nodes, for example. All surrounding circuitry will tend to couple the noise from these nodes trough stray capacitance. Do not oversize copper traces connected to these nodes. Do not place traces connected to the feedback components adjacent to these traces. Keep the wiring traces from the control IC to the MOSFET gate and source as short as possible and capable to handle peak currents up to 2A. Minimize the area within the gate- source path to reduce stray inductance and eliminate parasitic ringing at the gate. Locate small critical components like the soft-start capacitor and current sense resistors as close, as possible to the respective pins of the IC. PUPPER Io2 rDS ON() VOUT()× VIN Io V IN xFs ton toff+×× PLOWER Io2 rDS ON()× 1 VOUT VIN ×= TABLE 2 COMPONENT CIRCUIT 1 CIRCUIT 2 CIRCUIT 3 Maximum CPU Current 8.0A 12.0A 18.0A Inductor 2.0 µH Panasonic ETQP6F2R0BFA 1.0µH Panasonic ETQP6F2R0BFA 0.8µH Panasonic ETQP6F2R0BFA Output Capacitor 3x270µF Panasonic EEFUE0D271R or Sanyo 4x2R5TPC220M 5x270µF Panasonic EEFUE0D271R or Sanyo 6x2R5TPC220M 6x270µF Panasonic EEFUE0D271R High-Side MOSFET HUF76112SK8 HUF76112SK8 HUF76112SK8 Low-Side MOSFET ITF86130SK8T ITF86130SK8T ITF86130SK8T Current-Input Resistor for ~6% Droop At VO =1 . 6 V 1.27kΩ 1.00kΩ 1.50kΩ IPM6210A
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TST, Kowloon Hong Kong TEL: +852 2723 6339 FAX: +852 2730 1433 IPM6210A Shrink Small Outline Plastic Packages (SSOP) NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M -1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Inter- lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual in- dex feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “B” does not include dambar protrusion. Allowable dam- bar protrusion shall be 0.10mm (0.004 inch) total in excess of “B” dimension at maximum material condition. 10. Controlling dimension: INCHES. Converted millimeter dimensions are not necessarily exact. α INDEX AREA E D N 123 -B- 0.17(0.007) C AM BS e -A- B M -C- A SEATING PLANE 0.10(0.004) hx4 5 o C H 0.25(0.010) BM M L 0.25 0.010 GAUGE PLANE M28.15
28 LEAD SHRINK NARROW BODY SMALL OUTLINE
A 0.053 0.069 1.35 1.75 - A1 0.004 0.010 0.10 0.25 - B 0.008 0.012 0.20 0.30 9 C 0.007 0.010 0.18 0.25 - D 0.386 0.394 9.81 10.00 3 E 0.150 0.157 3.81 3.98 4 e 0.025 BSC 0.635 BSC - H 0.228 0.244 5.80 6.19 - h 0.0099 0.0196 0.26 0.49 5 L 0.016 0.050 0.41 1.27 6 N2 8 2 8 7 α 0o 8o 0o 8o - Rev. 0 2/95