IP2001 IRF | Alldatasheet

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Technical content

www.irf.com 1 iP2001 Features:

  • 20A continuous output current with no derating up to TPCB = 90°C
  • Very small 11mm x 11mm x 3mm profile
  • Internal features minimize layout sensitivity *
  • Optimized for very low power losses
  • 3.3 to 12V input voltage Synchronous Buck Multiphase Optimized BGA Power Block Integrated Power Semiconductors, Drivers & Passives

Description

The iP2001 is a fully optimized solution for high current synchronous buck multiphase applications. Board space and design time are greatly reduced because most of the components required for each phase of a typical discrete-based multiphase circuit are integrated into a single 11mm x 11mm x 3mm BGA power block. The only additional components required for a complete multiphase converter are a PWM IC, the external inductors, and the input and output capacitors. iPOWIR technology offers designers an innovative board space saving solution for applications requiring high power densities. iPOWIR technology eases design for applications where component integration offers benefits in performance and functionality. iPOWIR technology solutions are also optimized internally for layout, heat transfer and component selection. iP2001 Power Block 03/10/03 PD - 94089F * All of the difficult PCB layout and bypassing issues have been addressed with the internal design of the iPOWIR Block. There are no concerns about double pulsing, unwanted shutdown, or other malfunctions which often occur in switching power supplies. The iPOWIR Block will function normally without any additional input power supply bypass capacitors. However, for reliable long term operation it is recommended that the adequate amount of input decoupling is provided on the VIN pin. No additional bypassing is required on the VDD pin. iP2001 Internal Block Diagram MOSFET Driver with dead time control VIN VSW PG ND PRD Y ENAB LE PWM VDD SGND MOSFET Driver with dead time control VIN VSW PG ND PRD Y ENAB LE PWM VDD SGND

www.irf.com2 iP2001 All specifications @ 25°C (unless otherwise specified) c Measurement were made using four 10uF (TDK C3225X7R1C106M or equiv.) capacitors across the input (see Fig. 8). d Not associated with the rise and fall times. Does not affect Power Loss (see Fig. 9). Parameter Symbol Min Typ Max Units Conditions Supply Voltage V DD 4.6 5.0 5.5 V Input Voltage Range V IN 3.0 - 12.6 V Output Voltage Range V OUT 0.9 - 3.3 V see Figs. 2 & 4 Output Current Range I OUT -- 2 0 A see Fig. 2 Operating Frequency fsw 150 - 1000 kHz see Figs. 2 & 5 Operating Duty Cycle D - - 85 % Recommended Operating Conditions : Absolute Maximum Ratings : Electrical Specifications @ VDD = 5V (unless otherwise specified) : Parameter Symbol Min Typ Max Units Conditions Block Power Loss c PBLK - 3.1 3.8 W VIN = 12V, VOUT = 1.6V, Turn On Delay d td(on) -6 3- IOUT = 20A, fSW = 500kHz Turn Off Delay d td(off) -2 6- VIN Quiescent Current I Q-VIN - - 1.0 mA Enable = 0V, VIN = 12V VDD Quiescent Current I Q-VDD -- 1 0 µA Enable = 0V, VDD = 5V Under Voltage Lockout UVLO Start Threshold V START 4.2 4.4 4.5 V Hysteresis V Hys-UVLO - .05 - Enable Enable Input Voltage High V IH 2.0 - - V Input Voltage Low V IL - - 0.8 Power Ready PRDY Logic Level High V OH 4.5 4.6 - V VDD = 4.6V, ILoad = 10mA Logic Level Low V OL - 0.1 0.2 VDD < UVLO Threshold, ILoad = 1mA PWM nput PWM Logic Level High V OH 2.0 - - V Logic Level Low V OL - - 0.8 ns Parameter Min T yp Max Units Conditions VIN to PGND - - 16 V VDD to SGND - - 6.0 V PWM to SGND -0.3 - V DD+0.3 V not to exceed 6.0V Enable to SGND -0.3 - V DD+0.3 V not to exceed 6.0V Output RMS Current - - 20 A Storage Temperature -40 - 125 °C

www.irf.com 3 iP2001 Pin Description Table Pin Name Ball Designator Pin Function VDD A1 – A3, B1 – B3 Supply voltage for the internal circuitry. VIN A5 – A12, B5 – B12, C5 - C10 Input voltage for the DC-DC converter. PGND C11, C12, D11, D12, E11, E12, F6, F7, F12, G6, G7, G12, H6, H7, H12, J6, J7, J12, K5 – K7, K12, L5, L6, L12, M5 – M7, M12 Power Ground - connection to the ground of bulk and filter capacitors. VSW D5 – D10, E5 – E10, F8 – F11, G8 – G11, H8 – H11, J8 – J11, K8 – K11, L8 – L11, M8 – M11 Switching Node - connection to the output inductor. SGND C1 – C3, D1 –D3, E1 –E3 Signal Ground. ENABLE F1 When set to logic level high, internal circuitry of the device is enabled. When set to logic level low, the PRDY pin is forced low, the Control and Sychronous switches are turned off, and the supply current is less than µA. PRDY K1 Power Ready - This pin indicates the status of ENABLE or VDD. This output will be driven low when ENABLE is logic low or when VDD is less than 4.4V (typ.). When ENABLE is logic high and VDD is greater than 4.4V (typ.), this output is driven high. This output has a 10mA source and 1mA sink capability. PWM H1 TTL-level input signal to MOSFET drivers. NC B4, C4, D4, E4, F2 – F4, G2 – G4, H2 – H4, J1, J2 – J4, K3, L1, L2, M1 – M4 This pin is not for electrical connection. It should be attached only to dead copper.

www.irf.com4 iP2001 Fig 2. Safe Operating Area (SOA) vs. TPCB* (*see AN-1030 for details) Fig 1. Power Loss vs. Current Adjusting the Power Loss and SOA curves for different operating conditions To make adjustments to the power loss curves in Fig. 1, multiply the normalized value obtained from the curves in Figs. 3, 4, 5 or 6 by the value indicated on the power loss curve in Fig. 1. If multiple adjustments are required, multiply all of the normalized values together, then multiply that product by the value indicated on the power loss curve in Fig. 1. The resulting product is the final power loss based on all factors. To make adjustments to the SOA curve in Fig. 2, determine the maximum allowed PCB temperature in Fig. 2 at the required operating current. Then, add the correction temperature from the normalized curves in Figs. 3, 4, 5 or 6 to find the final maximum allowable PCB temperature. When multiple adjustments are required, add all of the temperatures together, then add the sum to the PCB temperature indicated on the SOA graph to determine the final maximum allowable PCB temperature based on all factors. Operating Conditions for the examples below: Output Current = 20A Input Voltage = 7V Output Voltage = 2.5V Sw Freq= 750kHz Adjusting for Maximum Power Loss: (Fig. 1) Maximum power loss = 5W (Fig. 3) Normalized power loss for input voltage ≈ 0.925 (Fig. 4) Normalized power loss for output voltage ≈ 1.1 (Fig. 5) Normalized power loss for frequency ≈ 1.225 Adjusted Power Loss = 5W x 1.1 x 0.925 x 1.225 ≈ 6.23W Adjusting for SOA Temperature: (Fig. 2) SOA PCB Temperature = 90°C (Fig. 3) Normalized SOA PCB Temperature for input voltage ≈ 2.6°C (Fig. 4) Normalized SOA PCB Temperature for output voltage ≈ -3.5°C (Fig. 5) Normalized SOA PCB Temperature for frequency ≈ -7.5°C Adjusted SOA PCB Temperature = 90°C - 3.5°C + 2.6°C - 7.5° ≈ 81.6°C 0 1 02 03 04 05 06 07 08 09 0 1 0 0 1 1 0 1 2 0 1 3 0 PCB Temperature (ºC) Output Current (A) Safe Operating Area VIN = 12V VOUT = 1.6V fSW = 500kHz 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 Output Current (A) Power Loss (W) VIN = 12V VOUT = 1.6V TBLK = 125°C fSW = 500kHz Maximum Typical

www.irf.com 5 iP2001 Fig 7. IDD vs. Frequency Fig 5. Normalized Power Loss vs. Frequency Fig 3. Normalized Power Loss vs. VIN Fig 4. Normalized Power Loss vs. VOUT Typical Performance Curves Fig 6. Normalized Power Loss vs. Ripple Current 0.92 0.93 0.94 0.95 0.96 0.97 0.98 0.99 1.00 1.01 1.02 3579 1 1 1 3 Input Voltage (V) Power Loss (Normalized) -0.7 -0.4 0.0 0.4 0.7 1.1 1.4 1.8 2.1 2.5 2.8 SOA PCB Temperature Adjustment (ºC)VOUT = 1.6V IOUT = 20A fSW = 500kHz TBLK = 125°C 0.92 0.96 1.00 1.04 1.08 1.12 1.16 1.20 Output Voltage (V) Power Loss (Normalized) -7.0 -5.6 -4.2 -2.8 -1.4 0.0 1.4 2.8 SOA PCB Temperature Adjustment (ºC) VIN = 12V IOUT = 20A fSW = 500kHz TBLK = 125°C 0 200 400 600 800 1000 Switching Frequency (kHz) Average Current (mA) Does not include PRDY current 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 100 250 500 750 1000 Switchin Frequency (kHz) Power Loss (Normalized) -17.5 -14.0 -10.5 -7.0 -3.5 0.0 3.5 7.0 10.5 SOA Board Temperature Adjustment (ºC) VIN = 12V VOUT = 1.6V IOUT = 20A TBLK = 125°C 0.9 1.0 1.1 1.2 1.3 1.4 1.5 0 5 10 15 20 25 Peak to Peak Inductor Ripple Current (A) Power Loss (Normalized) -17 -14 -10 SOA Temperature Adjustment (°C) VIN = 12V VOUT = 1.6V IOUT = 20A fSW = 500kHz TBLK = 125°C

www.irf.com6 iP2001 4-Phase Reference Design Schematic 10K +5V ENABLE C1 0.022uF open 51K 10uF VID41 VCC 20 VID32 PGOOD19 VID23 PWM4 18 VID14 ISEN4 17 VID05 ISEN1 16 COMP6 PWM1 15 FB7 PWM2 14 FS/DIS8 ISEN2 13 GND9 ISEN3 12 VSEN10 PWM3 11 HIP6311 +5V VDD SGND PWM1 ENABLE PRDY VIN VSW1 PGND IP2001 U2 VDD SGND PWM1 ENABLE PRDY VIN VSW1 PGND VDD SGND PWM2 ENABLE PRDY VIN VSW2 PGND IP2001 U3 VDD SGND PWM2 ENABLE PRDY VIN VSW2 PGND C15 Open C16 Open C18 Open C19 Open 0.54uH 0.54uH 2K 1% 2K 1% +5V +5V 10uF 10uF 10uF 10uF ENABLE SWNODE1 SWNODE2 C17 100uF C20 100uF 10uF 10uF TP6 SWNODE1 TP7 SWNODE2 VDD SGND PWM3 ENABLE PRDY VIN VSW3 PGND IP2001 U4 VDD SGND PWM3 ENABLE PRDY VIN VSW3 PGND C21 Open C22 Open 0.54uH +5V 10uF C10 10uF SWNODE3 C23 100uF C11 10uF TP8 SWNODE3 VDD SGND PWM4 ENABLE PRDY VIN VSW4 PGND IP2001 U5 VDD SGND PWM4 ENABLE PRDY VIN VSW4 PGND C24Open C25 Open 0.54uH +5V C12 10uF C13 10uF SWNODE4 C26100uF C14 10uF TP9 SWNODE4 2K 1% 2K 1% VOUT Freq. Set Resistor Vin Vin Vin Vin R10 R12 R13 R11 TP14 PGND TP15 PGND TP17 PGND TP16 PGND TP5 PGOOD TP13 VOUT TP12 VOUT TP11 VOUT TP10 VOUT TP18 Vin TP19 +5V TP20 PGND C27 10uF +5V VID4 VID3 VID2 VID1 VID0 C28 22pF TP21 VOUT SENSE TP22 PGND SENSE VOUT SENSENE R14 R16 10K R15 10K R17 10K R18 10K C2910uF C30 10uF C32 10uF C31 10uF ENABLE ENABLE ENABLE VOUT SENSE C330.01uF X7R PGNDSENSE Note: Rx and Cx are add on components Rx Cx 4700pF Rx &Cx are not parts of PCB*

www.irf.com 7 iP2001 4-Phase Reference Design Bill of Materials VSW PGND PRDY ENABLE VDD SGND A A DC V Average Input Voltage Average Input Current Average Output Current Averaging Circuit V Average Output Voltage DCV Average VDD Voltage A Average VDD Current iP2001 PIN = VIN Average x IIN Average PDD = VDD Average x IDD Average POUT = VOUT Average x IOUT Average PLOSS = (PIN + PDD) - POUT VIN PWM td(on) td(off) PWM VSW 90% 10% 90% 10% Fig 8. Power Loss Test Circuit Fig 9. Timing Diagram Designator Value 1 Value 2 T ype Tolerance Packa geM f r . M f r . P a r t N o . C1 0.022uF 50V X7R 10% 0805 TD K C2012X7R1H223K C2 - C14, C27, C29 - C32 10.0uF 16V X5R 10% 1210 TD K C3225X5R1C106K C15, C16, C18, C19, C21, C22, C17, C20, C23, C26 100uF 6.3V X5R 10% 2220 TD K C5750X5R0J107K C28 22.0pF 50V COG 5% 0805 TD K C2012COG1H220J C33 0.010uF 50V X7R 10% 0805 TDK C2012X7R1H103K Cx 4700pF 50V X7R 10% 0603 TD K C1608X7R1H472K L1 - L4 0.54uH 27A Ferrite 20% SMT Panasonic ETQP6F0R6BFA R1, R2 1K 1/8W Thick film 5% 0805 ROHM MCR10EZHJ102 R10 - R14 0 1/8W Thick film <50m 0805 ROHM MCR10EZHJ000 R6, R15 - R18 10 K 1/8W Thick film 5% 0805 ROHM MCR10EZHJ103 R4 51 K 1/8W Thick film 5% 0805 ROHM MCR10EZHJ513 R5, R7, R8, R9 2K 1/8W Thick film 5% 0805 ROHM MCR10EZHJ202 Rx 51 1/10W Thick film 5% 0603 KOA RM73B1J510J S1 SPST 6 position Switch - SMT C&K Components SD06H0SK ST1 - ST4 4-40 - - - - Ke ystone 8412 U1 - - PWM controller 0 - 70°C SOIC20 Intersil HIP6311CB U2 - U5 - - DC-DC - 11 x 11 x 3mm IR IP2001

www.irf.com8 iP2001 Recommended PCB Footprint (Top View) Dimensions shown in inches (millimeters) VDD NC VIN PGND ENABLE PRDY VSWPWM NC NC NC NC NC NC NC NC NCNC NC NC NC PGND SGND

www.irf.com 9 iP2001 0.15 [.006] C 0.12 [.005] C 11.00 [.433] 2. DIMENSIONS ARE SHOWN IN MILLIMETERS [INCHES]. 3. CONTROLLING DIMENSION: MILLIMETER 1. DIMENSIONING & TOLERANCING PER ASME Y14.5M-1994. NOTES: (4X 1.1 [.043]) B 11.00 [.433] A 0.15 [.006] C 0.40 [.016] 0.80 [.032] 22X 0.15 [.006] C A B 0.08 [.003] C 133X Ø 0.55 [.0216] 0.45 [.0178] 2.66 [.1047] 2.46 [.0969] TOP VIEW BOTTOM VIEW SIDE VIEW 3.11 [.1224] 2.81 [.1107] C 0.45 [.0177] 0.35 [.0138] PACKAGE BODY. BALL DIAMETER, IN A PLANE PARALLEL TO DATUM C. SPHERICAL CROWNS OF THE SOLDER BALLS. 4. SOLDER BALL POSITION DESIGNATION PER JESD 95-1, SPP-010.

7 SOLDER BALL DIAMETER IS MEASURED AT THE MAXIMUM SOLDER

5 PRIMARY DATUM C (SEATING PLANE) IS DEFINED BY THE

6 BILATERAL TOLERANCE ZONE IS APPLIED TO EACH SIDE OF THE

Refer to the following application notes for detailed guidelines and suggestions when implementing iP0WIR Technology products: AN-1028: Recommended Design, Integration and Rework Guidelines for International Rectifier’s iPOWIR Technology BGA Packages This paper discusses the assembly considerations that need to be taken when mounting iPOWIR BGA’s on printed circuit boards. This includes soldering, pick and place, reflow, inspection, cleaning and reworking recommendations. AN-1029: Optimizing a PCB Layout for an iPOWIR Technology Design This paper describes how to optimize the PCB layout design for both thermal and electrical performance. This includes placement, routing, and via interconnect suggestions. AN-1030: Applying iPOWIR Products in Your Thermal Environment This paper explains how to use the Power Loss and SOA curves in the data sheet to validate if the operating conditions and thermal environment are within the Safe Operating Area of the iPOWIR product.

www.irf.com10 iP2001 Data and specifications subject to change without notice. This product has been designed and qualified for the industrial market. Qualification Standards can be found on IR’s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information .8/01 Tape & Reel Information Part Marking iP2001 XXXX 0123 0123 XXXX iP2001 0123 iP2001 XXXX 16mm FEED DIRECTION 24mm