IP1827

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Highly Integrated 25A Single‐input Voltage, Synchronous Buck Regulator March 5, 2012 | V1.4 2 97599 PIN DIAGRAM VinFB PIN 17 PIN 6 SS PIN 5 PIN 16 PIN 7 VOSMCOMP PIN 15 PIN 8 VOSPVOSO RT PIN 9 EN PIN 14 PIN 10 VCC PGD PIN 13 PIN 11 OCSET PIN 12 PIN 4 PVCC BiasGND PIN 1 SW PGND PIN 2 PIN 3 LGND Figure 3: iP1827 Package Bottom View 7.65mm x 7.65mm LGA

ORDERING INFORMATION

Package Tape and Reel Qty Part Number LGA (7.65mm x 7.65mm body) 2000 iP1827TRPbF Θj-pcb=2.3 0C/W

Highly Integrated 25A Single‐input Voltage, Synchronous Buck Regulator March 5, 2012 | V1.4 3 97599 FUNCTIONAL BLOCK DIAGRAM Clock OScillator S R Q Thermal Shutdown UVPVCC UVEN OCP PGnd PGD LGnd Fb Comp Rt PVCC Clock Ramp E/A 0.51V LDRi Fault Clock VCC PVCC En DRIVER Vin SW 0.69V SS Charge Pump Vosp Vosm Vref POR Voso OCSet Digital Pulse Generation LDRiss x4CLK S R Q HDRi Pre-Bias POR Fault SD UVCC EN_CP BB control Clock Voso OVP OVP POWER GOOD OVER VOLTAGE Fault BBRAKING 20uA 0.1V Fault R SQ 200mV SD HDRi Clock OCP POR SW SW OVER CURRENT LDO IntVcc BiasGND Figure 4: iP1827 Simplified Block Diagram

Highly Integrated 25A Single‐input Voltage, Synchronous Buck Regulator March 5, 2012 | V1.4 4 97599 TYPICAL APPLICATION DIAGRAM Figure 5: iP1827 Application Circuit Diagram for a 12V to 1.8V, 25A Point of Load Converter PVCC Fb Comp LGnd PGnd SW OCSet Vo PGD PGood Rt Vin=12V Vin Vosp VCC SS En Vosm VCC=3.3V Voso R8 7.5 K Rbot 604 Co=10X22uF/ 0805/X5R/6.3V Lo 0.3uH 2.2nF R10 57.6 4.22 K 8.2 nF 120 pF ROCSet 20.5 K CSS 0.1 uF Rt 36.5 K RPG 10 K

49.9 KR2

7.5k CVCC 10uF CPVCC 4.7uF Rtop 1.21K Rcomp 402 Cin=1X330uF/25V + 5X22uF/1206/ X5R/16V iP1827 BiasGnd

Highly Integrated 25A Single‐input Voltage, Synchronous Buck Regulator March 5, 2012 | V1.4 5 97599 PIN DESCRIPTIONS PIN # PIN NAME PIN DESCRIPTION 1 VIN Input voltage for power stage. Bypass capacitors between VIN and PGND should be connected very close to this pin and PGND (pin 3). 2 SW Switch node. This pin is connected to the output inductor. 3 PGND Power ground. This pin should be connected to the system’s power ground plane. Bypass capacitors between VIN and PGND should be connected very close to VIN pin (pin 1) and this pin. 4 PVCC Output of internal charge pump. Connect a 4.7uF to 10uF capacitor from this pin to local bias PGND (pin 12), very close to the pins. External 5V may also be connected to this pin for operation from 5V bias. 5 SS Soft start; a capacitor from SS and LGND sets the startup timing. 6 LGND Signal ground for internal reference and control circuitry. 7 VOSM Remote Sense Amplifier input. Connect to ground at the load. 8 VOSP Remote Sense Amplifier input. Connect to output at the load. 9 RT Use an external resistor from this pin to GND to set the switching frequency, very close to the pin. 10 VCC Input bias voltage for internal IC. This also powers the charge pump circuit in the IC. Connect a 10uF capacitor from this pin to local bias PGND (pin 12), very close to the pins. For 5V bias operation, this pin should be tied to ground. 11 OCSET Current Limit setpoint. A resistor may be connected from this pin to SW pin to set thresholds lower than those allowed by maximum current rating of the device. 12 BIASGND This pin serves as a ground for the MOSFET drivers. It should be connected to the negative terminal of the bias voltage at the VCC and/or PVCC capacitors. 13 PGD Power Good status pin. Output is open collector. Connect a pull up resistor from this pin to VCC. 14 EN Enable pin to turn on and off the IC.

15 VOSO Remote Sense Amplifier Output; also forms an input to the power good comparator and

overvoltage comparator. 16 COMP Output of error amplifier. An external resistor and capacitor network is typically connected from this pin to FB to provide loop compensation. 17 FB Inverting input to the error amplifier. This pin is connected directly to the output of the regulator or to the output of the remote sense amplifier, via resistor divider to set the output voltage and provide feedback to the error amplifier.

Highly Integrated 25A Single‐input Voltage, Synchronous Buck Regulator March 5, 2012 | V1.4 6 97599 ABSOLUTE MAXIMUM RATINGS VIN ‐0.3V to 25V VCC ‐ 0.3V to 3.9V PVCC ‐0.3V to 8V (Note 2) SW ‐ 0.3V to 25V (DC), ‐4V to 25V (AC, 100ns) BOOT ‐0.3V to 33V Input/output pins, except PGD, Vosp and Voso ‐ 0.3V to VCC + 0.3V PGD, Vosp and Voso ‐0.3V to PVCC + 0.3V (Note 2) PGND to LGND, BIASGND to LGND, Vosm to LGND ‐ 0.3V to + 0.3V Storage Temperature Range ‐55°C to 150°C Junction Temperature Range ‐ 40°C to 150°C ESD Classification JEDEC Class 1C (1KV) Moisture Sensitivity level JEDEC Level 3@250°C Note 1: Must not exceed 8V. Note 2: PVCC must not exceed 7.5V for Junction Temperature between ‐10°C and ‐40°C. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications are not implied. These devices are ESD sensitive, observe handling precautions to prevent electrostatic discharge damage.

Highly Integrated 25A Single‐input Voltage, Synchronous Buck Regulator March 5, 2012 | V1.4 7 97599 ELECTRICAL SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS SYMBOL DEFINITION MIN MAX UNITS VIN Input Voltage 1.5 16 PVCC Supply Voltage 4.5 7.5 VCC Supply Voltage 3.13 3.46 Boot to SW Supply Voltage 4.5 7.5 VO Output Voltage 0.6 0.75 Vin V IO Output Current 0 25 A Fs Switching Frequency 225 1650 kHz TJ Junction Temperature ‐ 40 125 °C

ELECTRICAL CHARACTERISTICS

Typical values are specified at TA = 25oC. PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT Power Loss Power Loss PLOSS Vin = 12V, VCC = 3.3V, VO = 1.8V, IO = 25A, Fs = 600kHz, L=0.3uH, TA = 25°C 4.2 W MOSFET Rds(on) Top Switch Rds(on)_Top VBoot – VSW = 5V, ID = 5A, Tj = 25°C 4.8 6 PVCC = 5V, ID = 25A, Tj = 25°C 2.3 2.7 Bottom Switch VCC = 3.3V, ID = 25A, Tj = 25°C 1.8 2.2 mΩ Reference Voltage Feedback Voltage VFB 0.6 V 40°C < Tj < 105°C ‐ 0.5 +0.5 Accuracy Supply Current VCC Supply Current (Standby) ICC(Standby) Enable low, No Switching, VCC = 3.3V 400 600 uA VCC Supply Current (Dyn) ICC(Dyn) Enable high, Fs = 500kHz, VCC = 3.3V 75 mA PVCC Supply Current (Standby) IPCC(Standby) Enable low, No Switching, PVCC = 5V 150 200 uA PVCC Supply Current (Dyn) IPCC(Dyn) Enable high, Fs = 500kHz, PVCC = 5V 30 mA Under Voltage Lockout PVCC – Start – Threshold PVCC_UVLO_Start PVCC Rising Trip Level 4.0 4.2 4.4 PVCC – Stop – Threshold PVCC_UVLO_Stop PVCC Falling Trip Level 3.7 3.9 4.1 V

Highly Integrated 25A Single‐input Voltage, Synchronous Buck Regulator March 5, 2012 | V1.4 8 97599 PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT VCC – Start – Threshold VCC_UVLO_Start VCC Rising Trip Level 2.6 2.8 3.1 VCC – Stop – Threshold VCC_UVLO_Stop VCC Falling Trip Level 2 2.2 2.5 Enable – Start – Threshold Enable_UVLO_Start Supply ramping up 1.14 1.2 1.36 Enable – Stop – Threshold Enable_UVLO_Stop Supply ramping down 0.9 1.0 1.06 V Oscillator Rt Voltage 1 V 450 500 550 Frequency Range FS 1350 1500 1650 kHz Ramp Offset Ramp (os) Note 3 0.4 V Min Pulse Width Dmin (ctrl) Note 3 50 ns Fixed Off Time Note 3 130 200 ns Max Duty Cycle Dmax 75 % Error Amplifier Input Bias Current IFb(E/A) ‐ 1 +1 µA Input Bias Current IVp(E/A) ‐ 1 +1 µA Sink Current Isink(E/A) 0.6 0.9 1.2 mA Source Current Isource(E/A) 5 8 12 mA Slew Rate SR Note 3 7 12 20 V/µs Gain‐Bandwidth Product GBWP Note 3 20 30 40 MHz DC Gain Gain Note 3 100 110 120 dB Maximum Voltage Vmax(E/A) 1.7 2 2.3 V Minimum Voltage Vmin(E/A) 100 mV Remote Sense Differential Amplifier Unity Gain Bandwidth BW_RS Note 3 3 6.4 9 MHz DC Gain Gain_RS Note 3 110 dB Offset Voltage Offset_RS ‐ 3 0 3 mV Source Current Isource_RS 3 9 20 mA Sink Current Isink_RS 0.4 1 2 mA Slew Rate Slew_RS Note 3, Cload = 100pF 2 4 8 V/µs VOSEN+ input impedance Rin_RS+ 70 120 200 kohm VOSEN‐ input impedance Rin_RS‐ Note 3 70 120 200 kohm Maximum Voltage Vmax_RS V(PVCC) – V(Vosp) 0.5 1 1.5 V Minimum Voltage Min_RS 50 mV Soft Start Soft Start Charge Current Iss_Charg 14 20 26 µA Clamp Voltage Vss (Clamp) 3 3.3 3.6 µA Offset Voltage Vss (offset) 100 170 250 mV

Highly Integrated 25A Single‐input Voltage, Synchronous Buck Regulator March 5, 2012 | V1.4 9 97599 PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT Shutdown Output Threshold SD 0.1 V Bootstrap Diode Forward Voltage I(Boot) = 30mA, Note 3 360 520 960 mV Switch Node SW Leakage Current lsw SW = 0V, Enable = 0V 3 µA Charge Pump (PVCC) Output Voltage PVCC VCC = 3.3V, Fs = 1500 kHz, Cload = 2.2uF 5.7 6.15 6.5 V Oscillator Frequency Fs_CP Fs kHz Body Braking BB Threshold BB_threshold Fb > Vref, Sw duty cycle 0 % Power Good Power Good Lower Threshold VPG (lower) Voso rising 0.48 0.51 0.54 V Lower Threshold Delay VPG (lower)_Dly Voso rising 256/Fs s PGood Voltage Low PG (voltage) IPGood = ‐5mA 0.5 V Leakage Current ILEAKAGE 0 1 µA Over Voltage Protection (OVP) OVP Trip Threshold OVP (trip) Voso rising 0.67 0.7 0.73 V OVP Fault Prop Delay OVP (delay) Voso rising, Note 3 200 ns Over‐Current Protection OC Trip Current ITRIP OC set pin left floating, PVCC = 6.5V, TJ = 85°C 36 40 44 A SS Off Time SS_Hiccup Note 3 4096/ Fs s Thermal Shutdown Thermal Shutdown Note 3 145 °C Hysteresis Note 3 20 °C Notes 3. Guaranteed by design but not tested in production.

Highly Integrated 25A Single‐input Voltage, Synchronous Buck Regulator March 5, 2012 | V1.4 10 97599 TYPICAL OPERATING CHARACTERISTICS (‐40°C ‐ 125°C) Icc (Standby) 200 240 280 320 360 400 440 480 520 560 600 -40 -20 0 20 40 60 80 100 120 Temp[ 0C] [uA] IPVcc (Standby) 100 120 140 160 180 200 - 4 0 - 2 00 2 04 06 08 0 1 0 0 1 2 0 Temp[ 0C] [uA] Fs 450 460 470 480 490 500 510 520 530 540 550 -40 -20 0 20 40 60 80 100 120 Temp[ 0C] [kHz] VFB 0.591 0.593 0.595 0.597 0.599 0.601 0.603 0.605 0.607 0.609 - 4 0 - 2 00 2 04 06 08 0 1 0 0 1 2 0 Temp[ 0C] [V] + 0.5% - 0.5% VPG (lower) 0.48 0.485 0.49 0.495 0.5 0.505 0.51 0.515 0.52 0.525 0.53 0.535 0.54 - 4 0 - 2 00 2 04 06 08 0 1 0 0 1 2 0 Temp[0C] [V] Icc (Dyn) - 4 0 - 2 00 2 04 06 08 0 1 0 0 1 2 0 Temp[ 0C] [mA] IPVcc (Dyn) - 4 0 - 2 00 2 04 06 08 0 1 0 0 1 2 0 Temp[0C] [mA] Iss_charg - 4 0 - 2 00 2 04 06 08 0 1 0 0 1 2 0 Temp[ 0C] [uA] Offset_RS -2.5 -1.5 -0.5 0.5 1.5 2.5 - 4 0 - 2 00 2 04 06 08 0 1 0 0 1 2 0 Temp[0C] [mV] OVP (trip) 0.67 0.675 0.68 0.685 0.69 0.695 0.7 0.705 0.71 0.715 0.72 0.725 0.73 -40 -20 0 20 40 60 80 100 120 Temp[0C] [V]

Highly Integrated 25A Single‐input Voltage, Synchronous Buck Regulator March 5, 2012 | V1.4 11 97599 TYPICAL OPERATING CHARACTERISTICS (‐40°C ‐ 125°C) VCC_UVLO_Start 2.6 2.65 2.7 2.75 2.8 2.85 2.9 2.95 3.05 3.1 - 4 0 - 2 00 2 04 06 08 0 1 0 0 1 2 0 Temp [0C] [V] PVCC_UVLO_Start 4.04 4.08 4.12 4.16 4.2 4.24 4.28 4.32 4.36 4.4 - 4 0 - 2 00 2 04 06 08 0 1 0 0 1 2 0 Temp [ 0C] [V] Enable_UVLO_Start 1.14 1.16 1.18 1.2 1.22 1.24 1.26 1.28 1.3 1.32 1.34 1.36 - 4 0 - 2 00 2 04 06 08 0 1 0 0 1 2 0 Temp[ 0C] [V] VCC_UVLO_Stop 2.05 2.1 2.15 2.2 2.25 2.3 2.35 2.4 2.45 2.5 - 4 0 - 2 00 2 04 06 08 0 1 0 0 1 2 0 Temp[0C] [V] PVCC_UVLO_Stop 3.7 3.74 3.78 3.82 3.86 3.9 3.94 3.98 4.02 4.06 4.1 -40 -20 0 20 40 60 80 100 120 Temp [ 0C] [V] Enable_UVLO_Stop 0.9 0.916 0.932 0.948 0.964 0.98 0.996 1.012 1.028 1.044 1.06 -40 -20 0 20 40 60 80 100 120 Temp[ 0C] [V] ILtrip - 4 0 - 2 00 2 04 06 08 0 1 0 0 1 2 0 Temp[ 0C] [A] Vin=12V Vo=1.8V Fsw=600kHz PVcc=5V ROCSet open ILtrip - 4 0 - 2 00 2 04 06 08 0 1 0 0 1 2 0 Temp[ 0C] [A] Vin=12V Vo=1.8V Fsw=600kHz Vcc=3.3V ROCSet open

Highly Integrated 25A Single‐input Voltage, Synchronous Buck Regulator March 5, 2012 | V1.4 12 97599 TYPICAL OPERATING CHARACTERISTICS (‐40°C ‐ 125°C) RDSON of Control FET over temperature at PVCC=5V 3.5 3.75 4.25 4.5 4.75 5.25 5.5 5.75 -40 -20 0 20 40 60 80 100 120 Temp[0C] RDSON(mΩ) RDSON of Sync FET over temperature 0.7 0.8 0.9 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 - 4 0 - 2 00 2 04 06 08 0 1 0 0 1 2 0 Temp[0C] RDSON(mΩ) Rdson@Vcc=3.3V Rdson@PVcc=5V

Highly Integrated 25A Single‐input Voltage, Synchronous Buck Regulator March 5, 2012 | V1.4 14 97599 Figure 7a: Normal Start up, Device turns on when the Bus voltage reaches 10.2V Bus Voltage (12V) PVcc(5V) or Vcc(3.3V) Enable > 1.2V SS Figure 7b: Recommended startup sequence with Vcc or PVcc PRE‐BIAS STARTUP iP1827 is able to start up into pre‐charged output, which prevents oscillation and disturbances of the output voltage. The output starts in asynchronous fashion and keeps the synchronous MOSFET off until the first gate signal for control MOSFET is generated, following which, the synchronous MOSFET starts with a narrow duty cycle of 12.5% and gradually increases its duty cycle in steps of 12.5%, with 32 cycles at each step until the end of pre‐bias. Vo[V] [Time] Pre-Bias Voltage Figure 8: Pre‐Bias startup At the end of the pre‐bias stage, the synchronous MOSFET is switched complementary to the Control MOSFET. Figure 8 shows a typical Pre‐Bias condition at start up. HDRv

32 End of

... Figure 9: Pre‐Bias startup pulses SOFT‐START The iP1827 has a programmable soft‐start to control the output voltage rise and to limit the current surge at the start‐up. To ensure correct start‐up, the soft‐start sequence initiates when the Enable and Vcc rise above their UVLO thresholds and generate the Power On Ready (POR) signal. The internal current source (typically 20uA) charges the external capacitor Css linearly from 0V to Vcc. Figure 10 shows the waveforms during the soft start. The start up time can be estimated by:   (1) *0.2-0.8 ss SS start I CT  During the soft start the OCP is enabled to protect the device for any short circuit and over current condition.

Highly Integrated 25A Single‐input Voltage, Synchronous Buck Regulator March 5, 2012 | V1.4 16 97599 An overcorrect detection trips the OCP comparator, latches OCP signal and cycles the soft start function in hiccup mode. The hiccup is performed by shorting the soft‐start capacitor to ground and counting the number of switching cycles. The Soft Start pin is held low until 4096 cycles have been completed. Following this, the OCP signal resets and the converter recovers. After every soft start cycle, the converter stays in this mode until the overload or short circuit is removed. For the iP1827, the Sync FET is turned OFF on the falling edge of a PWMSet or Clock signal that has duration of 25% of the switching period. For operation at the maximum duty cycle, the OCP circuit samples current for 40 ns, starting 40 ns after the low drive signal for the Sync FET > 70% of PVcc. TABLE 2: OVERCURRENT SETTING VS. EXTERNAL ROCSET Iotrip (A) External Rocset (kohm) 15 2.61 16 2.94 17 3.24 18 3.65 19 4.02 20 4.53 21 4.99 22 5.62 23 6.34 24 7.15 25 8.06 26 9.09 27 10.5 28 12.1 29 14.3 30 16.9 31 20.5 32 26.1 33 34 34 48.7 35 80.6 36 226

37 Open

For operating duty cycles less than the maximum duty cycle of 75%, the OCP circuit still samples current for typically 40ns, but starts sampling 40 ns after the rising edge of PWMSet. Thus, for low duty cycle operation, the inductor current is sensed close to the valley. This allows a longer delay after the falling edge of the switch node, than the corresponding delay for an over‐current sensing scheme which samples the current at the peak of the inductor current. This longer delay serves to filter out any noise on the switch node and hence on the OCSet pin, making this method more immune to false tripping. THERMAL SHUTDOWN Temperature sensing is provided inside iP1827. The trip threshold is typically set to 145oC. When the trip threshold is exceeded, thermal shutdown turns off both MOSFETs and discharges the soft start capacitor. Automatic restart is initiated when the sensed temperature drops within the operating range. There is a 20oC hysteresis in the thermal shutdown threshold. TRIMMABLE RISING EDGE DEADBAND The iP1827 has a rising edge deadband that is post‐ package trimmable. It is typically trimmed to 5ns‐10ns which is an optimal range to minimize switching transition loss and at the same time, prevent cross conduction. REMOTE VOLTAGE SENSING True differential remote sensing in the feedback loop is critical to high current applications where the output voltage across the load may differ from the output voltage measured locally across an output capacitor at the output inductor, and to applications that require die voltage sensing. The Vosp and Vosm pins of the iP1827 form the inputs to a remote sense differential amplifier with high speed, low input offset (post‐package trimmed to +/‐3mV) and low input bias current which ensure accurate voltage sensing and fast transient response in such applications. It should be noted, however, that the output Voso of the difference amplifier also forms the input toa power good comparator and overvoltage comparator, both referenced to an upper threshold of 0.7V as discussed in the next section. Hence, in applications where Vo > 0.6V, it is necessary to use a resistive divider network after Vo to attenuate the sensed output voltage signal between the remote Vo and the remote ground to 0.6V, which is then applied between Vosp and Vosm.

Highly Integrated 25A Single‐input Voltage, Synchronous Buck Regulator March 5, 2012 | V1.4 19 97599 DESIGN PROCEDURE

APPLICATION INFORMATION

The following example is a typical application for iP1827. The application circuit is shown on page 1. Vin = 12V (13.2V max) Vo = 1.8V Io = 25A ΔVo (transient) ≤ ±90mV for ΔIo = 10.5A @ 2.5A/µs ΔVo (ripple) ≤ ±13.5mV (±0.75%) Fs = 600kHz ENABLING THE IP1827 As explained earlier, the precise threshold of the Enable lends itself well to implementation of a UVLO for the Bus Voltage. For a typical Enable threshold of VEN = 1.2 V VRR RV ENin (6) 1.2* (min)  (7) min EN)in( EN VV VRR  For a Vin (min) = 10.2V, R1 = 49.9K and R2 = 7.5K is a good choice. PROGRAMMING THE FREQUENCY For Fs = 600 kHz, select Rt = 36.5 kΩ, using Table 1. OUTPUT VOLTAGE PROGRAMMING Output voltage is programmed by the reference voltage and external voltage divider. If the remote sense feature is used, the divider is connected to the Vosp and Vosm pins. If only local sensing is used for feedback, with the remote sense amplifier used only in the over‐voltage protection, circuit, the resistive divider should be connected to the Fb pin. For this design, with high output current requirements, we choose to use the true differential remote sense feature. The Fb pin is the inverting input of the error amplifier, which is internally referenced to 0.6V. This references the output of the remote sense amplifier to 0.6V also. In order to satisfy this condition, the voltage between the Vosp and Vosm pins of the error amplifier should be 0.6V when the output is at its desired value. The output voltage is defined by using the following equation: (8) 1    bot top refo R RVV when an external resistor divider is connected to the output as shown in Figure 16. Equation (8) can be rewritten as: (9)    ref refo bottop V VVRR Figure 16: Typical application of the iP1827 for programming the output voltage iP 1827 Vin Enable R 1 R 2 Vosm VOUT Rbot Rtop Vosp iP1827 Rcomp

Highly Integrated 25A Single‐input Voltage, Synchronous Buck Regulator March 5, 2012 | V1.4 20 97599 For our design, Rbot is selected to be 604 ohm. This selection is based on a trade‐off between two considerations: 1) The resistive divider should be as low impedance as possible in order to have minimal impact on the impedance seen at the Vosp and Vosm pins. 2) The resistive divider should have high enough impedance so as to minimize the bleed current from the output. Hence, from Equation (9), Rtop = 1.21K. In order to ensure that the Vosp and Vosm see balanced impedances, it is advisable to use Rcomp such that: (10) Ω 402||  bottopcomp RRR SOFT‐START PROGRAMMING The soft‐start timing can be programmed by selecting the soft‐start capacitance value. From (1), for a desired start‐ up time of the converter, the soft start capacitor can be calculated by using: (11) 0.033 ) ms ( F) (  startSS TC  Where Tstart is the desired start‐up time (ms). For a start‐up time of 3ms, the soft‐start capacitor will be 0.099μF. Choose a 0.1μF ceramic capacitor. INPUT CAPACITOR SELECTION The ripple current generated during the on time of the upper MOSFET should be provided by the input capacitor. The RMS value of this ripple is expressed by: (12) )1( DDII oRMS  (13) in o V VD  Where: D is the Duty Cycle IRMS is the RMS value of the input capacitor current. Io is the output current. For Io=25A and D = 0.15, the IRMS = 8.93A. Ceramic capacitors are recommended due to their peak current capabilities. They also feature low ESR and ESL at higher frequency which enables better efficiency. For this application, it is advisable to have 5x22uF 16V ceramic capacitors ECJ‐3YX1C106K from Panasonic. In addition to these, although not mandatory, a 1X330uF, 25V SMD capacitor EEV‐FK1E331P may also be used as a bulk capacitor and is recommended if the input power supply is not located close to the converter. INDUCTOR SELECTION The inductor is selected based on output power, operating frequency and efficiency requirements. A low inductor value causes large ripple current, resulting in the smaller size, and a faster response to a load transient but poor efficiency and high output noise. Generally, the selection of the inductor value can be reduced to the desired maximum ripple current in the inductor. The optimum point is usually found between 20% and 50% ripple of the output current. For the buck converter, the inductor value for the desired operating ripple current can be determined using the following relation: (14) 1 ; sin o oin s oin FiV VVVL FDtt iLVV   Where: Vin = Maximum input voltage V0 = Output Voltage Δi = Inductor Ripple Current Fs = Switching Frequency Δt – Turn on time D – Duty Cycle If Δi ≈ 35%(Io), then the output inductor is calculated to be 0.29μH. Select L = 0.3μH. The 59PR9874N from Vitec provides a compact inductor suitable for this application.

Highly Integrated 25A Single‐input Voltage, Synchronous Buck Regulator March 5, 2012 | V1.4 22 97599 VOSO VREF CPOLE C4R3 Ve FZ FPOLE E/A Zf Frequency Gain(dB) H(s) dB Fb Comp ZIN Figure 18: Type II compensation network and its asymptotic gain plot The transfer function (Ve/Voso) is given by: (18) 1)( CsR CsR Z Z sHV V IN f oso The (s) indicates that the transfer function varies as a function of frequency. This configuration introduces a gain and zero, expressed by: (20) **2 (19) CRF R RsH z First select the desired zero‐crossover frequency (Fo):  sESRo FFF *1/10~1/5 F and o  Use the following equation to calculate R3: (21) *** LCmin ESRo FFV RFFR Where: Vin = Maximum Input Voltage Fo = Crossover Frequency FESR = Zero Frequency of the Output Capacitor FLC = Resonant Frequency of the Output Filter R8 = Feedback Resistor β = Vref/Vo Fm=Modulator gain To cancel one of the LC filter poles, place the zero before the LC filter resonant frequency pole: (22) 1*75.0 % 75 oo z LCz CL F FF Use equations (20), (21) and (22) to calculate C4. One more capacitor is sometimes added in parallel with C4 and R3. This introduces one more pole which is mainly used to suppress the switching noise. The additional pole is given by: (23) ***2 POLE POLE P CC CCR F The pole sets to one half of the switching frequency which results in the capacitor CPOLE: (24) 1 s s POLE *F*R C*F*R C  For a general solution for unconditional stability for any type of output capacitors, and a wide range of ESR values, we should implement local feedback with a type III compensation network. The typically used compensation network for voltage‐mode controller is shown in Figure 19. Again, the transfer function is given by: IN f oso e Z ZsHV V  )(

Highly Integrated 25A Single‐input Voltage, Synchronous Buck Regulator March 5, 2012 | V1.4 23 97599 By replacing Zin and Zf according to Figure 19, the transfer function can be expressed as:  (25) .... )1(*1)( 1)1( )( 710 3348 108743 CsRCC CCsRCCsR RRsCCsR sH    VOSO VREF R8R10 C4R3 Ve FZ1 FZ2 FP2 FP3 E/A Zf ZIN Frequency Gain(dB) H(s) dB Fb Comp Figure 19: Type III Compensation network and its asymptotic gain plot The compensation network has three poles and two zeros and they are expressed as follows: (30) 2 )(2 (29) 2 (28) 2 2 (27) 2 (26) 0 871087 710 RCRRCF CRF CR CC CCR F CRF F Z Z P P P  Cross over frequency is expressed as: (31) **2 oo mino CLFVCRF  Based on the frequency of the zero generated by the output capacitor and its ESR, relative to crossover frequency, the compensation type can be different. The table below shows the compensation types for relative locations of the crossover frequency. Compensator Type FESR v/s F0 Output Capacitor Type II FLC < FESR < F0 < FS/2 Electrolytic Tantalum Type III FLC < F0 < FESR Tantalum Ceramic The higher the crossover frequency, the potentially faster the load transient response will be. However, the crossover frequency should be low enough to allow attenuation of switching noise. Typically, the control loop bandwidth or crossover frequency is selected such that: The DC gain should be large enough to provide high DC‐regulation accuracy. The phase margin should be greater than 45o for overall stability. For this design we have: Vin = 12V Vo = 1.8V β = Vref/Vo=0.333 Modulator gain = Fm = 0.65, from Figure 15 Vref = 0.6V Lo = 0.3uH Co = 10x22uF, ESR = 3mOhm each It must be noted here that the value of the capacitance used in the compensator design must be the small signal value. For instance, the small signal capacitance of the 22uF capacitor used in this design is 12uF at 1.8V DC bias and 600kHz frequency. It is this value that must be used for all computations related to the compensation. The small signal value may be obtained from the manufacturer’s datasheets, design tools or SPICE models. Alternatively, they may also be inferred from measuring the power stage transfer function of the converter and measuring the double pole frequency FLC and using equation (16) to compute the small signal Co.

Highly Integrated 25A Single‐input Voltage, Synchronous Buck Regulator March 5, 2012 | V1.4 24 97599 These result in: FLC=26.53kHz FESR=4.4MHz Fs/2=300kHz Select crossover frequency Fo=110 kHz Since FLC<Fo<Fs/2<FESR, Type III is selected to place the pole and zeros. Detailed calculation of compensation Type III: Desired Phase Margin Θ = 80° kHz 9.62 sin1 sin1 2   oZ FF kHz 1257.31 sin1 sin1 2   oP FF kHz 4.81 *0.5 21  ZZ FF kHz 300*0.53  sP FF Select: C7 = 2.2nF Calculate: R3, C3 and C4: ***

2 RFVC

Select: R3 = 4.22 kΩ nF 8.2 :Select nF, 7.84 ;2 4  CCRFC pF 120 :Select ,pF 125.71 ;2 3  CCRFC Calculate: R10, R8 and R9: Ω 57.6 :Select ,Ω 60 ;2 1010 10  RRFCR ,kΩ 7.46 ;-2 810 8  RRFCR Select: R8 = 7.5 kΩ PROGRAMMING THE CURRENT‐LIMIT The Current‐Limit threshold can be set by connecting a resistor (ROCSet) from the SW pin to the OCSet pin. The resistor can be selected by using Table 2. In order to set a trip current of 31A, we may select ROCSet = 20.5K, using Table 2. SETTING THE POWER GOOD THRESHOLD A window comparator internally sets a lower Power Good threshold at 0.51V and an upper Power Good threshold at 0.7V. When the voltage at the Voso pin is within the window set by these thresholds, PGood is asserted. The power good output PGD is an open drain output. Hence, it is necessary to use a pull up resistor RPG from PGD pin to Vcc. The value of the pull‐up resistor must be chosen such as to limit the current flowing into the PGD pin, when the output voltage is not in regulation, to less than 5mA. A typical value used is 10kΩ. It must be noted that if the voltage on Voso exceeds the upper threshold 0.7V, not only is PGD de‐asserted, but also an overvoltage fault is flagged, following which, even if the overvoltage condition gets resolved, the converter can be re‐started only by cycling Vcc or Enable.

Highly Integrated 25A Single‐input Voltage, Synchronous Buck Regulator March 5, 2012 | V1.4 26 97599 TYPICAL OPERATING WAVEFORMS Vin=12.0V, Vcc=3.3V, Vo=1.8V, Io=3.5A ‐ 14A, Room Temperature, no airflow Figure 26: Transient Response, 3.5A to 14A step (2.5A/us) Ch2:Vout

Highly Integrated 25A Single‐input Voltage, Synchronous Buck Regulator March 5, 2012 | V1.4 27 97599 TYPICAL OPERATING WAVEFORMS Vin=12.0V, Vcc=3.3V, Vo=1.8V, Io=3.5A ‐ 14A, Room Temperature, no airflow Figure 27: Transient Response, 24.5A to 25A step (2.5A/us) Ch2:Vout

Highly Integrated 25A Single‐input Voltage, Synchronous Buck Regulator March 5, 2012 | V1.4 28 97599 TYPICAL OPERATING WAVEFORMS Vin=12.0V, Vcc=3.3V, Vo=1.8V, Io=0A ‐ 25A, Room Temperature Figure 28: Bode Plot at 25A load shows a bandwidth of 110.88kHz and phase margin of 51.29 degrees

Highly Integrated 25A Single‐input Voltage, Synchronous Buck Regulator March 5, 2012 | V1.4 30 97599 THERMAL IMAGES Vin=12.0V, Vcc=3.3V, Vo=1.8V, Io=0A‐25A, Room Temperature, 200 LFM Figure 31: Thermal Image of the board at 25A load Test point 1 is iP1827 Test point 2 is inductor

Highly Integrated 25A Single‐input Voltage, Synchronous Buck Regulator March 5, 2012 | V1.4 32 97599 PVCC Fb Comp LGnd PGnd SW OCSet Vo PGD PGood Rt Vin=3.3V Vin Vosp VCC SS En Vosm Voso BiasGnd Figure 34: Single 3.3V Application

Highly Integrated 25A Single‐input Voltage, Synchronous Buck Regulator March 5, 2012 | V1.4 33 97599 LAYOUT CONSIDERATIONS The layout is very important when designing high frequency switching converters. Layout will affect noise pickup and can cause a good design to perform with less than expected results. Make all the connections for the power components in the top layer with wide, copper filled areas or polygons. In general, it is desirable to make proper use of power planes and polygons for power distribution and heat dissipation. The inductor, output capacitors and the iP1827 should be as close to each other as possible. This helps to reduce the EMI radiated by the power traces due to the high switching currents through them. The input capacitors should be placed as close as possible to the PGnd pad. The connection of the Vin pad to the Vin power polygon should be low impedance, using several vias in parallel. The layout must ensure minimum length ground path and enough copper for input and output capacitors with a direct connection. The iP1827 has a local power ground pad called Bias Gnd (pin 12) for bypassing Vcc or PVcc supplies. The analog or signal ground, LGnd, is used as a separate control circuit ground to which all signals are referenced. The analog ground polygon should be connected to BiasGnd through a single point connection using a 0 ohm resistor, at a location away from noise sources. The PGnd pad (Pin 3) should be connected to system power Ground. In order to minimize coupling switching noise into other layers, the area of the switch node copper should be kept small. It is also advisable to keep the switch node copper localized to the top layer. The critical bypass components such as capacitors for Vcc should be close to their respective pins. It is important to place the feedback components including feedback resistors and compensation components close to Fb and Comp pins. A pair of sense traces running very close to each other and away from any noise sources should be used to implement true differential remote sensing of the voltage. If remote sense is not used, the output voltage sense trace used for feedback should be tapped from a low impedance point such as directly from an output capacitor. The iPOWiR package is a thermally enhanced package. Based on thermal performance it is recommended to use at least a 6‐layers PCB. Figures 25A‐f illustrate the implementation of the layout guidelines outlined above, on the IRDC1827 6 layer demoboard. Figure 35a: IRDC1827 demoboard layout considerations – Top Layer Enough copper & minimum length ground path between Input and Output All bypass caps (Marked in Cyan) should be placed as close as possible to their connecting pins BiasGnd Single Point Connection of AGND and BiasGnd Resistors Rt (marked in Brown) should be placed as close as possible to their pins Compensation parts (Marked in dark blue) should be placed as close as possible to the Comp pin Switch node should have small area and should be localized to Top layer Optional on board load transient circuit: Not Critical Switch node should have small area and should be localized to Top layer

Highly Integrated 25A Single‐input Voltage, Synchronous Buck Regulator March 5, 2012 | V1.4 35 97599 METAL AND COMPONENT PLACEMENT Figure 36: PCB Metal and Component Placement * Contact International Rectifier to receive an electronic PCB Library file in your preferred format.

Highly Integrated 25A Single‐input Voltage, Synchronous Buck Regulator March 5, 2012 | V1.4 36 97599 SOLDER RESIST  It is recommended that the lead lands are Non Solder Mask Defined (NSMD). The solder resist should be pulled away from the metal lead lands by a minimum of 0.025mm to ensure NSMD pads.  The three power land pads should be Solder Mask Defined (SMD), with a minimum overlap of the solder resist onto the copper of 0.05mm to accommodate solder resist mis‐alignment.  Ensure that the solder resist in‐between the lead lands and the pad land is ≥ 0.15mm due to the high aspect ratio of the solder resist strip separating the lead lands from the power pad lands. Figure 37: Solder resist * Contact International Rectifier to receive an electronic PCB Library file in your preferred format.

Highly Integrated 25A Single‐input Voltage, Synchronous Buck Regulator March 5, 2012 | V1.4 37 97599 STENCIL DESIGN  The Stencil apertures for the lead lands should be approximately 80% of the area of the lead pads. Reducing the amount of solder deposited will minimize the occurrences of lead shorts. If too much solder is deposited on the three power land pads the part will float and the lead pads will be open.  The maximum length and width of the power land pads stencil aperture should be equal to the solder resist opening minus an annular 0.2mm pull back to decrease the incidence of opens to the lead lands or use the recommended stencil design below. Figure 38: Stencil design * Contact International Rectifier to receive an electronic PCB Library file in your preferred format.

Highly Integrated 25A Single‐input Voltage, Synchronous Buck Regulator March 5, 2012 | V1.4 39 97599 0.12 [.005] C 2. DIMENSIONS ARE SHOWN IN MILLIMETERS [INCHES]. 3. CONTROLLING DIMENSION: MILLIMETERS 1. DIMENSIONING & TOLERANCING PER ASME Y14.5M-1994. NOTES: SIDE VIEW C PACKAGE BODY. LAND PAD OPENINGS. 4 LAND PAD OPENINGS.

5 PRIMARY DATUM C (SEATING PLANE) IS DEFINED BY THE

6 BILATERAL TOLERANCE ZONE IS APPLIED TO EACH SIDE OF THE

0.15 [.006] C 2X 6 B A 0.15 [.006] C 2X 6 7. NOT TO SCALE. 1.66 [.065] 14X 0.508 X 0.508 CORNER ID 7.650 [0.301] 7.650 [0.301] BOTTOM VIEW TOP VIEW 1.35 2.41 3.62 7.32 0.36 1.43 2.49 3.56 4.63 5.69 6.76 0.28 1.21 2.05 3.86 4.71 7.27 Figure 41: Mechanical Outline Drawing Data and specifications subject to change without notice 12/10. This product will be designed and qualified for the Consumer market. Qualification Standards can be found on IR’s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information. www.irf.com