IP1206PBF IRF | Alldatasheet

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Technical content

2/26/2008www.irf.com 1 iP1206PbF Synchronous Buck Multiphase Optimized LGA Power Block Integrated Power Semiconductors, PWM Control, & PassivesFeatures

  • Input voltage range of 7.5V to 14.5V
  • Output voltage range of 0.8V to 5.5V
  • Output voltage accuracy of +/-1%
  • Output current range of 0A to 30A
  • Operation up to 600kHz
  • Lossless current limit
  • Output overvoltage protection
  • Pre-Bias start-up
  • External synchronization
  • Output voltage tracking
  • Output voltage sequencing
  • Over temperature protection

Description

The iP1206 is a fully optimized solution for medium current synchronous buck applications. The iP1206 can be configured as a dual output voltage power supply delivering up to 15A of current per output. Alternatively, the iP1206 can be configured as a single output voltage power supply delivering up to 30A of current. In both cases, the power stages are operated 180º out of phase. This reduces the amount of input RMS current and lessens the quantity of input capacitors needed. iPOWIR Technology offers designers an innovative board space saving solution for applications requiring high power densities. iPOWIR technology eases design for applications where component integration offers benefits in performance and functionality. iPOWIR technology solutions are also optimized internally for layout, heat transfer, and component selection.

Applications

  • Embedded Telecom Systems
  • Distributed Point of Load Power Architectures
  • Powering Dual Voltage ASICs
  • Microprocessor Power Supplies
  • General DC/DC Converters Package

T & R Orientation iP1206PbF LGA 10 - Fig. 29 iP1206TRPbF LGA - 750 Single OutputDual Output Typical Application PD-60319

2/26/2008www.irf.com 2 iP1206PbF Package Pinout Diagram ABSOLUTE MAXIMUM RATINGS (Voltages referenced to GND)

  • ESD Classification ……………………………….. JEDE C, JESD22-A114 (HBM[1KV], Class 1C) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those listed in the “Recommended Operating Conditions” section of this specification is not implied. CC2 SS2 VIN2 PGND VSW2 PGND VCB2 OC2 VCH VCL OC1 VCB1 PGND

13 VSW1

2/26/2008www.irf.com 3 iP1206PbF Recommended Operating Conditions Electrical Specifications Unless otherwise specified, these specification apply over Vcc=12V, 0oC<Tj<105oC Symbol Definition Min Max Units VIN1, VIN2 Input Supply Voltage 7.5 14.5 V VCC Bias Supply Voltage 7.5 14.5 V Io (Note1) Output current per Phase 0 15 A Fs Operating frequency 200 600 kHz Tj Junction temperature -40 125 oC µA282318Sink/Source Current V0.25--Disable Voltage Level VIN = ENABLE = 12VV-3.0-Voltage Level Soft Start 1,2 Rising & FallingmV--150Hysteresis V1.34-1.14Turn-on Threshold (VIH ) Enable TJ = -40C to 125 (Note 2)V0.8100.80.784 TJ = 0ºC to 105ºC (Note 2)V0.8080.80.792 System Set Point Accuracy DC Output Regulation VIN Rising & FallingmV--500Hysteresis V6.75-6.1VCC Falling V7.5-6.9VCC Rising Power-On Reset (POR) VIN = 12V, ENABLE = 0VmA20.5-VIN Supply Current (Static) VIN = 12V, VO1 = V02 = 1.5V, IO1 = IO2 = 15A, fSW = 300kHz, TBLK = 25ºCW6.55-Power Loss Supply Power ConditionsUnitsMaxTypMinPARAMETER SS=0V ; no switching; Vcc tied to VCLmA3025-VCC Supply Current (Static) SS=0V ; no switchingmA1210-VCH Supply Current (Static)

2/26/2008www.irf.com 4 iP1206PbF Electrical Specifications V--0.3Turn off Threshold V5--Turn on Threshold V0.6--SYNC LOW Level Threshold (VIL ) V--2SYNC HIGH Level Threshold (VIH ) ns-300200SYNC Pulse Duration 20% above Free Running FreqkHz1200--SYNC Frequency Range FS = 300kHzns150--Minimum Pulse Width FS = 300kHz, FB = 0V%--84Maximum Duty Cycle FB = 1V%0--Minimum Duty Cycle V-1.25-Ramp Amplitude FS = 300kHz%112-88Frequency Accuracy kHz600-200Frequency Range (Note 3)VVO 3-0TRACK pin Voltage Range (Note 3)VVCC -2-0.4VP pin Voltage Range FB to VrefmV3.5--3.5Input Offset Voltage µmho5000-3000Transconductance µA280200120Sink/Source Current Soft Start Pin = 3VµA-0.5-0.1-Input Bias Current Error Amplifier 1,2 Output Voltage set to 1.25Vref (Note3)µs5--Propagation Delay to Shutdown Percentage of Voltage Reference%120115110Start Threshold Over Voltage Protection ISINK = 2mAV0.50.1-PGOOD1/2 Output Low Voltage Percentage of Voltage Reference%959080FB1/2S Threshold POWER GOOD Monitor Oscillator Sequence ConditionsUnitsMaxTypMinPARAMETER

2/26/2008www.irf.com 5 iP1206PbF Note1: Continuous output current determined by input and output voltage setting. Refer to SOA curve. Note2: FB1,2 connected to CC1,2. Measured at the CC1,2 pin. Production tested at 25ºC. Other temperatures guaranteed by design. Note3: Guaranteed by design but not tested in production. Note4: Block Temperature is defined as any Die temperature within the package. Electrical Specifications mA110Current Limit VCC = 9V, ILOAD = 100mAV2Dropout Voltage VCC = 12V, ILOAD = 50mAV7.77.26.7Output Accuracy Internal Regulator (VO3 ) ºC-20-Temperature Hysteresis (Note 3) ºC-145130Start Threshold Thermal Shutdown (Note 3)%-5-Hiccup Duty Cycle VIN = 12V, ROCSET = 7.5KΩA2924.520Start Threshold Over Current Protection ConditionsUnitsMaxTypMinPARAMETER

2/26/2008www.irf.com 6 iP1206PbF Pin Description Pin Number Pin Name Description

1 CC2 Compensation pin for Error Amplifier 2

2 SS2 Soft Start/Shutdown pin for output 2

3 VIN2 Input supply voltage connection to output 2

4, 6, 13, 15 PGND Power Ground

5 VSW2 Voltage Switching Node for output 2 – pin connection to the output inductor

7 VCB2 Boot strap capacitor pin for output 2 - connect a 0.1µF from this pin to VSW2

8 OC2 Over current threshold setting pin for output 2

9 VCH Supply voltage for internal high side FET drivers of both outputs

10 VCL Supply voltage for internal low side FET drivers of both outputs

11 OC1 Over current threshold setting pin for output 1

12 VCB1 Boot strap capacitor pin for output 1 - connect a 0.1µF from this pin to VSW1

14 VSW1 Voltage Switching Node for output 1 – pin connection to the output inductor

16 VIN1 Input supply voltage connection to output 1

17 SS1 Soft Start/Shutdown pin for output 1

18 CC1 Compensation pin for Error Amplifier 1

19 FB1 Inverting input for Error Amplifier 1

20 FB1S Output over voltage protection sense pin for output 1

21 SEQ Sequence Enable pin

22 SYNC External clock synchronization pin – when not in use, leave pin floating

23 PGOOD2 Power Good status pin of output 2 – output is open collector

24 VP1 Non-inverting input of error amplifier 1

25 VP2 Non-inverting input of error amplifier 2

26 VREF Internal voltage reference pin - connect a 100pF from this pin to AGND

27 PGOOD1 Power Good status pin of output 1 – output is open collector

28 VCC Input supply voltage of internal control IC - connect a 1.0µF from this pin to AGND 29 VO3 Output of internal regulator used to supply VCH – connect a 1.0µF from this pin to PGND

30 TRACK Secondary non-inverting input to Error Amplifier 2 – used to set the type of power up/down

sequence of the output voltages 31 ENABLE Master enable pin. Recycling this pin will reset OV, SS, and Pre-Bias latch for both outputs. 32 NC No connect. This pin is not for electrical connection.

33 RT Switching frequency setting pin

34 FB2S Output over voltage protection sense pin for output 2

35 FB2 Inverting input for Error Amplifier 2

36 AGND Analog Ground

2/26/2008www.irf.com 7 iP1206PbF Fig. 2: Simplified block diagram of the iP1206 Block Diagram Bias Generator VSW2 Two Phase Oscillator 0.8V Ramp1 Sync AGnd VSW1 VIN2 SS1 / SD CC2 Error Amp2 PWM Comp2 POR PGood2 25uA VCB1 Fb1 CC1 Error Amp1 PWM Comp1 Ramp2 64uA Max UVLO VCH1 Fb2 Vcc Rt SS2 / SD VP2 VREF PGood / OVP PGood1 FBS1 FBS2 OC2 Thermal Shutdown PGND OC1 25uA 64uA Hiccup Control SS1 SS2 Mode Regulator Mode 20uA 20uA POR 0.8V PBias1 0.3V SS1 Q R S PBias1 SS1 SS2 3uA 3uA POR VP1 TrackingSeq Track SS1 / SD VO3 Enable OVP1 OVP2 PGND VIN1 SS2 0.3VPORQ S R PBias2 VCB2 Driver VCH VCL VCH2

2/26/2008www.irf.com 8 iP1206PbF TYPICAL OPERATING CHARACTERISTICS Fig. 4: Power Loss vs. Output Current Fig. 3: Safe Operating Curve 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Output Current per Channel (A) Total Power Loss, Both Outputs (W) Typical Maximum VI = 12V VO1 = VO2 = 1.5V Fsw = 300kHz LO = 1.0µH TBLK = 125ºC 0 1 02 03 04 05 06 07 08 09 0 1 0 0 1 1 0 1 2 0 1 3 0 PCB Temperature (ºC) Output Current per Channel (A) VI = 12V VO1 = VO2 = 1.5V Fsw = 300kHz LO = 1.0µH Safe Operating Area

2/26/2008www.irf.com 9 iP1206PbF Fig. 4a: Power Loss vs. Input Voltage Fig. 4b: Power Loss vs. Output Voltage Fig. 4c: Power Loss vs. Switching Frequency Fig. 4d: Power Loss vs. Output Inductor 1.00 1.08 1.16 1.24 1.32 1.40 1.48 1.56 1.64 1.72 Output Inductance (µH) Normalized Power Loss 0.0 2.2 4.4 6.6 8.8 11.0 13.2 15.4 17.6 19.8 SOA Temp Adjustment (0C) VI = 12.0V VO = 1.5V IOUT = 30A FSW = 300KHz TBLK = 125ºC 200 250 300 350 400 450 500 550 600 Switching Frequency (KHz) Max Duty Cycle (%) TYPICAL OPERATING CHARACTERISTICS Fig. 5 Maximum Duty Cycle vs. Switching Frequency 0.80 0.90 1.00 1.10 1.20 1.30 1.40 1.50 1.60 Output Voltage (V) Normalized Power Loss -4.5 -2.3 0.0 2.3 4.5 6.8 9.0 11.3 13.5 SOA Temp Adjustment( deg. C) VI = 12.0V IOUT = 30A FSW = 300KHz LO = 1µH TBLK = 125ºC 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 200 300 400 500 600 Switching Frequency (kHz) Normalized Power Loss -4.3 -2.2 0.0 2.2 4.3 6.5 8.7 10.8 SOA Temp Adjustment (ºC) VI = 12.0V VO = 1.5V IOUT = 30A LO = 1µH TBL K = 125ºC 0.80 0.90 1.00 1.10 1.20 1.30 1.40 1.50 1.60 1.70 7 8 9 1 01 11 21 31 41 5 Input Voltage(V) Normalized Power Loss -5.6 -2.8 0.0 2.8 5.6 8.4 11.1 13.9 16.7 19.5 SOA temperature adjustment (deg. VO = 1.5V IO = 30A FSW = 300KHz LO = 1µH TBLK = 125ºC

2/26/2008www.irf.com 10 iP1206PbF Circuit Description THEORY OF OPERATION Introduction The iP1206 is a versatile device for high performance buck converters. It consists of two synchronous buck controllers which can be operated either in a two independent outputs mode or in a current share single output mode for high current applications. The timing of the IC is provided by an internal oscillator circuit which generates two-180 o-out-of- phase clock that can be externally programmed up to 600kHz per phase. Under-Voltage Lockout The under-voltage lockout circuit monitors four signals (Vcc, Enable, V CH1, VCH2). This ensures the correct operation of the converter during power up and power down sequence. The driver outputs remain in the off state whenever one of these signals drops below set thresholds. Normal operation resumes once these signals rise above the set values. Fig. 6 shows a typical start up sequence. Enable The enable features another level of flexibility for start up. The Enable has precise threshold which is internally monitored by an under-voltage lockout circuit. It’s threshold can be externally programmed to desired level by using two external resistors, so the converter doesn’t start up until the input voltage has reached the specified threshold level (see Fig. 6). Fig. 6: Normal Start up, Enable threshold is externally set to 11V Seq pin is pulled high prior to start up Vcc 7.2V Vout3 Enable Vbus 7.25V 11V 12V 12V SS Enable OK (IC's POR) Vcc OK Seq VIN

2/26/2008www.irf.com 11 iP1206PbF Internal Regulator iP1206 features an on-board regulator capable of sourcing current up to 100mA. This integrated regulator can be used to generate the necessary bias voltage for drivers. An example of how this can be used is shown in Fig. 25. The output of the regulator is protected for short circuit and thermal shutdown. Out-of-Phase Operation The iP1206 drives its two output stages 180o out- of-phase. In current share mode (single output), the two inductor ripple currents cancel each other and result in a reduction of the output current ripple and yield a smaller output capacitor for the same ripple voltage requirement. Fig. 7 shows two channels inductor current and the resulting voltage ripple at output. IL1 IL2 HDRV1 HDRV2 0D T T Ic Io Mode Selection The iP1206 can operate as a dual output independently regulated buck converter, or as a 2 phase single output buck converter (in current share mode). The SS2 pin is used for mode selection. In current share mode this pin should be floating and in dual output mode a soft start capacitor must be connected from this pin to ground to program the start time for the second output. Independent Mode In this mode the iP1206 provides control to two independent output power supplies with either common or different input voltages. The output voltage of each individual channel is set and controlled by the output of the error amplifier, which is the amplified error signal from the sensed output voltage and the reference voltage. The error amplifier output voltage is compared to the ramp signal thus generating fixed frequency pulses of variable duty-cycle, (PWM) which are applied to the internal MOSEFT drivers. Fig. 25b shows a typical schematic for such an application. Fig. 7: Current ripple cancellation for output In addition, the 180 o out of phase operation contributes to input current cancellation. This results in a much smaller input capacitor - RMS current thereby reducing the input capacitor quantity. Fig. 8 shows the equivalent RMS current. Single Phase

2 Phase

Duty Cycle (Vo/Vin) RMS Current Normalized (IRMS/Iout) Fig. 8: Input RMS value vs. Duty Cycle

2/26/2008www.irf.com 12 iP1206PbF Current Share Mode This feature allows the connection of both outputs together to increase current handling capability of the converter to support a common load. In current sharing mode, error amplifier 1 becomes the master which regulates the common output voltage and the error amplifier 2 performs the current sharing function, Fig. 9 shows the configuration of error amplifiers. See Fig 25a for a typical application. In this mode iP1206 makes sure the master channel starts first followed by slave channel to prevent any glitch during start up. This is done by clamping the output of slave’s error amplifier until the master channel generates the first PWM signal. At no load condition the slave channel may be kept off depending on the offset of error amplifier. Lossless Inductor Current Sensing The iP1206 uses a lossless current sensing technique for current share purposes. The inductor current is sensed by connecting a series resistor and a capacitor network in parallel with the inductor and measuring the voltage across the capacitor, this voltage is proportional to the inductor current. As shown in Fig. 9 the voltage across the inductor’s DCR can be expressed by: The voltage across the C 1 can expressed by: Combining equations (1),(2) and (3) result in the following expression for VC1 : Usually the resistor R 1 and C1 are chosen so that the time constant of R 1 and C 1 equals the time constant of the inductor which is the inductance L 1 over the inductor’s DCR (R L1 ). If the two time constants match, the voltage across C 1 is proportional to the current through L1 , and Fig. 9: Loss Less inductor current sensing and current sharing L1 RL1 L2 RL2 R2 C2 VP2 FB2 VOUT Master Phase Slave Phase + VC1(s) - + VL1 (s) - Vin Vin IL1 the sense circuit can be treated as if only a sense resistor with the value R L1 was used. The mismatch of the time constants does not affect the measurements of inductor DC current, but affects the AC component of the inductor current. Soft-Start The iP1206 has a programmable soft-start to control the output voltage rise and limit the inrush current during start-up. It provides a separate Soft-start function for each output. This enables the user to sequence the outputs by controlling the rise time of each output through the selection of different value soft-start capacitors. To ensure correct start-up, the soft-start sequence initiates when the Vcc and Enable rise above their threshold and generate the Power On Reset (POR) signal. Soft-start function operates by sourcing an internal current to charge an external capacitor to about 3V. Initially, the soft- start function clamps the error amplifier’s output of the PWM converter. ) 1 ( - - - - sL R RV V s V 11 L 1 L outin1 RL +− = * ) ( ) ( ) 3 ( - - - - sC1R sC1 V V s V outin1 C − = * ) ( ) ( sL RI s V 1 1 11 L

1 L1 C

** ) (+

1 L 1 LC

R LC R If * ) ( * :

2/26/2008www.irf.com 13 iP1206PbF Soft-Start (cont.) During power up, the converter output starts at zero and thus the voltage at Fb is about 0V. A current (64µA) injects into the Fb pin and generates a voltage about 1.6V (64µAx25K) across the negative input of error amplifier, see Fig. 10. The magnitude of this current is inversely proportional to the voltage at the soft-start pin. The 28µA current source starts to charge up the external capacitor. In the mean time, the soft- start voltage ramps up, the current flowing into Fb pin starts to decrease linearly and so does the voltage at negative input of error amplifier. When the soft-start capacitor is around 1V, the voltage at the negative input of the error amplifier is approximately 0.8V. As the soft-start capacitor voltage charges up, the current flowing into the Fb pin keeps decreasing. The feedback voltage increases linearly as the injecting current decreases. The injecting current drops to zero when soft-start voltage is around 1.8V and the output voltage goes into steady state. Fig. 11 shows the theoretical operational waveforms during soft-start. The output start-up time is the time period when soft-start capacitor voltage increases from 1V to 2V. The start-up time will be dependent on the size of the external soft-start capacitor. The start- up time can be estimated by: For a given start up time, the soft-start capacitor (nF) can be estimated as: For normal start up the Seq pin should be pulled high (usually can be connected to Vout3). Fig. 10: Soft-Start circuit for iP1206 Fig. 11: Theoretical operation waveforms during soft-start ms T A 20C start SS ) ( . ) ( * ) (μ≅ V 1 V 8 1C TμA 28 ss start − = ∗. Soft-Start Voltage Voltage at negative input of Error Amp Voltage at Fb pin Current flowing into Fb pin 64uA 0uA 0.8V ≅1.6V 0.8V ≅1.8V ≅1V Output of POR E/A2 VP2 Fb2 SS2/SD2 ISS2 = 28uA Track POR OCP2 Ihiccup2 = 3uA 64uA E/A1 VP1 Fb1 SS1/SD1 ISS1 = 28uA POR OCP1 Ihiccup1 = 3uA 64uA Seq

2/26/2008www.irf.com 14 iP1206PbF Fig. 13: Ratiometric Power up /down Output Voltage Tracking and Sequencing The iP1206 can accommodate a full spectrum of user programmable tracking and sequencing options using Track, Seq, Enable and Power Good pins. Through these pins both simple voltage tracking such as that required by the DDR memory application and more sophisticated sequencing such ratiometric or simultaneously can be implemented. The Seq pin controls the internal current sources to set the power up or down sequencing, toggle this pin high for power up and toggle this pin low for power down. The Track pin is used to determine the second channel output for either ratiometric or simultaneously by using two external resistors. Fig. 12 shows how these pins are configured for different sequencing mode. E/A1 VP1 Fb1 SS1/SD1 ISS1 = 28uA POR OCP1 Ihiccup1 = 3uA 64uA Seq VREF Vo1 RA RB CSS1 Fig.12: Using Seq and Track pin for different sequencing In general the R A and RB set the output voltage for the first output and R C and RD set the output voltage for the second output. For simultaneously vs. ratiometric, RE and RF can be selected according to the table below: Fig. 14: Simultaneously Power Up / down E/A2 VP2 Fb2 SS2/SD2 ISS2 = 28uA Track POR OCP2 Ihiccup2 = 3uA 64uA Floating Vo2 Vo1 RC RD RE RF VREF And RF = RBAnd RF = RD Set RE = RASet RE = RC ratiometricsimultaneously

2/26/2008www.irf.com 15 iP1206PbF Fault Protection The iP1206 monitors the output voltage for over vo ltage protection and power good indication. It senses the R ds(on) of low side MOSFET for over current protection. It also protects the output for prebias conditions. Fig. 15 below shows the IC’s operating waveforms under different fault conditions. t0 –t 1 : Vcc, VCH and Enable signals passed their respective UVLO threshold. Soft start sequence starts. t1 –t 2 : Power Good signal flags high. t1 –t 3 : Output voltage ramps up and reaches the set voltage. t4 –t 5 : OC event, SS ramps down. IC in Hiccup mode. t5–t 6 : OC is removed, recovery sequence, fresh SS. t6 –t7 : Output voltage reaches the set voltage. t8 : OVP event. HDrv turns off and LDrv Turns on. The IC latches off. t9 –t10 : Manually recycled the Vcc after latched OVP. t11 : PreBias start up. Fig. 15: Fault Conditions SS PGood t1 t2 t3 Vo 1.0V 1.8V 90%Vfb Set Voltage OCP Threshold Iout POR t0 t4 t5 t6 t7 t8 t9 t10 Pre_Bias Voltage t11

2/26/2008www.irf.com 16 iP1206PbF Over-Current Protection The over current protection is performed by sensing current through the R DS(on) of low side MOSFET. This method enhances the converter’s efficiency and reduce cost by eliminating a current sense resistor. As shown in Fig. 16, an external resistor (R OCSET) is connected between OCSet pin and the drain of low side MOSFET (Q2) which sets the current limit set point. When the overcurrent trip threshold is reached, the power supply output shuts down and attempts to restart, entering into the hiccup mode. The time duration between the shutdown of the output and the restart is determined by the time it takes to discharge the soft start capacitor. Fig. 16: Connection of over current sensing resistor Fig. 17: 3uA current source for discharging soft-start capacitor during hiccup The duty cycle of the hiccup process is typically 5%. The hiccup is performed by charging and discharging the soft-start capacitor at a certain slope rate. As shown in Fig. 17 a 3µA current source is used to discharge the soft-star t capacitor. The OCP comparator resets after every soft start cycle, the converter stays in this mode until the overload or short circuit is removed. Once the condition is removed the converter will automatically recover. Refer to Fig. 24 for R OCSET selection. ROCSETiP1206 OC1 IOCSET VOUT Hiccup Control Q2 VSW PGND SS1 / SD 20 28uA 3uA OCP22uA Pre-Bias iP1206 is able to start up into a pre-charged output, which prevents oscillation and disturbances of the output voltage. The output starts in asynchronous fashion and keeps the synchronous MOSFET off until the first gate signal for control MOSFET is generated. The figure below shows a typical Pre-Bias condition at start up. Depending on the system configuration, specific amount of output capacitors may be required to prevent discharging the output voltage. Over Voltage Protection Over-voltage is sensed through two dedicated sense pins FBS1, FBS2. A separate OVP circuit is provided for each channel. The OVP threshold is user programmable and can be set by two external resistors. Upon over- voltage condition of either one of the outputs, the OVP forces a latched shutdown on the fault output and pulls low the low side driver. Reset is performed by recycling the Vcc or Enable. Overvoltage can be sensed either by connecting FB1s and FB2s to their corresponding outputs through separate output voltage divider resistor networks, or they can be connected directly to their corresponding feedback pins FB1 and FB2. For Type III compensation, FB1s and FB2s should be connected through voltage dividers only. Power Good The iP1206 provides two separate open collector power good signals which report the status of the outputs. The outputs are sensed through the two dedicated V SEN1 and VSEN2 pins. Once the iP1206 is enabled and the outputs reach the set value (90% of set value) the power good signals go open and stay open as long as the outputs stay within the set values.These pins are open collector and need to be externally pulled high. Vo Time Volt Pre-Bias Voltage (Output Voltage before startup)

2/26/2008www.irf.com 17 iP1206PbF Fig. 18: Switching Frequency vs. External Resistor (Rt ) Shutdown using Soft Start pins The outputs can be shutdown by pulling the soft-start pin below 0.25V. This can be easily done by using an external small signa l transistor. During shutdown both MOSFET drivers will be turned off. Normal operation will resume by cycling soft start pin. Operating Frequency Selection The switching frequency is determined by connecting an external resistor (Rt) to ground. Fig. 18 provides a graph of oscillator frequency versus Rt. The maximum recommended channel frequency is 600kHz. 100 200 300 400 500 600 700 0 1 02 03 04 05 06 07 0 Rt (kOhm) Fsw (kHz) Frequency Synchronization The iP1206 is capable of accepting an external digital synchronization signal. Synchronization will be enabled by the rising edge at an external clock. Per–channel switching frequency is set by external resistor (Rt). The free running frequency oscillator frequency is twice the per- channel frequency. During synchronization, Rt is selected such that the free running frequency is 20% below the synchronization frequency. Synchronization capability is provided for both single output current share mode and dual output configuration. When unused, the sync pin will remain floating and is noise immune. Thermal Shutdown Temperature sensing is provided inside iP1206. The trip threshold is typically set to 135 oC. When trip threshold is exceeded, therma l shutdown turns off both MOSFETs. Thermal shutdown is not latched and automatic restart is initiated when the sensed temperature drops to normal range. There is a 20 oC hysteresis in the shutdown threshold.

2/26/2008www.irf.com 18 iP1206PbF

Application Information

Design Example: The following example is a typical application for iP1206. The application circuit is shown in page25.Output Voltage Programming Output voltage is programmed by the reference voltage and an external voltage divider. The Fb pin is the inverting input of the error amplifier, which is internally referenced to 0.8V. The divider ratio is chosen to provide 0.8V at the Fb pin when the output is at its desired value. The output voltage is defined by using the following equation: When an external resistor divider is connected to the output as shown in Fig. 19. Equation (6) can be rewritten as: For the calculated values of R 5 and R 6 see feedback compensation section. kHz F mV V A I V V V V V s o o o in 300 2 . 1 max) , 2 . 13 ( , 12 ≤ Δ ) (R RV VREFo 61 6 - - - - ⎟⎟ ⎛ + ∗ = Fig. 19: Typical application of the iP1206 for programming the output voltage ) (V V VR R ref o ref 76 5 - - - - ⎟⎟ −∗ = Soft-Start Programming The soft-start timing can be programmed by selecting the soft-start capacitance value. The start-up time of the converter can be calculated by using: Where Tstart is the desired start-up time (ms) For a start-up time of 5ms, the soft-start capacitor will be 0.1uF. Choose a ceramic capacitor at 0.1uF. Input Capacitor Selection The 180 o out of phase feature will reduce the RMS value of the ripple current seen by input capacitors. This reduces numbers of input capacitors. The input capacitors selected must handle both the maximum ripple RMS at highest ambient temperature as well as the maximum input voltage. The RMS value of current ripple for duty cycle under 50% is expressed by: Where: RMS is the RMS value of the input capacitor current -D1 and D2 are the duty cycle for each channel -I1 and I2 are the output current for each channel For Io=30A and D=0.10, the IRMS = 12A. Ceramic capacitors are recommended due to their peak current capabilities, they also feature low ESR and ESL at higher frequency which enhance better efficiency, Use 8x22uF, 16V ceramic capacitor from TDK (C3225X5R1C226M). For the single output application when the duty cycle is larger than 50% the following equation can be used to calculate the total RMS value input capacitor current: ) (T A CstartSS 8* 20 - - - - μ≅ Fb1 iP1206 VOUT () ()( ) ) ( D D I I D D I D D I IRMS 92 11 2 1 2 1 2 2 2 1 1

2/26/2008www.irf.com 19 iP1206PbF Inductor Selection The inductor is selected based on output power, operating frequency and efficiency requirements. A low inductor value causes a large ripple current, resulting in a smaller size, faster response to a load transient but poor efficiency and high output noise. Generally, the selection of inductor value can be reduced to the choice of desired maximum ripple current in the inductor. The optimum point is usually found between 20% and 50% ripple of the output current. For the buck converter, the inductor value for desired operating ripple current can be determined using the following relation: Where: For 2-phase single output application the inductor ripple current is chosen between 10-40% of maximum phase current If , then the output inductor will be: L = 1uH The Delta MPL105-1R0IR (L 1 =1uH, 25A, RL1 =2.3mOhm) provides a low profile inductor suitable for this application. Use the following equation to calculate C 12 and R12 for current sensing: This results to C12 =1uF and R12 =402Ohm s o in F 1D t t iL V V ∗ = ∗ = −ΔΔ Δ ; ) (iΔ () ) (F i V VV V L sin o cycle Duty D time on Turn t frequency SwitchingF current ripple Inductor i Voltage OutputV voltage input MaximumV s o in Δ Δ Output Capacitor Selection The voltage ripple and transient requirements determine the output capacitors types and values. The criteria is normally based on the value of the Effective Series Resistance (ESR). However the actual capacitance value and the Equivalent Series Inductance (ESL) are other contributing components, these components can be described as: Since the output capacitor has a major role in overall performance of converter and determines the result of transient response, the selection of capacitors is critical. The iP1206 can perform well with all types of capacitors. As a rule the capacitor must have low enough ESR to meet output ripple and load transient requirements, yet have high enough ESR to satisfy stability requirements. The goal for this design is to meet the voltage ripple requirement in smallest possible capacitor size. Therefore ceramic capacitors are selected due to low ESR and small size. Panasonic ECJ24YB0J107M (4*100uF, 6.3V, X5R and EIA 1210 case size) are a good choice. In the case of tantalum or low ESR electrolytic capacitors, the ESR dominates the output voltage ripple, equation (13) can be used to calculate the required ESR for the specific voltage ripple. ) %( 12oI i≈ Δ current ripple InductorI ripple voltage Output -(11) - - - L = Δ = Δ Δ= Δ ⎛= Δ Δ = Δ Δ + Δ +Δ=Δ o s o L C o in ESL o LESR o C oESL oESR o o V F C IV ESLL VV ESR I V V V V V * * 8 ) ( ) ( ) ( ) ( ) ( ) ( 1 L 1212 R LC R=*

2/26/2008www.irf.com 20 iP1206PbF Feedback Compensation The iP1206 is a voltage mode controller; the control loop is a single voltage feedback path including error amplifier and error comparator. To achieve fast transient response and accurate output regulation, a compensation circuit is necessary. The goal of the compensation network is to provide a closed loop transfer function with the highest 0dB crossing frequency and adequate phase margin (greater than 45 o). The output LC filter introduces a double pole, – 40dB/decade gain slope above its corner resonant frequency, and a total phase lag of 180 o (see Fig. 20). The resonant frequency of the LC filter expressed as follows: Since we already have 180 o phase shift just from the output filter, the system risks being unstable. The iP1206’s error amplifier is a differential-input transconductance amplifier. The output is available for DC gain control or AC phase compensation. The E/A can be compensated either in type II or type III compensation. When it is used in type II compensation the transconductance properties of the E/A become evident and can be used to cancel one of the output filter poles. This will be accomplished with a series RC circuit from Comp pin to ground as shown in Fig. 21. This method requires that the output capacitor should have enough ESR to satisfy stability requirements. In general the output capacitor’s ESR generates a zero typically at 5kHz to 50kHz which is essential for an acceptable phase margin. The ESR zero of the output capacitor expressed as follows: -(12)- - - o o LC C L F ∗ ∗ Gain FLC 0dB Phase FLC -180 Frequency Frequency -40dB/decade Fig. 20: Gain and Phase of LC filter The transfer function (Ve/Vo) is given by: The (s) indicates that the transfer function varies as a function of frequency. This configuratio n introduces a gain and zero, expressed by: The gain is determined by the voltage divider and E/A’s transconductance gain. First select the desired zero-crossover frequency (Fo): Use the following equation to calculate R 4 : Where: Vin = Maximum Input Voltage Vosc = Oscillator Ramp Voltage Fo = Crossover Frequency FESR = Zero Frequency of the Output Capacitor FLC = Resonant Frequency of the Output Filter gm = Error Amplifier Transconductance -(13) - - - o ESR C ESRF * * 2 π∗= Ve VOUT VREF E/A FZ H(s) dB Frequency Gain(dB) Fb Comp CPOLE Fig. 21: TypeII compensation network and its asymptotic gain plot -(14) - - - 9 4 6 5 5 1* * ) (sC C sR R R Rg s Hm ()[] -(16) - - - F -(15)- - - R * z 9 4 6 5 * * 2 C R R R Rg s Hm ( ) soESRo F 1/10 ~ 1/5 F and F F*≤> -(17) - - - mLC in ESR o osc g R F V R R F F VR * * * ) ( * * * 6 5

2/26/2008www.irf.com 21 iP1206PbF To cancel one of the LC filter poles, place the zero before the LC filter resonant frequency pole: Using equations (16) and (18) to calculate C9. One more capacitor is sometimes added in parallel with C 9 and R 4 . This introduces one more pole which is mainly used to suppress the switching noise. The additional pole is given by: The pole sets to one half of switching frequency which results in the capacitor C POLE : For a general solution fo r unconditionally stability and any type of output capacitors, in a wide range of ESR values we should implement local feedback with a compensation network (typeIII). The typically used compensation network for voltage-mode controller is shown in Fig. 22. In such configuration, the transfer function is given by: The error amplifier gain is independent of the transconductance under the following condition: By replacing Z in and Zf according to figure 15, the transformer function can be expressed as: -(18)- - - o o z LCz C L F F F * 2 1* 75 . 0 % 75 π As known, transconductance amplifiers have high impedance (current source) outputs, therefore, care should be taken when loading the E/A output. It may exceed its source/sink output current capability, so that the amplifier will not be able to swing its output voltage over the necessary range. The compensation network has three poles and two zeros and they are expressed as follows: Cross over frequency is expressed as: C C C CR 2 POLE9 POLE9 P = ** *π F F For F R * C 1F R s P s 4 s 4 POLE = ** * ππ VOUT VREF R6R8 C10 C12 C11R7 Ve FZ1 FZ2 FP2 FP3 E/A Zf ZIN Frequency Gain(dB) H(s) dB Fb Comp Fig. 22: Compensation network with local feedback and its asymptotic gain plot IN m f m o e Z g 1 Z g 1 V V ( )[] ) ( ** * ) (*) () ( 10 8 1211 1211 8 6 1011 7 1211 6 C sR 1C C C CsR 1 R R sC 1 C sR 1 C C sR 1s H +++ 6 108 610 2 z 11 7 1 z 12 7 1211 1211 3 P 10 8 2 P 1 P R C 2 R R C 2 C R 2 C R 2 C C C CR 2 C R 2 0 F * * ) ( * * * * * *** * * ππ π ππ π ≅+= o oosc in 10 7 o C L 2 V -(19) - - - 1 Z * g and 1 Z * gin mf m >>>> F R 2 z 4 * *π=

2/26/2008www.irf.com 22 iP1206PbF Based on the frequency of the zero generated by output capacitor and its ESR versus crossover frequency, the compensation type can be different. The table below shows the compensation types and location of crossover frequency. The following design rules will give a crossover frequency approximately one-sixth of the switching frequency. The higher the band width, the potentially faster the load transient response. The DC gain will be large enough to provide high DC-regulation accuracy (typically -5dB to -12dB). The phase margin should be greater than 45 o for overall stability. Desired Phase Margin: Compensator type FESR vs. Fo Output capacitor TypII(PI) FLC <FESR <Fo <Fs/2 Electrolytic , Tantalum TypeIII(PID) Method A FLC <Fo <FESR <Fs/2 Tantalum, ceramic TypeIII(PID) Method B FLC <Fo <Fs/2 <FESR Ceramic Ω =Ω =−= Ω =Ω = −= Ω =Ω == === === Ω =Ω ≥ ≥ Θ − Θ += Θ + Θ −= KKRV V VR KKRF CR KKF CR Calculate nF nFV R V C L FC pFpFR F R FSelect kHzF Sin SinF F kHzF Sin SinF F ref o ref Z P in osc o o o P Z P o P Z o Z 2 . 392 . 39 ; * 2, 96 . 1* * 2 , 85 . 0 ;* * * * * 2 100, 155 ;* * 2 36 .* 81 . 672 . 0 * 5 . 0 : 2 . 81 72 . 10 2 10 2 10 7 3 56 8 121212 1111 7Z1 1012 11 m sP3Z1 R : Select ,R R : Select R R : Select R ; R and R R C : Select C C : Select C C 5.6nF C : Select nF, 4 C ;F * 2 : C and C , C Calculate K R : Select ; K R ; g F * 0.5 F and F π π π π π πΘ =max Table1- The compensation type and location of FESR versus Fo The details of these compensation types are discussed in application note AN-1043 which can be downloaded from the IR Web-Site. For this design we have: V in =12V Vo =1.2V Vosc =1.25V Vref =0.8V gm =2800umoh Lo =1uH, DCR=2.4mOhm Co =15x22uF, ESR= 0.33mOhm Fs =300kHz These result to: FLC =10.73kHz (Replace L to L/2 in formula#14 for current share configuration) FESR =1.46MHz Fs/2 =150kHz Select crossover frequency: Fo =40kHz Since: FLC <Fo <Fs/2 <FESR , typeIII method B is selected to place the pole and zeros. ( ) soESRo F 1/10 ~ 1/5 F and F F*≤<

2/26/2008www.irf.com 23 iP1206PbF Compensation for Current Loop (slave channel) The slave error amplifier is differentia l transconductance amplifier, in 2-phase configuration the main goal for the slave channel feedback loop is to control the inductor current to match the master channel inductor current as well provides highest bandwidth and adequate phase margin for overall stability. The following analysis is valid for both using external current sense resistors and using DCR of inductor. The transfer function of power stage is expressed by: Where: V in =Input voltage L2 =Output inductor Vosc =Oscillator Peak Voltage As shown the G(s) is a function of inductor current. The transfer function for compensation network is given by equation (21), when using a series RC circuit as shown in Fig 23. The loop gain function is: ) (V sL V V s Is G osc in e L 20* ) () ( 2 - - - - = = L1 C2 RS2 RS1 Ve IL2 IL1 Fb2 E/A2 Comp2 Vp2 ) (sC R sC R RgR s Vs D s s m s e 211* *) () ( 2 2 - - - - ⎟⎟ ⎛ + ⎛= = ⎛ + osc 2 in 2 2 2 s 1 s m2 s V sL V sC C sR 1 R Select a zero frequency for current loop (Fo2 ) 1.5 times larger than zero cross frequency for voltage loop (Fo1 ). From (22), R2 can be expressed as: Vin =12V Vosc =1.25V gm =2800umoh L2 =1uH Rs1 =DCR=2.4mOhm Fo2 =60kHz This results to : R2 =5.84K The power stage of current loop has a dominant pole (Fp) at frequency expressed by: Where Rds(on1) is the on-resistance of control FET, Rds(on2) is the on-resistance of synchronous FET, RL is the DCR of output inductance and D is the duty cycle Req=9.48mOhm Set the zero of compensator at 10 times the dominant pole frequency FP, the compensator capacitor, C2 can be expressed as: C2=1nF All designs should be tested for stability to verify the calculated values. 1 O2 O F 5 1 F* % .≅ ) (V L F VR R g F H oscO in 2 2 2 12 - - - - == π ) (V V L F R gR in oscO s m 1 2 2 2 - - - - π= s Lon dseq R R R R+ += ) ( z 2 Pz F R 2 F 10 F * * Fig. 23: The Compensation network for current loop L 2 RF eq P *π= L2 on ds1 on dseq R D 1 R D R R+ −+= ) ( ** ) () (

2/26/2008www.irf.com 24 iP1206PbF Programming the Current-Limit The Current-Limit threshold can be set by connecting a resistor (R OCSET) from drain of low side MOSFET to the OCSet pin. The resistor value can be obtained by using Fig. 24. It is important to pay careful attention to the layout of this resistor. It is recommended to place this resistor close to the IC and away from possible noisy traces. A small ceramic capacitor from this pin to ground can also be place for noise rejection purposes. Ω = = + = ⇒ K I I I I where ) ( I I I trip Peak L Peak L Peak Ltrip 23 . 5 5 . max , max OCSETR get we 24 Fig. From 14.25A1.5A 1.5 * 8.5 A 1 3A of ripple inductor an and 8.5A of current load DC maximum a For Current Inductor Peak 1.5 * current load DC Maximum - - - - Fig. 24: ROCSET selection from Peak Inductor Current The trip current Itrip is given by: 56789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 Peak Inductor Current (A) Current Limit Resistor (kOhms) : Note 2 sin o o in Peak L F L V VV ViI ∗∗ − =Δ=

2/26/2008www.irf.com 25 iP1206PbF Fig. 25a: Typical Single Output Application circuit for 12V to 1.2V @ 30A Typical Application Circuit 12V Vo = 1.2V Fig. 25b: Typical Dual Output Application circuit for 12V to 2.5V @ 15A , 12V to 1.5V@ 15A

2/26/2008www.irf.com 26 iP1206PbF Recommended PCB Footprint 2626 Fig. 26

2/26/2008www.irf.com 27 iP1206PbF Fig. 27 Top component and via placement (Topside, transparent view down) PCB Layout Guidelines The following guidelines are recommended to reduce the parasitic values and optimize overall performance.

  • All pads on the iP1206 footprint design need to be Solder-mask defined (see Figure 26). Also refer to International Rectifier application notes AN1028 and AN1029 for further footprint design guidance.
  • Place as many vias around the Power pads (VIN, VSW, and PGND) for both electrical and optimal thermal performance.
  • Vias in between the different power pads may overlap the pad opening and solder mask edge without the need to plug the via hole. Vias with a 13mil drill hole and 25mil capture pad were used in this example.
  • A minimum of six 10µF, X5R, 16V ceramic capacitors per iP1206 are recommended for the lowest loss due to input capacitor ESR.
  • Placement of the ceramic input capacitors is critical to optimize switching performance. In cases where there is a space constraint on the top layer capacitors C3,C4, C7 and C8 can be placed on the bottom layer directly below the footprints of C1, C2, C5 and C6.
  • Dedicate at least two layers for PGND only.
  • Duplicate the Power Nodes on multiple layers (refer to AN1029).
  • Refer to AN-1030 for information on applying IPOWIR products in your thermal environment for Safe Operation. PGND4 PGND6 PGND13 PGND15

2/26/2008www.irf.com 28 iP1206PbF .005 [0.12] C 2. DIMENSIONS ARE SHOWN IN INCHES[MILLIMETERS]. 3. CONTROLLING DIMENSION: INCHES 1. DIMENSIONING & TOLERANCING PER ASME Y14.5M-1994. NOTES: TOP VIEW SIDE VIEW C PACKAGE BODY. LAND PAD OPENINGS. 4. LAND PAD OPENINGS.

5 PRIMARY DATUM C (SEATING PLANE) IS DEFINED BY THE

6 BILATERAL TOLERANCE ZONE IS APPLIED TO EACH SIDE OF THE

.006 [0.15] C CORNER ID 2X 6 B A .006 [0.15] C 2X 6 7. NOT TO SCALE. 23X CORNER ID 27X Mechanical Outline 2828 Fig. 28

2/26/2008www.irf.com 29 iP1206PbF Tape and Reel Information Fig. 29

2/26/2008www.irf.com 30 iP1206PbF Fig. 30 Fig. 31 Part Marking Recommended Solder Paste Stencil Design IR WORLD HEADQUARTERS: 233 Kansas Street., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 This product has been designed for the Industrial market. Visit us at www.irf.com for sales contact information Data and specifications subject to change without notice. 08/08/2007 The recommended reflow peak temperature is 260 oC. The total furnace time is approximately 5 minutes with approximately 10 seconds at peak temperature. Pin 1 Identifier International Rectifier Logo Assembly Code Date Code (YYWW) YY= Year WW = Week Part Number Factory Code