IP1001

IP1001 IRF | Alldatasheet

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• Although, all of the difficult PCB layout and bypassing issues have been addressed with the internal design of the iPOWIR block, proper layout techniques should be applied for the design of the power supply board. There are no concerns about unwanted shutdowns common to switching power supplies, if operated as specified. The iPOWIR block will function normally, but not optimally without any additional input decoupling capacitors. Input decoupling capacitors should be added at Vin pin for stable and reliable long term operation. No additional bypassing is required on the Vdd pin. See layout guidelines in datasheet for more detailed information. PD - 94336c 05/20/03 iP1001 www.irf.com 1 iP1001 Internal Block Diagram VFSGNDSSGND PGND VSW VIN VF PWM & Driver ENABLE PGOOD

5 Bit

& Driver ENABLE PGOOD

www.irf.com2 iP1001 Absolute Maximum Ratings Recommended Operating Conditions Electrical Specifications @ VDD = 5V & TPCB 0°C - 90°C (Unless otherwise specified) All specifications @ 25°C (unless otherwise specified) Parameter Symbol Min Typ Max Units Conditions VIN to PGND -0.3 - 16.0 VDD to PGND -0.3 - 6.0 VFS -0.3 - VDD+0.3 VF -0.3 - VDD+0.3 D0-D4 -0.3 - VDD+0.3 PGOOD to PGND -0.3 - 6.0 ENABLE to PGND -0.3 - 6.0 ILIM -0.3 - VDD+0.3 FREQ -0.3 - VDD+0.3 Output RMS Current - - 20 A Block Temperature TBLK -40 - 125 °C V Parameter Symbol Min Typ Max Units Conditions Supply Voltage VDD 4.5 - 5.5 Input Voltage Range 1 VIN 3.3 - 12 With 4.5V<VDD<5.5V Output RMS Current from VSW 4 IoutVSW -- 2 0 A Output Voltage Range 2 VOUT 0.925 - 2.0 V DAC Setting see VID code, Table1. V Parameter Symbol Min Typ Max Units Conditions Power Loss PLOSS -3 . 1 3 . 9 W 300kHz, 12VIN, 1.3Vout, 20A Over Current Shutdown - 25 - A VIN=12V, VOUT=1.3V, FREQ=300KHz, RLIM=340k Soft Start Time -1 . 8-m s Output Voltage Accuracy -2 - 2 % All DAC codes TBLK = -40°C to 125°C VF Input Resistance -1 8 1- kΩ -2 0 0- freq pin connected to VDD -3 0 0- freq pin floating VDD Undervoltage Lockout -4 . 2- V 200mV hysteresis Output Undervoltage Shutdown Threshold -0 . 8- V Output Undervoltage Protection Blanking Time -2 0-m s ENABLE going high on start-up Output Overvoltage Shutdown Threshold at VF -2 . 2 5- V See OVP note in Design Guidelines PGOOD Trip Threshold PGOOD - VDAC -5% -V At VF PGOOD Leakage Current - 1 - µA PGOOD output high Forced to 5.5V PGOOD Output Low Voltage - - 0.4 V Isink = 1mA Logic Input High Voltage 2.4 - - V D0-D4, Enable Logic Input Low Voltage - - 0.8 V D0-D4, Enable FREQFrequency kHz

www.irf.com 3 iP1001 Electrical Specifications (continued) Notes : 1 For Vin less than 4.5V requires external 5V DD supply. 2 Can be modified to operate up to 3.3V OUT, outside of DAC settable range. See Design Guidelines on how to set output voltage greater than 2V. 3 See design guidelines. 4 See Fig. 5 for Recommended Operating Area Parameter Symbol Min Typ Max Units Conditions VDD Operating Current I VDD -2 5- m A Enable High, 300kHz VDD Quiescent Current I QVDD -6 0 0- µA Shutdown mode VIN Quiescent Current I QVIN --1 m A Enable Low, VIN = 12V ILIM to SGND Internal Resistance -3 0 0- kΩ Measured ILIM pin to SGND

www.irf.com4 iP1001 Fig 1. Power Loss vs Current Fig 2. Safe Operating Area (SOA) vs TPCB Adjusting the Power Loss and SOA curves for different operating conditions To make adjustments to the power loss curves in Fig. 1, multiply the normalized value obtained from the curves in Figs. 3, or 4 by the value indicated on the power loss curve in Fig. 1. If multiple adjustments are required, multiply all of the normalized values together, then multiply that product by the value indicated on the power loss curve in Fig. 1. The resulting product is the final power loss based on all factors. To make adjustments to the SOA curve in Fig. 2, determine the maximum allowed PCB temperature in Fig. 2 at the required operating current. Then, add the correction temperature from the normalized curves in Figs. 3 or 4 to find the final maximum allowable PCB temperature. When multiple adjustments are required, add all of the temperatures together, then add the sum to the PCB temperature indicated on the SOA graph to determine the final maximum allowable PCB temperature based on all factors. Note: If input voltage <5Vin nominal operation is required then first see Fig. 5 for maximum current capability limit. Operating Conditions for the examples below: Output Current = 20A Input Voltage = 7V Output Voltage = 2.5V Adjusting for Maximum Power Loss: (Fig. 1) Maximum power loss =5 W (Fig. 3) Normalized power loss for output voltage ≈1.14 (Fig. 4) Normalized power loss for input voltage ≈0.89 Adjusted Power Loss = 5W x 0.89 x 1.14 ≈ 5.07W Adjusting for SOA Temperature: (Fig. 2) SOA PCB Temperature = 90°C (Fig. 3) Normalized SOA PCB Temperature for output voltage ≈ -4.5°C (Fig. 4) Normalized SOA PCB Temperature for input voltage ≈ 4°C Adjusted SOA PCB Temperature = 90°C + 4°C -4.5°C ≈ 89.5°C Guaranteed Performance Curves 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 2 4 6 8 10 12 14 16 18 20 Output Current (A) Power Loss (W) VIN = 12V VOUT = 1.3V TBLK=125°C fsw set to 300kHZ Maximum Typical 0 1 02 03 04 05 06 07 08 09 0 1 0 0 1 1 0 1 2 0 1 3 0 PCB Temperature (°C) Output Current (A)VIN = 12V VOUT = 1.3V fsw set to 300kHZ Safe Operating Area

www.irf.com 5 iP1001 Fig 4. Normalized Power Loss vs VINFig 3. Normalized Power Loss vs VOUT Fig 5. Recommended Operating Area For 200kHz frequency setting there will be a 10% power loss reduction and a positive PCB temperature adjustment of 3°C. Typical Performance Curves Output Voltage (V) VIN = 3.3V, 200kHz VIN = 5V to 12V 200kHz/300kHz Input Voltage (V) SOA PCB Temperature Adjustmentltage (°C) SOA PCB Temperature Adjustmentltage (°C) Power Loss (Normalized) Power Loss (Normalized) Output Voltage (V) Load Current (A) 0.88 0.94 1.00 1.06 1.12 1.18 1.24 1.30 1.36 -13 -11 VIN = 12V IOUT = 20A fsw set to 300kHz TBLK = 125°C 0.83 0.86 0.89 0.91 0.94 0.97 1.00 3456789 1 0 1 1 1 2 VOUT = 1.3V IOUT = 20A fsw set to 300kHz TBLK = 125°C

the output is discharged as the undervoltage protection is activated. Table 1. VID Code Table22222

Table 2. Pin Description Input voltage connection node. Output inductor connection node. SGND A2-A3, B2-B3 Signal ground. synchronous MOSFET is turned ON. PGOOD R1, S1 Internally pulled-up to V DD . VF C1-C2 Output voltage feedback local sense. VID code setting D/A i nputs. Internally pulled high. for external resistor values. 300kHz, tied to V DD selects 200kHz.

www.irf.com8 iP1001 AA V V A Averaging V Average Input Average Output Average Output Current Average VDD Average VDD DC Average Input Circuit Voltage Voltage Current DC VO VOS Voltage Current D1D2 GNDS ENABLE PGND VSW VDD PGOOD VF SGND VFS VIN FREQ ILIM iP1001 Fig 7. Power loss test circuit PIN = VIN Average x IIN Average PDD = VDD Average x IDD Average POUT = VOUT Average x IOUT Average PLOSS = (PIN + PDD) - POUT

www.irf.com 9 iP1001 Fig 8. Recommended PCB Footprint (Top View) NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC ENABLEPGOOD VDD VSW PGND PGND V IN GNDS SGND FREQ ILIM V F NC VFS

www.irf.com10 iP1001 iP1001 User’s Design Guidelines The iP1001 is a 20A power block that consists of optimized power semiconductors, PWM control and its associated passive components. It is based on a synchronous buck topology and offers an optimized solution where space, efficiency and noise caused by stray parasitics are of concern. The iP1001 com- ponents are integrated in a ball grid array (BGA) pack- age where the electrical and thermal conduction is accomplished through solder balls. FUNCTIONAL DESCRIPTION VIN The standard iP1001 operating input voltage range is 5V to 12V. The input voltage can also be easily configured to run at voltages down to 3.3V. FREQ The PWM control is pseudo current mode. The ESR of the output filter capacitor is used for current sens- ing and the output voltage ripple developed across the ESR provides the PWM ramp signal. iP1001 offers two switching frequency settings, 200kHz and 300kHz. At a given setting the switching frequency will remain relatively constant indepen- dent of load current. V DD (+5V bias) An external 5V bias supply is required to operate the iP1001. In applications where input voltages are lower than 4.5V, and where 5V is not available, a special boost circuit is required to supply V DD with 5V (as shown in the reference design). Soft Start, VDD Undervoltage Lockout When VDD rises above 4.2V a soft start is initiated by ramping the maximum allowable current limit. The ramp time is typically 1.8ms. An external capacitor can be added across the current limit resistor from ILIM to PGND to provide up to 5ms ramp time. Select the capacitor according to the 10nf/ms rule. PGOOD The PGOOD comparator constantly monitors V F for undervoltage. A 5% drop in output voltage can cause PGOOD to go low. PGOOD pin is internally pulled- up to V DD through a 100K, 5% resistor. If it is desired to use the PGOOD signal to enable another stage using iP1001, then it is recommended to filter and buffer PGOOD to prevent transients appearing at the output from pulling PGOOD low. OVP (Output Overvoltage Protection) If the overvoltage trip 2.25V threshold is reached, the OVP is triggered, the circuit is shutdown and the bottom FET is latched on discharging the output filter capacitor. Pulling ENABLE low resets the latch. The overvoltage trip threshold is scaled accordingly, if output voltages greater than 2V are set through voltage dividers. UVP (Output Undervoltage Protection) The Output Undervoltage Protection trip threshold is fixed at 0.8V. If ENABLE is pulled up and V F is below 0.8V for a duration of 10-20ms, the PWM will be in a latched state, with the bottom FET latched on, and will not restart until ENABLE is recycled. DAC Converter (D0-D4) The output voltage is programmed through a 5-bit DAC (see the VID code in table 1). The output volt- age can be programmed from 0.925V to 2V. To elimi- nate external resistors, the DAC pins are internally pulled up. To set for output voltages above 2V, the DAC must be set to 2V and a resistor divider, R3 & R4 (see Fig 10.), is used. The values of the resistors are selected using equation 1. Equation 1 : Vout = VF x (1 + R3/R4) where VF is equal to the DAC setting and R4 is recommended to be ~1kΩ Table 3 - iP1001 Operating Truth Table ENABLE Bottom FET Mode Comments Low ON Shutdown High OFF Shutdown DAC code = X1111, Both FETs are turned OFF. High Switching PWM (Running) High ON Fault Fault latch set by OVP or UVP. This mode will sustain until V DD is cycled or ENABLE is reset.

www.irf.com 11 iP1001 DESIGN PROCEDURE Inductor Selection The inductor is selected according to the following expression. L = V OUT x (1-D) / (fsw x ∆IL) where, D = V OUT / V IN VOUT is the output voltage in Volts, fsw is the switching frequency in kHz, ∆IL is the output inductor ripple current. The inductor value should be selected from 0.8 µH to 2.0µH range. Output Capacitor Selection Use tantalum or POSCAP type capacitors for iP1001. Selection of the output capacitors depends on several factors.

• Low effective ESR for ripple and load transient requirements.
• Stability. To support the load transients and to stay within a specified voltage dip ∆V due to the transients, ESR selection should satisfy the following equation: RESR ≤ ∆V/∆I where, ∆I is the transient load step If output voltage ripple is required to be maintained at specified levels then, the following expression should be used to select the output capacitors. RESR ≤ Vp-p / ∆IL where, Vp-p is the peak to peak output voltage ripple. The value of the output capacitor ESR zero frequency also determines stability. The value of the ESR zero frequency is calculated by the expression: RESR = 1 / (2π x fESR x COUT) A 470µF POSCAP capacitor has a maximum 35mΩ of ESR which provides 9.7kHz zero frequency. The ESR zero frequency must be set below 12kHz. This value is calculated assuming the capacitor datasheet maximum ESR value. Example: To determine the amount of capacitance to meet a 30mVp-p output ripple, with 4A inductor current ripple requirement. The calculated ESR will be = 30mV/4A = 7.5mΩ . This will require 5 x 470uF POSCAP capacitors. The total ESR will result in a 9.7kHz zero frequency. For stable operation:
• Set the resonant frequency f o of the output inductor and capacitor between 2kHz and 4kHz. The resonant frequency is calculated using the following expression: fo = 1/ (2π x (√LC))
• Select the output inductor value between 0.8µµµµµH to 2.0 µµµµµH and the output capacitance between 1880µµµµµF (4x 470µµµµµF) and 5600µµµµµF (12x470µµµµµF)
• Set the minimum output ripple voltage to be greater than 0.5% of the output voltage. Select the capacitor by ESR and by voltage rating rather than capacitance. External Input Capacitor Selection The switching currents impose RMS current requirements on the input capacitors. The following expression allows the selection of the input capacitors, based on the input RMS current: IRMS = ILOAD x ( √D x (1-D)) where, D = VOUT/VIN

www.irf.com12 iP1001 Application Issues Setting VOUT above 2V In certain applications where the output voltage is required to be set higher than the maximum DAC code setting of 2V, it is possible to use an external resistive voltage divider which, for accuracy, needs to have 1% or better tolerance. The switching frequency should be set at 200kHz by connecting the FREQ pin to V DD. Also, the output voltage should never be set higher than 3.3V with a VIN minimum of 5V, or 2.5V with a V IN minimum of 3.3V. The DAC code should be set to 2V and the following equation used to select the resistors: VOUT = VF x (1 + R3/R4) See the reference design for reference designators. Note that the impedance at V F is 180KΩ ±35%. It is recommended that R3 be calculated assuming a value of 1kΩ for R4. Connect V FS to VF and GNDS to PGND. Duty Cycle D = VOUT / VIN >50% For duty cycles >50% the switching frequency should be set at 200kHz. 300kHz switching frequency can be selected if the output is less than 2V and the duty cycle is <50%. For duty cycles >50%, add external compensation ramp from the Vsw terminal of the iP1001 device as shown in the reference design through R9 resistor and C21 capacitor (Fig 10a.). For optimum perfor- mance maintain a RC time constant of approximately 5µs.

www.irf.com 13 iP1001 For stable and noise free operation of the whole power system it is recommended that the designer uses to the following guidelines. 1. Follow the layout scheme presented in Fig.9. Make sure that the output inductor L1 is placed as close to the iP1001 as possible to prevent noise propagation that can be caused by switching of power at the switching node V SW, to sensitive circuits. 2. Provide a mid-layer solid ground with connections to the top layer through vias. The two PGND pads of the iP1001 also need to be connected to the same ground plane through vias. 3. Do not connect SGND pins of the iP1001 to PGND. 4. To increase power supply noise immunity, place input and output capacitors close to one another, as shown in the layout diagram. This will provide short high current paths that are essential at the ground terminals. Fig 9. iP1001 suggested layout 5. Although there is a certain degree of V IN bypassing inside the iP1001, the external input decoupling capacitors should be as close to the device as possible. 6. In situations where the load is located at an appreciable distance from the iP1001 block, it is recommended that at least one or two capacitors be placed close to the iP1001 to derive the V F signal. 7. The VF connection to the output capacitors should be as short as possible and should be routed as far away from noise generating traces as possible. 8. V FS & GNDS pins need to be connected at the load for remote sensing. If remote sensing is not used connect V FS to VF and GNDS to PGND. 9. Refer to IR application note AN-1029 to determine what size vias and what copper weight and thickness to use when designing the PCB. Layout Guidelines Input Terminal Load Terminal VOUT Output Caps (COUT) Input Caps (CIN) VIN PGND VSW Output Inductor (L1) PGND iP1001 Block

www.irf.com14 iP1001 The schematics in Fig.10a & 10b and complete Bill of Materials in Table 4 are provided as a reference design to enable a preliminary evaluation of iP1001. They represent a simple method of applying the iP1001 solution in a synchronous buck topology. Fig. 10a shows the implementation for <5V IN nominal applications, and Fig. 10b shows the implementation for 5V IN - 12V IN nominal applications. The connection pins are provided through the solder balls on the bottom layer of the package. A total power supply solution is presented with the addition of inductor L1 and the output capacitors C11-C14. Input capacitors C1-C10 are for bypassing in the IN - 12VIN application, but only C1-C3 are required for <5VIN applications (refer to the BOM for values). Switches 1-5 of SW1 are used to program the output voltage. Refer to the VID table provided in this datasheet for the code that corresponds to the desired output voltage. Resistors R2 & R4 need to be removed for operation at standard VID levels (0.925V - 2.0V, leave R3 = 0 Ω ). Switch 8 of SW1 enables the output when floating (internally pulled high). The 5V V DD power terminal and input power terminals are provided as separate inputs. They can be connected together if the application requires only 5V nominal input voltage. The reference design also offers a higher output voltage option for greater than 2.0V, up to 3.3V. For output voltages above 2V, the DAC setting must be set to 2V, and then select resistors R3 & R4 per Equation 1 on page 10 for the desired output volt- age. Remove R5 and connect V F to VFS through R2, where R2=0Ω. In this case, GNDS should be refer- enced to PGND. Tighter regulation can be achieved by using resistors with less than 1% tolerance. For Vin < 5V and Vout > 2V, the frequency select pin (FREQ) must be set to 200kHz (connected to V DD). For applications with VIN < 5V and where there is no auxiliary 5V available, connections JP2 and JP3 must be provided in order to enable the boost cir- cuit. This will provide 5V V DD necessary for the iP1001 internal logic to function. The boost circuit will convert 3.3V input voltage to 5V, to power the V DD, and will provide enough power to supply the internal logic for up to five iP1001 power blocks. iP1001 Reference Design

www.irf.com 15 iP1001 10uF 10uF 10uF 10uF 1.06uH SW1 C16 0.1µF 10uF 10uF PGND C11 470uF D1 10MQ040N R5R4 10uF 10uF 10uF C10 10uF +5V VOSVO GNDS ENABLE PGND VSW VDD PGOOD VF SGND VFS VIN FREQ ILIM VIN VOUT PGND TP3 TP4 TP5 TP2 TP1 iP1001 +5V 340K, 1% C12 470uF C13 470uF 25V 25V 25V 25V 25V 25V 25V 25V 25V 25V C14 470uF 6.3V 6.3V 6.3V 6.3V 5-12V Fig 10a. - Reference Design Schematic For <4.5VIN Fig 10b. - Reference Design Schematic For 5VIN - 12VIN Nominal 100uF 1.06uH SW1 C16 0.1µF 100uF 100uF PGND C11 470uF D1 10MQ040N R5R4 R6 +5V VOSVO VIN VOUT PGND TP3 TP4 TP5 TP2 TP1 iP1001 +5V 340K, 1% 1 2JP1 FB1 LBI2 LBO3 REF4 SHDN 5 GND 6 LX 7 OUT 8 MAX1675 22µH C17 10µF C20 1µF C19 0.1µF C18 10µF JP2 JP3 100K 91K C21 47pF C12 470uF C13 470uF Optional 6.3V 6.3V 6.3V C14 470uF 6.3V 6.3V 6.3V 6.3V 3.3-4.5V GNDS ENABLE PGND VSW VDD PGOOD VF SGND VFS VIN FREQ ILIM iP1001

www.irf.com16 iP1001 Table 4 - Reference Design Bill of Materials IRDCiP1001-A (For operation <4.5VIN) Designator Value Part Type Footprint Mfr. Mfr. P/N C1, C3, C5 100uF Capacitor, 6.3V, 20%, X5R 1812 TDK C4532X5R0J107MT C2, C4, C6, C7, C8, C9, C10, C15 - Not Installed - - - C11, C12, C13, C14 470uF Capacitor, 6.3V, 20%, Tantalum 7343 Sanyo 6TPB470M C16, C19 0.100uF Capacitor, 50V, 10%, X7R 1206 Novacap 1206B104K500N C17, C18 10.0uF Capacitor, 16V, 10%, X5R 1210 TDK C3225X5R1C106KT C20 1.00uF Capacitor, 10V, 10%, X7R 0805 MuRata GRM40X7R105K010 C21 47.0pF Capacitor, 50V, 5%, C0G 1206 MuRata GRM42-6C0G470J050A D1 40V Schottky Diode, 40V, 2.1A D-64 International Rectifier 10MQ040N JP1, JP2, JP3 - Test Point - Samtec TSW-102-07-LS JP1-1, JP2-1, JP3-1 - Shunt - Samtec SNT-100-BKT L1 1.06uH Inductor, 16A, 20%, Ferrite SMT Panasonic ETQP6F1R1BFA L2 22uH Inductor, 0.68A, 20%, Ferrite SMT Sumida CR43-220 R1 0: Resistor, 0: Jum per 2716 Isotek Corp SMT-R000 R2 - For <2Vout, Not installed For >2Vout, Resistor, 0: Jumper SMT - - R3 - For <2Vout, Resistor, 0: Jumper For >2Vout see formula for value SMT - - For <2Vout, Not installed For >2Vout recommend 1k: see formula for detail SMT - - R5 - For <2Vout, Resistor, 0: Jumper For >2Vout, Not installed 1206 Panasonic ERJ-8GEY0R00 R6 0: Resistor, 0: Jumper 1206 - - R7 340k: Resistor, 340k:, 1% 340k: sets for 20A limit. See ILIM formula for other values

1206 ROHM MCR18EZHF3403

R8 100k: Resistor, 100k:, 5% 1206 ROHM MCR18EZHJ104 R9 91k: Resistor, 91k:, 5% 1206 ROHM MCR18EZHJ913 SW1 - 8-position DIP switch SMT C&K Components SD08H0SK TP1, TP3 - Not Installed - - - TP2, TP4, TP5 - Test Point - Keystone 1502-2 U1 - Power Block SSBGA 14mmx14mm International Rectifier iP1001 U2 - IC, Step-Up DC-DC Converter, 0.5A 8uMAX Maxim MAX1675EUA IRDCiP1001-B (For operation 5VIN to 12VIN) Designator Value Part Type Footprint Mfr. Mfr. P/N C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 10.0uF Capacitor, 25V, 10%, X5R 1812 MuRata GRM43-2X5R106K25A C11 C12 C13 C14 470uF Capacitor, 6.3V, 20%, Tantalum 7343 Sanyo 6TPB470M C16 0.100uF Capacitor, 50V, 10%, X7R 1206 Novacap 1206B104K500N C15, C17, C18, C19, C20, C21 - Not Installed - - - D1 40V Schottky Diode, 40V, 2.1A D-64 International Rectifier 10MQ040N JP1, JP2, JP3 - Not Installed - - - JP1-1, JP2-1, JP3-1 - Not Installed - - - L1 1.06uH Inductor, 16A, 20%, Ferrite SMT Panasonic ETQP6F1R1BFA L2 - Not Installed - - - R1 0: Resistor, 0: Jum per 2716 Isotek Corp SMT-R000 R2 - For <2Vout, Not installed For >2Vout, Resistor, 0: Jumper SMT - - R3 - For <2Vout, Resistor, 0: Jumper For >2Vout see formula for value SMT - - R4 - For <2Vout, Not installed For >2Vout recommend 1k: see formula for detail SMT - - R5 - For <2Vout, Resistor, 0: Jumper For >2Vout, Not installed 1206 Panasonic ERJ-8GEY0R00 R6 0: Resistor, 0: Jumper 1206 - - R7 340k: Resistor, 340k:, 1% 340k: sets for 20A limit. See ILIM formula for other values R8, R9 - Not Installed - - - SW1 - 8-position DIP switch SMT C&K Components SD08H0SK TP1 TP2 TP4 TP5 - Test Point - Keystone 1502-2 TP3 - Not Installed - - - U1 - Power Block SSBGA 14mmx14mm International Rectifier iP1001 U2 - Not Installed - - -

www.irf.com 17 iP1001 Mechanical Drawing Refer to the following application notes for detailed guidelines and suggestions when implementing iPOWIR Technology products: AN-1028: Recommended Design, Integration and Rework Guidelines for International Rectifier’s iPOWIR Technology BGA Packages This paper discusses the assembly considerations that need to be taken when mounting iPOWIR BGA’s on printed circuit boards. This includes soldering, pick and place, reflow, inspection, cleaning and reworking recommendations. AN-1029: Optimizing a PCB Layout for an iPOWIR Technology Design This paper describes how to optimize the PCB layout design for both thermal and electrical performance. This includes placement, routing, and via interconnect suggestions. AN-1030: Applying iPOWIR Products in Your Thermal Environment This paper explains how to use the Power Loss and SOA curves in the data sheet to validate if the operating conditions and thermal environment are within the Safe Operating Area of the iPOWIR product. 0.12 [.005] C 2. DIMENSIONS ARE SHOWN IN MILLIMETERS [INCHES]. 3. CONTROLLING DIMENSION: MILLIMETER 1. DIMENSIONING & TOLERANCING PER ASME Y14.5M-1994. NOTES: (4X 1.0 [.039]) 2.66 [.1047] 2.46 [.0969] TOP VIEW BOTTOM VIEW SIDE VIEW 3.11 [.1224] 2.81 [.1107] C 0.45 [.0177] 0.35 [.0138] PACKAGE BODY. BALL DIAMETER, IN A PLANE PARALLEL TO DATUM C. SPHERICAL CROWNS OF THE SOLDER BALLS. 4. SOLDER BALL POSITION DESIGNATION PER JESD 95-1, SPP-010.

7 SOLDER BALL DIAMETER IS MEASURED AT THE MAXIMUM SOLDER

5 PRIMARY DATUM C (SEATING PLANE) IS DEFINED BY THE

6 BILATERAL TOLERANCE ZONE IS APPLIED TO EACH SIDE OF THE

0.15 [.006] C CORNER ID BALL A1 2X 6 14.00 [.551] B 14.00 [.551] A 0.15 [.006] C 2X 6 0.15 [.006] C A B 0.08 [.003] C 218X Ø 0.45 [.0178] 0.55 [.0216] 0.40 [.016] 0.80 [.032] 30X

www.irf.com18 iP1001 Part Marking Tape & Reel Information Data and specifications subject to change without notice. This product has been designed and qualified for the industrial market. Qualification Standards can be found on IR’s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information .03/02 0123 XXXX iP1001 TOP 24mm FEED DIRECTION20mm NOTES: 1. OUTLINE CONFORMS TO EIA-481 & EIA-541. XXXX iP1001 0123 XXXX 0123 iP1001