IMXRT1060IEC

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Technical content

Data Sheet: Technical Data Document Number: IMXRT1060IEC Rev. 0.2, 02/2020 MIMXRT1061CVL5A MIMXRT1062CVL5A MIMXRT1061CVJ5A MIMXRT1062CVJ5A

Package Information

196-pin MAPBGA, 10 x 10 mm, 0.65 mm pitch 196-pin MAPBGA, 12 x 12 mm, 0.8 mm pitch

Ordering Information

NXP reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products. 1 i.MX RT1060 Introduction The i.MX RT1060 is a new processor family featuring NXP’s advanced implementation of the Arm Cortex®-M7 core, which operates at speeds up to 528 MHz to provide high CPU performance and best real-time response. The i.MX RT1060 processor has 1 MB on-chip RAM.

512 KB can be flexibly configured as TCM or general

purpose on-chip RAM, while the other 512 KB is general-purpose on-chip RAM. The i.MX RT1060 integrates advanced power management module with DCDC and LDO that reduces complexity of external power supply and simplifies power sequencing. The i.MX RT1060 also provides various memory interfaces, including SDRAM, RAW NAND FLASH, NOR FLASH, SD/eMMC, Quad SPI, and a wide range of other interfaces for connecting peripherals, such as WLAN, Bluetooth™, GPS, displays, and camera sensors. The i.MX RT1060 has rich audio and video features, including LCD display, basic 2D graphics, camera interface, SPDIF, and I2S audio interface. The i.MX RT1060 has analog interfaces, such as ADC, ACMP, and TSC. i.MX RT1060 Crossover Processors for Industrial Products 3.2. Recommended connections for unused analog

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i.MX RT1060 Introduction The i.MX RT1060 is specifically useful for applications such as:

• Industrial Human Machine Interfaces (HMI)
• Motor Control
• Home Appliance

1.1 Features

The i.MX RT1060 processors are based on Arm Cortex-M7 MPCore™ Platform, which has the following features:

• Supports single Arm Cortex-M7 MPCore with: — 32 KB L1 Instruction Cache — 32 KB L1 Data Cache — Full featured Floating Point Unit (FPU) with support of the VFPv5 architecture — Support the Armv7-M Thumb instruction set
• Integrated MPU, up to 16 individual protection regions
• Tightly coupled GPI Os, operating at the same frequency as Arm Core
• Up to 512 KB I-TCM and D-TCM in total
• Frequency of 528 MHz
• Cortex M7 CoreSight™ compone nts integration for debug
• Frequency of the core, as per Table 10, "Operating ranges," on page 22. The SoC-level memory system consists of the following additional components: — Boot ROM (128 KB) — On-chip RAM (1 MB) – 512 KB OCRAM shared betw een ITCM/DTCM and OCRAM – Dedicate 512 KB OCRAM
• External memory interfaces: — 8/16-bit SDRAM, up to SDRAM-133/SDRAM-166 — 8/16-bit SLC NAND FLASH, with ECC handled in software —S D / e M M C — SPI NOR/NAND FLASH — Parallel NOR FLASH with XIP support — Two single/dual channel Quad SPI FLASH with XIP support
• Timers and PWMs: — Two General Programmable Timers (GPT) – 4-channel generic 32-bit resolution timer for each – Each support standard cap ture and compare operation — Four Periodical Interrupt Timers (PIT) – Generic 32-bit resolution timer

i.MX RT1060 Introduction i.MX RT1060 Crossover Processors for Industrial Products, Rev. 0.2, 02/2020 NXP Semiconductors 3 – Periodical interrupt generation — Four Quad Timers (QTimer) – 4-channel generic 16-bit resolution timer for each – Each support standard cap ture and compare operation – Quadrature decoder integrated — Four FlexPWMs – Up to 8 individual PWM channels per each – 16-bit resolution PWM suitable for Motor Control applications — Four Quadrature Encoder/Decoders Each i.MX RT1060 processor enables the following interfaces to external devices (some of them are muxed and not available simultaneously):

• Display Interface: — Parallel RGB LCD interface – Support 8/16/24 bit interface – Support up to WXGA resolution – Support Index color with 256 entry x 24 bit color LUT – Smart LCD display with 8/ 16-bit MPU/8080 interface
• Audio: — S/PDIF input and output — Three synchronous audio interface (SAI) modules supporting I2S, AC97, TDM, and codec/DSP interfaces — MQS interface for medium quality audio via GPIO pads
• Generic 2D graphics engine: — BitBlit — Flexible image composition options—alpha, chroma key — Porter-duff blending — Image rotation (90 , 180, 270) — Image size — Color space conversion — Multiple pixel format support (RGB, YUV444, YUV422, YUV420, YUV400) — Standard 2D-DMA operation
• Camera sensors: — Support 24-bit, 16-bit, and 8-bit CSI input
• Connectivity: — Two USB 2.0 OTG controllers with integrated PHY interfaces — Two Ultra Secure Digital Host Controller (uSDHC) interfaces – MMC 4.5 compliance wit h HS200 support up to 200 MB/sec

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i.MX RT1060 Introduction – SD/SDIO 3.0 compliance with 200 M Hz SDR signaling to support up to 100 MB/sec – Support for SDXC (extended capacity) — Two 10/100M Ethernet controller with support for IEEE1588 — Eight universal asynchronous receiver/transmitter (UARTs) modules — Four I2C modules — Four SPI modules — Two FlexCAN modules — One FlexCAN (with Flexible Data-Rate supported) — Three FlexIO modules

• GPIO and Pin Multiplexing: — General-purpose input/output (GPIO) modules with interrupt capability — Input/output multiplexing controller (IOMUXC) to provide centralized pad control The i.MX RT1060 processors integrate advanced power management unit and controllers:
• Full PMIC integration, inc luding on-chip DCDC and LDO
• Temperature sensor wit h programmable trim points
• GPC hardware power management controller The i.MX RT1060 processors support the following system debug:
• Arm CoreSight debug and trace architecture
• Trace Port Interface Unit (TPI U) to support off-chip real-time trace
• Cross Triggering Interface (CTI)
• Support for 5-pin (JTAG) and SWD debug interfaces The i.MX RT1060 processors support the following analog interfaces:
• Two Analog-Digital-Converters (ADC), 16-channel for each, 20-channel in total
• Four Analog Comparators (ACMP) Security functions are enabled and accelerated by the following hardware:
• High Assurance Boot (HAB)
• Data Co-Processor (DCP): — AES-128, ECB, and CBC mode — SHA-1 and SHA-256 — CRC-32
• Bus Encryption Engine (BEE) — AES-128, ECB, and CTR mode — On-the-fly QSPI Flash decryption
• True random number generation (TRNG)
• Secure Non-V olatile Storage (SNVS) — Secure real-time clock (RTC)

i.MX RT1060 Introduction i.MX RT1060 Crossover Processors for Industrial Products, Rev. 0.2, 02/2020 NXP Semiconductors 5 — Zero Master Key (ZMK)

• Secure JTAG Controller (SJC) NOTE The actual feature set depends on the part numbers as described in Table 1. Functions such as display and camera interfaces, connectivity interfaces, and security features are not offered on all derivatives.

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1.2 Ordering information

Table 1 provides examples of orderable part numbers covered by this Data Sheet. Table 1. Ordering information

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contact an NXP representative for details. Figure 1. Part number nomenclature—i.MX RT1060

400 MHz 4

500 MHz 5

600 MHz 6

700 MHz 7

800 MHz 8

1000 MHz A

1 Reduced Feature General Purpose

2 Full Feature General Purpose

02 RT1020

05 RT1050

06 RT1060

2 Architectural Overview

The following subsections provide an architectural overview of the i.MX RT1060 processor system.

2.1 Block diagram

Figure 2 shows the functional modules in the i.MX RT1060 processor system1. Figure 2. i.MX RT1060 system block diagram

1. Some modules shown in this block diagram are not offered on all derivatives. See Table 1 for details.

512 KB SRAM

128 KB ROM

32 KB I-cache 32 KB D-cache

512 KB TCM/OCRAM

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3 Modules List

modules in alphabetical order. Table 2. i.MX RT1060 modules list voltage (rail-to-rail operation). values of the four selected inputs (A, B, C, D). and 8-bit/10-bit/16-bit Bayer data input.

• System memory and peripheral registers
• All debug configuration registers The DAP also provides debugger access to JTAG scan chains. The DAP module is internal to the Cortex-M7 Core Platform.

• Adjustable high efficiency regulator
• Supports 3.3 V input voltage
• Supports nominal run and low power standby modes
• Supports at 0.9 ~ 1.3 V output in run mode
• Supports at 0.9 ~ 1.0 V output in standby mode
• Over current and over voltage detection eDMA enhanced Direct Memory Access System Control Peripherals There is an enhanced DMA (eDMA) engine and two DMA_MUX.
• The eDMA is a 32 channel DMA engine, which is capable of performing complex data transfers with minimal intervention from a host processor.
• The DMA_MUX is capable of multiplexing up to 128 DMA request sources to the 32 DMA channels of eDMA. ENC Quadrature Encoder/Decoder Timer Peripherals The enhanced quadr ature encoder/decoder module provides interfacing capability to position/speed sensors. There are five input signals: PHASEA, PHASEB, INDEX, TRIGGER, and HOME. This module is used to decode shaft position, revolution count, and speed. ENET Ethernet Controller Connectivity Peripherals The Ethernet Media Access Controller (MAC) is designed to support 10/100 Mbit/s Ethernet/IEEE 802.3 networks. An external transceiver interface and transceiver function are required to complete the interface to the media. The module has dedicated hardware to support the IEEE 1588 standard. See the ENET chapter of the reference manual for details. EWM External Watchdog Monitor Timer Peripherals The EWM modules is designed to monitor external circuits, as well as the software flow. This provides a back-up mechanism to the internal WDOG that can reset the system. The EWM differs from the internal WDOG in that it does not reset the system. The EWM, if allowed to time-out, provides an independent trigger pin that when asserted resets or places an external circuit into a safe mode. FLEXCAN1 FLEXCAN2 Flexible Controller Area Network Connectivity Peripherals The CAN protocol was primarily, but not only, designed to be used as a vehicle serial data bus, meeting the specific requirements of this field: real-time processing, reliable operation in the Electromagnetic interference (EMI) environment of a vehicle, cost-effectiveness and required bandwidth. The FlexCAN module is a full implementation of the CAN protocol specification, Version 2.0 B, which supports both standard and extended message frames.

Table 2. i.MX RT1060 modules list (continued)

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provided the clock it is using remain active. FlexRAM is the manager of the on-chip RAM array. Used for general purpose input/output to external ICs. Each GPIO module supports up to 32 bits of I/O. on an external clock or on an internal clock.

• Multiple-key detection
• Long key-press detection
• Standby key-press detection
• Supports a 2-point and 3-point contact key matrix LCDIF LCD interface Multimedia Peripherals The LCDIF is a general purpose display controller used to drive a wide range of display devices varying in size and capabilities. The LCDIF is designed to support dumb (synchronous 24-bit Parallel RGB interface) and smart (asynchronous parallel MPU interface) LCD devices. LPI2C1 LPI2C2 LPI2C3 LPI2C4 Low Power Inter-integrated Circuit Connectivity and Communications The LPI2C is a low power Inter-Integrated Circuit (I2C) module that supports an efficient interface to an I2C bus as a master. The I2C provides a method of communication between a number of external devices. More detailed information, see Section 4.9.2, LPI2C module timing parameters. LPSPI1 LPSPI2 LPSPI3 LPSPI4 Low Power Serial Peripheral Interface Connectivity and Communications The LPSPI is a low power Serial Peripheral Interface (SPI) module that support an efficient interface to an SPI bus as a master and/or a slave.
• It can continue operating while the chip is in stop modes, if an appropriate clock is available
• Designed for low CPU overhead, with DMA off loading of FIFO register access LPUART1 LPUART2 LPUART3 LPUART4 LPUART5 LPUART6 LPUART7 LPUART8 UART Interface Connectivity Peripherals Each of the UART modules support the following serial data transmit/receive protocols and configurations:
• 7- or 8-bit data words, 1 or 2 stop bits, programmable parity (even, odd or none)
• Programmable baud rates up to 5 Mbps. MQS Medium Quality Sound Multimedia Peripherals MQS is used to generate 2-channel medium quality PWM-like audio via two standard digital GPIO pins. PXP Pixel Processing Pipeline Multimedia Peripherals A high-performance pixel processor capable of 1 pixel/clock performance for combined operations, such as color-space conversion, alpha blending, and rotation. The PXP is enhanced with features specifically for gray scale applications. In addition, the PXP supports traditional pixel/frame processing paths for still-image and video processing applications.

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input filters, and multi-channel synchronization. boot up. Size of the ROM is 96 KB. kHz reference clock for the RTC. MCU. Windowed refresh mode is supported as well. module or by other post processing functions. optimized for both high-performance and low pin-count.

Control, Violation, and reporting. temperature-dependent voltage to time conversion.

• Two high-speed OTG 2.0 modules with integrated HS USB PHYs
• Support eight Transmit (TX) and eight Receive (Rx) endpoints, including endpoint 0

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• Fully compliant with MMC command/response sets and Physical Layer as defined in the Multimedia including high-capacity (size > 2 GB) cards HC MMC.
• Fully compliant with SD command/response sets and Physical Layer as defined in the SD Memory Card Specifications, v3.0 including high-capacity SDXC cards up to 2 TB.
• Fully compliant with SDIO command/response sets and interrupt/read-wait mode as defined in the SDIO Card Specification, Part E1, v3.0 Two ports support:
• 1-bit or 4-bit transfer mode specifications for SD and SDIO cards up to UHS-I SDR104 mode (104 MB/s max)
• 1-bit, 4-bit, or 8-bit transfer mode specifications for MMC cards up to 52 MHz in both SDR and DDR modes (104 MB/s max)
• 4-bit or 8-bit transfer mode specifications for eMMC chips up to 200 MHz in HS200 mode (200 MB/s max) WDOG1 WDOG2 Watch Dog Timer Peripherals The wa tchdog (WDOG) Timer supports two comparison points during each counting period. Each of the comparison points is configurable to evoke an interrupt to the Arm core, and a second point evokes an external event on the WDOG line. XBAR Cross BAR Cross Trigger Each crossbar switch is an array of m uxes with shared inputs. Each mux output provides one output of the crossbar. The number of inputs and the number of muxes/outputs are user configurable and registers are provided to select which of the shared inputs are routed to each output.

3.1 Special signal considerations

Table 3. Special signal considerations One general purpose differential high speed clock Input/output (LVDS I/O) is provided.

• To feed external reference clock to the PLLs and further to the modules inside SoC.
• To output internal SoC clock to be used outside the SoC as either reference clock or as a functional clock for peripherals. See the i.MX RT1060 Reference Manual (IMXRT1060RM) for details on the respective clock trees. Alternatively one may use single ended signal to drive CLK1_P input. In this case corresponding CLK1_N input should be tied to the constant voltage level equal 1/2 of the input signal swing. Termination should be provided in case of high frequency signals. After initialization, the CLK1 input/output can be disabled (if not used). If unused either or both of the CLK1_N/P pairs may remain unconnected. DCDC_PSWITCH PAD is in DCDC_IN dom ain and connected the ground to bypass DCDC. To enable DCDC function, assert to DCDC_IN with at least 1ms delay for DCDC_IN rising edge. RTC_XTALI/RTC_XTALO If the user wishes to configure RTC_XTALI and RTC_XTALO as an RTC oscillator, a 32.768 kHz crystal, (100 k ESR, 10 pF load) should be connected between RTC_XTALI and RTC_XTALO. Keep in mind the capacitors implemented on either side of the crystal are about twice the crystal load capacitor. To hit the exact oscillation frequency, the board capacitors need to be reduced to account for board and chip parasitics. The integrated oscillation amplifier is self biasing, but relatively weak. Care must be taken to limit parasitic leakage from RTC_XTALI and RTC_XTALO to either power or ground (>100 M). This will debias the amplifier and cause a reduction of startup margin. Typically RTC_XTALI and RTC_XTALO should bias to approximately 0.5 V. If it is desired to feed an external low frequency clock into RTC_XTALI the RTC_XTALO pin must remain unconnected or driven with a complimentary signal. The logic level of this forcing clock should not exceed VDD_SNVS_CAP level and the frequency should be <100 kHz under typical conditions. In case when high accuracy real time clock are not required system may use internal low frequency ring oscillator. It is recommended to connect RTC_XTALI to GND and keep RTC_XTALO unconnected. XTALI/XTALO A 24.0 MHz crystal shou ld be connected between XTALI and XTALO. The crystal must be rated for a maximum drive level of 250 W. An ESR (equivalent series resistance) of typical 80  is recommended. NXP SDK software requires 24 MHz on XTALI/XTALO. The crystal can be eliminated if an external 24 MHz oscillator i s available in the system. In this case, XTALO must be directly driven by the external oscillator and XTALI mounted with 18 pF capacitor. The logic level of this forcing clock cannot exceed NVCC_PLL level. If this clock is used as a reference for USB, then there are strict frequency tolerance and jitter requirements. See OSC24M chapter and relevant interface specifications chapters for details. GPANAIO This signal is reserved for NXP manufacturing use only. This output must remain unconnected.

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3.2 Recommended connections for unused analog interfaces

Table 5 shows the recommended connections for unused analog interfaces. followed. For example, do not use an external pull down on an input that has on-chip pull-up. JTAG_MOD is referenced as SJC_MOD in the i.MX RT1060 reference manual (IMXRT1060RM). operation. Termination to GND through an external pull-down resistor (such as 1 k) is allowed. JTAG_MOD set to hi configures the JTAG interface to mode compliant with IEEE1149.1 standard. NC These signals are No Connect ( NC) and should be disconnected by the user. POR_B This cold reset negative lo gic input resets all modules and logic in the IC. and external signals are considered active low). if ONOFF button is pressed longer than the off to on time, the state will transition from OFF to ON. TEST_MODE TEST_MODE is for NXP factory use. The user must tie th is pin directly to GND. Table 4. JTAG Controller interface summary Table 3. Special signal considerations (continued)

Table 5. Recommended connections for unused analog interfaces

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Electrical Characteristics

4 Electrical Characteristics

This section provides the device and module-level electrical characteristics for the i.MX RT1060 processors.

4.1 Chip-Level conditions

This section provides the device-level electrical characteristics for the IC. See Table 6 for a quick reference to the individual tables and sections.

4.1.1 Absolute maximum ratings

Stress beyond those listed under Table 7 may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Table 7 shows the absolute maximum operating ratings. Table 6. i.MX RT1060 chip-Level conditions Table 7. Absolute maximum ratings

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4.1.2 Thermal resistance

4.1.2.1 10 x 10 MM thermal resistance Table 9 shows the 10 x 10 MM package thermal resistance data. IO supply for GPIO in SDIO1 bank (3.3 V mode) NVCC_SD0 -0.3 3.6 V IO supply for GPIO in SDIO1 bank (1.8 V mode) -0.3 1.95 V IO supply for GPIO in SDIO2 bank (3.3 V mode) NVCC_SD1 -0.3 3.6 V IO supply for GPIO in SDIO2 bank (1.8 V mode) -0.3 1.95 V IO supply for GPIO in EMC bank (3.3 V mode) NVCC_EMC -0.3 3.6 V IO supply for GPIO in EMC bank (1.8 V mode) -0.3 1.95 V ESD damage Immunity: Human Body Model (HBM) Charge Device Model (CDM) Vesd 1000 500 V Input/Output Voltage range V in/Vout -0.5 OVDD + 0.3 1 V Storage Temperature range T STORAGE -40 150 o C 1 OVDD is the I/O supply voltage. Table 8. 10 x 10 MM thermal resistance data 1 Thermal test board meets JEDEC specification for this package (JESD51-9). meant to predict the performance of a package in an application-specific environment. temperature at eh package top side dead Centre. Table 7. Absolute maximum ratings (continued)

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4.1.2.2 12 x 12 MM thermal resistance Table 9 shows the 12 x 12 MM package thermal resistance data.

4.1.3 Operating ranges

Table 10 provides the operating ranges of the i.MX RT1060 processors. For details on the chip's power structure, see the “Power Management Unit (PMU)” chapter of the i.MX RT1060 Reference Manual (IMXRT1060RM). Table 9. 12 x 12 MM thermal resistance data 1 Thermal test board meets JEDEC specification for this package (JESD51-9). meant to predict the performance of a package in an application-specific environment. temperature at eh package top side dead Centre. the top surface of the board near the package. Table 10. Operating ranges

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4.1.4 External clock sources

Each i.MX RT1060 processor has two external input system clocks: a low frequency (RTC_XTALI) and a high frequency (XTALI). The RTC_XTALI is used for low-frequency functions. It supplies the clock for wake-up circuit, power-down real time clock operation, and slow system and watch-dog counters. The clock input can be VDD_HIGH internal Regulator VDD_HIGH_IN2 — 3.0 — 3.6 V Must match th e range of voltages that the rechargeable backup battery supports. Backup battery supply range VDD_SNVS_IN 3 — 2.40 — 3.6 V Can be combined with VDD_HIGH_IN, if the system does not require keeping real time and other data on OFF state. USB supply voltages USB_OTG1_VBUS — 4.40 — 5.5 V — USB_OTG2_VBUS — 4.40 — 5.5 V — GPIO supplies NVCC_GPIO — 3.0 3. 3 3.6 V All digital I/O supplies (NVCC_xxxx) must be powered (unless otherwise specified in this data sheet) under normal conditions whether the associated I/O pins are in use or not. NVCC_SD0 — 1.65 1.8 1.95 V 3.0 3.3 3.6 V NVCC_SD1 — 1.65 1.8 1.95 V 3.0 3.3 3.6 V NVCC_EMC — 1.65 1.8 1.95 V 3.0 3.3 1.95 V A/D converter VDDA_ADC_3P3 — 3.0 3 .3 3.6 V VDDA_ADC_3P3 must be powered even if the ADC is not used. VDDA_ADC_3P3 cannot be powered when the other SoC supplies (except VDD_SNVS_IN) are off. Temperature Operating Ranges Junction temperature Tj Standard Commercial -40 — 105 oC See the application note, i.MX RT1060 Product Lifetime Usage Estimates for information on product lifetime (power-on years) for this processor. 1 Applying the maximum voltage results in maximum power consumption and heat generation. NXP recommends a voltage set point = (Vmin + the supply tolerance). This result in an optimized power/speed ratio. 2 Applying the maximum voltage results in shorten lifetime. 3.6 V usage limited to < 1% of the use profile. Reset of profile limited to below 3.49 V. 3 In setting VDD_SNVS_IN voltage with regards to Charging Currents and RTC, refer to the i.MX RT1060 Hardware Development Guide (IMXRT1060HDG). Table 10. Operating ranges (continued)

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connected to either external oscillator or a crystal using internal oscillator amplifier. Additionally, there is an internal ring oscillator, which can be used instead of the RTC_XTALI if accuracy is not important. The system clock input XTALI is used to generate the main system clock. It supplies the PLLs and other peripherals. The system clock input can be connected to either external oscillator or a crystal using internal oscillator amplifier. Table 11 shows the interface frequency requirements. The typical values shown in Table 11 are required for use with NXP SDK to ensure precise time keeping and USB operation. For RTC_XTALI operation, two clock sources are available.

• On-chip 40 kHz ring oscillator—thi s clock source has the following characteristics: — Approximately 25 µA more Idd than crystal oscillator — Approximately ±50% tolerance — No external component required — Starts up quicker than 32 kHz crystal oscillator
• External crystal oscillat or with on-chip support circuit: — At power up, ring oscillator is utilized. After crystal oscillator is stable, the clock circuit switches over to the crystal oscillator automatically. — Higher accuracy than ring oscillator — If no external crystal is present, then the ring oscillator is utilized The decision of choosing a clock source should be taken based on real-time clock use and precision time-out.

4.1.5 Maximum supply currents

The data shown in Table 12 represent a use case designed specifically to show the maximum current consumption possible. All cores are running at the defined maximum frequency and are limited to L1 cache accesses only to ensure no pipeline stalls. Although a valid condition, it would have a very limited practical use case, if at all, and be limited to an extremely low duty cycle unless the intention were to specifically show the worst case power consumption. Table 11. External input clock frequency 1 External oscillator or a crystal with internal oscillator amplifier. Development Guide for i.MX RT1060 Crossover Processors (IMXRT1060HDG). 3 Recommended nominal frequency 32.768 kHz. 4 External oscillator or a fundamental frequency crystal with internal oscillator amplifier.

i.MX RT1060 Crossover Processors for Industrial Products, Rev. 0.2, 02/2020 NXP Semiconductors 25 See the i.MX RT1060 Power Consumption Measurement Application Note for more details on typical power consumption under various use case definitions. Table 12. Maximum supply currents A typical, 750 A max, for each ADC.

100 Ohm max loading for touch panel,

In this equation, Imax is in Amps, C in Farads, V in Volts, and F in Hertz.

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4.1.6 Low power mode supply currents

Table 13 shows the current core consumption (not including I/O) of i.MX RT1060 processors in selected low power modes.

4.1.7 USB PHY current consumption

4.1.7.1 Power down mode

In power down mode, everything is powered down, including the USB VBUS valid detectors in typical condition. Table 14 shows the USB interface current consumption in power down mode. Table 13. Low power mode current and power consumption on a typical process wafer at 25oC.

• CPU in WFI, CPU clock gated
• 24 MHz XTAL is ON
• System PLL is active, other PLLs are power down
• Peripheral clock gated, but remain powered
• 1024 KB RAM retention DCDC_IN (3.3 V) 4.04 mA VDD_HIGH_IN (3.3 V) 7.66 VDD_SNVS_IN (3.3 V) 0.032 Total 38.72 mW LOW POWER IDLE • LDO_2P5 and LDO_1P1 are set to Weak mode
• WFI, half FlexRAM power down in power gate mode
• All PLLs are power down
• 24 MHz XTAL is off, 24 MHz RCOSC used as clock source
• Peripheral clock gated, but remain powered
• 1024 KB RAM retention DCDC_IN (3.3 V) 1.11 mA VDD_HIGH_IN (3.3 V) 0.309 VDD_SNVS_IN (3.3 V) 0.048 Total 4.84 mW SUSPEND (DSM)
• LDO_2P5 and LDO_1P1 are shut off
• CPU in Power Gate mode
• All PLLs are power down
• 24 MHz XTAL is off, 24 MHz RCOSC is off
• All clocks are shut off, except 32 kHz RTC
• Peripheral clock gated, but remain powered
• 64 KB RAM retention DCDC_IN (3.3 V) 0.19 mA VDD_HIGH_IN (3.3 V) 0.029 VDD_SNVS_IN (3.3 V) 0.020 Total 0.789 mW SNVS (RTC) • All SOC digital lo gic, analog module are shut off
• 32 kHz RTC is alive DCDC_IN (0 V) 0 mA VDD_HIGH_IN (0 V) 0 VDD_SNVS_IN (3.3 V) 0.02 Total 0.066 mW

Table 14. USB PHY current consumption in power down mode

i.MX RT1060 Crossover Processors for Industrial Products, Rev. 0.2, 02/2020 NXP Semiconductors 27 NOTE The currents on the VDD_HIGH_CAP and VDD_USB_CAP were identified to be the voltage divider circuits in the USB-specific level shifters.

4.2 System power and clocks

This section provide the information about the system power and clocks.

4.2.1 Power supplies requir ements and restrictions

The system design must comply with power-up sequence, power-down sequence, and steady state guidelines as described in this section to guarantee the reliable operation of the device. Any deviation from these sequences may result in the following situations:

• Excessive current during power-up phase
• Prevention of the de vice from booting
• Irreversible damage to the pro cessor (worst-case scenario)

4.2.1.1 Power-up sequence

The below restrictions must be followed:

• VDD_SNVS_IN supply must be t urned on before any other power supply or be connected (shorted) with VDD_HIGH_IN supply.
• If a coin cell is used to power VDD_SNVS_IN, then ensure that it is connected before any other supply is switched on.
• When internal DCDC is enabled, e xternal delay circuit is required to delay the “DCDC_PSWITCH” signal 1 ms after DCDC_IN is stable.
• POR_B should be held low during t he entire power up sequence. NOTE The POR_B input (if used) must be immediately asserted at power-up and remain asserted until after the last power rail reaches its working voltage. In the absence of an external reset feeding the POR_B input, the internal POR module takes control. See the i.MX RT1060 Reference Manual (IMXRT1060RM) for further details and to ensure that all necessary requirements are being met. NOTE Need to ensure that there is no back voltage (leakage) from any supply on the board towards the 3.3 V supply (for example, from the external components that use both the 1.8 V and 3.3 V supplies). NOTE USB_OTG1_VBUS, USB_OTG2_VBUS, and VDDA_ADC_3P3 are not part of the power supply sequence and may be powered at any time.

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4.2.1.2 Power-down sequence

The following restrictions must be followed:

• VDD_SNVS_IN supply must be turn ed off after any other power supply or be connected (shorted) with VDD_HIGH_IN supply.
• If a coin cell is used to power VDD_SNVS_IN, then ensure that it is removed after any other supply is switched off.

4.2.1.3 Power supplies usage

All I/O pins should not be externally driven while the I/O power supply for the pin (NVCC_xxx) is OFF. This can cause internal latch-up and malfunctions due to reverse current flows. For information about I/O power supply of each pin, see “Power Rail” columns in pin list tables of Section 6, Package information and contact assignments.”

4.2.2 Integrated LDO voltage regulator parameters

Various internal supplies can be powered ON from internal LDO voltage regulators. All the supply pins named *_CAP must be connected to external capacitors. The on-board LDOs are intended for internal use only and should not be used to power any external circuitry. See the i.MX RT1060 Reference Manual (IMXRT1060RM) for details on the power tree scheme. NOTE The *_CAP signals should not be powered externally. These signals are intended for internal LDO operation only.

4.2.2.1 Digital regulators (LDO_SNVS)

There are one digital LDO regulator (“Digital”, because of the logic loads that they drive, not because of their construction). The advantages of the regulator is to reduce the input supply variation because of its input supply ripple rejection and its on-die trimming. This translates into more stable voltage for the on-chip logics. The regulator has two basic modes:

• Power Gate. The regulation FET is switched fully off limiting the current draw from the supply. The analog part of the regulator is powered down here limiting the power consumption.
• Analog regulation mode. The regu lation FET is controlled such that the output voltage of the regulator equals the target voltage. For additional information, see the i.MX RT1060 Reference Manual (IMXRT1060RM).

4.2.2.2 Regulators for analog modules

4.2.2.2.1 LDO_1P1

The LDO_1P1 regulator implements a programmable linear-regulator function from VDD_HIGH_IN (see Table 10 for minimum and maximum input requirements). Typical Programming Operating Range is 1.0

i.MX RT1060 Crossover Processors for Industrial Products, Rev. 0.2, 02/2020 NXP Semiconductors 29 V to 1.2 V with the nominal default setting as 1.1 V . The LDO_1P1 supplies the USB Phy, and PLLs. A programmable brown-out detector is included in the regulator that can be used by the system to determine when the load capability of the regulator is being exceeded to take the necessary steps. Current-limiting can be enabled to allow for in-rush current requirements during start-up, if needed. Active-pull-down can also be enabled for systems requiring this feature. For information on external capacitor requirements for this regulator, see the Hardware Development Guide for i.MX RT1060 Crossover Processors (IMXRT1060HDG). For additional information, see the i.MX RT1060 Reference Manual (IMXRT1060RM).

4.2.2.2.2 LDO_2P5

The LDO_2P5 module implements a programmable linear-regulator function from VDD_HIGH_IN (see Table 10 for minimum and maximum input requirements). Typical Programming Operating Range is 2.25 V to 2.75 V with the nominal default setting as 2.5 V . LDO_2P5 supplies the USB PHY , E-fuse module, and PLLs. A programmable brown-out detector is included in the regulator that can be used by the system to determine when the load capability of the regulator is being exceeded, to take the necessary steps. Current-limiting can be enabled to allow for in-rush current requirements during start-up, if needed. Active-pull-down can also be enabled for systems requiring this feature. An alternate self-biased low-precision weak-regulator is included that can be enabled for applications needing to keep the output voltage alive during low-power modes where the main regulator driver and its associated global bandgap reference module are disabled. The output of the weak-regulator is not programmable and is a function of the input supply as well as the load current. Typically, with a 3 V input supply the weak-regulator output is 2.525 V and its output impedance is approximately 40 . For information on external capacitor requirements for this regulator, see the Hardware Development Guide for i.MX RT1060 Crossover Processors (IMXRT1060HDG). For additional information, see the i.MX RT1060 Reference Manual (IMXRT1060RM).

4.2.2.2.3 LDO_USB

The LDO_USB module implements a programmable linear-regulator function from the USB VUSB voltages (4.4 V–5.5 V) to produce a nominal 3.0 V output voltage. A programmable brown-out detector is included in the regulator that can be used by the system to determine when the load capability of the regulator is being exceeded, to take the necessary steps. This regulator has a built in power-mux that allows the user to select to run the regulator from either USB VBUS supply, when both are present. If only one of the USB VBUS voltages is present, then, the regulator automatically selects this supply. Current limit is also included to help the system meet in-rush current targets. For information on external capacitor requirements for this regulator, see the Hardware Development Guide for i.MX RT1060 Crossover Processors (IMXRT1060HDG). For additional information, see the i.MX RT1060 Reference Manual (IMXRT1060RM).

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4.2.2.2.4 DCDC

DCDC can be configured to operate on power-save mode when the load current is less than 50 mA. During the power-save mode, the converter operates with reduced switching frequency in PFM mode and with a minimum quiescent current to maintain high efficiency. DCDC can detect the peak current in the P-channel switch. When the peak current exceeds the threshold, DCDC will give an alert signal, and the threshold can be configured. By this way, DCDC can roughly detect the current loading. DCDC also includes the following protection functions:

• Over current protection. In run mode, DCDC shuts down when detecting abnormal large current in the P-type power switch.
• Over voltage protection. DCDC shuts down when detecting the output voltage is too high.
• Low voltage detection. DCDC sh uts down when detecting the input voltage is too low. For additional information, see the i.MX RT1060 Reference Manual (IMXRT1060RM).

4.2.3 PLL’s electrical characteristics

This section provides PLL electrical characteristics.

4.2.3.1 Audio/Video PLL’s electrical parameters

4.2.3.2 System PLL

Table 15. Audio/Video PLL’s electrical parameters Table 16. System PLL’s electrical parameters

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4.2.3.3 Ethernet PLL

4.2.3.4 USB PLL

4.2.3.5 Arm PLL

4.2.4 On-chip oscillators

4.2.4.1 OSC24M

This block implements an amplifier that when combined with a suitable quartz crystal and external load capacitors implement an oscillator. The oscillator is powered from NVCC_PLL. The system crystal oscillator consists of a Pierce-type structure running off the digital supply. A straight forward biased-inverter implementation is used.

4.2.4.2 OSC32K

This block implements an amplifier that when combined with a suitable quartz crystal and external load capacitors implement a low power oscillator. It also implements a power mux such that it can be powered from either a ~3 V backup battery (VDD_SNVS_IN) or VDD_HIGH_IN such as the oscillator consumes Table 17. Ethernet PLL’s electrical parameters Table 18. USB PLL’s electrical parameters Table 19. Arm PLL’s electrical parameters

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power from VDD_HIGH_IN when that supply is available and transitions to the backup battery when VDD_HIGH_IN is lost. In addition, if the clock monitor determines that the OSC32K is not present, then the source of the 32 K will automatically switch to a crude internal ring oscillator. The frequency range of this block is approximately 10–45 kHz. It highly depends on the process, voltage, and temperature. The OSC32k runs from VDD_SNVS_CAP supply, which comes from the VDD_HIGH_IN/VDD_SNVS_IN. The target battery is a ~3 V coin cell. Proper choice of coin cell type is necessary for chosen VDD_HIGH_IN range. Appropriate series resistor (Rs) must be used when connecting the coin cell. Rs depends on the charge current limit that depends on the chosen coin cell. For example, for Panasonic ML621:

• Average Discharge V oltage is 2.5 V
• Maximum Charge Current is 0.6 mA

4.3 I/O parameters

This section provide parameters on I/O interfaces.

4.3.1 I/O DC parameters

This section includes the DC parameters of the following I/O types: Table 20. OSC32K main characteristics Fosc — 32.768 KHz — This frequency is nominal and determined main ly by the crystal selected. consumption will depend on what the digital portion of the RTC consumes. ring oscillator is not running. up and maintain oscillations. increases current oscillating through the crystal. value will decrease the oscillating margin.

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• XTALI and RTC_XTALI (Cl ock Inputs) DC Parameters
• General Purpose I/O (GPIO)
• LVDS I/O DC Parameters NOTE The term ‘NVCC_XXXX’ in this section refers to the associated supply rail of an input or output.

Figure 3. Circuit for parameters Voh and Vol for I/O cells

4.3.1.1 XTALI and RTC_XTALI ( clock inputs) DC parameters

Table 21 shows the DC parameters for the clock inputs.

4.3.1.2 Single voltage general purpose I/O (GPIO) DC parameters

operating ranges in Table 10, unless otherwise noted. Table 21. XTALI and RTC_XTALI DC parameters1 1 The DC parameters are for external clock input only.

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Table 22. Single voltage GPIO DC parameters level through to the target DC level, Vil or Vih. Monotonic input transition time is from 0.1 ns to 1 s. 3 Hysteresis of 250 mV is guaranteed over all operating conditions when hysteresis is enabled.

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4.3.1.3 LVDS I/O DC parameters

The LVDS interface complies with TIA/EIA 644-A standard. See TIA/EIA STANDARD 644-A, “Electrical Characteristics of Low V oltage Differential Signaling (LVDS) Interface Circuits” for details. Table 23 shows the Low Voltage Differential Signaling (LVDS) I/O DC parameters.

4.3.2 I/O AC parameters

This section includes the AC parameters of the following I/O types:

• General Purpose I/O (GPIO) Figure 4 shows load circuit for output, and Figure 5 show the output transition time waveform.

Figure 4. Load circuit for output Figure 5. Output transition time waveform

4.3.2.1 General purpose I/O AC parameters

Table 23. LVDS I/O DC characteristics1 1 Note: The LVDS interface is limited to CCM_CLK1_P and CCM_CLK1_N.

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4.3.3 Output buffer impedance parameters

This section defines the I/O impedance parameters of the i.MX RT1060 processors for the following I/O types:

• Single V oltage General Purpose I/O (GPIO) NOTE GPIO I/O output driver impedance is measured with “long” transmission line of impedance Ztl attached to I/O pad and incident wave launched into transmission line. Rpu/Rpd and Ztl form a voltage divider that defines specific voltage of incident wave relative to NVCC_XXXX. Output driver impedance is calculated from this voltage divider (see Figure 6).

Table 24. General purpose I/O AC parameters 1.8 V mode 1 Hysteresis mode is recommended for inputs with transition times greater than 25 ns. Table 25. General purpose I/O AC parameters 3.3 V mode 1 Hysteresis mode is recommended for inputs with transition times greater than 25 ns.

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4.3.3.1 Single voltage GPIO output buffer impedance

Table 26 shows the GPIO output buffer impedance (NVCC_XXXX 1.8 V). Table 27 shows the GPIO output buffer impedance (NVCC_XXXX 3.3 V).

4.4 System modules

This section contains the timing and electrical parameters for the modules in the i.MX RT1060 processor.

4.4.1 Reset timings parameters

Figure 7 shows the reset timing and Table 28 lists the timing parameters. Figure 7. Reset timing diagram Table 26. GPIO output buffer average impedance (NVCC_XXXX 1.8 V) Table 27. GPIO output buffer average impedance (NVCC_XXXX 3.3 V) Table 28. Reset timing parameters

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4.4.2 WDOG reset timing parameters

Figure 8 shows the WDOG reset timing and Table 29 lists the timing parameters. Figure 8. WDOGn_B timing diagram manual for detailed information.

4.4.3 SCAN JTAG Controller (SJC) timing parameters

Figure 9 depicts the SJC test clock input timing. Figure 10 depicts the SJC boundary scan timing. Figure 11 depicts the SJC test access port. Signal parameters are listed in Table 30. Figure 9. Test clock input timing diagram Table 29. WDOGn_B timing parameters

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Figure 10. Boundary Scan (JTAG) timing diagram

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4.4.4 Debug trace timing specifications

Figure 13. ARM_TRACE_CLK specifications

1 TDC = target frequency of SJC

2 VM = mid-point voltage

Table 31. Debug trace operating behaviors Table 30. JTAG timing (continued)

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4.5 External memory interface

The following sections provide information about external memory interfaces.

4.5.1 SEMC specifications

The following sections provide information on SEMC interface. Measurements are with a load of 15 pf and an input slew rate of 1 V/ns.

4.5.1.1 SEMC output timing

There are ASYNC and SYNC mode for SEMC output timing.

4.5.1.1.1 SEMC output timing in ASYNC mode

Table 32 shows SEMC output timing in ASYNC mode. Table 32. SEMC output timing in ASYNC mode detail about SEMC_*CR0.AH register field.

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Figure 15 shows the output timing in ASYNC mode. Figure 15. SEMC output timing in ASYNC mode

4.5.1.1.2 SEMC output timing in SYNC mode

Table 33 shows SEMC output timing in SYNC mode. SEMC_*CR0.AS register field. detail about SEMC_*CR0.WEH register field. about SEMC_*CR0.WEL register field. Table 33. SEMC output timing in SYNC mode

i.MX RT1060 Crossover Processors for Industrial Products, Rev. 0.2, 02/2020 NXP Semiconductors 45 Figure 16 shows the output timing in SYNC mode. Figure 16. SEMC output timing in SYNC mode

4.5.1.2 SEMC input timing

There are ASYNC and SYNC mode for SEMC input timing.

4.5.1.2.1 SEMC input t iming in ASYNC mode

Table 34 shows SEMC output timing in ASYNC mode. Figure 17 shows the input timing in ASYNC mode. Table 34. SEMC output timing in ASYNC mode

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Figure 17. SEMC input timing in ASYNC mode

4.5.1.2.2 SEMC input t iming in SYNC mode

Table 35 and Table 36 show SEMC input timing in SYNC mode. Figure 18 shows the input timing in SYNC mode. Table 35. SEMC input timing in SYNC mode (SEMC_MCR.DQSMD = 0x0) Table 36. SEMC input timing in SYNC mode (SEMC_MCR.DQSMD = 0x1)

i.MX RT1060 Crossover Processors for Industrial Products, Rev. 0.2, 02/2020 NXP Semiconductors 47 Figure 18. SEMC input timing in SYNC mode

4.5.2 FlexSPI parameters

Measurements are with a load 15 pf and input slew rate of 1 V/ns.

4.5.2.1 FlexSPI input/read timing

• Dummy read strobe generated by FlexSPI controller and looped back internally (FlexSPIn_MCR0[RXCLKSRC] = 0x0)
• Dummy read strobe generated by FlexSPI controller and looped back through the DQS pad (FlexSPIn_MCR0[RXCLKSRC] = 0x1)
• Read strobe provided by memory device and input from DQS pad (FlexSPIn_MCR0[RXCLKSRC] = 0x3) The following sections describe input signal timing for each of these four internal sample clock sources.

4.5.2.1.1 SDR mode with FlexSPI n_MCR0[RXCLKSRC] = 0x0, 0x1

Table 37. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0X0 Table 38. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0X1

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Figure 19. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0X0, 0X1 falling edge, and FlexSPI controller sampling read data on the falling edge.

4.5.2.1.2 SDR mode with FlexSPI n_MCR0[RXCLKSRC] = 0x3

• A1—Memory generates both read data and read strobe on SCK rising edge (or falling edge)
• A2—Memory generates read data on SCK falling edge and generates read strobe on SCK rising edgeSCK rising edge

Figure 20. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0X3 (case A1) Table 39. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (case A1)

i.MX RT1060 Crossover Processors for Industrial Products, Rev. 0.2, 02/2020 NXP Semiconductors 49 NOTE Timing shown is based on the memory generating read data and read strobe on the SCK rising edge. The FlexSPI controller samples read data on the DQS falling edge. Figure 21. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0X3 (case A2) samples read data on a half cycle delayed DQS falling edge.

4.5.2.1.3 DDR mode with FlexSPI n_MCR0[RXCLKSRC] = 0x0, 0x1

Table 40. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (case A2) Table 41. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x0

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Figure 22. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x0, 0x1

4.5.2.1.4 DDR mode with FlexSPI n_MCR0[RXCLKSRC] = 0x3

• B1—Memory generates both read data and read strobe on SCK edge
• B2—Memory generates read data on SCK edge and generates read strobe on SCK2 edge

Table 42. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x1 Table 43. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (case B1)

i.MX RT1060 Crossover Processors for Industrial Products, Rev. 0.2, 02/2020 NXP Semiconductors 51 Figure 23. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (case B1) Figure 24. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (case B2)

4.5.2.2 FlexSPI output/write timing

4.5.2.2.1 SDR mode

Table 44. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (case B2) Table 45. FlexSPI output timing in SDR mode

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TCSS and TCSH are configured by the FlexSPIn_FLSHAxCR1 register, the default values are shown above. See more details in the i.MX RT1060 Reference Manual (IMXRT1060RM). Figure 25. FlexSPI output timing in SDR mode

4.5.2.2.2 SDR mode

RT1060 Reference Manual (IMXRT1060RM). Table 46. FlexSPI output timing in SDR mode Table 45. FlexSPI output timing in SDR mode (continued)

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4.6 Display and graphics

The following sections provide information on display and graphic interfaces.

4.6.1 CMOS Sensor Interface (CSI) timing parameters

The following sections describe the CSI timing in gated and ungated clock modes.

4.6.1.0.1 Gated clock mode timing

CSI_PIXCLK (PIXCLK), is valid as long as HSYNC is asserted. Figure 27. CSI Gated clock mode—sensor data at falling edge, latch data at rising edge

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Figure 28. CSI Gated clock mode—sensor data at rising edge, latch data at falling edge Table 47. CSI gated clock mode timing parameters

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4.6.1.0.2 Ungated clock mode timing

Figure 29 shows the ungated clock mode timings of CSI, and Table 48 describes the timing parameters (P1–P6) that are shown in the figure. In ungated mode the CSI_VSYNC and CSI_PIXCLK signals are used, and the CSI_HSYNC signal is ignored. Figure 29. CSI ungated clock mode—sensor data at falling edge, latch data at rising edge

• Dumb sensors only support tradit ional sensor timing (vertical sync (VSYNC) and horizontal sync (HSYNC)) and output-only Bayer and statistics data.
• Smart sensors support CCIR656 vi deo decoder formats and perform additional processing of the image (for example, image compression, image pre-filtering, and various data output formats).

Table 48. CSI ungated clock mode timing parameters

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4.6.2 LCD Controller (LCD IF) timing parameters

Figure 30 shows the LCDIF timing and Table 49 lists the timing parameters. Figure 30. LCD timing

4.7 Audio

This section provide information about SAI/I2S and SPDIF.

4.7.1 SAI/I2S switching specifications

This section provides the AC timings for the SAI in master (clocks driven) and slave (clocks input) modes. (SAI_BCLK) and/or the frame sync (SAI_FS) shown in the figures below. Table 49. LCD timing parameters

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Figure 32. SAI timing—Slave mode

4.7.2 SPDIF timing parameters

encoding, the SPDIF data signal is modulated by a clock that is twice the bit rate of the data signal. SPDIF in Rx mode and the timing of the modulating Tx clock (SPDIF_ST_CLK) for SPDIF in Tx mode. Table 52. SPDIF timing parameters

• Skew
• Transition rising
• Transition falling 1.5 24.2 31.3 ns SPDIF_OUT1 output (Load = 30pf)
• Skew
• Transition rising
• Transition falling 1.5 13.6 18.0 ns Modulating Rx clock (SPDIF_SR_CLK) period srckp 40.0 — ns

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4.8 Analog

The following sections provide information about analog interfaces.

4.8.1 DCDC

Table 53 introduces the DCDC electrical specifications. Table 53. DCDC electrical specifications Table 52. SPDIF timing parameters (continued)

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4.8.2 A/D converter

This section introduces information about A/D converter. 4.8.2.1 12-bit ADC electrical characteristics The section provide information about 12-bit ADC electrical characteristics. 4.8.2.1.1 12-bit ADC operating conditions Efficiency 90% max @150 mA Low power mode Open loop mode Ri pple is about 15 mV in Run mode Run mode • Always continuous mode

• Support discontinuous mode Configurable by register Inductor 4.7 H— Capacitor 33 F— Over voltage protection 1.55 V Det ect VDDSOC, when the voltage is higher than 1.6 V, shutdown DCDC. Over Current protection 1 A Detect the peak current
• Run mode: when the current is larger than 1 A, shutdown DCDC. Low DCDC_IN detection 2.6 V Detec t the DCDC_IN, when battery is lower than 2.6 V, shutdown DCDC.

Table 54. 12-bit ADC operating conditions Table 53. DCDC electrical specifications (continued)

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2 DC potential differences

Table 54. 12-bit ADC operating conditions (continued)

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12-bit ADC characteristics Table 55. 12-bit ADC characteristics (VREFH = VDDA, VREFL = VSSAD)

i.MX RT1060 Crossover Processors for Industrial Products, Rev. 0.2, 02/2020 NXP Semiconductors 63 Conversion Cycles ADLSMP=0 ADSTS=00 Cconv — 28 — cycles — ADLSMP=0 ADSTS=01 ADLSMP=0 ADSTS=10 ADLSMP=0 ADSTS=11 ADLSMP=1 ADSTS=00 ADLSMP=1 ADSTS=01 ADLSMP=1 ADSTS=10 ADLSMP=1, ADSTS=11 Conversion Time ADLSMP=0 ADSTS=00 Tconv — 0.7 — µs Fadc=40 MHz ADLSMP=0 ADSTS=01 0.75 ADLSMP=0 ADSTS=10 0.8 ADLSMP=0 ADSTS=11 0.85 ADLSMP=1 ADSTS=00 0.95 ADLSMP=1 ADSTS=01 1.05 ADLSMP=1 ADSTS=10 1.15 ADLSMP=1, ADSTS=11 1.25 Total Unadjusted Error 12 bit mode TUE — 3.4 — LSB

1 LSB =

(VREFH - VREFL)/2 N AVGE = 1, AVGS = 1110 bit mode — 1.5 — 8 bit mode — 1.2 — Differential Non-Linearity 12 bit mode DNL — 0.76 — LS B AVGE = 1, AVGS = 1110bit mode — 0.36 — 8 bit mode — 0.14 — Table 55. 12-bit ADC characteristics (VREFH = VDDA, VREFL = VSSAD) (continued)

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The ADC electrical spec is met with the calibration enabled configuration. Figure 36. Minimum Sample Time Vs Ras (Cas = 2pF)

1 All accuracy numbers assume the ADC is calibrated with VREFH = VDDAD

only and are not tested in production.

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4.8.3 ACMP

Table 56 lists the ACMP electrical specifications. Table 56. Comparator and 6-bit DAC electrical specifications

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4.9 Communication interfaces

The following sections provide the information about communication interfaces.

4.9.1 LPSPI timing parameters

The Low Power Serial Peripheral Interface (LPSPI) provides a synchronous serial bus with master and slave operations. Many of the transfer attributes are programmable. The following tables provide timing characteristics for classic LPSPI timing modes. All timing is shown with respect to 20% VDD and 80% VDD thresholds, unless noted, as well as input signal transitions of 3 ns and a 30 pF maximum load on all LPSPI pins. VH Analog comparator hysteresis1 mV

• CR0[HYSTCTR] = 00 — 1 2
• CR0[HYSTCTR] = 01 — 21 54
• CR0[HYSTCTR] = 10 — 42 108
• CR0[HYSTCTR] = 11 — 64 184 V CMPOH Output high V DD - 0.5 — — V VCMPOI Output low — — 0.5 V tDHS Propagation delay, high-speed mode (EN = 1, PMODE = 1)2 —2 54 0n s tDLS Propagation delay, low-speed mode (EN = 1, PMODE = 0)2 —5 09 0n s tDInit Analog comparator initialization delay3 —1 . 5 — s IDAC6b 6-bit DAC current adder (enabled) — 5 — A RDAC6b 6-bit DAC reference inputs — V DD —V INLDAC6b 6-bit DAC integral non-linearity -0.3 — 0.3 LSB 4 DNLDAC6b 6-bit DAC differential non-linearity -0.15 — 0.15 LSB 4 1 Typical hysteresis is measured with input voltage range limited to 0.7 to VDD - 0.7 V in high speed mode. 2 Signal swing is 100 mV. 3 Comparator initialization delay is defined as the time between software writes to the enable comparator module and the comparator output setting to a stable level. 4 1 LSB = Vreference / 64

Table 56. Comparator and 6-bit DAC electrical specifications (continued)

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1. If configured as an output.

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Figure 40. LPSPI Master mode timing (CPHA = 1) Table 58. LPSPI Slave mode timing guaranteed this limit is not exceeded.

3 Time to data active from high-impedance state

4 Hold time to high-impedance state

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4.9.2 LPI2C module timing parameters

This section describes the timing parameters of the LPI2C module.

4.9.3 Ultra High Speed SD/SDIO/MMC Host Interface (uSDHC) AC

This section describes the electrical information of the uSDHC, which includes SD/eMMC4.3 (Single 4.9.3.1 SD/eMMC4.3 (single data rate) AC timing Figure 43 depicts the timing of SD/eMMC4.3, and Table 60 lists the SD/eMMC4.3 timing characteristics. Figure 43. SD/eMMC4.3 timing Table 59. LPI2C module timing parameters 1 Hs-mode is only supported in slave mode. 2 See General switching specifications.

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Figure 44. eMMC4.4/4.41 timing Table 61. eMMC4.4/4.41 interface timing specification

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4.9.3.3 SDR50/SDR104 AC timing

Figure 45 depicts the timing of SDR50/SDR104, and Table 62 lists the SDR50/SDR104 timing characteristics. Figure 45. SDR50/SDR104 timing Table 62. SDR50/SDR104 interface timing specification 1Data window in SDR104 mode is variable.

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4.9.3.4 HS200 mode timing

Figure 46 depicts the timing of HS200 mode, and Table 63 lists the HS200 timing characteristics. Figure 46. HS200 mode timing "Single voltage GPIO DC parameters," on page 34.

4.9.4 Ethernet controller (ENET) AC electrical specifications

at timing specs/constraints for the physical interface. Table 63. HS200 interface timing specification 1HS200 is for 8 bits while SDR104 is for 4 bits.

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4.9.4.1 ENET MII mode timing

This subsection describes MII receive, transmit, asynchronous inputs, and serial management signal timings.

4.9.4.1.1 MII receive s ignal timing (ENET_RX_DATA3,2,1,0, ENET_RX_EN,

ENET_RX_ER, and ENET_RX_CLK) The receiver functions correctly up to an ENET_RX_CLK maximum frequency of 25 MHz + 1%. There is no minimum frequency requirement. Additionally, the processor clock frequency must exceed twice the ENET_RX_CLK frequency. Figure 47 shows MII receive signal timings. Table 64 describes the timing parameters (M1–M4) shown in the figure. Figure 47. MII receive signal timing diagram 1 ENET_RX_EN, ENET_RX_CLK, and ENET0_RXD0 have the same timing in 10 Mbps 7-wire interface mode.

4.9.4.1.2 MII transmit signal tim ing (ENET_TX_DATA3,2,1,0, ENET_TX_EN,

The transmitter functions correctly up to an ENET_TX_CLK maximum frequency of 25 MHz + 1%. twice the ENET_TX_CLK frequency. Table 64. MII receive signal timing

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Figure 48 shows MII transmit signal timings. Table 65 describes the timing parameters (M5–M8) shown in the figure. Figure 48. MII transmit signal timing diagram 1 ENET_TX_EN, ENET_TX_CLK, and ENET0_TXD0 have the same timing in 10-Mbps 7-wire interface mode.

4.9.4.1.3 MII asynchr onous inputs signal timing (ENET_CRS and ENET_COL)

Figure 49. MII asynchronous inputs timing diagram 1 ENET_COL has the same timing in 10-Mbit 7-wire interface mode. Table 65. MII transmit signal timing Table 66. MII asynchronous inputs signal timing

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4.9.4.1.4 MII serial ma nagement channel timing (ENET_MDIO and ENET_MDC)

The MDC frequency is designed to be equal to or less than 2.5 MHz to be compatible with the IEEE 802.3 MII specification. However the ENET can function correctly with a maximum MDC frequency of 15 MHz. Figure 50 shows MII asynchronous input timings. Table 67 describes the timing parameters (M10–M15) shown in the figure. Figure 50. MII serial management channel timing diagram

4.9.4.2 RMII mode timing

ENET_TX_EN, ENET_TX_DATA[1:0], ENET_RX_DATA[1:0] and ENET_RX_ER. Table 67. MII serial management channel timing M10 ENET_MDC falling edge to ENET _MDIO output invalid (min. M11 ENET_MDC falling edge to EN ET_MDIO output valid (max.

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Figure 51 shows RMII mode timings. Table 68 describes the timing parameters (M16–M21) shown in the figure. Figure 51. RMII mode signal timing diagram

4.9.5 Flexible Controller Area N etwork (FLEXCAN) AC electrical

Please refer to Section 4.3.2.1, General purpose I/O AC parameters.

4.9.6 LPUART electrical specifications

Please refer to Section 4.3.2.1, General purpose I/O AC parameters. Table 68. RMII signal timing

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4.9.7 USB PHY parameters

This section describes the USB-OTG PHY parameters. The USB PHY meets the electrical compliance requirements defined in the Universal Serial Bus Revision 2.0 OTG with the following amendments.

• USB ENGINEERING CHANGE NOTICE — Title: 5V Short Circuit Withstand Requirement Change — Applies to: Universal Serial Bus Specification, Revision 2.0
• Errata for USB Revision 2.0 April 27, 2000 as of 12/7/2000
• USB ENGINEERING CHANGE NOTICE — Title: Pull-up/Pull-down resistors — Applies to: Universal Serial Bus Specification, Revision 2.0
• USB ENGINEERING CHANGE NOTICE — Title: Suspend Current Limit Changes — Applies to: Universal Serial Bus Specification, Revision 2.0
• USB ENGINEERING CHANGE NOTICE — Title: USB 2.0 Phase Locked SOFs — Applies to: Universal Serial Bus Specification, Revision 2.0
• On-The-Go and Embedded Host S upplement to the USB Revision 2.0 Specification — Revision 2.0 plus errata and ecn June 4, 2010
• Battery Charging Specificat ion (available from USB-IF) — Revision 1.2, December 7, 2010 — Portable device only

4.10 Timers

This section provide information on timers.

4.10.1 Pulse Width Modulat or (PWM) characteristics

This section describes the electrical information of the PWM.

4.10.2 Quad timer timing

Table 70 listed the timing parameters. Table 69. PWM timing parameters

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Figure 52. Quad timer timing Table 70. Quad timer timing 1 T = clock cycle. For 60 MHz operation, T = 16.7 ns.

5 Boot mode configuration

5.1 Boot mode configuration pins

sampled at reset and can be used to override fuse values, depending on the value of BT_FUSE_SEL fuse. Fuse Map document and the System Boot chapter in i.MX RT1060 Reference Manual (IMXRT1060RM).

5.2 Boot device interface allocation

which are configured during boot when appropriate. Table 71. Fuses and associated pins used for boot Table 72. Boot trough NAND

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Table 73. Boot trough NOR

Table 74. Boot through FlexSPI

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Table 75. Boot through SD1 Table 76. Boot through SD2 Table 77. Boot through SPI-1 Table 74. Boot through FlexSPI (continued)

Table 78. Boot through SPI-2 Table 79. Boot through SPI-3 Table 80. Boot through SPI-4 Table 81. Boot through UART1

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Package information and contact assignments

6 Package information and contact assignments

This section includes the contact assignment information and mechanical package drawing. 6.1 10 x 10 mm package information 6.1.1 10 x 10 mm, 0.65 mm pitch, ball matrix Figure 53 shows the top, bottom, and side views of the 10 x 10 mm MAPBGA package.

Figure 53. 10 x 10 mm BGA, case x package top, bottom, and side Views

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Table 82 shows the device connection list for ground, sense, and reference contact signals. Table 83 shows an alpha-sorted list of functional contact assignments for the 10 x 10 mm package. Table 82. 10 x 10 mm supplies contact assignment Table 83. 10 x 10 mm functional contact assignments

Table 83. 10 x 10 mm functional contact assignments (continued)

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Table 84 shows the 10 x 10 mm, 0.65 mm pitch ball map for the i.MX RT1060. Table 84. 10x10 mm, 0.65 mm pitch, ball map

Table 84. 10x10 mm, 0.65 mm pitch, ball map (continued)

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Package information and contact assignments 6.2 12 x 12 mm package information 6.2.1 12 x 12 mm, 0.8 mm pitch, ball matrix Figure 54 shows the top, bottom, and side views of the 12 x 12 mm MAPBGA package.

Figure 54. 12 x 12 mm BGA, case x package top, bottom, and side Views

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Table 85 shows the device connection list for ground, sense, and reference contact signals. Table 86 shows an alpha-sorted list of functional contact assignments for the 12 x 12 mm package. Table 85. 12 x 12 mm supplies contact assignment Table 86. 12 x 12 mm functional contact assignments

Table 86. 12 x 12 mm functional contact assignments (continued)

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Table 87 shows the 10 x 10 mm, 0.8 mm pitch ball map for the i.MX RT1060. Table 87. 12 x 12 mm, 0.8 mm pitch, ball map

Table 87. 12 x 12 mm, 0.8 mm pitch, ball map (continued)

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Revision history

7 Revision history

Table 88 provides a revision history for this data sheet. Table 88. i.MX RT1060 Data Sheet document revision history

• Updated the Table 81, Boot through UART1 and removed the Table, Boot through UART2
• Updated the figure and table numbers in the Section 6.2, 12 x 12 mm package information
• Updated the Figure 53, "10 x 10 mm BGA, case x package top, bottom, and side Views" and Figure 54, "12 x 12 mm BGA, case x package top, bottom, and side Views" Rev. 0.1 04/2019 • Updated ADC in formation and removed DAC from Section 1.1, Features and Figure 2, "i.MX RT1060 system block diagram"
• Updated the RT website link in the Section 1.2, Ordering information
• Removed tamper detection from the Table 2, i.MX RT1060 modules list
• Updated the on-chip termination values of JTAG_TCK and JTAG_MOD in the Table 4, JTAG Controller interface summary
• Updated the maximum value of VDD_SOC_IN in the Table 7, Absolute maximum ratings
• Changed 528 MHz PLL to System PLL in the Table 16, System PLL’s electrical parameters
• Changed 480 MHz PLL to USB PLL in the Table 18, USB PLL’s electrical parameters
• Updated the VDD name of supply voltage conditions column in the Table 54, 12-bit ADC operating conditions
• Added the Figure 36, "Minimum Sample Time Vs Ras (Cas = 2pF)", Figure 37, "Minimum Sample Time Vs Ras (Cas = 5 pF)", and Figure 38, "Minimum Sample Time Vs Ras (Cas = 10 pF)" in the Section 4.8.2, A/D converter
• Updated the Section 4.9.1, LPSPI timing parameters Rev. 0 08/2018 • Initial version

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