IMX8DXAEC

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Technical content

Ordering Information

See Section 1.1Table 2 on page 5 MIMX8UXnAVxFZAC NXP Semiconductors Data Sheet: Technical Data Document Number: IMX8DXAEC Rev. 3, 05/2020

Package Information

21 x 21 mm package case outline 17 x 17 mm package case outline © 2018-2020 NXP B.V. NXP reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.

1 Introduction

This data sheet contains specifications for the i.MX 8DualX processor, which, along with the i.MX 8QuadXPlus and 8DualXPlus processors, comprise the i.MX 8X Family (for i.MX 8QuadXPlus and 8DualXPlus specifications, see i.MX 8QuadXPlus and 8DualXPlus Automotive and Infotainment Processors [IMX8QXPAEC]). The i.MX 8X processors consist of three to five Arm cores (two to four Arm Cortex®-A35 and one Cortex®-M4F). All devices include separate GPU and VPU subsystems as well as a failover-ready display controller. Advanced multicore audio processing is supported by the Arm cores and a high performance Tensilica® HiFi 4 DSP for pre- and post-audio processing as well as voice recognition. The i.MX 8X Family supports up to three displays with multiple display output options, including parallel, MIPI-DSI, and LVDS. Memory interfaces for this device include:

• L P D D R 4
• DDR3L i.MX 8DualX Automotive and Infotainment Applications Processors

1.2 System Controller Firmware (SCFW) Requirements5

3.2 Recommended Connections for Unused Interfaces14

4.9 General-Purpose Media Interface (GPMI) Timing. 50

• 2 × Quad SPI or 1× Octal SPI (FlexSPI)
• eMMC 5.1, RAW NAND, and SD 3.0 A wide range of peripheral I/Os such as CAN, parallel or MIPI CSI camera input, Gigabit Ethernet, USB 2.0 OTG, USB 3.0 (8QuadXPlus/8DualXPlus only), ADC, and PCIe 3.0 provide impressive flexibility. The i.MX 8DualX processor offers numerous advanced features as shown in this table.

Table 1. i.MX 8DualX advanced features Cortex-A35 cores support ARM virtualization extensions.

640 MHz

32 KB instruction cache, 48 KB data cache, 512 KB SRAM (448 KB of OCRAM and

64 KB of TCM)

be a single dual-channel LVDS interface. See the security reference manual for this chip for a full list of security features.

• The tightly coupled M4 I 2C ports cannot be used for general-purpose use
• System Control Unit (SCU):
• Power control, clocks, reset
• Boot ROMs
• PMIC interface
• Resource Domain Controller

Table 1. i.MX 8DualX advanced features (continued)

enhanced RX FIFO or DMA support in FD mode.

• 4 × UARTs (3× with hardware flow control)
• 1 × UART tightly coupled with Cortex-M4F cores
• 1 × SCU UART (Note: SCU UART is dedicated to the SCU and not available for general use) 10× I2C (note that there are two types of I2C: High-speed I2C ports with DMA support, and low-speed I2C ports with no DMA support, which are used in conjunction with a specific PHY interface—for example, for touchscreen):
• 4 × I2C: High Speed, DMA support
• 4 × I2C: Low Speed, no DMA support
• 1 × I2C: PMIC control (dedicated)
• 1 × I2C: Cortex M4F (dedicated) Note: I2C ports associated with a PHY (e.g. MIPI DSI) can be used generally but require the PHY to be powered on even if the PHY interface itself is not used. 4× SAI (SAI0 and SAI1 are transmit/receive; SAI2 and SAI3 are receive only) 1× Enhanced Serial Audio Interface (ESAI) 2× ASRC (Asynchronous Sample Rate Converter) (note: no I/O signals are directly connected to this module) 1× SPDIF (Tx and Rx) 1× 6-channel ADC converter 3.3 V/1.8 V GPIO 4× PWM channels 1× 4×4 KPP (Key Pad Port) 1× MQS (Medium Quality Sound) 4× SPI Packaging Case FCPBGA 21 x 21 mm, 0.8 mm pitch Case FCPBGA 17 x 17 mm, 0.8 mm pitch

1.1 Ordering Information

For ordering information, contact an NXP representative at nxp.com.

1.2 System Controller Firmware (SCFW) Requirements

potential reliability issues. support the wider BSP functionality. BSP release. Customers should not mix newer BSP versions with older revisions of the SCFW. Table 2. i.MX 8DualX Orderable part numbers Parallel LCD, 2 USB2, 16-bit DDR.

1.3 Package options

1.4 Related resources

2 Architectural Overview

The following subsections provide an architectural overview of the i.MX 8DualX processor system. Table 3. Feature differences per package1 will place different restrictions on the overall IOMUX capabilities of the smaller package parts. Table 4. Related resources Data sheet This data sheet includes electrical characteristics and signal connections. Hardware guide Contact an NXP representative for access.

2.1 Block Diagram

The following figure shows the functional modules in the processor system. Figure 1. i.MX 8DualX System Block Diagram

3 Modules List

processor modules in alphabetical order. Table 5. i.MX 8DualX modules list designed for operation within a SoC. devices on this bus and a vectored interrupt controller for the Arm core. A35 Arm (CPU1) 2x Cortex-A35 CPUs with a 32KB L1 instruction cache and a 32 KB data cache. The CPUs share a 512 KB L2 cache. up to three sampling rate pairs. Pseudo Random Number Generator (PRNG). used by features of the Coresight infrastructure. CTM Cross Trigger Matrix Cross Trigger Matrix IP is used to route triggering events between CTIs.

• System memory and peripheral registers
• All debug configuration registers The DAP also provides debugger access to JTAG scan chains. DC Display Controller Dual display controller DDR Controller DRAM Controller • Memory types: LPDDR4and DDR3L
• One channel of 16-bit memory:
• LPDDR4 up to 1.2 GHz
• DDR3L up to 933MHz DPR Display/Prefetch/ Resolve The DPR prefetches data from memory and converts the data to raster format for display output. Raster source buffers can also be prefetched unconverted. The resolve process supports graphics and video formatted tile frame buffers and converts them to raster format. Embedded display memory is used as temporary storage for data which is sourced by the display controller to drive the display.

standard for traffic over MLB25/50.

• 4 × eDMA with a total of 96 channels (note: all channels are not assigned; see the product reference manual for more information):
• 2 × instances with 32 channels each
• 2 × instances with 16 channels each
• Programmable source, destination addresses, transfer size, plus support for enhanced addressing modes
• Internal data buffer, used as temporary storage to support 64-byte burst transfers, one outstanding transaction per DMA controller.
• Transfer control descriptor organized to support two-deep, nested transfer operations
• Channel service request via one of three methods:
• Explicit software initiation
• Initiation via a channel-to-channel linking mechanism for continuous transfers
• Peripheral-paced hardware requests (one per channel)
• Support for fixed-priority and round-robin channel arbitration
• Channel completion reported via interrupt requests
• Support for scatter/gather DMA processing
• Support for complex data structures via transfer descriptors
• Support to cancel transfers via software or hardware
• Each eDMA instance can be uniquely assigned to a different resource domain, security (TZ) state, and virtual machine
• In scatter-gather mode, each transfer descriptor’s buffers can be assigned to different SMMU translation ENET Ethernet Controller 1 × 1 Gbps Ethernet + 1× 10/100 Mbps Ethernet + AVB (Audio Video Bridging, IEEE 802.1Qav) ESAI Enhanced Serial Audio Interface The Enhanced Serial Audio Interface (ESAI) provides a full-duplex serial port for serial communication with a variety of serial devices, including industry-standard codecs, SPDIF transceivers, and other processors. The ESAI consists of independent transmitter and receiver sections, each section with its own clock generator. All serial transfers are synchronized to a clock. Additional synchronization signals are used to delineate the word frames. The normal mode of operation is used to transfer data at a periodic rate, one word per period. The network mode is also intended for periodic transfers; however, it supports up to 32 words (time slots) per period. This mode can be used to build time division multiplexed (TDM) networks. In contrast, the on-demand mode is intended for non-periodic transfers of data and to transfer data serially at high speed when the data becomes available. The ESAI has 12 pins for data and clocking connection to external devices. FTM FlexTimer Provides input signal capture and PWM support FlexCAN Flexible Controller Area Network Communication controller implementing the CAN with Flexible Data rate (CAN FD) protocol and the CAN protocol according to the CAN 2.0B protocol specification.

Table 5. i.MX 8DualX modules list (continued)

• Flexible sequence engine to support various flash vendor devices, including HyperBus™ devices:
• Support for FPGA interface
• Single, dual, quad, and octal mode of operation.
• DDR/DTR mode wherein the data is generated on every edge of the serial flash clock.
• Support for flash data strobe signal for data sampling in DDR and SDR mode.
• Two identical serial flash devices can be connected and accessed in parallel for data read operations, forming one (virtual) flash memory with doubled readout bandwidth. GIC Generic Interrupt Controller The GIC-500 handles all interrupts from the various subsystems and is ready for virtualization. GPIO General Purpose I/O Modules Used for general purpose input/output to external devices. Each GPIO module supports 32 bits of I/O. GPMI General Purpose Media Interface The GPMI module supports up to 8× NAND devices. 62-bit ECC (BCH) for NAND Flash controller (GPMI). The GPMI supports separate DMA channels per NAND device. GPT General Purpose Timer Each GPT is a 32-bit “fr ee-running” or “set and forget” mode timer with programmable prescaler and compare and capture register. A timer counter value can be captured using an external event and can be configured to trigger a capture event on either the leading or trailing edges of an input pulse. When the timer is configured to operate in “set and forget” mode, it is capable of providing precise interrupts at regular intervals with minimal processor intervention. The counter has output compare logic to provide the status and interrupt at comparison. This timer can be configured to run either on an external clock or on an internal clock. GPU Graphics Processing 1 × GC7000Lite with 4x Vec4 shader cores (16 execution units) HiFi 4 DSP Audio Processor A highly optimized audio processor geared for efficient execution of audio and voice codecs and pre- and post-processing modules to offload the Arm core. I 2CI 2C Interface I 2C provides serial interface for external devices. IEE • Supports direct encryption and decryption of FlexSPI memory type
• Provides decryption services (lower performance) for DRAM traffic
• Supports I/O direct encrypted storage and retrieval
• Support for a number of cryptographic standards:
• 128/256-bit AES Encryption (AES-CTR, AES-XTS mode options)
• Multiple keys supported:
• Loaded via secure key channel from security block
• Key selection is per access and based on source of transaction IOMUXC IOMUX Control This module enables flexible I/O multiplexing. Each I/O pad has default and several alternate functions. The alternate functions are software configurable. JPEG/dec MJPEG engine for decode Provides up to 4-stream decoding in parallel. JPEG/enc MJPEG engine for encode Provides up to 4-stream encoding in parallel.

matrix interface or as general purpose input/output (I/O). counter value can be programmed on the fly. Master/Slave modes, four chip selects to support multiple peripherals.

• AHB LMEM (Local Memory Controller) including controllers for TCM and cache memories
• 256 KB tightly coupled memory(TCM) (128 KB TCMU, 128 KB TCML)
• 16 KB Code Bus Cache
• 16 KB System Bus Cache
• ECC for TCM memories and parity for code and system caches
• Integrated Nested Vector Interrupt Controller (NVIC)
• Wakeup Interrupt Controller (WIC)
• FPU (Floating Point Unit)
• Core MPU (Memory Protection Unit)
• Support for exclusive access on the system bus
• MMCAU (Crypto Acceleration Unit)
• MCM (Miscellaneous Control Module) MIPI CSI-2 MIPI CSI-2 Interface The MIPI CSI-2 IP provi des MIPI CSI-2 standard camera interface ports. The MIPI CSI-2 interface supports up to 1.5 Gbps for up to 4 data lanes MIPI-DSI/LVDS MIPI DSI/LVDS Combo interface The MIPI DSI IP provides DSI standard display serial interface with 4 data lines. The DSI interface supports 80 Mbps to 1.05 Gbps speed per data lane. The LVDS is a high-performance 2-channel serializer that interfaces with LVDS displays. Note: This is a combination PHY interface. It includes the digital logic and physical interface pins for both MIPI DSI (4 data lanes) and LVDS (4 differential pairs plus one for clock). The interface can be pinned out either as MIPI DSI or as LVDS. However, it does not allow for simultaneous use on one interface MLB MediaLB Media local bus interface m odule that provides a link to a MOST® data network, using the standardized MediaLB protocol. Supports 3-wire interface (MLB25, MLB50). MQS Medium Quality Sound Medium Quality Sound (MQS) is used to generate 2-channel medium quality PWM-like audio via two standard digital GPIO pins. OCOTP_CTRL OTP Controller The On-Chip OTP controller (OCOTP_CTRL) provides an interface for reading, programming, and/or overriding identification and control information stored in on-chip fuse elements. The module supports electrically-programmable poly fuses (eFUSEs). The OCOTP_CTRL also provides a set of volatile software-accessible signals that can be used for software control of hardware elements, not requiring non-volatility. The OCOTP_CTRL provides the primary user-visible mechanism for interfacing with on-chip fuse elements. Among the uses for the fuses are unique chip identifiers, mask revision numbers, cryptographic keys, JTAG secure mode, boot characteristics, and various control signals requiring permanent nonvolatility.

between the system’s AXI bus and the internal (on-chip) SRAM memory module.

• Configurable interface logic to support the most commonly used parallel CMOS sensors
• Configurable master clock output to drive external sensor (24 MHz nominal)
• Up to 150 MHz input clock from sensor
• Input data formats supported:
• 8-bit/10-bit BT.656
• 8-bit data port for RGB, YCbCr, and YUV data input
• 8-bit/10-bit data port for Bayer data input Note: For some formats a single pixel is sent per clock, for others two or three are sent per clock. PCIe PCI Express 3.0 The PCIe IP provides PCI Express Gen 3.0 functionality . PRG Prefetch/Resolve Gasket The PRG is a gasket which translates system memory accesses to local display RTRAM accesses for display refresh. It works with the DPR to complete the prefetch and resolving operations needed to drive the display. PWM Pulse Width Modulation The pulse-width modulato r (PWM) has a 16-bit counter and is optimized to generate sound from stored sample audio images and it can also generate tones. It uses 16-bit resolution and a 4×16 data FIFO to generate square waveforms. RAM

64 KB Secure

Secure/non-secure Internal RAM, interfaced through the CAAM. Internal RAM Internal RAM, which is a ccessed through OCRAM memory controllers. challenges, and other similar quantities used in cryptographic algorithms. SECO Security Controller Core and associated memory and hardware responsible for key management. standard support, which is compatible with IEEE1149.1 and IEEE1149.6 standards. against unauthorized accesses. Modes are selected through eFUSE configuration.

Machine, Master Key Control, and Violation/Tamper Detection and reporting. an incoming sampling frequency. conditions. The temperature read out does not reflect case or ambient temperature. It reflects the temperature in proximity of the sensor location on the die. value may not be the reflection of the temperature value for the entire die.

• Serial IR interface low-speed, IrDA-compatible (up to 115.2 Kbit/s)
• 9-bit or Multidrop mode (RS-485) support (automatic slave address detection)
• 7, 8, 9, or 10-bit data characters (7-bits only with parity)
• 1 or 2 stop bits
• Programmable parity (even, odd, and no parity)
• Hardware flow control support for request to send (RTS_B) and clear to send (CTS_B) signals USB2 The USB2 OTG module has been specified to perform USB 2.0 On-The-Go (OTG) compatible with the USB 2.0 specification with OTG supplementary specifications. Specific features requested for this updated module:
• High Speed (480 Mbps), full speed (12 Mbps) and low speed (1.5 Mbps)
• Fully compatible with the USB On-The-Go supplement to the USB 2.0 specification
• Hardware support for OTG signaling
• Host Negotiation Protocol (HNP) and Session Request Protocol (SRP) implemented in hardware, which can also be controlled by software USBOH The USBOH module has been specif ied which performs USB 2.0 On-The-Go (OTG) and USB 2.0 Host functionality compatible with the USB 2.0 with OTG supplement specification. This controller supports one independent USB core (1 USB2.0 OTG) and includes the PHY and I/O interfaces to support this operation. Key features:
• One USB2.0 OTG controller
• High Speed (480 Mbps), full speed (12 Mbps) and low speed (1.5 Mbps)
• Fully compatible with the USB 2.0 specification
• Fully compatible with the USB On-The-Go supplement to the USB 2.0 specification
• Hardware support for OTG signaling Host Negotiation Protocol (HNP) and Session Request Protocol (SRP) implemented in hardware, which can also be controlled by software

3.1 Special Signal Considerations

assignments".” Signal descriptions are defined in the device reference manual.

3.2 Recommended Connections for Unused Interfaces

Input/Output Terminations,” in the hardware development guide for this device.

• SD Host Controller Standard Specification v3.0 with the exception that all the registers do not match the standards address mapping.
• SD Physical Layer Specification v3.0 UHS-I (SDR104/DDR50)
• SDIO specification v3.0
• eMMC System Specification v5.1 VPU Video Processing Unit See the device reference manual for the complete list of the VPU’s decoding/encoding capabilities. WDOG Watchdog The Watchdog Timer supports two comp arison points during each counting period. Each of the comparison points is configurable to evoke an interrupt to the Arm core, and a second point evokes an external event on the WDOG line. XTAL OSC24M The 24 MHz clock source is an external crystal that acts as one of two main clock sources to the chip. The OSC24M is used as the source clock for subsystem PLLs. OSC24M can be turned off by the System Control Unit (SCU) during sleep mode. XTAL OSC32K The 32 KHz clock source is an external crystal that is one of two main clock sources to the chip. The OSC32K is intended to be always on and is distributed by the SCU to modules in the chip.

Electrical characteristics

i.MX 8DualX Automotive and Infotainment Applications Processors, Rev. 3, 05/2020 NXP Semiconductors 15

4 Electrical characteristics

This section provides the device and module-level electrical characteristics for these processors.

4.1 Chip-level conditions

This section provides the device-level electrical characteristics for the SoC. See the following table for a quick reference to the individual tables and sections.

4.1.1 Absolute Maximum Ratings

Stresses beyond those listed under Table 7 may affect reliability or cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated in the “Operating ranges” or other parameter tables is not implied. Exposure to absolute-maximum-rated conditions for extended periods will affect device reliability. Table 6. Chip-level conditions Table 7. Absolute maximum ratings

i.MX 8DualX Automotive and Infotainment Applications Processors, Rev. 3, 05/2020 NXP Semiconductors16 IO Supply for GPIO Type 1.8V IO Single supply VDD_ADC_1P8 -0.5 2.1 V VDD_ADC_DIG_1P8 VDD_ANA0_1P8 (IO, analog,OSC SCU) VDD_ANA1_1P8 (IO, analog,OSC SCU) VDD_DDR_PLL_1P8 (memory PLLs) VDD_MIPI_1P8 (PHY, GPIO) VDD_MIPI_CSI_DIG_1P8 (PHY , GPIO) VDD_PCIE_1P8 (PHY) VDD_USB_1P8 (PHY, GPIO) IO Supply for GPIO Type 1.8 / 2.5 / 3.3V IO Tri-voltage Supply VDD_ENET0_VSELECT_1P8_2P5_3P3 -0.3 3.8 V VDD_ENET0_1P8_2P5_3P3 VDD_ESAI_SPDIF_1P8_2P5_3P3 IO Supply for GPIO Type 1.8 / 3.3V IO Dual Voltage Supply VDD_CAN_UART_1P8_3P3 -0.3 3.8 V VDD_CSI_1P8_3P3 VDD_EMMC0_1P8_3P3 VDD_EMMC0_VSELECT_1P8_3P3 VDD_ENET_MDIO_1P8_3P3 VDD_PCIE_DIG_1P8_3P3 VDD_QSPI0A_1P8_3P3 VDD_QSPI0B_1P8_3P3 VDD_SPI_MCLK_UART_1P8_3P3 VDD_SPI_SAI_1P8_3P3 VDD_TMPR_CSI_1P8_3P3 VDD_USB_3P3 (PHY & GPIO) VDD_USDHC1_1P8_3P3 VDD_USDHC1_VSELECT_1P8_3P3 SNVS Coin Cell VDD_SNVS_4P2 -0.3 4.3 V USB VBUS (OTG1) USB_OTG1_VBUS -0.3 5.5 V I/O Voltage for USB Drivers USB_OTG1_DP/USB_OTG1_DN -0.3 3.63 V I/O Voltage for ADC ADC_IN x -0.1 2.1 V Vin/Vout input/output voltage range (GPIO Type Pins) Vin/Vout -0.3 OVDD+0.3 1 V Table 7. Absolute maximum ratings (continued)

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4.1.2 Thermal resistance

4.1.2.1 FCPBGA package thermal resistance

This table provides the FCPBGA package thermal resistance data. Vin/Vout input/output voltage range (DDR pins) Vin/Vout -0.3 OVDD+0.4 1,2 V ESD immunity (HBM). Vesd_HBMX — 1000 V ESD immunity (CDM). Vesd_CDM — 250 V Storage temperature range Tstorage -55 150 °C 1 OVDD is the I/O supply voltage. 2 The absolute maximum voltage includes an allowance for 400 mV of overshoot on the I/O pins. Per JEDEC standard the allowed signal overshoot must be derated if NVCC_DRAM exceeds 1.575 V. Table 8. FCPBGA package thermal resistance data 1 Thermal test board meets JEDEC specification for this package (JESD51-9). to predict the performance of a package in an application-specific environment. temperature at the package top side dead center.

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4.1.3 Operating Ranges

The following table provides the operating ranges of these processors. Table 9. Operating ranges1

i.MX 8DualX Automotive and Infotainment Applications Processors, Rev. 3, 05/2020 NXP Semiconductors 19 VDD_CAN_UART_1P8_3P3 VDD_CSI_1P8_3P3 VDD_EMMC0_1P8_3P3 VDD_EMMC0_VSELECT_1P8_3P3 VDD_ENET_MDIO_1P8_3P3 VDD_PCIE_DIG_1P8_3P3 VDD_QSPI0A_1P8_3P3 VDD_QSPI0B_1P8_3P3 VDD_SPI_MCLK_UART_1P8_3P3 VDD_SPI_SAI_1P8_3P3 VDD_TMPR_CSI_1P8_3P3 VDD_USDHC1_1P8_3P3 VDD_USDHC1_VSELECT_1P8_3P3 Power supplies of GPIO supporting both 1.8V or 3.3V 1.8V 1.65 1.80 1.95 V When VDD_USDHC1_1P8_3P 3 is used to support an SD card, then it shall be on a dedicated 1.8V/3.3V regulator. When VDD_TMPR_CSI_1P8_ 3P3 is used as a GPIO it can be connected to the 1.8/3.3V supply. VDDs of this list targeting 1.8V can share 1.8V regulator of 1.8V only VDDs VDDs of this list targeting 3.3V can share 3.3V regulator of 3.3V only VDDs 3.3V 3.00 3.30 3.60 V — VDD_ENET0_1P8_2P5_3P3 VDD_ENET0_VSELECT_1P8_2P5_3P3 VDD_ESAI_SPDIF_1P8_2P5_3P3 Power supplies of ethernet IOs 1.8V 1.65 1.80 1.95 V — 2.5V 2.40 2.50 2.60 V — 3.3V 3.00 3.30 3.60 V — VDD_SNVS_4P2 Power supply of SNVS N/A 2.80 3.30 4.20 V It can be supplied by a backup battery: a coin cell or a super cap. Output of embedded LDOs VDD_PCIE_LDO_1P0_CAP 1.0V output of embedded LDOs N/A — 1.00 — V — VDD_SNVS_LDO_1P8_CAP 1.8V output of SNVS embedded LDO N/A — 1.80 — V — Power supplies that shall be connected to output of an embedded LDO VDD_TMPR_CSI_1P8_3P3 — N/A — 1.80 — V Shall be connected to VDD_SNVS_LDO_1P8_ CAP when used as a tamper pin. In CSI mode use an external 1.8 V supply. In this case, follow the 1.8 V I/O specification above. Table 9. Operating ranges1 (continued)

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4.1.4 External clock sources

Each processor has two external input system clocks: a low frequency (RTC_XTALI) and a high frequency (XTALI). The RTC_XTALI is used for real time functions. It supplies the clock for real time clock operation and for slow-system and watchdog counters. The clock input can be connected to either an external oscillator or a crystal using the internal oscillator amplifier. The system clock input XTALI is used to generate the main system clock. It supplies the PLLs and other peripherals. The system clock input requires a crystal using the internal oscillator amplifier. The PCIe oscillator can be sourced internally or input to the chip. In both cases, it is a 100 MHz nominal clock using HCSL signaling to provide the PCIe reference clock. The following table shows the interface frequency requirements. VDD_USB_OTG_1P0 — N/A — 1.00 — V Shall be externally connected to VDD_USB_SS3_LDO_1 P0_CAP Junction temperature Junction temperature — — -40 — 125 °C— 1 Voltage ranges are defined to group as many supplies as possible. Some supplies may have a wider range than listed here. 2 VDD_A35 and VDD_GPU can be combined with one power supply. 3 During low power state (see Section 4.1.6, “Low power mode supply currents"), this voltage can be dropped to 0.8 V +/- 3% for retention. Table 10. External Input Clock Frequency 1 External oscillator or a crystal with internal oscillator amplifier. development guide for this device. 3 Recommended nominal frequency 32.768 kHz. 4 Fundamental frequency crystal with internal oscillator amplifier. 5 If using an external clock instead of the internal clock source, an HCSL-compatible clock is required.

i.MX 8DualX Automotive and Infotainment Applications Processors, Rev. 3, 05/2020 NXP Semiconductors 21 The typical values shown in Table 10 are required for use with NXP board support packages (BSPs) to ensure precise time keeping and USB operations.

4.1.5 Maximum Supply Currents

Some of the numbers shown in this table are based on the companion regulator limits and not actual use cases. Work is in progress to provide use case–based numbers in future data sheet releases. Table 11. Maximum supply currents

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4.1.6 Low power mode supply currents

The following table shows the current core consumption (not including I/O) in selected low power modes. VDD_SPI_SAI_1P8_3P3 48 mA VDD_TMPR_CSI_1P8_3P3 30 mA VDD_USDHC1_1P8_3P3 30 mA VDD_USDHC1_VSELECT_1P8_3P3 20 mA VDD_ADC_1P8 5 mA VDD_USB_OTG_1P0 36 mA Shall be externally connected to VDD_USB_SS3_LDO_1P0_CAP VDD_USB_1P8 175 mA VDD_USB_3P3 40 mA VDD_PCIE_1P8 255 mA VDD_SNVS_4P2 2 5 mA Start-up current 1 VDD_A35 and VDD_GPU can be combined with one power supply. 2 Under normal operating conditions, the maximum current on VDD_SNVS_4P2 is shown Table 11. During initial power on, VDD_SNVS_4P2 can draw up to 5 mA if the supply is capable of sourcing that current. If less than 5 mA is available, the VDD_SNVS_LDO_1P8_CAP charge time will increase. Table 12. i.MX 8DualX Key State (KSx) power consumption 1 Maximum values are for 25 °C Tambient . DRAM in self-refresh, associated I/O’s OFF. 32K running, 24M, PLLs and ring oscillators OFF. 2 0.8 V nominal—voltage specification under this case is ± 3%. 3 Maximum values are for 125 °C Tjunction . Leakage test, not intended as a customer use case. Overdrive conditions set, memories active, all sub-systems powered ON. Table 11. Maximum supply currents (continued)

i.MX 8DualX Automotive and Infotainment Applications Processors, Rev. 3, 05/2020 NXP Semiconductors 23 4.1.7 USB 2.0 PHY typical current consumption in Power-Down mode In power down mode, everything is powered down, including the VBUS valid detectors, typical condition. The following table shows the USB interface typical current consumption in Power-Down mode. Table 13. USB 2.0 PHY typical current consumption in Power-Down Mode

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4.2 Power supplies requir ements and restrictions

The system design must comply with power-up sequence, power-down sequence, and steady state guidelines as described in this section to ensure the reliable operation of the device. Any deviation from these sequences may result in the following situations:

• Excessive current during power-up phase
• Prevention of the device from booting
• Irreversible damage to the processor

4.2.1 Power-up sequence

The device has the following power-up sequence requirements:

• Supply group 0 (SNVS) must be powered first. It is expected that group 0 will typically remain always on after the first power-on.
• Supply group 1 (MAIN and SC U) and group 0 must both be powered to their nominal values prior to boot. They must power up after or simultaneously with group 0.
• Supply group 2 (I/O’s and DDR inte rface) consists of those modules required to start the boot process by accessing external storage devices. These must be fully powered prior to POR release if booting from one of these supplies interfaces. They must power up after or simultaneously with group 1.
• Supply group 3 consists of the remaining portions of the SoC. This includes nonboot I/O voltages and supplies for the major computational units. These can be sequenced in any order and as required to perform the desired functions for the intended application. They must power up after or simultaneously with group 2. NOTE The definition of “power-up” refers to a stable voltage operating within the range defined in Table 9. This should be taken into consideration, along with the different capacitive loading on each rail, if considering simultaneous switch-on of the different supply groups.

4.2.2 Power-down sequence

The device processor has the following power-down sequence requirements:

• Supply group 0 must be turned off last, after all other supplies.
• Supply group 1 can be turned off just prior to group 0. All remaining supplies can be turned off prior to group 1.

i.MX 8DualX Automotive and Infotainment Applications Processors, Rev. 3, 05/2020 NXP Semiconductors 25 NOTE When switching off supply group 0 (SNVS), VDD_SNVS_4P2 must be discharged below 2.4 V before starting the next power-up sequence to ensure correct operation. This will generate a full SNVS reset, allowing correct operation on the next power-up sequence. This would also be a requirement to clear any security related flag as a result of an SNVS voltage drop, when tamper features are enabled.

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26 NXP Semiconductors

4.2.3 Power Supplies Usage

The following table shows the power supplies usage by group. Table 14. Power supplies usage CSI/SAI, it is tied to I/O supply. 2 VDD_A35 and VDD_GPU can be combined with one power supply.

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4.3 PLL electrical characteristics

4.3.1 PLLs of subsystems

i.MX 8DualX embeds a large number of PLLs to address clocking requirements of the various subsystems. These PLLs are controlled through the SCU and not directly by Cortex-A or Cortex-M4F processors. A software API shall be used by those processors to access the PLL settings. Additional PLLs are specific to high-performance interfaces. These are described in the following sections. This table summarizes the PLLs controlled by the SCU. Table 15. PLLs controlled by SCU

• Nominal: 9002 GPU PLL #0: subsystem 24 648 1344 • Nominal: 744 3 MHz PLL #1: shaders 24 648 1344 • Nominal: 744 3 MHz DRC (DRAM Controller) Subsystem 24 1250 2500 • LPDDR4: 2400
• DDR3L: 18664 MHz DB (DRAM Block) Subsystem 24 650 1300 1200 MHz Display Controller 0 PLL #0: subsystem 24 650 1300 800 MHz PLL #1: display clock #0 24 650 1300 User-configurable MHz PLL #2: display clock #1 24 650 1300 User-configurable MHz Imaging Subsystem 24 650 1300 1200 MHz ADMA

5 PLL #0: subsystem 24 650 1300 1280 MHz

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4.3.2 PLLs dedicated to specific interfaces

The following sections cover PLLs used for specific interfaces. Clock output frequency and clock output range refer to the output of the PLL. Additional clock dividers may be on the output path to divide the output frequency down to the targeted frequency. See the related sections in the reference manual for settings of these clock dividers.

4.3.2.1 Ethernet PLL

This PLL is controlled by the SCU. 4.3.2.2 USB 2.0 B PLLs USB 2.0 B has one PLL. It is embedded in the USB 2.0 OTG PHY B. The table below describes the PLL embedded in the USBOTG PHY. MIPI-DSI Subsystem 24 650 1300 864 MHz MIPI-CSI Subsystem 24 650 1300 720 MHz SCU (System Controller Unit) Subsystem 24 650 1300 1056 MHz 1 Operating frequencies are limited to only those supported by the SCFW. 2 1200 MHz is used to generate the max frequency points, and 1000 MHz for the typical frequency point. See Table 9 to get associated voltages. 3 744 MHz is used to generate the 372 MHz operating point for both the GPU core and shaders. 4 2400 MHz is used to generate 1200 MHz when in LPDDR4 mode. 1866 MHz is used to generate 933 MHz when in DDR3L mode. See Table 9 to get associated voltages. 5 The audio PLLs support on-the-fly frequency changes for clock synchronization applications, 25 Hz steps, up to a maximum change of +/- 250 KHz is supported. Table 16. Ethernet PLL Table 17. USB 2.0 PLL embedded in USBOTG PHY Table 15. PLLs controlled by SCU (continued)

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4.3.2.4 PCIe PLLs

The PCIe interface has three PLLs:

• One is used to generate the single, common 100 MHz reference clock to each lane
• One Transmit and one Receive PLL in one lane The table below shows the characteristics for the reference clock PLL. The table below shows characteristics of the TX and RX PLLs used in each lane.

4.3.2.5 MIPI-DSI/LVDS combo PLL

The table below shows characteristics of the PLL embedded in the MIPI-DSI/LVDS combo PHY. Table 18. USB 2.0 OTG PLLs Table 19. PCIe reference clock PLLs Table 20. PCIe Transmit and Receive PLLs

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4.4 On-chip oscillators

4.4.1 OSC24M

This block integrates trimmable internal loading capacitors and driving circuitry. When combined with a suitable 24 MHz external quartz element, it can generate a low-jitter clock. The oscillator is powered from VDD_ANA1_1P8. The internal loading capacitors are trimmable to provide fine adjustment of the 24 MHz oscillation frequency. It is expected that customers burn appropriate trim values for the selected crystal and board parasitics. Figure 2. Normal Crystal Oscillation mode Table 22. Crystal specifications respective standard documents.

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4.4.2 OSC32K

This block implements an internal amplifier, trimmable load capacitors and a bias network that when combined with a suitable quartz crystal implements a low power oscillator. Additionally, if the clock monitor determines that the 32KHz oscillation is not present, then the source of the 32 KHz clock will automatically switch to the internal relaxation oscillator of lesser frequency accuracy. CAUTION The internal ring oscillator is not meant to be used in customer applications, due to gross frequency variation over wafer processing, temperature, and supply voltage. These variations will cause timing issues to many different circuits that use the internal ring oscillator for reference; and, if this timing is critical, application issues will occur. To prevent application issues, it is recommended to only use an external crystal or an accurate external clock. If this recommendation is not followed, NXP cannot guarantee full compliance of any circuit using this clock. The OSC32K runs from VDD_SNVS_LDO_1P8_CAP, which is regulated from VDD_SNVS. The target battery/voltage range is 2.8 to 4.2 V for VDD_SNVS, with a regulated output of approximately 1.75 V . 2 Cload is the specification of the quartz element, not for the capacitors coupled to the quartz element. Table 23. OSC32K main characteristics the crystal selected. 32.0 KHz is also supported.

• 32K internal oscillator mode: 10 μA — These values are for typical process and room temperature. Values will be updated after silicon characterization. Bias resistor — 200 M Ω — This the integrated bias resistor that sets the amplifier into a high gain state. Any leakage through the ESD network, external board leakage, or even a scope probe that is significant relative to this value will debias the amplifier. The debiasing will result in low gain, and will impact the circuit's ability to start up and maintain oscillations.

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4.5 I/O DC Parameters

This section includes the DC parameters of the following I/O types:

• XTALI and RTC_XTALI (clock inputs) DC parameters
• General Purpose I/O (GPIO) DC parameters NOTE The term ‘OVDD’ in this section refers to the associated supply rail of an input or output.

Figure 3. Circuit for Parameters Voh and Vol for I/O Cells Table 24. External input clock for OSC32K 1 The external clock is fed into the chip from the RTC_XTALI pin; the RTC_XTALO pin should be left floating. 2 The parameter specified here is a peak-to-peak value and VIH/VIL specifications do not apply. 3 The voltage applied on RTC_XTALI must be within the range of VSS to VDD_SNVS_LDO_1P8_CAP. 4 The rise/fall time of the applied clock are not strictly confined. Table 23. OSC32K main characteristics (continued)

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4.5.1 XTALI and RTC_XTALI (Clock Inputs) DC Parameters

For RTC_XTALI, VIH/VIL specifications do not apply. The high and low levels of the applied clock on this pin are not strictly defined, as long as the input’s peak-to-peak amplitude meet the requirements and the input’s voltage value does not exceed the limits.

4.5.2 General-purpose I/O (GPIO) DC parameters

4.5.2.1 Tri-voltage GPIO DC parameters

The following tables show tri-voltage 1.8V , 2.5 V , and 3.3 V DC parameters, respectively, for GPIO pads. These parameters are guaranteed per the operating ranges in Table 9, unless otherwise noted. Table 25. Tri-voltage 1.8 V GPIO DC parameters1 1 For tri-voltage I/O, the associated IOMUXD compensation control register PSW_OVR and COMP bits must be set correctly. PSW_OVR = 0b1 and COMP = 0b010. level through to the target DC level, VIL or VIH. Monotonic input transition time is from 0.1 ns to 1 ns.

i.MX 8DualX Automotive and Infotainment Applications Processors, Rev. 3, 05/2020 NXP Semiconductors34 Table 26. Tri-voltage 2.5 V GPIO DC parameters1 1 For tri-voltage I/O, the associated IOMUXD compensation control register PSW_OVR and COMP bits must be set correctly. PSW_OVR = 0b1 and COMP = 0b010. level through to the target DC level, VIL or VIH. Monotonic input transition time is from 0.1 ns to 1 ns. Table 27. Tri-voltage 3.3 V GPIO DC parameters1

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4.5.2.2 Dual-voltage GPIO DC parameters

The following two tables show dual-voltage 1.8 V and 3.3 V DC parameters, respectively, for GPIO pads. These parameters are guaranteed per the operating ranges in Table 9, unless otherwise noted. Pull-up resistance RPU V IN=0V (Pullup Resistor) PUN = "L", PDN = "H" 10 100 k Ω Pull-down resistance R DOWN VIN=OVDD( Pulldown Resistor) PUN = "H", PDN = "L" 10 100 k Ω Input current (no PU/PD) IIN VI = 0, VI = OVDD PUN = "H", PDN = "H" -2 2 μA 1 For tri-voltage I/O, the associated IOMUXD compensation control register PSW_OVR and COMP bits must be set correctly. For 1.8 or 3.3 V operation, the SCFW API must be used to set PSW_OVR = 0b0 and COMP=0b000. For 2.5 V operation, PSW_OVR = 0b1 and COMP = 0b010. 2 Overshoot and undershoot conditions (transitions above OVDD and below GND) on switching pads must be held below 0.3 V, and the duration of the overshoot/undershoot must not exceed 10% of the system clock cycle. Overshoot/ undershoot must be controlled through printed circuit board layout, transmission line impedance matching, signal line termination, or other methods. Noncompliance to this specification may affect device reliability or cause permanent damage to the device. (OVDD is the I/O Supply.) 3 DSE is the setting of the PDRV register. High Drive mode recommended for 3v3 and 2v5 modes. Low Drive mode is recommended for 1v8 mode. 4 To maintain a valid level, the transition edge of the input must sustain a constant slew rate (monotonic) from the current DC level through to the target DC level, VIL or VIH. Monotonic input transition time is from 0.1 ns to 1 ns. Table 28. Dual-voltage 1.8 V GPIO DC parameters Table 27. Tri-voltage 3.3 V GPIO DC parameters1 (continued)

i.MX 8DualX Automotive and Infotainment Applications Processors, Rev. 3, 05/2020 NXP Semiconductors36 Pull-down resistance R down Vin=OVDD( Pulldown Resistor) PUN = "H", PDN = "L" 15 50 k Ω Input current (no PU/PD) I IN VI = 0, VI = OVDD PUN = "H", PDN = "H" -1 1 μA 1 Overshoot and undershoot conditions (transitions above OVDD and below GND) on switching pads must be held below 0.3 V, and the duration of the overshoot/undershoot must not exceed 10% of the system clock cycle. Overshoot/undershoot must be controlled through printed circuit board layout, transmission line impedance matching, signal line termination, or other methods. Noncompliance to this specification may affect device reliability or cause permanent damage to the device. (OVDD is the IO Supply.) 2 DSE is the setting of the PDRV register. High Drive mode is recommended for SD standard (3v3 mode) and MMC standard (1v8/3v3 modes). Low Drive mode is recommended for SD standard (1v8 mode). 3 To maintain a valid level, the transition edge of the input must sustain a constant slew rate (monotonic) from the current DC level through to the target DC level, Vil or Vih. Monotonic input transition time is from 0.1 ns to 1 ns. Table 29. Dual-voltage 3.3 V GPIO DC parameters controlled through printed circuit board layout, transmission line impedance matching, signal line termination, or other methods. (1v8/3v3 modes). Low Drive mode is recommended for SD standard (1v8 mode). level through to the target DC level, VIL or VIH. Monotonic input transition time is from 0.1 ns to 1 ns. Table 28. Dual-voltage 1.8 V GPIO DC parameters (continued)

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4.5.2.3 Single-voltage GPIO DC parameters

Table 30 and Table 31 show single-voltage 1.8 V and 3.3 V DC parameters, respectively, for GPIO pads. These parameters are guaranteed per the operating ranges in Table 9 unless otherwise noted. Table 30. Single-voltage 1.8 V GPIO DC parameters 1 As programmed in the associated IOMUX (DSE field) register. level through to the target DC level, VIL or VIH. Monotonic input transition time is from 0.1 ns to 1 ns.

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4.5.3 DDR I/O DC parameters

4.5.3.1 LPDDR4 mode I/O DC parameters

These parameters are guaranteed per the operating ranges in Table 9 unless otherwise noted. Table 31. Single-voltage 3.3 V GPIO DC parameters 1 As programmed in the associated IOMUX (DSE field) register. level through to the target DC level, VIL or VIH. Monotonic input transition time is from 0.1 ns to 1 ns.

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4.5.3.2 DDR3L mode I/O DC parameters

Table 32. LPDDR4 DC parameters 0.8 V-ns; maximum undershoot area below VSS/VSSQ 0.8 V-ns. Table 33. SSTL DDR3L DC parameters 0.8 V-ns; maximum undershoot area below VSS/VSSQ 0.8 V-ns.

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4.6 I/O AC Parameters

The GPIO and DDR I/O load circuit and output transition time waveforms are shown in Figure 4 and Figure 5. Figure 4. Load Circuit for Output Figure 5. Output Transition Time Waveform

4.6.1 General Purpose I/O (GPIO) AC Parameters

Table 34. General Purpose I/O AC Parameters1

1.8 V application2

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4.7 Output Buffer Impedance Parameters

This section defines the I/O impedance parameters for the following I/O types:

• General Purpose I/O (GPI O) output buffer impedance
• Double Data Rate I/O (DDR) output buff er impedance for LPDDR4 and DDR3L modes NOTE GPIO and DDR I/O output driver impedance is measured with “long” transmission line of impedance Ztl attached to I/O pad and incident wave launched into transmission line. Rpu/Rpd and Ztl form a voltage divider that defines specific voltage of incident wave relative to OVDD. Output driver impedance is calculated from this voltage divider (see Figure 6). 3 All timing specifications in 3.3 V application are valid for Type B driver only. In Type A, the driver is functional.

Table 35. Dynamic input characteristics 1 For all supply ranges of operation. 2 The dynamic input characteristic specifications are applicable for the digital bidirectional cells.

i.MX 8DualX Automotive and Infotainment Applications Processors, Rev. 3, 05/2020 NXP Semiconductors42 Figure 6. Impedance Matching Load for Measurement

4.7.1 GPIO output buffer impedance

4.7.1.1 Tri-voltage GP IO output buffer impedance

Table 36. Tri-voltage 1.8 V GPIO output impedance DC parameters

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4.7.1.2 Dual-voltage GPIO output buffer impedance

1 As programmed in the associated IOMUX (PDRV field) register. Table 37. Tri-voltage 2.5 V GPIO output impedance DC parameters 1 As programmed in the associated IOMUX (PDRV field) register. Table 38. Tri-voltage 3.3 V GPIO output impedance DC parameters 1 As programmed in the associated IOMUX (PDRV field) register. Table 39. Dual-voltage 1.8 V GPIO output impedance DC parameters 1 ‘As programmed in the associated IOMUX (PDRV field) register. Table 40. Dual-voltage 3.3 V GPIO output impedance DC parameters 1 As programmed in the associated IOMUX (PDRV field) register.

i.MX 8DualX Automotive and Infotainment Applications Processors, Rev. 3, 05/2020 NXP Semiconductors44 4.7.1.3 Single-voltage 1.8 V GPIO output buffer drive strength The following table shows the GPIO output buffer drive strength (OVDD 1.8 V). 4.7.1.4 Single-voltage 3.3 V GPIO output buffer drive strength The following table shows the GPIO output buffer drive strength (OVDD 3.3 V). Table 41. Single-voltage GPIO 1.8 V output impedance DC parameters 1 As programmed in the associated IOMUX (DSE field) register. Table 42. Single-voltage GPIO 3.3 V output impedance DC parameters 1 As programmed in the associated IOMUX (DSE field) register.

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4.7.2 DDR I/O output buffer impedance

The following tables show DDR3L and LPDDR4 I/O output buffer impedance of the device. The ZQ Calibration cell uses a single register (ZQnPR0) to determine the target output buffer impedances of the pull-up driver and the pull-down driver, as well as the target on-die termination impedance. The resulting calibration setting is then applied to all DDR pads within the PHY complex. Table 43 and Table 45 show, respectively, the recommended ZQnPR0 field settings for the DDR3L and LPDDR4 I/Os to achieve the desired output buffer impedances. Table 44 and Table 46 show, respectively, the recommended ZQnPR0 field settings for the DDR3L and LPDDR4 I/Os to achieve the desired ODT settings. Table 43. LPDDR4 I/O output buffer impedance Table 44. LPDDR4 I/O on-die termination impedance Table 45. DDR3L I/O output buffer impedance

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• Output driver impedance is contro lled across PVTs using ZQ calibration procedure.
• Calibration is done against 240 Ω external reference resistor.
• Output driver impedance deviatio n (calibration accuracy) is ±5% (max/min impedance) across PVTs.

4.8 System Modules Timing

This section contains the timing and electrical parameters for the modules in each processor.

4.8.1 Reset Timing Parameters

The following figure shows the reset timing and Table 47 lists the timing parameters. Figure 7. Reset timing diagram Table 46. DDR3L I/O on-die termination impedance Table 47. Reset timing parameters

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4.8.2 WDOG reset timing parameters

The following figure shows the WDOG reset timing and Table 48 lists the timing parameters. Figure 8. SCU_WDOG_OUT timing diagram XTALOSC_RTC_XTALI is approximately 32 kHz. XTALOSC_RTC_XTALI cycle is one period or approximately 30 μs.

4.8.3 DDR SDRAM–specific parameters (LPDDR4 and DDR3L)

compliant LPDDR4 memory and with JEDEC JESD79-3-1 DDR3L compliant with DDR3L memory. documents and are not reprinted here. bulk/decoupling capacitors and DDR trace routing between the processor and the selected DDR memory. Table 48. WDOG1_B timing parameters

i.MX 8DualX Automotive and Infotainment Applications Processors, Rev. 3, 05/2020 NXP Semiconductors48 https://www.nxp.com/products/processors-and-microcontrollers/applications-processors/i.mx-applicatio ns-processors/i.mx-8-processors:IMX8-SERIES . Processors that demonstrate full DDR performance on NXP validated designs, but do not function on customer designs, are not considered marginal parts. A report detailing how the returned part behaved on an NXP validated system will be provided to the customer as closure to a customer’s reported DDR issue. Customers bear the responsibility of properly designing the Printed Circuit Board, correctly simulating and modeling the designed DDR system, and validating the system under all expected operating conditions (temperatures, voltages) prior to releasing their product to market.

4.8.3.1 Clock/data/command/ address pin allocations

These processors uses generic names for clock, data and command address bus (DCF—DRAM controller functions); the following table provides mapping of clock, data and command address signals for LPDDR4 and DDR3L modes. Table 49. i.MX 8 Family DRAM controller supported SDRAM configurations 1 Only 16-bit external memory configurations are supported. Table 50. i.MX 8DualX DRAM controller supported SDRAM configurations Table 51. Clock, data, and command address signals for LPDDR4 and DDR3L modes

i.MX 8DualX Automotive and Infotainment Applications Processors, Rev. 3, 05/2020 NXP Semiconductors 49 DDR_CK1_P CK_t_B DDR_CK1_N CK_c_B DDR_DQ_[15:0] DQ[15:0]_A DDR_DQS_N_[1:0] DQS_N_[1:0] DDR_DQS_P_[1:0] DQS_P_[1:0] DDR_DM_[1:0] DM_[1:0] DDR_DCF00 CA2_A DDR_DCF01 CA4_A DDR_DCF03 CA5_A DDR_DCF04 DDR_DCF05 DDR_DCF07 DDR_DCF08 CA3_A DDR_DCF09 ODT_CA_A DDR_DCF10 CS0_A DDR_DCF11 CA0_A DDR_DCF12 CS1_A DDR_DCF14 CKE0_A DDR_DCF15 CKE1_A DDR_DCF16 CA1_A DDR_DCF17 CA4_B DDR_DCF18 RESET_N DDR_DCF19 CA5_B DDR_DCF20 DDR_DCF21 DDR_DCF22 DDR_DCF23 DDR_DCF24 DDR_DCF25 ODT_CA_B DDR_DCF26 CA3_B DDR_DCF27 CA0_B DDR_DCF28 CS0_B DDR_DCF29 CS1_B Table 51. Clock, data, and command address signals for LPDDR4 and DDR3L modes (continued)

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4.9 General-Purpose Media Interface (GPMI) Timing

The GPMI controller is a flexible interface NAND Flash controller with 8-bit data width, up to 400 MB/s I/O speed, and individual chip select. It supports Asynchronous Timing mode, Source Synchronous Timing mode, and Toggle Timing mode, as described in the following subsections. DDR_DCF30 CKE0_B DDR_DCF31 CKE1_B DDR_DCF32 CA1_B DDR_DCF33 CA2_B

i.MX 8DualX Automotive and Infotainment Applications Processors, Rev. 3, 05/2020 NXP Semiconductors 53 In EDO mode (Figure 13), NF16/NF17 are different from the definition in non-EDO mode (Figure 12). They are called tREA/tRHOH (NAND_RE_B access time/NAND_RE_B HIGH to output hold). The typical value for them are 16 ns (max for tREA)/15 ns (min for tRHOH) at 50 MB/s EDO mode. In EDO mode, GPMI will sample NAND_DATAxx at rising edge of delayed NAND_RE_B provided by an internal DPLL. The delay value can be controlled by GPMI_CTRL1.RDN_DELAY (see the GPMI chapter of the device reference manual. The typical value of this control register is 0x8 at 50 MT/s EDO mode. However, if the board delay is large enough and cannot be ignored, the delay value should be made larger to compensate the board delay. NF16 Data setup on read tDSR — (DS × T -0.67)/18.38 [see 5,6]n s NF17 Data hold on read tDHR 0.82/11.83 [see 5,6]— n s

1 The GPMI asynchronous mode output timing can be controlled by the module’s internal registers

HW_GPMI_TIMING0_ADDRESS_SETUP , HW_GPMI_TIMING0_DATA_SETUP, and HW_GPMI_TIMING0_DATA_HOLD. This AC timing depends on these registers settings. In the table, AS/DS/DH represents each of these settings. 2 AS minimum value can be 0, while DS/DH minimum value is 1. 3 T = GPMI clock period -0.075ns (half of maximum p-p jitter). 4 NF12 is met automatically by the design. 5 Non-EDO mode.

6 EDO mode, GPMI clock ≈ 100 MHz

(AS=DS=DH=1, GPMI_CTL1 [RDN_DELAY] = 8, GPMI_CTL1 [HALF_PERIOD] = 0). Table 52. Asynchronous Mode Timing Parameters1 (continued)

i.MX 8DualX Automotive and Infotainment Applications Processors, Rev. 3, 05/2020 NXP Semiconductors54 4.9.2 GPMI Source Synchronous mode AC timing (ONFI 2.x compatible) The following figure shows the write and read timing of Source Synchronous mode. Figure 14. Source Synchronous Mode Command and Address Timing Diagram

i.MX 8DualX Automotive and Infotainment Applications Processors, Rev. 3, 05/2020 NXP Semiconductors56 Figure 17. NAND_DQS/NAND_DQ Read Valid Window Synchronous mode, the typical value of tDQSQ is 0.85 ns (max) and 1 ns (max) for tQHS at 200 MB/s. be made larger to compensate the board delay. Table 53. Source Synchronous Mode Timing Parameters1

1 The GPMI source synchronous mode output timing can be controlled by the module’s internal registers

depends on these registers settings. In the table, CE_DELAY/PRE_DELAY/POST_DELAY represents each of these settings. 2 T = tCK (GPMI clock period) -0.075ns (half of maximum p-p jitter).

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4.9.3.1 Command and address timing

ONFI 3.2 mode command and address timing is the same as ONFI 1.0 compatible Async mode AC timing. See Section 4.9.1, “GPMI Asynchronous mode AC timing (ONFI 1.0 compatible)",” for details.

4.9.3.2 Read and write timing

ONFI 3.2 mode read and write timing is the same as Toggle mode AC timing. See Section 4.9.4, “Toggle mode AC Timing",” for details.

4.9.4 Toggle mode AC Timing

4.9.4.1 Command and address timing

Toggle mode command and address timing is the same as ONFI 1.0 compatible Asynchronous mode AC timing. See Section 4.9.1, “GPMI Asynchronous mode AC timing (ONFI 1.0 compatible)",” for details.

4.9.4.2 Read and write timing

Figure 18. Toggle mode data write timing

i.MX 8DualX Automotive and Infotainment Applications Processors, Rev. 3, 05/2020 NXP Semiconductors58 Figure 19. Toggle mode data read timing Table 54. Toggle mode timing parameters1

i.MX 8DualX Automotive and Infotainment Applications Processors, Rev. 3, 05/2020 NXP Semiconductors 59 For DDR Toggle mode, Figure 19 shows the timing diagram of NAND_DQS/NAND_DATAxx read valid window. The typical value of tDQSQ is 1.4 ns (max) and 1.4 ns (max) for tQHS at 133 MB/s. GPMI will sample NAND_DATA[7:0] at both rising and falling edge of an delayed NAND_DQS signal, which is provided by an internal DPLL. The delay value of this register can be controlled by GPMI register GPMI_READ_DDR_DLL_CTRL.SLV_DLY_TARGET (see the GPMI chapter of the device reference manual. Generally, the typical delay value is equal to 0x7 which means 1/4 clock cycle delay expected. But if the board delay is big enough and cannot be ignored, the delay value should be made larger to compensate the board delay.

4.10 External Peripheral Interface Parameters

The following subsections provide information on external peripheral interfaces.

4.10.1 LPSPI timing parameters

All LPSPI interfaces do not have the same maximum serial clock frequency. There are two groups. LPSPI interfaces which can operate at 60 MHz in Master mode and 40 MHz in Slave mode and the other group where interfaces operate at 40 MHz in Master mode and 20 MHz in Slave mode. The same performance is achieved at 1.8 V and 3.3 V unless otherwise stated. NF28 Data write setup tDS 6 0.25 × tCK - 0.32 — ns NF29 Data write hold tDH 6 0.25 × tCK - 0.79 — ns NF30 NAND_DQS/NAND_DQ read setup skew tDQSQ 7 —3 . 1 8 NF31 NAND_DQS/NAND_DQ read hold skew tQHS 7 —3 . 2 7

1 The GPMI toggle mode output timing can be controlled by the module’s internal registers

HW_GPMI_TIMING0_ADDRESS_SETUP, HW_GPMI_TIMING0_DATA_SETUP , and HW_GPMI_TIMING0_DATA_HOLD. This AC timing depends on these registers settings. In the table, AS/DS/DH represents each of these settings. 2 AS minimum value can be 0, while DS/DH minimum value is 1. 3 T = tCK (GPMI clock period) -0.075 ns (half of maximum p-p jitter). 4 CE_DELAY represents HW_GPMI_TIMING2[CE_DELAY]. NF18 is guaranteed by the design. Read/Write operation is started with enough time of ALE/CLE assertion to low level.

5 PRE_DELAY+1) ≥ (AS+DS)

6 Shown in Figure 18. 7 Shown in Figure 19. Table 54. Toggle mode timing parameters1 (continued)

i.MX 8DualX Automotive and Infotainment Applications Processors, Rev. 3, 05/2020 NXP Semiconductors60 Below are the LPSPI interfaces and their respective chip selects:

4.10.1.1 LPSPI Master mode

parameters are valid for all modes using appropriate edge of the clock. Figure 20. LPSPI Master mode Table 55. LPSPI interfaces and chip selects

60 MHz in Master mode and 40 MHz in

40 MHz in Master mode and 20 MHz in

Table 56. LPSPI timings—M aster mode at 60 MHz

i.MX 8DualX Automotive and Infotainment Applications Processors, Rev. 3, 05/2020 NXP Semiconductors 61 t4 SPIx_CSy Lag Time (3) FCLK_PERIOD(2) x (SCKPCS + 1) / 2PRESCALE + 3 —n s t5 SPIx_SDO output Delay (CLOAD = 20 pF) — 3 ns t6 SPIx_SDI Setup Time 2 — ns t7 SPIx_SDI Hold Time 2 — ns 1 This timing is controllable through CCR.PCSSCK and TCR.PRESCALE registers. 2 FCLK_PERIOD is the period of the functional clock provided to LPSPI module. Maximum allowed frequency is 240 MHz. 3 This timing is controllable through CCR.SCKPCS and TCR.PRESCALE registers. Table 57. LPSPI timings—M aster mode at 40 MHz 1 This timing is controllable through CCR.PCSSCK and TCR.PRESCALE registers. 2 FCLK_PERIOD is the period of the functional clock provided to LPSPI module. Maximum allowed frequency is 240 MHz. 3 This timing is controllable through CCR.SCKPCS and TCR.PRESCALE registers. Table 56. LPSPI timings—Master mode at 60 MHz (continued)

i.MX 8DualX Automotive and Infotainment Applications Processors, Rev. 3, 05/2020 NXP Semiconductors62 Figure 21. LPSPI Slave mode Table 58. LPSPI timings—Slave mode at 40 MHz Table 59. LPSPI timings—Slave mode at 20 MHz

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4.10.2 Serial audio interfa ce (SAI) timing parameters

The timings and figures in this section are valid for noninverted clock polarity (I2S_TCR2.BCP = 0b0, I2S_RCR2.BCP = 0b0) and non-inverted frame sync polarity (I2S_TCR4.FSP = 0b0, I2S_RCR4.FSP = 0b0). If the polarity of the clock and/or the frame sync have been inverted, all the timings remain valid by inverting the clock signal (SAI_TXC / SAI_RXC) and/or the frame sync (SAI_TXFS / SAI_RXFS) shown in the figures below. The same performance is achieved at both 1.8 V and 3.3 V unless otherwise stated. NOTE SAI0 and SAI1 are transmit/receive capable. SAI2 and SAI3 are receive only.

4.10.2.1 SAI Master Synchronous mode

In this mode, transmitter clock and frame sync are used by both transmitter and receiver (I2S_TCR2.SYNC=0b00, I2S_RCR2.SYNC=0b01). In that case, SAI interface requires only 4 signals to be routed: SAI_TXC, SAI_TXFS, SAI_TXD and SAI_RXD. SAI_RXC and SAI_RXFS can be left unconnected. I2S_RCR2.BCI shall be set to 0b1 to get setup and hold times provided in Table 60. Figure 22. SAI Master Synchronous mode Table 59. LPSPI timings—Slave mode at 20 MHz (continued)

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4.10.2.2 SAI Master mode

In this mode, transmitter and/or receiver part are set to bring out transmit and/or receive clock. Frame sync can be either input or output. Figure 23. SAI Master mode Table 60. SAI timings—Master Synchronous mode Table 61. SAI timings—Master mode

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4.10.2.3 SAI Slave mode

In this mode, transmitter and/or receiver parts are set to receive transmit and/or receive clock from external world. Frame sync can be either input or output. Figure 24. SAI Slave mode a lower frequency. This frequency will be driven by characteristics of the external component connected to the interface. Table 62. SAI timings—Slave mode Table 61. SAI timings—Master mode (continued)

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4.10.3 Enhanced serial au dio interface (ESAI)

The same performance is achieved at both 1.8 V and 3.3 V unless otherwise stated. Figure 25. ESAI Transmit timing

i.MX 8DualX Automotive and Infotainment Applications Processors, Rev. 3, 05/2020 NXP Semiconductors 67 Figure 26. ESAI Receive timing found in Figure 25 and Figure 26. Table 63. Enhanced Serial Audio Interface (ESAI) Timing

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4.10.4 Ultra High Speed SD/SDIO/MMC Host Interface (uSDHC) AC

This section describes the electrical information of the uSDHC, including:

• SD3.1/eMMC5.1 High-Speed mode AC Timing
• eMMC5.1 DDR 52 mode/SD3.1 DDR 50 mode timing
• HS400 AC timing—eMMC 5.1 only
• HS200 Mode Timing
• SDR50/SDR104 AC Timing t8 FSR output delay 7 x ck i ck a ns t9 RX data pins - setup requirement 2 —x c k i ck ns t10 RX data pins - hold requirement 2 —x c k i ck ns t11 FSR - setup requirement 2 —x c k i ck a ns t12 FSR - hold requirement 2 —x c k i ck a ns t13 Flags - setup requirement 2 —x c k i ck s ns t14 Flags - hold requirement 2 —x c k i ck s ns — RX_HF_CLK / TX_HX_CLK clock cycle 20 — — ns — TX_HF_CLK input to SCKT 10 — ns — RX_HF_CLK input to SCKR 10 — ns 1 i ck = internal clock x ck = external clock i ck a = internal clock, asynchronous mode (SCKT and SCKR are two different clocks) i ck s = internal clock, synchronous mode (SCKT and SCKR are the same clock)

Table 63. Enhanced Serial Audio Interface (ESAI) Timing (continued)

i.MX 8DualX Automotive and Infotainment Applications Processors, Rev. 3, 05/2020 NXP Semiconductors 69 The following figure depicts the timing of SD3.1/eMMC5.1 High-Speed mode, and Table 64 lists the timing characteristics. Figure 27. SD3.1/eMMC5.1 High-Speed mode Timing Table 64. SD3.1/eMMC5.1 High-Speed mode interface timing specification 1 In low speed mode, card clock must be lower than 400 kHz, voltage ranges from 2.7 to 3.6 V. clock frequency can be any value between 0–50 MHz.

i.MX 8DualX Automotive and Infotainment Applications Processors, Rev. 3, 05/2020 NXP Semiconductors 71 HS400 mode is the same as CMD input/output timing for SDR104 mode. Check SD5, SD6 and SD7 parameters in Table 68 SDR50/SDR104 Interface Timing Specification for CMD input/output timing for HS400 mode. Figure 30. HS400 timing Table 66. HS400 interface timing specifications

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4.10.4.4 HS200 Mode Timing

The following figure depicts the timing of HS200 mode, and Table 67 lists the HS200 timing characteristics. Figure 31. HS200 Mode Timing Table 67. HS200 Interface Timing Specification 1HS200 is for 8 bits while SDR104 is for 4 bits.

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4.10.4.5 SDR50/SDR104 AC Timing

The following figure depicts the timing of SDR50/SDR104, and Table 68 lists the SDR50/SDR104 timing characteristics. Figure 32. SDR50/SDR104 timing Table 68. SDR50/SDR104 Interface Timing Specification 1Data window in SDR100 mode is variable.

i.MX 8DualX Automotive and Infotainment Applications Processors, Rev. 3, 05/2020 NXP Semiconductors74 Signaling level of SD/eMMC 5.1 and eMMC 5.1 modes is 3.3 V . Signaling level of SDR104/SDR50 mode is 1.8 V . The DC parameters for the NVCC_SD1, NVCC_SD2, and NVCC_SD3 supplies are identical to those shown in “,” and Table 28, "Dual-voltage 1.8 V GPIO DC parameters," on page 35Table 29, "Dual-voltage 3.3 V GPIO DC parameters," on page 36.

4.10.5 Ethernet Controller (ENET) AC Electrical Specifications

ENET interface supporting RGMII protocol in delay and non-delay mode. RGMII is used to support up to 1000 Mbps Ethernet as well as RMII protocol. RMII is used to support up to 100 Mbps Ethernet. NOTE Both ENET0 and ENET1 support RGMII at 1.8 V and 2.5 V , and RMII at 3.3 V . For i.MX 8DualX, ENET1, muxed with ESAI0, is limited to RMII clock speeds. Table 69. RGMII/RMII pin mapping Refer to pin muxing for details.

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4.10.5.1 RGMII

4.10.5.1.1 No-Internal-Delay mode

This mode corresponds to the RGMIIv1.3 specification. Figure 33. RGMII timing diagram—No-Internal-Delay mode 2 Except for RCLK50M and RMII_RXER, all other RMII functions are using the same pin muxing mode as RGMII. Table 70. RGMII timings—No-Internal-Delay mode less than 2.0 ns is added to the associated clock signal.

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4.10.5.1.2 Internal-delay mode

This mode corresponds to RGMIIv2.0 specification. Figure 34. RGMII timing diagram—Internal-Delay mode

4.10.5.2 RMII

generator which is connected to the PHY and to i.MX8 through RCLK50M_IN pin. Table 71. RGMII timing—Internal-Delay mode

i.MX 8DualX Automotive and Infotainment Applications Processors, Rev. 3, 05/2020 NXP Semiconductors 77 Figure 35. RMII timing diagram Timings in table below are covering both cases: reference clock generated internally or externally.

4.10.5.3 MDIO

MDIO is the control link used to configure Ethernet PHY connected to i.MX8 device. Table 72. RMII timing

i.MX 8DualX Automotive and Infotainment Applications Processors, Rev. 3, 05/2020 NXP Semiconductors78 Figure 36. MDIO timing diagram

4.10.6 CAN network AC El ectrical Specifications

Table 73. MDIO timing

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4.10.7 I 2C Module Timing Parameters

This section describes the timing parameters of the I2C module. The following figure depicts the timing of the I2C module, and Table 74 lists the I2C module timing characteristics. Figure 37. I2C bus timing Table 74. I2C Module Timing Parameters the falling edge of I2Cx_SCL. 2 The maximum hold time has only to be met if the device does not stretch the LOW period (ID no IC5) of the I2Cx_SCL signal. of 250 ns must be met. This automatically is the case if the device does not stretch the LOW period of the I2Cx_SCL signal. before the I2Cx_SCL line is released. 4 Cb = total capacitance of one bus line in pF.

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4.10.8 MIPI-DSI/LVDS combo disp lay output specifications

The physical pins of the combo display output controller can be used in LVDS mode or in DSI display mode.

4.10.8.1 MIPI-DSI/LVDS displa y bridge module parameters

Maximum frequency support for combination MIPI-DSI/LVDS modules: Table 75. I2C timing 1 High-speed mode is only available for I2C modules in DMA, SCU and Cortex-M4 subsystems. Table 76. MIPI-DSI/LVDS combo pins

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4.10.8.2 LVDS display bridge (LDB) module electrical specifications

The MIPI DSI/LVDS interface is compatible with TIA/EIA 644-A standard. For more details, see TIA/EIA STANDARD 644-A, “Electrical Characteristics of Low V oltage Differential Signaling (LVDS) Interface Circuits.”

4.10.8.3 MIPI-DSI HS-TX specifications

LVDS (single channel) 4 pairs LVDS up to 1.05 Gb per pair 4 pairs LVDS up to 1.05 Gb per pair LVDS (dual channel) 8 pairs LVDS up to 595 Mb per pair 1 For DSI the maximum clock speed is 1.05 GHz. 2 For LVDS in single-channel operation the maximum clock speed is 150 MHz; in dual-channel operation with a single synchronized clock the maximum clock speed is 85 MHz. Table 77. LVDS Display Bridge (LDB) Electrical Specifications Table 78. MIPI high-speed transmitter DC specifications

1 High Speed Transmit Static Common Mode Voltage 150 200 250 mV

Table 76. MIPI-DSI/LVDS combo pins (continued)

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4.10.8.4 MIPI-DSI LP-TX specifications

|ΔVOD|V OD mismatch when Output is Differential-1 or Differential-0 — — 10 mV VOHHS

1 High Speed Output High Voltage — — 360 mV

ZOS Single Ended Output Impedance 40 50 62.5 Ω ΔZOS Single Ended Output Impedance Mismatch — — 10 % 1 Value when driving into load impedance anywhere in the ZID range. Table 79. MIPI high-speed transmitter AC specifications 1 UI is the long-term average unit interval. Table 80. MIPI low-power transmitter DC specifications 1 This specification can only be met when limiting the core supply variation from 1.1 V till 1.3 V. Table 81. MIPI low-power transmitter AC specifications

4 Pulse width of the LP exclusive-OR clock: First LP exclusive-OR clock pulse after Stop

Table 78. MIPI high-speed transmitter DC specifications (continued)

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4.10.8.5 MIPI-DSI LP-RX specifications

δV/δtSR 1,5,6,7 Slew Rate @ CLOAD= 0 pF 30 — 500 mV/ns Slew Rate @ CLOAD= 5 pF 30 — 200 mV/ns Slew Rate @ CLOAD= 20 pF 30 — 150 mV/ns Slew Rate @ CLOAD= 70 pF 30 — 100 mV/ns CLOAD Load Capacitance 0 — 70 pF 1 CLOAD includes the low equivalent transmission line capacitance. The capacitance of TX and RX are assumed to always be < 10 pF. The distributed line capacitance can be up to 50 pF for a transmission line with 2 ns delay. 2 The rise-time of TREOT starts from the HS common-level at the moment of the differential amplitude drops below 70 mV, due to stopping the differential drive. 3 With an additional load capacitance CCM between 0 to 60 pF on the termination center tap at RX side of the lane. 4 This parameter value can be lower then TLPX due to differences in rise vs. fall signal slopes and trip levels and mismatches between Dp and Dn LP transmitters. Any LP exclusive-OR pulse observed during HS EoT (transition from HS level to LP-11) is glitch behavior as described in Low-Power Receiver section. 5 When the output voltage is between 15% and below 85% of the fully settled LP signal levels. 6 Measured as average across any 50 mV segment of the output signal transition. 7 This value represents a corner point in a piecewise linear curve. Table 82. MIPI low power receiver DC specifications Table 83. MIPI low power receiver AC specifications 1 Time-voltage integration of a spike above VIL when in LP-0 state or below VIH when in LP-1 state. 2 An impulse below this value will not change the receiver state. 3 An input pulse greater than this value shall toggle the output. Table 81. MIPI low-power transmitter AC specifications (continued)

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4.10.8.6 MIPI-DSI LP-CD specifications

4.10.8.7 MIPI-DSI DC specifications

4.10.9 PCIe 3.0 PHY Parameters The TX and RX eye diagrams specifications are per the template shown in the following figure. The summary of specifications is shown in Table 86 and Table 87. Note that the time closure (1–A OPENING) in the eye templates needs not match jitter specifications in the Standards Specifications, as there are such discrepancies in some Standards Specifications. The design meets the tightest of specifications in case of discrepancy. Table 84. MIPI contention detector DC specifications Table 85. MIPI input characteristics DC specifications 2 This value includes ground shift. transition or vice versa. For all other situations it must stay within the VPIN range.

i.MX 8DualX Automotive and Infotainment Applications Processors, Rev. 3, 05/2020 NXP Semiconductors 85 Figure 38. TX and RX eye diagram template Table 86. PCIe transmitter eye specifications for example standards 1 VDIFFp-p eye opening is limited to VDDIO under matched termination conditions. Table 87. PCIe receiver eye specifications for example standards 1 PCIE 3.0 8 GT/s measured using PCIE reference equalizer + CDR per PCIE specification.

i.MX 8DualX Automotive and Infotainment Applications Processors, Rev. 3, 05/2020 NXP Semiconductors86 Table 88. PCIe differential output driver characteristics (including board and load) times are defined by 25% and 75% crossing points.

2 Calculated as: 2 × (TR–TF) / (TR+ TF)

VDD spread, and so a VDD tighter than ±10% may be required to achieve this spread. transiently occur during initialization period following TXENA assertion. 5 Peak change in output differential voltage when driving a logic 0 and when driving a logic 1 under DC conditions. 6 Peak change in output differential voltage when driving a logic 0 and when driving a logic 1 under AC conditions. 8 Power supply induced jitter is included under this category, and the power supply variation is to be less than 8mVpp. Note that customer has to be uncommonly careful with power supply fidelity due to the small jitter numbers.

9 Power consumption is simulated under the following conditions:

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4.10.9.1 PCIE_REXT refere nce resistor connection

The following figure shows the PCIE_REXT reference resistor connection. Figure 39. PCIE_REXT reference resistor connection

4.10.9.2 PCIE_REF_CLK

details on the PCIe reference clock requirements.

4.10.10 Pulse Width Modulato r (PWM) Timing Parameters

The following figure depicts the timing of the PWM, and Table 89 lists the PWM timing parameters. Figure 40. PWM Timing Table 89. PWM Output Timing Parameters

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4.10.11 LCD controller (LCDIF) parameters

Figure 41 shows the LCDIF timing, and the table below lists the timing parameters. Figure 41. LCD Timing

4.10.11.1 LCDIF signal mapping

The table below lists the details about the mapping signals. Table 90. LCD Timing Parameters Table 91. LCD Signal Parameters

i.MX 8DualX Automotive and Infotainment Applications Processors, Rev. 3, 05/2020 NXP Semiconductors 89 LCD_DOTCLK LCD_DOTCLK LCD_DOTCLK LCD_DOTCLK LCD_DOTCLK — LCD_ENABLE LCD_ENABLE LCD_EN ABLE LCD_ENABLE LCD_ENABLE — LCD_D17 — — R[5] R[1] — LCD_D16 — — R[4] R[0] — LCD_D15 / VSYNC* — R[4] R[3] G[7] — LCD_D14 / HSYNC — R[3] R[2] G[6] — LCD_D13 / LCD_DOTCLK — R21] R[1] G[5] — LCD_D12 / ENABLE — R[1] R[0] G[4] — LCD_D11 — R[0] G[5] G[3] — LCD_D10 — G[5] G[4] G[2] — LCD_D9 — G[4] G[3] G[1] — LCD_D8 — G[3] G[2] G[0] — LCD_D8 — G[3] G[2] G[0] — LCD_D7 R[2] G[2] G[1] B[7] Y/C[7] LCD_D6 R[1] G[1] G[0] B[6] Y/C[6] LCD_D5 R[0] G[0] B[5] B[5] Y/C[5] LCD_D4 G[2] B[4] B[4] B[4] Y/C[4] LCD_D3 G[1] B[3] B[3] B[3] Y/C[3] LCD_D2 G[0] B[2] B[2] B[2] Y/C[2] LCD_D1 B[1] B[1] B[1] B[1] Y/C[1] LCD_D0 B[0] B[0] B[0] B[0] Y/C[0] LCD_RESET LCD_RESET LCD_RE SET LCD_RESET LCD_RESET — LCD_BUSY / LCD_VSYNC LCD_BUSY (or optional LCD_VSYNC) LCD_BUSY (or optional LCD_VSYNC) LCD_BUSY (or optional LCD_VSYNC) LCD_BUSY (or optional LCD_VSYNC) Table 91. LCD Signal Parameters (continued)

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4.10.12 FlexSPI (Quad SPI/Octal SPI) timing parameters

The FlexSPI interface can work in SDR or DDR modes. It can operate up to 60 MHz at 3.3 V , 166 MHz at 1.8 V SDR mode or 200 MHz at 1.8 V DDR mode. It supports single-ended and differential DQS signaling. FlexSPI supports the following clocking scheme for a read data path:

• Dummy read strobe genera ted by FlexSPI controller and looped back internally (FlexSPIn_MCR0[RXCLKSRC] = 0x0)
• Dummy read strobe generate d by FlexSPI controller and looped back through the DQS pad (FlexSPIn_MCR0[RXCLKSRC] = 0x1). It means the I/O cannot be used for another feature.
• Read strobe provided by memory device and input from DQS pad (FlexSPIn_MCR0[RXCLKSRC] = 0x3)

4.10.12.1 SDR mode

4.10.12.1.1 SDR mode timing diagrams

The following write timing diagram is valid for any FlexSPIn_MCR0[RXCLKSRC] value. Figure 42. FlexSPI write timing diagram (SDR mode) The following read timing diagram is valid for FlexSPIn_MCR0[RXCLKSRC] = 0x0 or 0x1. Figure 43. FlexSPI read timing diagram (SDR mode)

i.MX 8DualX Automotive and Infotainment Applications Processors, Rev. 3, 05/2020 NXP Semiconductors 91 The following read timing diagram is valid for FlexSPIn_MCR0[RXCLKSRC] = 0x3. Figure 44. FlexSPI read with DQS timing diagram (SDR mode)

4.10.12.1.2 SDR mode ti ming parameter tables

Table 92. FlexSPI timings with FlexSPIn_MCR0[RXCLKSRC] = 0x0 (SDR mode) 1 Timing is controlled from FLSHxCR1 register (x=A1, A2, B1, or B2). Table 93. FlexSPI timings with FlexSPIn_MCR0[RXCLKSRC] = 0x1 (SDR mode)

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4.10.12.2 DDR mode

4.10.12.2.1 DDR mode timing diagrams

Figure 45. FlexSPI write timing diagram (DDR mode) Figure 46. FlexSPI read timing diagram (DDR mode) 1 Timing is controlled from FLSHxCR1 register (x=A1, A2, B1, or B2). Table 94. FlexSPI timings with FlexSPIn_MCR0[RXCLKSRC] = 0x3 (SDR mode) 1 Minimum is 2 SCLK cycles even if CSINTERVAL value is less than 2. 2 Timing is controlled from FLSHxCR1 register (x=A1, A2, B1, or B2).

i.MX 8DualX Automotive and Infotainment Applications Processors, Rev. 3, 05/2020 NXP Semiconductors 93 Figure 47. FlexSPI read with DQS timing diagram (DDR mode) Table 95. FlexSPI timings with FlexSPIn_MCR0[RXCLKSRC] = 0x0 (DDR mode) 1 Timing is controlled from FLSHxCR1 register (x=A1, A2, B1, or B2). Table 96. FlexSPI timings with FlexSPIn_MCR0[RXCLKSRC] = 0x1 (DDR mode) 1 Timing is controlled from FLSHxCR1 register (x=A1, A2, B1, or B2).

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4.10.13 Secure JTAG controller (SJC)

4.10.13.1 Internal pull-up /pull-down configuration

The following table describes the default configuration of internal pull-ups and pull-downs of the JTAG interface. External pull-ups and pull-downs are needed when this interface is routed to a connector. Table 97. FlexSPI timings with FlexSPIn_MCR0[RXCLKSRC] = 0x3 (DDR mode) 1 Timing is controlled from FLSHxCR1 register (x=A1, A2, B1, or B2). Table 98. JTAG default configuration for internal pull-up/pull-down

1 PU = pull-up; PD = pull-down

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4.10.13.2 JTAG timing parameters

Figure 48 depicts the SJC test clock input timing. Figure 49 depicts the SJC boundary scan timing. Figure 50 depicts the SJC test access port. Signal parameters are listed in Table 99. Figure 48. Test Clock Input Timing Diagram Figure 49. Boundary system (JTAG) timing diagram

i.MX 8DualX Automotive and Infotainment Applications Processors, Rev. 3, 05/2020 NXP Semiconductors96 Figure 50. Test Access Port Timing Diagram Table 99. JTAG Timing

1 TDC = target frequency of SJC

2 VM = mid-point voltage

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4.10.14 SPDIF Timing Parameters

The Sony/Philips Digital Interconnect Format (SPDIF) data is sent using the bi-phase marking code. When encoding, the SPDIF data signal is modulated by a clock that is twice the bit rate of the data signal. Table 100, Figure 51, and Figure 52 show SPDIF timing parameters for the Sony/Philips Digital Interconnect Format (SPDIF), including the timing of the modulating Rx clock (SPDIF_SR_CLK) for SPDIF in Rx mode and the timing of the modulating Tx clock (SPDIF_ST_CLK) for SPDIF in Tx mode. Figure 51. SPDIF_SR_CLK Timing Diagram Figure 52. SPDIF_ST_CLK Timing Diagram Table 100. SPDIF Timing Parameters

• Skew
• Transition rising
• Transition falling 1.5 24.2 31.3 ns SPDIF_OUT output (Load = 30pf)
• Skew
• Transition rising
• Transition falling 1.5 13.6 18.0 ns Modulating Rx clock (SPDIF_SR_CLK) period srckp 40.0 — ns SPDIF_SR_CLK high period srckph 16.0 — ns SPDIF_SR_CLK low period srckpl 16.0 — ns Modulating Tx clock (SPDIF_ST_CLK) period stclkp 40.0 — ns SPDIF_ST_CLK high period stclkph 16.0 — ns SPDIF_ST_CLK low period stclkpl 16.0 — ns SPDIF_SR_CLK (Output) VM VM srckp srckphsrckpl SPDIF_ST_CLK (Input) VM VM stclkp stclkphstclkpl

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4.10.15 UART I/O configuration and timing parameters

4.10.15.0.1 UART Transmitter

The following figure depicts the transmit timing of UART in the RS-232 serial mode, with 8 data bit/1 stop bit format. Table 101 lists the UART RS-232 serial mode transmit timing characteristics. Figure 53. UART RS-232 Serial Mode Transmit Timing Diagram

4.10.15.0.2 UART Receiver

The following figure depicts the RS-232 serial mode receive timing with 8 data bit/1 stop bit format. Table 102 lists serial mode receive timing characteristics. Figure 54. UART RS-232 Serial Mode Receive Timing Diagram Table 101. UART RS-232 Serial Mode Transmit Timing Parameters 2 Tref_clk: The period of UART reference clock ref_clk (LPUART_clk after SBR divider). Table 102. RS-232 Serial Mode Receive Timing Parameters not exceed 3/((OSR+1) × Fbaud_rate).

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4.10.15.0.3 UART IrDA Mode Timing

The following subsections give the UART transmit and receive timings in IrDA mode. UART IrDA Mode Transmitter The following figure depicts the UART IrDA mode transmit timing, with 8 data bit/1 stop bit format. Table 103 lists the transmit timing characteristics. Figure 55. UART IrDA Mode Transmit Timing Diagram The following figure depicts the UART IrDA mode receive timing, with 8 data bit/1 stop bit format. Table 104 lists the receive timing characteristics. Figure 56. UART IrDA Mode Receive Timing Diagram Table 103. IrDA Mode Transmit Timing Parameters 2 Tref_clk: The period of UART reference clock ref_clk (LPUART_clk after SBR divider). Table 104. IrDA Mode Receive Timing Parameters must not exceed 3/((OSR+1) × Fbaud_rate).

i.MX 8DualX Automotive and Infotainment Applications Processors, Rev. 3, 05/2020 NXP Semiconductors100 4.10.16 USB 2.0 PHY Parameters 4.10.16.1 USB 2.0 PHY Transmitter specifications This section describes the transmitter specifications for USB2.0 PHY . The following table lists the full-speed/low-speed (FS/LS) transmitter specifications for USB2.0 PHY. 2 Fbaud_rate: Baud rate frequency. The maximum baud rate the UART can support is (LPUART_clk frequency)/(SBR[12:0] × (OSR+1)). Table 105. USB 2.0 PHY FS/LS transmitter specifications

i.MX 8DualX Automotive and Infotainment Applications Processors, Rev. 3, 05/2020 NXP Semiconductors 101 4.10.16.2 USB 2.0 PHY high-spe ed transmitter specifications The following table lists the high-speed (HS) transmitter specifications for USB 2.0 PHY. 4.10.16.3 USB 2.0 PHY receiver specifications This section describes the receiver specifications implemented in USB 2.0 PHY . Table 106. USB 2.0 PHY HS transmitter specifications device with a captive cable measured at TP2. Table 107. USB 2.0 PHY FS/LS receiver specifications

i.MX 8DualX Automotive and Infotainment Applications Processors, Rev. 3, 05/2020 NXP Semiconductors102 The following table lists the high-speed (HS) receiver specifications for USB 2.0 PHY. The following table lists the high-speed (HS) Envelope Detector Specifications of USB 2.0 PHY. TJR2 Receiver Jitter Budget (Paired Transition) - FS -9 — 9 ns TFEOPR Receiver EOP Interval of EOP - FS 82 — — ns TUJR1 US Port Differential Receiver Jitter (Next Transition) - LS -152 — 152 ns TUJR2 US Port Differential Receiver Jitt er (Paired Transition) - LS -200 — 200 ns TDJR1 DS Port Differential Receiver Jitter (Next Transition) - LS -75 — 75 ns TDJR2 DS Port Differential Receiver Jitter (Paired Transition) - LS -45 — 45 ns TLEOPR Receiver EOP Interv al of EOP - LS 670 — — ns Table 108. USB 2.0 PHY HS receiver specifications device with captive cable when signal applied at TP2. device without captive cable at TP3 and for a hub at TP2. device with captive cable when signal is applied at TP2. hub when a signal is applied at TP2. Table 109. USB 2.0 PHY HS envelope detector specifications Table 107. USB 2.0 PHY FS/LS receiver specifications (continued)

i.MX 8DualX Automotive and Infotainment Applications Processors, Rev. 3, 05/2020 NXP Semiconductors 103 4.10.16.4 USB 2.0 PHY full-speed/hig h-speed terminations specification The following table lists the full-speed/low-speed (FS/LS) Terminations Specification of USB 2.0 PHY.

4.10.16.5 Voltage threshold specification

The following table lists the OTG Comparator Specifications of USB2.0 PHY.

4.11 Analog-to-digital converter (ADC)

The following table shows the ADC electrical specifications for VREFH=VDD_ADC_1P8. Table 110. USB 2.0 PHY FS/LS terminations specification Table 111. USB 2.0 PHY OTG comparator specifications Table 112. ADC electrical specifications (VREFH=VDD_ADC_1P8)

i.MX 8DualX Automotive and Infotainment Applications Processors, Rev. 3, 05/2020 NXP Semiconductors104 The following table shows the ADC electrical specifications for 1V≤VREFH<VDD_ADC_1P8. ENOB Effective Number of Bits — — — — 5,6,7 Avg = 1 10.1 10.4 — Bits Avg = 2 10.5 10.7 — Bits Avg = 16 11.1 11.3 — Bits SINAD Signal to Noise plus Distortion SINAD=6.02 x ENOB + 1.76 dB — E G Gain error — -0.29 — %FSV 8 EO Offset error — 0.01 — %FSV 9 IVDDA18 Supply Current — 480 — μA 10 Iin,ext,leak External Channel Leakage Current — 30 500 nA — EIL Input leakage error RAS * I in mV — 1 Typical values assume VDD_ADC_1P8 = 1.8 V, Temp = 25 °C, fACLK = Max, unless otherwise stated. Typical values are for reference only. All values, including Min and Max, are derived from lab characterization and are not tested in production. 2 This resistance is external to the input pad. To achieve the best results, the analog source resistance must be kept as low as possible. The results in this data sheet were derived from a system that had < 15 Ω analog source resistance. The RAS/CAS (analog source capacitance) time constant should be kept to < 1 ns. 3 See Figure 57. 4 ADC conversion clock at max frequency and using linear histogram. 5 Input data used for test was 1 kHz sine wave. 6 Measured at VREFH = 1.8 V and pwrsel = 2. 7 ENOB can be lower than shown, if an ADC channel corrupts other ADC channels through capacitive coupling. This coupling may be dominated by board parasitics. Care must be taken not to corrupt the desired channel being measured. This coupling becomes worse at higher analog frequencies and with switching waveforms due to the harmonic content. 8 Error measured at fullscale at 1.8 V. 9 Error measured at zero scale at 0 V. 10 Power Configuration Select, PWRSEL, is set to 10 binary. Table 113. ADC electrical specifications (1V≤VREFH<VDD_ADC_1P8) Table 112. ADC electrical specifications (VREFH=VDD_ADC_1P8) (continued)

i.MX 8DualX Automotive and Infotainment Applications Processors, Rev. 3, 05/2020 NXP Semiconductors 105 Cconversion Conversion cycles C conversion = Csample + Ccompare cycles — DNL Differential Non-Linearity — ± 0.6 -0.5 to +1.1 LSB 4 INL Integral Non-Linearity — ± 0.9 ±1.1 LSB 4 ENOB Effective Number of Bits — — — — 5,6,7 Avg = 1 9.5 9.7 — Bits Avg = 2 9.9 10.1 — Bits Avg = 16 10.8 11 — Bits SINAD Signal to Noise plus Distortion SINAD=6.02 x ENOB + 1.76 dB — E G Gain error — 0.29 — %FSV 8 EO Offset error — 0.01 — %FSV 9 IVDDA18 Supply Current — 480 — μA 10 Iin,ext,leak External Channel Leakage Current — 30 500 nA — EIL Input leakage error RAS * I in mV — 1 Typical values assume VDD_ANA_1P8 = 1.8 V, Temp = 25 °C, fACLK = Max, unless otherwise stated. Typical values are for reference only. All values, including Min and Max, are derived from lab characterization and are not tested in production. 2 This resistance is external to the input pad. To achieve the best results, the analog source resistance must be kept as low as possible. The results in this data sheet were derived from a system that had < 15 Ω analog source resistance. The RAS/CAS (analog source capacitance) time constant should be kept to < 1 ns. 3 See Figure 57. 4 ADC conversion clock at max frequency and using linear histogram. 5 Input data used for test was 1 kHz sine wave. 6 Measured at VREFH = 1 V and pwrsel = 2. 7 ENOB can be lower than shown, if an ADC channel corrupts other ADC channels through capacitive coupling. This coupling may be dominated by board parasitics. Care must be taken not to corrupt the desired channel being measured. This coupling becomes worse at higher analog frequencies and with switching waveforms due to the harmonic content. 8 Error measured at fullscale at 1.0 V. 9 Error measured at zero scale at 0 V. 10 Power Configuration Select, PWRSEL, is set to 10 binary. Table 113. ADC electrical specifications (1V≤VREFH<VDD_ADC_1P8) (continued)

i.MX 8DualX Automotive and Infotainment Applications Processors, Rev. 3, 05/2020 NXP Semiconductors106 The following figure shows a plot of the ADC sample time versus RAS. Figure 57. Sample time vs. RAS

5 Boot mode configuration

5.1 Boot mode configuration pins

5.2 Boot devices interfaces allocation

allocation, which are configured during boot when appropriate. Table 114. Fuse and associated pins used for Boot Table 115. Interface allocation during boot USDHC1_CD_B is used by first (A0) silicon only.

high when booting if specified in fuse.

• USDHC1_CD_B Single-ended RE:
• USDHC1_VSELECT Differential DQS:
• _N use USDHC1_WP
• _P use USDHC1_CD_B Differential RE:
• _N use USDHC1_RESET_B
• _P use USDHC1_VSELECT Quad SPI QSPI0 QSPI0A_D ATA0, QSPI0A_DATA1, QSPI0A_DATA2, QSPI0A_DATA3, QSPI0A_DQS, QSPI0A_SCLK, QSPI0A_SS0_B, QSPI0A_SS1_B, QSPI0B_DATA0, QSPI0B_DATA1, QSPI0B_DATA2, QSPI0B_DATA3, QSPI0B_DQS, QSPI0B_SCLK, QSPI0B_SS0_B, QSPI0B_SS1_B 4, dual-4, or 8 bit USB USB-OTG1 USB_OTG1_DN, USB_OTG2_DN, USB_OTG1_DP, USB_OTG2_DP, USB_OTG1_ID, USB_OTG2_ID, USB_OTG1_VBUS, USB_OTG2_VBUS

Table 115. Interface allocation during boot (continued)

Package information and contact assignments i.MX 8DualX Automotive and Infotainment Applications Processors, Rev. 3, 05/2020 NXP Semiconductors 109

6 Package information and contact assignments

This section contains package information and contact assignments for the following package(s):

• FCPBGA, 21 x 21 mm, 0.8 mm pitch
• FCPBGA, 17 x 17 mm, 0.8 mm pitch 6.1 FCPBGA, 21 x 21 mm, 0.8 mm pitch This section includes the following information for the 21 x 21 mm, 0.8 mm pitch package:
• Mechanical package drawing
• Ball map
• Contact assignments

The following figure shows the top, bottom, and side views of the 21 x 21 mm package. Figure 58. 21 x 21 mm Package Top, Bottom, and Side Views

Figure 59. Notes on 21 x 21 mm Package Top, Bottom, and Side Views

Package information and contact assignments i.MX 8DualX Automotive and Infotainment Applications Processors, Rev. 3, 05/2020 NXP Semiconductors112 6.1.2 21 x 21 mm, 0.8 mm pitch ball map The following page shows the 21 x 21 mm, 0.8 mm pitch ball map.

Package information and functional contact assignments for FCPBGAT 21 x 21 mmT 0Y8 mm pitch NXP Semiconductors 113 i.MX 8DualX Automotive and Infotainment Applications Processors, Rev. 3, 05/2020 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 A VSS_MAI N NC NC PCIE0_T X0_N PCIE_CT RL0_WA KE_B PCIE0_R X0_P NC VSS_MAI N NC EMMC0_ DATA1 EMMC0_ DATA6 USDHC1_ VSELECT USDHC1_ DATA0 ENET0_R GMII_TX _CTL ENET0_R GMII_RX VSS_MAI N B NC NC NC VSS_MAI N PCIE0_T X0_P PCIE0_R X0_N VSS_MAI N NC NC VSS_MAI N EMMC0_ DATA4 USDHC1_ RESET_B USDHC1_ DATA1 ENET0_R GMII_TX ENET0_R GMII_RX _CTL ENET0_ MDIO ESAI0_T C VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N USB_SS3 _TC3 VSS_MAI N VSS_MAI N EMMC0_ DATA0 VSS_MAI N USDHC1_ CMD VSS_MAI N ENET0_R GMII_RX VSS_MAI N ESAI0_T X3_RX2 VSS_MAI N D NC NC NC NC PCIE_CT RL0_CLK REQ_B PCIE_RE FCLK100 M_N USB_OT G2_REXT USB_OT G2_DN USB_OT G1_DP EMMC0_ CMD EMMC0_ DATA7 USDHC1_ WP USDHC1_ DATA2 ENET0_R GMII_RX C ENET0_ MDC ESAI0_T SPDIF0_T X E NC NC NC NC NC PCIE_RE FCLK100 M_P USB_SS3 _REXT VSS_MAI N USB_OT G2_DP USB_OT G1_DN EMMC0_ DATA2 USDHC1_ CD_B USDHC1_ DATA3 ENET0_R GMII_TX VSS_MAI N ESAI0_S CKT VSS_MAI N SPDIF0_E XT_CLK F VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N PCIE_RE F_QR USB_SS3 _TC0 USB_OT G2_ID VSS_MAI N VSS_MAI N EMMC0_ STROBE VSS_MAI N ENET0_R GMII_TX ENET0_R EFCLK_12 5M_25M ESAI0_FS R ESAI0_T X4_RX1 SPI3_SD O G NC NC NC NC DDR_ZQ PCIE0_PH Y_PLL_R EF_RETU RN VDD_PCI E_1P8 USB_SS3 _TC2 USB_OT G1_ID EMMC0_ CLK EMMC0_ DATA5 USDHC1_ CLK ENET0_R GMII_TX ENET0_R GMII_RX ESAI0_FS T SPDIF0_ RX SPI3_SDI MCLK_IN H NC NC NC NC PCIE_CT RL0_PER ST_B PCIE_RE XT USB_SS3 _TC1 USB_OT G2_VBU S USB_OT G1_VBUS EMMC0_ DATA3 EMMC0_ RESET_B ENET0_R GMII_TX C ENET0_R GMII_RX ESAI0_S CKR VSS_MAI N SPI3_SCK UART1_T X J VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N ESAI0_T X5_RX0 SPI3_CS0 VSS_MAI N SAI0_TX C K DDR_DC F29 DDR_DC F27 DDR_DC F28 DDR_DC F25 VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N ESAI0_T X2_RX3 SPI3_CS1 UART1_C TS_B SAI0_TX D L DDR_DC F18 DDR_DC F32 DDR_DC F31 DDR_DC F26 VSS_MAI N VDD_PCI E_DIG_1P 8_3P3 VDD_PCI E_LDO_1 P0_CAP VDD_US B_3P3 VDD_US B_OTG_1 VDD_EM MC0_1P8 _3P3 VDD_US DHC1_VS ELECT_1P 8_3P3 VDD_EN ET0_VSE LECT_1P8 _2P5_3P VDD_EN ET_MDIO _1P8_3P3 VSS_MAI N MCLK_O UT0 UART1_R X SAI0_TX FS SAI1_RX C M VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VDD_DD R_VDDQ VDD_AN A0_1P8 VDD_US B_SS3_L DO_1P0_ CAP VDD_US B_1P8 VDD_EM MC0_VS ELECT_1P 8_3P3 VDD_US DHC1_1P8 _3P3 VDD_EN ET0_1P8_ 2P5_3P3 VSS_MAI N MCLK_IN VSS_MAI N SAI1_RX D SAI0_RX D N DDR_DC F19 DDR_DC F17 DDR_CK1 DDR_DC F30 VDD_DD R_VDDQ VDD_DD R_VDDQ VSS_MAI N VDD_MA IN VSS_MAI N VDD_MA IN VSS_MAI N VDD_GP U VDD_ES AI_SPDIF _1P8_2P5 _3P3 VSS_MAI N UART1_R TS_B SPI2_SDI VSS_MAI N SAI1_RXF S P DDR_DC F22 DDR_DC F20 DDR_CK1 DDR_DC F33 VSS_MAI N VDD_MA IN VSS_MAI N VDD_MA IN VSS_MAI N VDD_GP U VDD_GP U VDD_MA IN VSS_MAI N SPI2_CS0 SPI0_SCK SPI2_SD O SPI0_SDI R VSS_MAI N VSS_MAI N VSS_MAI N VDD_DD R_VDDQ VSS_MAI N VDD_DD R_VDDQ VDD_MA IN VSS_MAI N VDD_MA IN VSS_MAI N VDD_GP U VSS_MAI N VDD_SPI _MCLK_ UART_1P 8_3P3 VSS_MAI N SPI2_SCK SPI0_SD O SPI0_CS0 SPI0_CS1 T DDR_DC F07 DDR_DC F23 DDR_DC F24 DDR_DC F21 VSS_MAI N VDD_DD R_VDDQ VDD_MA IN VSS_MAI N VDD_MA IN VSS_MAI N VDD_GP U VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N U DDR_DC F03 DDR_DC F01 DDR_DC F05 DDR_DC F04 VSS_MAI N VDD_DD R_VDDQ VSS_MAI N VDD_MA IN VSS_MAI N VDD_MA IN VSS_MAI N VDD_GP U VDD_SPI _SAI_1P8 _3P3 VSS_MAI N ADC_VR EFH ADC_VR EFL ADC_IN1 ADC_IN0 V VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VDD_MA IN VSS_MAI N VDD_MA IN VSS_MAI N VDD_GP U VSS_MAI N VDD_MA IN VSS_MAI N VDD_AD C_1P8 ADC_IN3 ADC_IN2 ADC_IN5 W DDR_DC F00 DDR_DC F11 DDR_CK 0_P DDR_DC F16 VSS_MAI N VDD_DD R_VDDQ VDD_MA IN VSS_MAI N VDD_MA IN VSS_MAI N VDD_GP U VSS_MAI N VDD_AD C_DIG_1P VSS_MAI N ADC_IN4 VSS_MAI N VSS_MAI N VSS_MAI N Y DDR_DC F14 DDR_DC F15 DDR_CK 0_N DDR_DC F12 VSS_MAI N VDD_DD R_VDDQ VDD_MA IN VSS_MAI N VDD_MA IN VSS_MAI N VDD_MA IN VDD_CA N_UART _1P8_3P3 VSS_MAI N VSS_MAI N VSS_MAI N FLEXCAN 0_TX FLEXCAN 0_RX AA VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VDD_DD R_VDDQ VDD_DD R_VDDQ VSS_MAI N VDD_A35 VDD_A35 VDD_A35 VSS_MAI N VDD_MA IN VDD_MIP I_DSI_DI G_1P8_3 VSS_MAI N UART0_T X FLEXCAN 2_TX FLEXCAN 1_RX FLEXCAN 1_TX AB DDR_DQ1 DDR_DC F08 DDR_DC F09 DDR_AT O VSS_MAI N VDD_MA IN VSS_MAI N VDD_A35 VDD_A35 VDD_A35 VSS_MAI N VDD_AN A1_1P8 VSS_MAI N MIPI_DSI 0_I2C0_S DA VSS_MAI N UART0_ RX FLEXCAN 2_RX AC DDR_DQ1 DDR_DQ1 DDR_DC F10 DDR_DT VDD_DD R_PLL_1P VDD_DD R_VDDQ VDD_MA IN VSS_MAI N VDD_MA IN VSS_MAI N VDD_MA IN VSS_MAI N VDD_SN VS_4P2 VSS_MAI N MIPI_DSI1 _I2C0_S DA MIPI_DSI 0_I2C0_S CL VSS_MAI N UART2_T X AD VSS_MAI N VSS_MAI N VSS_MAI N DDR_VR EF VSS_MAI N VDD_DD R_VDDQ VDD_MA IN VDD_MIP I_1P8 VDD_MIP I_1P0 VSS_MAI N VDD_MA IN VDD_TM PR_CSI_1 P8_3P3 VSS_MAI N SCU_WD OG_OUT MIPI_DSI1 _GPIO0_ MIPI_DSI 0_GPIO0 _00 UART2_ RX AE DDR_DQ S1_N DDR_DQ1 DDR_DQ DDR_DT VSS_MAI N VDD_DD R_VDDQ VDD_QS PI0B_1P8 _3P3 VDD_QS PI0A_1P8 _3P3 VDD_MIP I_1P8 VDD_MIP I_1P0 VDD_MIP I_CSI_DI G_1P8 VDD_CSI _1P8_3P3 VDD_SN VS_LDO_ 1P8_CAP VSS_MAI N TEST_M ODE_SEL ECT JTAG_TC K MIPI_DSI1 _I2C0_S CL MIPI_DSI 0_GPIO0 _01 AF DDR_DQ S1_P DDR_DM DDR_DQ DDR_DQ VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N SCU_GPI O0_00 VSS_MAI N JTAG_TD O MIPI_DSI1 _GPIO0_ AG VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N SCU_PMI C_STAN DBY POR_B VSS_MAI N JTAG_T MS AH DDR_DQ1 DDR_DQ1 DDR_DQ S0_N DDR_DQ QSPI0B_ SS0_B QSPI0A_ DATA3 VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N ON_OFF_ BUTTON SCU_GPI O0_01 PMIC_I2 C_SDA JTAG_TD I AJ DDR_DQ DDR_DQ DDR_DQ S0_P DDR_DM QSPI0B_ SS1_B QSPI0B_ DATA2 QSPI0A_ DATA2 MIPI_DSI 0_DATA3 MIPI_DSI 0_DATA1 MIPI_DSI 0_CLK_N MIPI_DSI 0_DATA0 MIPI_DSI 0_DATA2 CSI_D06 CSI_D03 SCU_BO OT_MOD SCU_BO OT_MOD PMIC_IN T_B PMIC_I2 C_SCL AK VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N QSPI0B_ DQS QSPI0A_ SS1_B QSPI0A_ DATA0 MIPI_DSI 0_DATA3 MIPI_DSI 0_DATA1 MIPI_DSI 0_CLK_P MIPI_DSI 0_DATA0 MIPI_DSI 0_DATA2 CSI_PCLK CSI_D00 VSS_MAI N SCU_BO OT_MOD ANA_TES T_OUT_N AL NC NC DDR_DQ DDR_DQ QSPI0B_ DATA1 QSPI0A_ DQS VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N CSI_VSY NC CSI_D01 SCU_BO OT_MOD VSS_MAI N ANA_TES T_OUT_P AM NC DDR_DQ DDR_DQ QSPI0B_ DATA3 QSPI0B_ DATA0 QSPI0A_ SS0_B MIPI_DSI1 _DATA2_ N MIPI_DSI1 _CLK_N MIPI_DSI1 _DATA3_ N MIPI_CSI 0_DATA1 MIPI_CSI 0_DATA0 MIPI_CSI 0_I2C0_S DA CSI_MCL K CSI_D07 CSI_D05 RTC_XT ALO XTALO AN VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N MIPI_DSI1 _DATA0_ N MIPI_DSI1 _DATA1_ N MIPI_CSI 0_DATA3 MIPI_CSI 0_CLK_N MIPI_CSI 0_DATA2 MIPI_CSI 0_MCLK_ OUT VSS_MAI N CSI_D04 VSS_MAI N VSS_SCU _XTAL VSS_SCU _XTAL AP NC NC NC NC NC QSPI0A_ SCLK MIPI_DSI1 _DATA2_ P MIPI_DSI1 _CLK_P MIPI_DSI1 _DATA3_ P MIPI_CSI 0_DATA1 MIPI_CSI 0_DATA0 MIPI_CSI 0_GPIO0 _01 MIPI_CSI 0_I2C0_S CL CSI_EN CSI_D02 RTC_XT ALI XTALI AR VSS_MAI N NC NC NC QSPI0B_ SCLK QSPI0A_ DATA1 MIPI_DSI1 _DATA0_ P MIPI_DSI1 _DATA1_ P MIPI_CSI 0_DATA3 MIPI_CSI 0_CLK_P MIPI_CSI 0_DATA2 MIPI_CSI 0_GPIO0 _00 CSI_RES ET CSI_HSY NC PMIC_ON _REQ VSS_SCU _XTAL

Table 116. 21 x 21 mm power supplies contact assignments

1 N23,P20,P22,R21,T22,U23,V20,W21

1 VDD_A35 and VDD_GPU can be combined with one power supply. Table 116. 21 x 21 mm power supplies contact assignments (continued)

The following table shows functional contact assignments for the 21 × 21 mm package. Table 117. 21 x 21 mm functional contact assignments

Table 117. 21 x 21 mm functional contact assignments (continued)

1 FASTD are GPIO balls configured for high speed operation using the FASTRZ control. of the device reference manual. 3 SCU_WDOG_OUT was previously named JTAG_TRST_B; it has been renamed because its functionality has changed.

The following table shows DDR pin function. Table 118. DRAM pin function

Table 118. DRAM pin function (continued)

Package information and contact assignments i.MX 8DualX Automotive and Infotainment Applications Processors, Rev. 3, 05/2020 NXP Semiconductors 125 6.2 FCPBGA, 17 x 17 mm, 0.8 mm pitch This section includes the following:

• Mechanical package drawing
• Ball map for case FCPBGA, 17 x 17 mm, 0.8 mm pitch
• Contact assignments

The following figure shows the top, bottom, and side views of the 17 x 17 mm package. Figure 60. 17 x 17 mm Package Top, Bottom, and Side Views

Figure 61. Notes on 17 x 17 mm Package Top, Bottom, and Side Views

Package information and contact assignments i.MX 8DualX Automotive and Infotainment Applications Processors, Rev. 3, 05/2020 NXP Semiconductors128 6.2.2 17 x 17 mm, 0.8 mm pitch, ball map The following page shows the 17 x 17 mm, 0.8 mm pitch, ball map.

Package information and functional contact assignments for FCPBGAT 17 x 17 mmT 0Y8 mm pitch NXP Semiconductors 129 iYMX 8DualX Automotive and Infotainment Applications ProcessorsT RevY 3T 05/2020 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 A VSS_MAIN DDR_DCF18 DDR_CK1_P DDR_DCF26 PCIE_CTRL0_ PERST_B PCIE0_TX0_P PCIE0_RX0_P USB_OTG1_ID USB_OTG1_D P EMMC0_DAT ENET0_RGMII _RXC ENET0_MDC VSS_MAIN B DDR_DCF01 DDR_DCF07 DDR_DCF17 DDR_CK1_N DDR_DCF21 PCIE0_TX0_N PCIE_CTRL0_ WAKE_B PCIE0_RX0_N USB_OTG1_D N EMMC0_RES ET_B ENET0_RGMII _TXD3 ENET0_RGMII _RXD3 ESAI0_FSR ESAI0_TX4_R C VSS_MAIN VSS_MAIN VSS_MAIN VSS_MAIN VSS_MAIN VSS_MAIN PCIE_REFCLK 100M_N VSS_MAIN VSS_MAIN VDD_EMMC0 _VSELECT_1P 8_3P3 ENET0_RGMII _TXD1 ENET0_RGMII _RXD0 ESAI0_SCKT ESAI0_TX2_R VSS_MAIN D DDR_DCF12 DDR_DCF05 DDR_DCF20 DDR_DCF29 DDR_DCF28 VDD_USB_3P PCIE_REFCLK 100M_P VDD_USB_SS 3_LDO_1P0_C AP VDD_EMMC0 _1P8_3P3 VDD_ENET0_ VSELECT_1P8 _2P5_3P3 ENET0_RGMII _RXD1 ESAI0_TX3_R SPI3_CS0 SPI3_SCK E DDR_DCF15 DDR_DCF03 DDR_DCF22 DDR_DCF32 DDR_DCF27 PCIE_CTRL0_ CLKREQ_B EMMC0_CM D EMMC0_DAT VSS_MAIN EMMC0_DAT VDD_ENET0_ 1P8_2P5_3P3 ESAI0_FST ESAI0_TX1 SPDIF0_EXT_ CLK UART1_RX F VSS_MAIN VSS_MAIN VSS_MAIN VSS_MAIN DDR_ZQ PCIE_REF_QR EMMC0_CLK EMMC0_DAT EMMC0_DAT ENET0_RGMII _TXD0 ENET0_REFC LK_125M_25M SPDIF0_RX VDD_ENET_ MDIO_1P8_3P SPI3_CS1 G DDR_DCF10 DDR_CK0_N DDR_DCF00 DDR_DCF33 DDR_DCF31 PCIE0_PHY_P LL_REF_RETU RN USB_SS3_TC1 EMMC0_DAT EMMC0_DAT ENET0_RGMII _TXC ENET0_RGMII _RXD2 ESAI0_TX0 SPI3_SDO UART1_CTS_ B UART1_RTS_ B H DDR_CK0_P DDR_DCF24 DDR_DCF19 DDR_DCF30 DDR_DCF25 PCIE_REXT USB_SS3_TC EMMC0_DAT ENET0_RGMII _TX_CTL ENET0_RGMII _RX_CTL ESAI0_SCKR SPI3_SDI VSS_MAIN SPI0_CS0 J VSS_MAIN VSS_MAIN VSS_MAIN VSS_MAIN VDD_PCIE_DI G_1P8_3P3 VDD_PCIE_1P VSS_MAIN USB_OTG1_V BUS EMMC0_STR OBE ENET0_RGMII _TXD2 ENET0_MDIO SPDIF0_TX UART1_TX SPI0_SDO SPI0_SDI K DDR_DCF08 DDR_DCF14 DDR_DCF04 VDD_DDR_V DDQ VDD_ANA0_1 VDD_PCIE_LD O_1P0_CAP VDD_USB_1P

8 VDD_MAIN VSS_MAIN VDD_GPU

ESAI0_TX5_R MCLK_OUT0 VDD_ESAI_SP DIF_1P8_2P5_ 3P3 SPI0_CS1 L DDR_DCF11 DDR_DCF09 DDR_DCF23 DDR_DCF16 VSS_MAIN VSS_MAIN VDD_MAIN VSS_MAIN VDD_GPU VDD_GPU VDD_MAIN MCLK_IN0 SPI0_SCK VDD_SPI_MC LK_UART_1P8 _3P3 VSS_MAIN M VSS_MAIN VSS_MAIN VSS_MAIN VDD_DDR_V DDQ VDD_MAIN VSS_MAIN VDD_MAIN VSS_MAIN VDD_GPU VSS_MAIN MCLK_IN1 VSS_MAIN VSS_MAIN ADC_VREFH N DDR_DQ02 DDR_DQ00 DDR_DQ13 DDR_DQ15 VDD_DDR_V DDQ VDD_MAIN VSS_MAIN VDD_MAIN VSS_MAIN VDD_GPU VSS_MAIN ADC_IN1 ADC_IN3 ADC_IN2 ADC_VREFL P DDR_DQ01 DDR_DQ12 DDR_DQ14 VDD_DDR_V DDQ VSS_MAIN VDD_MAIN VSS_MAIN VDD_MAIN VSS_MAIN VDD_GPU VDD_ADC_1P ADC_IN0 ADC_IN5 ADC_IN4 R VSS_MAIN VSS_MAIN VSS_MAIN VSS_MAIN VSS_MAIN VSS_MAIN VDD_MAIN VSS_MAIN VDD_GPU VSS_MAIN VDD_MAIN VSS_MAIN VSS_MAIN VSS_MAIN VSS_MAIN T DDR_DQ03 DDR_DQS1_N DDR_DM1 VDD_DDR_V DDQ VDD_MAIN VSS_MAIN VDD_MAIN VSS_MAIN VDD_GPU VSS_MAIN FLEXCAN0_R X FLEXCAN1_R X VDD_ADC_DI G_1P8 FLEXCAN2_R X U DDR_DQS0_N DDR_DQS0_P DDR_DQS1_P DDR_DTO0 VDD_DDR_V DDQ VDD_MAIN VSS_MAIN VDD_MAIN VSS_MAIN VDD_MAIN VDD_CAN_U ART_1P8_3P3 UART0_TX FLEXCAN0_T X FLEXCAN2_T X FLEXCAN1_T X V VSS_MAIN VSS_MAIN VSS_MAIN VDD_DDR_V DDQ VSS_MAIN VDD_A35 VDD_A35 VDD_A35 VSS_MAIN VDD_MAIN MIPI_DSI0_I2 C0_SDA VSS_MAIN UART2_TX UART0_RX W DDR_DM0 DDR_DQ10 DDR_ATO VDD_DDR_PL L_1P8 VSS_MAIN VSS_MAIN VDD_A35 VDD_A35 VDD_A35 VSS_MAIN VDD_ANA1_1 JTAG_TMS MIPI_DSI1_I2C 0_SDA MIPI_DSI0_I2 C0_SCL UART2_RX Y DDR_DQ04 DDR_DQ08 DDR_VREF VDD_DDR_V DDQ VDD_MAIN VSS_MAIN VDD_MAIN VSS_MAIN VDD_MAIN VSS_MAIN SCU_GPIO0_0 JTAG_TDO VDD_SNVS_4 MIPI_DSI1_I2C 0_SCL AA VSS_MAIN VSS_MAIN VSS_MAIN VSS_MAIN VDD_DDR_V DDQ VDD_MAIN VDD_MIPI_1P VDD_MIPI_1P

0 VSS_MAIN VDD_MAIN

VDD_TMPR_ CSI_1P8_3P3 PMIC_INT_B TEST_MODE_ SELECT VSS_MAIN JTAG_TCK AB DDR_DQ05 DDR_DQ11 DDR_DTO1 VDD_DDR_V DDQ QSPI0A_DQS QSPI0A_SS0_ B VDD_MIPI_1P VDD_MIPI_1P VDD_MIPI_CS I_DIG_1P8 PMIC_ON_RE Q SCU_BOOT_ MODE3 SCU_PMIC_S TANDBY VDD_SNVS_L DO_1P8_CAP SCU_WDOG_ OUT AC DDR_DQ06 DDR_DQ07 DDR_DQ09 QSPI0B_DAT QSPI0A_DAT MIPI_CSI0_D ATA3_N MIPI_CSI0_D ATA1_N MIPI_CSI0_CL K_N MIPI_CSI0_D ATA0_N MIPI_CSI0_D ATA2_N CSI_D00 SCU_BOOT_ MODE1 SCU_GPIO0_0 PMIC_I2C_SC L JTAG_TDI AD VSS_MAIN VSS_MAIN VSS_MAIN VDD_QSPI0A _1P8_3P3 QSPI0A_SS1_ B MIPI_CSI0_D ATA3_P MIPI_CSI0_D ATA1_P MIPI_CSI0_CL K_P MIPI_CSI0_D ATA0_P MIPI_CSI0_D ATA2_P CSI_D02 VSS_MAIN SCU_BOOT_ MODE0 POR_B AE QSPI0B_DAT QSPI0B_DAT VDD_QSPI0B _1P8_3P3 QSPI0B_SS0_ B VSS_MAIN VSS_MAIN VSS_MAIN VSS_MAIN VSS_MAIN VSS_MAIN VSS_MAIN ANA_TEST_O UT_P SCU_BOOT_ MODE2 VSS_MAIN PMIC_I2C_SD A AF QSPI0B_DAT QSPI0B_DQS QSPI0B_SS1_ B MIPI_DSI1_DA TA0_N MIPI_DSI1_DA TA1_N MIPI_DSI0_D ATA3_N MIPI_DSI0_CL K_N MIPI_DSI0_D ATA2_N MIPI_CSI0_M CLK_OUT CSI_VSYNC VDD_CSI_1P8 _3P3 ANA_TEST_O UT_N RTC_XTALO XTALO AG VSS_MAIN QSPI0A_SCLK QSPI0A_DAT MIPI_DSI1_DA TA2_N MIPI_DSI1_CL K_N MIPI_DSI1_DA TA3_N MIPI_DSI0_D ATA1_N MIPI_DSI0_D ATA0_N VSS_MAIN CSI_PCLK CSI_D04 CSI_D03 VSS_MAIN VSS_SCU_XT AL VSS_SCU_XT AL AH QSPI0B_SCLK QSPI0A_DAT VSS_MAIN MIPI_DSI1_DA TA0_P MIPI_DSI1_DA TA1_P MIPI_DSI0_D ATA3_P MIPI_DSI0_CL K_P MIPI_DSI0_D ATA2_P CSI_RESET CSI_HSYNC CSI_D07 CSI_D01 RTC_XTALI XTALI AJ VSS_MAIN QSPI0A_DAT MIPI_DSI1_DA TA2_P MIPI_DSI1_CL K_P MIPI_DSI1_DA TA3_P MIPI_DSI0_D ATA1_P MIPI_DSI0_D ATA0_P CSI_EN CSI_MCLK CSI_D06 CSI_D05 ON_OFF_BUT TON VSS_SCU_XT AL

The following table shows the power supplies contact assignments for the 17 x 17 mm package. Table 119. 17 x 17 mm power supplies contact assignments

Table 119. 17 x 17 mm power supplies contact assignments (continued)

The following table shows functional contact assignments for the 17 x 17 mm package. Table 120. 17 x 17 mm functional contact assignments

Table 120. 17 x 17 mm functional contact assignments (continued)

1 FASTD are GPIO balls configured for high speed operation using the FASTRZ control. the device reference manual. 3 Power domain and associated IO grouping differs from 21 x 21 package. 4 SCU_WDOG_OUT was previously named JTAG_TRST_B; it has been renamed because its functionality has changed.

The following table shows the DDR 17 x 17 mm pin function. Table 121. i.MX 8QXP 17 x 17 mm DRAM pin function

Table 121. i.MX 8QXP 17 x 17 mm DRAM pin function (continued)

7 Release Notes

This table provides release notes for the data sheet. Table 122. Data sheet release notes

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