IMX53IEC

IMX53IEC FREESCALE | Alldatasheet

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Technical content

Data Sheet: Technical Data Document Number: IMX53IEC Rev. 6, 03/2013 MCIMX53xC

Package Information

Case TEPBGA-2 19 x 19 mm, 0.8 mm pitch

Ordering Information

© 2011, 2012, 2013 Freescale Semiconductor, Inc. All rights reserved.

1 Introduction

The i.MX53 processor features ARM Cortex™-A8 core, which operates at clock speeds as high as 800 MHz. It provides DDR2/LVDDR2-800, LPDDR2-800, or DDR3-800 DRAM memories. The flexibility of the i.MX53 architecture allows for its use in a wide variety of applications. As the heart of the application chipset, the i.MX53 processor provides all the interfaces for connecting peripherals, such as WLAN, Bluetooth™, GPS, hard drive, camera sensors, and dual displays. Features of the i.MX53 processor include the following:  Applications processor—The i.MX53xD processors boost the capabilities of high-tier portable applications by satisfying the ever increasing MIPS needs of operating systems and games. Freescale’s Dynamic V oltage and Frequency Scaling (DVFS) provides significant power reduction, allowing the device to run at lower voltage and frequency with sufficient MIPS for tasks such as audio decode. i.MX53 Applications Processors for Industrial Products Silicon Version 2.1 1.1. Functional Part Differences and Ordering

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including eMMC up to rev 4.4. feature-rich product requiring levels of power far lower than industry expectations. programmable smart DMA (SDMA) controller. 2C, and I2S serial audio, among others). contact a Freescale representative. efficiency, and multimedia capabilities.

1.1 Functional Part Differences and Ordering Information

shows the functional differences between the different parts in the i.MX53 family. Table 1 provides ordering information. Table 1. Ordering Information 1 Case TEPBGA-2 is RoHS compliant, lead-free MSL (moisture sensitivity level) 3.

i.MX53 Applications Processors for Industrial Products, Rev. 6 Freescale Semiconductor 3

1.2 Features

The i.MX53 multimedia applications processor (AP) is based on the ARM Platform, which has the following features:  MMU, L1 instruction and L1 data cache  Unified L2 cache  Maximum frequency of the core (incl uding Neon, VFPv3 and L1 cache): 800 MHz  Neon coprocessor (SIMD media processing archit ecture) and vector floating point (VFP-Lite) coprocessor supporting VFPv3  TrustZone The memory system consists of the following components:  Level 1 cache: — Instruction (32 Kbyte) — Data (32 Kbyte)  Level 2 cache: — Unified instruction and data (256 Kbyte)  Level 2 (internal) memory: — Boot ROM, including HAB (64 Kbyte) — Internal multimedia/shared, fast access RAM (128 Kbyte) — Secure/non-secure RAM (16 Kbyte)  External memory interfaces: — 16/32-bit DDR2-800, LV-DDR2-800 or DDR3-800 up to 2 Gbyte — 32-bit LPDDR2 — 8/16-bit NAND SLC/MLC Flash, up to 66 MHz, 4/8/14/16-bit ECC — 8/16-bit NOR Flash, PSRAM, and cellular RAM. — 32-bit multiplexed mode NOR Flash, PSRAM & cellular RAM. — 8-bit Asynchronous (DTACK mode) EIM interface. — All EIM pins are muxed on other interfaces (dat a with NFC pins). I/O muxing logic selects EIM port, as primary muxing at system boot. — Samsung OneNAND™ and managed NAND including eMMC up to rev 4.4 (in muxed I/O mode) The i.MX53 system is built around the following system on chip interfaces:  64-bit AMBA AXI v1.0 bus—used by ARM platform, multimedia accelerators (such as VPU, IPU, GPU3D, GPU2D) and the external memory controller (EXTMC) operating at 200 MHz.  32-bit AMBA AHB 2.0 bus—used by the rest of the bus master peripherals operating at 133 MHz.  32-bit IP bus—peripheral bus used for control (and slow data traffic) of the most system peripheral devices operating at 66 MHz.

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The i.MX53 makes use of dedicated hardware accelerators to achieve state-of-the-art multimedia performance. The use of hardware accelerators provides both high performance and low power consumption while freeing up the CPU core for other tasks. The i.MX53 incorporates the following hardware accelerators:  VPU, version 3—video processing unit  GPU3D—3D graphics processing unit, OpenGL ES 2.0, version 3, 33 Mtri/s, 200 Mpix/s, and

800 Mpix/s z-plane performance, 256 Kbyte RAM memory

 GPU2D—2D graphics accelerator, OpenVG 1.1, version 1, 200 Mpix/s performance,  IPU, version 3M—image processing unit  ASRC—asynchronous sample rate converter The i.MX53 includes the following interfaces to external devices: NOTE Not all interfaces are available simultaneously, depending on I/O multiplexer configuration.  Hard disk drives: — PA TA, up to U-DMA mode 5, 100 MByte/s — SA TA II, 1.5 Gbps D i s p l a y s : — Five interfaces available. Total rate of all interfaces is up to 180 Mpixels/s, 24 bpp. Up to two interfaces may be active at once. — Two parallel 24-bit display ports. The primary port is up to 165 Mpix/s (for example, UXGA at 60 Hz). — LVDS serial ports: one dual channel port up to 165 Mpix/s or two independent single channel ports up to 85 MP/s (for example, WXGA at 60 Hz) each. — TV-out/VGA port up to 150 Mpix/s (for example, 1080p60).  Camera sensors: — Two parallel 20-bit camera ports. Primary up to 180-MHz peak clock frequency, secondary up to 120-MHz peak clock frequency.  Expansion cards: — Four SD/MMC card ports: three supporting 416 Mbps (8-bit i/f) and one enhanced port supporting 832 Mbps (8-bit, eMMC 4.4). U S B — High-speed (HS) USB 2.0 OTG (up to 480 Mbps), with integrated HS USB PHY — Three USB 2.0 (480 Mbps) hosts: – High-speed host with integrated on-chip high-speed PHY – Two high-speed hosts for external HS/FS transceivers through ULPI/serial, support IC-USB  Miscellaneous interfaces: — One-wire (OWIRE) port

i.MX53 Applications Processors for Industrial Products, Rev. 6 Freescale Semiconductor 5 — Three I2S/SSI/AC97 ports, supporting up to 1.4 Mbps, each connected to audio multiplexer (AUDMUX) providing four external ports. — Five UART RS232 ports, up to 4.0 Mbps each. One supports 8-wire, the other four support 4-wire. — Two high speed enhanced CSPI (ECSPI) ports plus one CSPI port — Three I 2C ports, supporting 400 kbps — Fast Ethernet controller, IEEE1588 V1 compliant, 10/100 Mbps — Two controller area network (FlexCAN) interfaces, 1 Mbps each — Sony Phillips Digital Interface (SPDIF), Rx and Tx — Key pad port (KPP) — Two pulse-width modulators (PWM) — GPIO with interrupt capabilities The system supports efficient and smart power control and clocking:  Supporting DVFS (dynamic voltage and frequenc y scaling) technique for low power modes  Power gating SRPG (State Retention Power Gating) for ARM core and Neon  Support for various levels of system power modes  Flexible clock gating control scheme  On-chip temperature monitor  On-chip oscillator amplifier supporting 32.768 kHz external crystal  On-chip LDO voltage regulators for PLLs Security functions are enabled and accelerated by the following hardware/features:  ARM TrustZone including the TZ architecture (separation of interrupts, memory mapping, and so on)  Secure JTAG controller (SJC)—Protecting JTAG from debug port attacks by regulating or blocking the access to the system debug features  Secure real-time clock (SRTC)—Tamper resi stant RTC with dedicated power domain and mechanism to detect voltage and clock glitches  Real-time integrity checker, version 3 (RTIC v3)—RTIC type1, enhanced with SHA-256 engine  SAHARAv4 Lite—Cryptographic accelerator that includes true random number generator (TRNG)  Security controller, version 2 (SCCv2)—Improved SCC with AES engine, secure/non-secure RAM and support for multiple keys as well as TZ/non-TZ separation  Central security unit (CSU)—Enhancement for the IIM (IC Identification Module). CSU is configured during boot by eFUSEs, and determines the security level operation mode as well as the TrustZone (TZ) policy  Advanced High Assurance Boot (A-HAB)—HAB with the following embedded enhancements: SHA-256, 2048-bit RSA key, version control mechanism, warm boot, CSU, and TZ initialization  Tamper detection mechanism—Provides evidence of any physical attempt to remove the device cover. Upon detection of such an attack, sensitive information can immediately be erased.

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2 Architectural Overview

The following subsections provide an architectural overview of the i.MX53 processor system.

2.1 Block Diagram

Figure 1 shows the functional modules in the i.MX53 processor system. Figure 1. i.MX53 System Block Diagram PWM (2) indicates two separate PWM peripherals.

3 HS Ports

(IEEE1149.1)BluetoothKeypad Access.

3 Modules List

Table 2. i.MX53 Digital and Analog Blocks sampling rates. The ASRC supports up to three sampling rate pairs. SSI2, and SSI3) and peripheral serial interfaces (audio and voice codecs). achieved by configuring two or more AUDMUX ports. system, as well as for system power management. The system includes four PLLs. mode it supports four slave selects for multiple peripherals. boot (HAB) code and are locked to prevent further writing.

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the ARM Real Time Debug solution (RealView). cross-system triggers (CTI), counters, and sequencers. debug configuration registers and JTAG scan chains.  Support 16/32-bit DDR2-800 or DDR3-800 or LPDDR2.  Support up to 2 GByte DDR memories.  Support NFC, EIM signal muxing scheme.  Multiple chip selects (up to 4). for the interrupts to occur, and counter values can be programmed on the fly. industry-standard codecs, SPDIF transceivers, and other processors. section with its own clock generator. The ESAI has 12 pins for data and clocking connection to external devices. Table 2. i.MX53 Digital and Analog Blocks (continued)

4.4 standard specification, for 832 MBps. double data rate (832 Mbps, 8-bit port). features of ESDHCV2 as described below. version 4.3, full support and supporting 1, 4 or 8-bit data.

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These modules are used for general purpose input/output to external ICs. Each GPIO module supports up to 32 bits of I/O. either on an external clock or on an internal clock. graphics applications on displays up to HD1080 resolution. up to 400 kbps are supported. of signals visible outside the module.

 Synchronization and control capabilities, allowing autonomous operation. On-chip differential drivers are provided for each pair. smart battery interfaces, for example, Dallas DS2502. bus buffer between the host side and the device side. Internal RAM, shared with VPU. used for controlling the 128 KB multimedia RAM, through a 64-bit AXI bus. Supports secure and regular boot modes. The ROM controller supports ROM patching.

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complete mixed-signal IP solution for SA TA HDD connectivity. system performance by off loading various cores in dynamic data routing.

Secure / non-secure Internal RAM, controlled by SCC. hardware blocks including the ARM processor and the system bus. unauthorized JTAG usage should be strictly forbidden. interfaces connect internally to the AUDMUX for mapping to external ports. time slots are being used simultaneously.

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functionality, generating and reading the needed timestamps. trigger the CCM, to reduce the core operating frequency. software Priority Masking are also supported.

40 Mpixel/s bit rate for 4:4:4 format

80 Mpixel/s bit rate for 4:2:2 format

module is activated, it must be serviced by TZ software on a periodic basis. WDOG asserts a TZ mapped interrupt that forces switching to the TZ mode. 1 VPU can generate higher bit rate than the maximum specified by the corresponding standard.

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Electrical Characteristics

3.1 Special Signal Considerations

The package contact assignments can be found in Section 6, “Package Information and Contact Assignments.” Signal descriptions are defined in the i.MX53 Reference Manual. Special signal considerations information is contained in Chapter 1 of i.MX53 System Development User's Guide (MX53UG).

4 Electrical Characteristics

This section provides the device and module-level electrical characteristics for the i.MX53 processor.

4.1 Chip-Level Conditions

This section provides the device-level electrical characteristics for the IC. See Table 3 for a quick reference to the individual tables and sections.

4.1.1 Absolute Maximum Ratings

Stresses beyond those listed under Table 4 may affect reliability or cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated in the Operating Ranges table is not implied. Table 3. i.MX53 Chip-Level Conditions Table 4. Absolute Maximum Ratings

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4.1.2 Thermal Resistance

4.1.2.1 TEPBGA-2 Package Thermal Resistance

Table 5 provides the TEPBGA-2 package thermal resistance data. Input voltage on USB_OTG_DP , USB_OTG_DN, USB_H1_DP , USB_H1_DN pins USB_DP/USB_DN -0.3 3.63 1 V Input/Output Voltage Range V in/Vout -0.5 OVDD +0.32 V ESD Damage Immunity: V esd V  Human Body Model (HBM)  Charge Device Model (CDM) 2000 500 Storage T emperature Range T STORAGE -40 150 oC 1 USB_DN and USB_DP can tolerate 5 V for up to 24 hours. 2 The term OVDD in this section refers to the associated supply rail of an input or output. The association is described in Table 111 on page 148. The maximum range can be superseded by the DC tables. Table 5. TEPBGA-2 Package Thermal Resistance Data 2 Per JEDEC JESD51-2 with the single layer board horizontal. Board meets JESD51-9 specification. 3 Per JEDEC JESD51-6 with the board horizontal. the top surface of the board near the package. Table 4. Absolute Maximum Ratings (continued)

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4.1.3 Operating Ranges

Table 6 provides the operating ranges of i.MX53 processor. Table 6. i.MX53 Operating Ranges

i.MX53 Applications Processors for Industrial Products, Rev. 6 Freescale Semiconductor 19 TVDAC_DHVDD9 TVDAC_AHVDDRGB9 TVE digital and analog power supply, TVE-to-DAC level shifter supply, cable detector supply, analog power supply to RGB channel 2.69 2.75 2.91 V For GPIO use only, when TVE is not in use 1.65 1.8 or 2.775 3.1 V NVCC_SRTC_POW SRTC Core and slow I/O Supply (GPIO) 10 1.25 1.3 1.35 V NVCC_RESET LVIO 1.65 1.8 or 2.775 3.1 V USB_H1_VDDA25 USB_OTG_VDDA25 NVCC_XTAL USB_PHY analog supply, oscillator amplifier analog supply11 2.25 2.5 2.75 V USB_H1_VDDA33 USB_OTG_VDDA33 USB PHY I/O analog supply 3.0 3.3 3.6 V VBUS See Ta ble 4 on page 16 and Ta ble 10 4 on page 141 for details. Note that this is not a power supply. ——— — VDD_REG12 Power supply input for the integrated linear regulators 2.37 2.5 2.63 V VP SAT A PHY core power supply 1.25 1.3 1.35 V VPH SAT A PHY I/O supply voltage 2.25 2.5 2.75 V TJ Junction temperature -40 105 13 125 oC 1 Voltage at the package power supply contact must be maintained between the minimum and maximum voltages. The design must allow for supply tolerances and system voltage drops. 2 The nominal values for the supplies indicate the target setpoint for a tolerance no tighter than ± 50 mV. Use of supplies with a tighter tolerance allows reduction of the setpoint with commensurate power savings. 3 A voltage transition is allowed for the required supply ramp up to the nominal value prior to achieving a clock speed increase. Similarly, to accommodate a frequency reduction, a voltage transition is allowed for a supply ramp down to the nominal value after the frequency is decreased. 4 For BSDL mode, the minimum operating temperature is 20 oC and the maximum operating temperature is the maximum temperature specified for the particular part grade. 5 VDDA and VDDAL1 can be driven by the VDD_DIG_PLL internal regulator using external connections. When operating in this configuration, the regulator is still operating at the default 1.2 V, as bootup start. During bootup initialization, software s hould increase this regulator voltage to match VCC (1.3 V nominal) in order to reduce internal leakage current. 6 By default, VDD_DIG_PLL is driven from internal on-die 1.2 V linear regulator (LDO). In this case, there is no need driving this supply externally. LDO output to VDD_DIG_PLL should be configured by software after power-up to 1.3 V output. A bypass capacitor of minimal value 22 μF should be connected to this pad in any case whether it is driven internally or externally. Use of the on-chip LDO is preferred. See i.MX53 System Development User’s Guide. 7 By default, the VDD_ANA_PLL is driven from internal on-die 1.8 V linear regulator (LDO). In this case there is no need driving this supply externally. A bypass capacitor of minimal value 22 μF should be connected to this pad in any case whether it is driven internally or externally. Use of the on-chip LDO is preferred. See i.MX53 System Development User’s Guide. 8 After fuses are programmed, Freescale strongly recommends the best practice of reading the fuses to verify that they are written correctly. In Read mode, VDD_FUSE should be floated or grounded. Tying VDD_FUSE to a positive supply (3.0 V–3.3 V) increases the possibility of inadvertently blowing fuses and is not recommended in read mode.

9 If not using the TVE module or other pads in this power domain for the product, the TVDAC_DHVDD and

TVDAC_AHVDDRGB can be kept floating or tied to GND—the recommendation is to float.

10 GPIO pad operational at low frequency

Table 6. i.MX53 Operating Ranges (continued)

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4.1.4 External Clock Sources

The i.MX53 device has four external input system clocks, a low frequency (CKIL), a high frequency (XTAL), and two general purpose CKIH1 and CKIH2 clocks. The CKIL is used for low-frequency functions. It supplies the clock for wake-up circuit, power-down real time clock operation, and slow system and watch-dog counters. The clock input can be connected to either external oscillator or a crystal using internal oscillator amplifier. The system clock input XTAL is used to generate the main system clock. It supplies the PLLs and other peripherals. The system clock input can be connected to either external oscillator or a crystal using internal oscillator amplifier. CKIH1 and CKIH2 provide additional clock source option for peripherals that require specific and accurate frequencies. Table 7 shows the interface frequency requirements. See Chapter 1 of i.MX53 System Development User's Guide (MX53UG) for additional clock and oscillator information.

4.1.5 Maximal Supply Currents

Table 8 represents the maximal momentary current transients on power lines, and should be used for power supply selection. Maximal currents higher by far than the average power consumption of typical use cases. For typical power consumption information, see i.MX53 power consumption application note. 11 The analog supplies should be isolated in the application design. Use of series inductors is recommended. 12 VDD_REG is power supply input for the integrated linear regulators of VDD_ANA_PLL and VDD_DIG_PLL when they are configured to the internal supply option. VDDR_REG st ill has to be tied to 2.5 V supply when VDD_ANA_PLL and VDD_DIG_PLL are configured for external power supply mode although in this case it is not used as supply source. 13 Lifetime of 87,600 hours based on 105 oC junction temperature at nominal supply voltages. Table 7. External Input Clock Frequency 1 External oscillator or a crystal with internal oscillator amplifier. 2 Recommended nominal frequency 32.768 kHz. Table 8. Maximal Supply Currents

i.MX53 Applications Processors for Industrial Products, Rev. 6 Freescale Semiconductor 21 VP 20 mA VDD_ANA_PLL 10 mA NVCC_XT AL 25 mA VDD_REG 325 mA VDD_FUSE Fuse Write Mode operation 120 mA NVCC_EMI_DRAM 1.8V (DDR2) 800 mA 1.5V (DDR3) 650 mA 1.2V (LPDDR2) 250 mA TVDAC_DHVDD + TVDAC_AHVDDRGB 200 mA NVCC_SRTC_POW 50 2 μA USB_H1_VDDA25 + USB_OTG_VDDA25 50 mA USB_H1_VDDA33 + USB_OTG_VDDA33 20 mA VPH 60 mA NVCC_CKIH Use maximal I/O Eq 3, N=4 NVCC_CSI Use maximal I/O Eq 3, N=20 NVCC_EIM_MAIN Use maximal I/O Eq 3, N=39 NVCC_EIM_SEC Use maximal I/O Eq 3, N=16 NVCC_FEC Use maximal I/O Eq 3, N=11 NVCC_GPIO Use maximal I/O Eq 3, N=13 NVCC_JTAG Use maximal I/O Eq 3, N=6 NVCC_KP AD Use maximal I/O Eq 3, N=11 NVCC_LCD Use maximal I/O Eq 3, N=29 NVCC_L VDS Use maximal I/O Eq 3, N=20 NVCC_LVDS_BG Use maximal I/O Eq 3, N=1 NVCC_NANDF Use maximal I/O Eq 3, N=8 NVCC_P AT A Use maximal I/O Eq 3, N=29 NVCC_REST Use maximal I/O Eq 3, N=5 Table 8. Maximal Supply Currents (continued)

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NVCC_SD1 Use maximal I/O Eq 3, N=6 NVCC_SD2 Use maximal I/O Eq 3, N=6

1 The results are based on calculation assuming the following conditions:

—Four 16-bit DDR devices —Heavy use profile —On-Die Termination (ODT) of 50 Ω for DDR2 and 40 Ω for DDR3 —Dual rank termination schema —Command and Address line termination to NVCC_EMI_DRAM/2 voltage These numbers include both i.MX53 DDR controller I/O current consumption and DDR memory I/O power consumption for data and DQS lines. 2 50 μA current is the worst case for fast silicon at 125 °C. The typical current is 3 μA for typical silicon at 25 °C.

3 General Equation for estimated, maximal power consumption of an I/O power supply:

Imax = N x C x V x (0.5 x F) Where: N - Number of I/O pins supplies by the power line C - Equivalent external capacitive load V - I/O voltage (0.5 x F) - Data change rate. Up to 0.5 of the clock rate (F).

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4.1.6 USB-OH-3 (OTG + 3 Host ports) Module and the Two USB PHY (OTG

and H1) Current Consumption Table 9 shows the USB interface current consumption.

4.2 Power Supply Requirements and Restrictions

The system design must comply with power-up sequence, power-down sequence and steady state guidelines as described in this section to guarantee the reliable operation of the device. Any deviation from these sequences may result in the following situations:  Excessive current during power-up phase  Prevention of the device from booting  Irreversible damage to the i.MX53 processor (worst-case scenario)

4.2.1 Power-Up Sequence

The following observations should be considered:  The consequent steps in power up sequence should not start before the previous step supplies have been stabilized within 90-110% of their nominal voltage, unless stated otherwise.  NVCC_SRTC_POW should remain powered ON continuously, to maintain internal real-time clock status. Otherwise, it has to be powered ON together with VCC, or preceding VCC.  The VCC should be powered ON together, or any time after NVCC_SRTC_POW.  NVCC_CKIH should be powered ON after VCC is stable and before other I/O supplies (NVCC_xxx) are powered ON. Table 9. USB Interface Current Consumption

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 I/O Supplies (NVCC_xxx) below or equal to 2.8 V nom./3.1 V max. should not precede NVCC_CKIH. They can start powering ON during NVCC_CKIH ramp-up, before it is stabilized. Within this group, the supplies can be powered-up in any order. Alternatively, the on-chip regulator VDD_ANA_PLL can be used to power NVCC_CKIH and NVCC_RESET. In this case, the sequence defined in the “Interfacing the i.MX53 Processor with LTC3589-1” section of the i.MX53 System Development User's Guide (MX53UG) must be followed.  I/O Supplies (NVCC_xxx) above 2.8 V nom./3.1 V max. should be powered ON only after NVCC_CKIH is stable.  In case VDD_DIG_PLL and VDD_ANA_PLL are power ed ON from internal voltage regulator (default case for i.MX53), there are no related restrictions on VDD_REG, as it is used as their internal regulators power source. If VDD_DIG_PLL and VDD_ANA_PLL are powered on externally, to reduce current leakage during the power-up, it is recommended to activate the VDD_REG before or at the same time with VDD_DIG_PLL and VDD_ANA_PLL. If this sequencing is not possible, make sure that the 2.5 V VDD_REG supply shut-off output impedance is higher than 1 kΩ when it is inactive.  VDD_REG supply is required to be powered ON to enable DDR operation. It must be powered on after VCC and before NVCC_EMI_DRAM. The sequence should be: VCC →VDD_REG →NVCC_EMI_DRAM  VDDA and VDDAL1 can be powered ON anytime befo re POR_B, regardless of any other power signal.  VDDGP can be powered ON anytime before PO R_B, regardless of any other power signal.  VP and VPH can be powered up together, or any time after, the VCC. VP and VPH should come before POR.  TVDAC_DHVDD and TVDAC_AHVDDRGB should be powered from the same regulator. This is due to ESD diode protection circuit, that may cause current leakage if one of the supplies is powered ON before the other. NOTE The POR_B input must be immediately asserted at power-up and remain asserted until after the last power rail reaches its working voltage.

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4.2.2 Power-Down Sequence

Power-down sequence should follow one of the following two options:  Option 1: Switch all supplies down simultaneously with further free discharge. A deviation of few microseconds of actual power-down of the different power rails is acceptable.  Option 2: Switch down supplies, in a ny order, keeping the following rules: — NVCC_CKIH must be powered down at the same time or after the UHVIO I/O cell supplies (for full supply list, see Table 6, Ultra High voltage I/O (UHVIO) supplies). A deviation of few microseconds of actual power-down of the different power rails is acceptable. — VDD_REG must be powered down at the same time or after NVCC_EMI_DRAM supply. A deviation of few microseconds of actual power-down of the different power rails is acceptable. — If all of the following conditions are met: – VDD_REG is powered down to 0V (Not Hi-Z) – VDD_DIG_PLL and VDD_ANA_PLL are provided externally, – VDD_REG is powered down before VDD_DIG_PLL and VDD_ANA_PLL Then the following rule should be kept: VDD_REG output impedance must be higher than 1 kW, when inactive.

4.2.3 Power Supplies Usage

 All I/O pins should not be externally driven while the I/O power supply for the pin (NVCC_xxx) is off. This can cause internal latch-up and malfunctions due to reverse current flows. For information about I/O power supply of each pin, see “Power Rail” columns in pin list tables of Section 6, “Package Information and Contact Assignments.”  If not using SATA interface and the embedde d thermal sensor, the VP and VPH should be grounded. In particular, keeping VPH turned OFF while the VP is powered ON is not recommended and might lead to excessive power consumption.  When internal clock source is used for SA TA temperature monitor the USB_PHY supplies and PLL need to be active because they are providing the clock.  If not using the TVE module, the TVDAC_DHVDD and TVDAC_AHVDDRGB can be kept floating or tied to GND—the recommendation is to float. If only the GPIO pads in TVDAC_AHVDDRGB domain are in use, the supplies can be set to GPIO pad voltage range ( 1 . 6 5V t o 3 . 1V ) .

4.3 I/O DC Parameters

This section includes the DC parameters of the following I/O types:  General Purpose I/O (GPIO)  Double Data Rate 3 I/O (DDR3) for DDR2/LVDDR2, LPDDR2 and DDR3 modes  Low V oltage I/O (LVIO)  Ultra High V oltage I/O (UHVIO)  LVDS I/O

i.MX53 Applications Processors for Industrial Products, Rev. 6 Freescale Semiconductor 27 NOTE The term ‘OVDD’ in this section refers to the associated supply rail of an input or output. The association is shown in Table 111. Figure 3. Circuit for Parameters Voh and Vol for I/O Cells

4.3.1 General Purpose I/O (GPIO) DC Parameters

The parameters in Table 10 are guaranteed per the operating ranges in Table 6, unless otherwise noted. Table 10. GPIO I/O DC Electrical Characteristics

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4.3.2 LPDDR2 I/O DC Parameters

The LPDDR2 I/O pads support DDR2/LVDDR2, LPDDR2, and DDR3 operational modes.

4.3.2.1 DDR2 Mode I/O DC Parameters

The DDR2 interface fully complies with JESD79-2E DDR2 JEDEC standard release April, 2008. The parameters in Table 11 are guaranteed per the operating ranges in Table 6, unless otherwise noted. Input current (100 kΩ Pull-down) Iin Vin = 0 V Vin = OVDD —— 1 0 μA Keeper Circuit Resistance — 130 4 —k Ω 1 Overshoot and undershoot conditions (transitions above OVDD and below GND) on switching pads must be held below 0.6 V, and the duration of the overshoot/undershoot must not exceed 10% of the system clock cycle. Overshoot/ undershoot must be controlled through printed circuit board layout, transmission line impedance matching, signal line termination, or other methods. Non-compliance to this specification may affect device reliability or cause permanent damage to the device. 2 To maintain a valid level, the transition edge of the input must sustain a constant slew rate (monotonic) from the current DC level through to the target DC level, VIL or VIH. Monotonic input transition time is from 0.1 ns to 1 s. 3 Hysteresis of 250 mV is guaranteed over all operating conditions when hysteresis is enabled. 4 Use an off-chip pull resistor of less than 60 k Ω to override this keeper. Table 11. DDR2 I/O DC Electrical Parameters 1 specification in this document. 3 Vin(dc) specifies the allowable DC voltage exertion of each differential input. Table 10. GPIO I/O DC Electrical Characteristics (continued)

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4.3.2.2 LPDDR2 Mode I/O DC Parameters

The LPDDR2 interface fully complies with JESD209-2B LPDDR2 JEDEC standard release June, 2009. The parameters in Table 12 are guaranteed per the operating ranges in Table 6, unless otherwise noted.

4.3.2.3 DDR3 Mode I/O DC Parameters

The DDR3 interface fully complies with JESD79-3D DDR3 JEDEC standard release April, 2008. The parameters in Table 13 are guaranteed per the operating ranges in Table 6, unless otherwise noted. 4 Vid(dc) specifies the input differential voltage |Vtr-Vcp| required for switching, where Vtr is the “true” input level and Vcp is the “complementary” input level. The minimum value is equal to Vih(dc) -Vil(dc). 5 Use an off-chip pull resistor of less than 60 k Ω to override this keeper. Table 12. LPDDR2 I/O DC Electrical Parameters 1 1 Note that the JEDEC LPDDR2 specification (JESD209_2B) supersedes any specification in this document. the limitations for overshoot and undershoot. 3 Use an off-chip pull resistor of less than 60 k Ω to override this keeper. Table 13. DDR3 I/O DC Electrical Parameters

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4.3.3 Low Voltage I/O (LVIO) DC Parameters

The parameters in Table 14 are guaranteed per the operating ranges in Table 6, unless otherwise noted. The LVIO pads operate only as inputs. Over/undershoot peak Vpeak — — — 0.4 V Over/undershoot area (above OVDD or below OVSS) Varea — — — 0.67 V-ns T ermination Voltage Vtt Vtt tracking OVDD/2 0.49 x OVDD Vref 0.51 x OVDD V Input current (no pull-up/down) Iin VI = 0 V VI=OVDD μA Pull-up/Pull-down impedance mismatch — Minimum impedance configuration ——3 Ω 240 Ω unit calibration resolution — — — — 10 Ω Keeper Circuit Resistance — — — 130 4 —k Ω 1 OVDD— I/O power supply (1.425 V–1.575 V for DDR3)

2 Vref— DDR3 external reference voltage

3 The single-ended signals need to be within the respective limits (Vih(dc) max, Vil(dc) min) for single-ended signals as well as the limitations for overshoot and undershoot. 4 Use an off-chip pull resistor of less than 60 k Ω to override this keeper. Table 14. LVIO DC Electrical Characteristics Table 13. DDR3 I/O DC Electrical Parameters (continued)

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4.3.4 Ultra-High Voltage I/O (UHVIO) DC Parameters

The parameters in Table 15 are guaranteed per the operating ranges in Table 6, unless otherwise noted. 1 Overshoot and undershoot conditions (transitions above OVDD and below GND) on switching pads must be held below 0.6 V, and the duration of the overshoot/undershoot must not exceed 10% of the system clock cycle. Overshoot/undershoot must be controlled through printed circuit board layout, transmission line impedance matching, signal line termination, or other methods. Non-compliance to this specification may affect device reliability or cause permanent damage to the device. 2 To maintain a valid level, the transition edge of the input must sustain a constant slew rate (monotonic) from the current DC level through to the target DC level, VIL or VIH. Monotonic input transition time is from 0.1 ns to 1 s. VIL and VIH do not apply when hysteresis is enabled. 3 Hysteresis of 350 mV is guaranteed over all operating conditions when hysteresis is enabled. 4 Use an off-chip pull resistor of less than 60 k Ω to override this keeper. Table 15. UHVIO DC Electrical Characteristics methods. Non-compliance to this specification may affect device reliability or cause permanent damage to the device. 3 Hysteresis of 250 mV is guaranteed over all operating conditions when hysteresis is enabled. 4 Use an off-chip pull resistor of less than 60 k Ω to override this keeper.

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4.3.5 LVDS I/O DC Parameters

The LVDS interface complies with TIA/EIA 644-A standard. See TIA/EIA STANDARD 644-A, “Electrical Characteristics of Low V oltage Differential Signaling (LVDS) Interface Circuits” for details. Table 16 shows the Low V oltage Differential Signaling (LVDS) DC electrical characteristics. The parameters in Table 16 are guaranteed per the operating ranges in Table 6, unless otherwise noted.

4.4 Output Buffer Impedance Characteristics

This section defines the I/O Impedance parameters of the i.MX53 processor for the following I/O types:  General Purpose I/O (GPIO)  Double Data Rate 3 I/O (DDR3) for DDR2/LVDDR2, LPDDR2, and DDR3 modes  Ultra High V oltage I/O (UHVIO)  LVDS I/O NOTE Output driver impedance is measured with “long” transmission line of impedance Ztl attached to I/O pad and incident wave launched into transmission lime. Rpu/Rpd and Ztl form a voltage divider that defines specific voltage of incident wave relative to OVDD. Output driver impedance is calculated from this voltage divider (see Figure 4). Table 16. LVDS DC Electrical Characteristics

i.MX53 Applications Processors for Industrial Products, Rev. 6 Freescale Semiconductor 33 Figure 4. Impedance Matching Load for Measurement

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4.4.1 GPIO Output Buffer Impedance

Table 17 shows the GPIO output buffer impedance.

4.4.2 DDR Output Driver Average Impedance

The DDR2/LVDDR2 interface fully complies with JESD79-2E DDR2 JEDEC standard release April, 2008. The DDR3 interface fully complies with JESD79-3D DDR3 JEDEC standard release April, 2008. Table 17. GPIO Output Buffer Impedance

i.MX53 Applications Processors for Industrial Products, Rev. 6 Freescale Semiconductor 35 Table 18 shows DDR output driver average impedance of the i.MX53 processor. Table 18. DDR Output Driver Average Impedance 1 pu_*cal, pd_*cal input pins. 2 Output driver impedance deviation (calibration accuracy) is ±5% (max/min impedance) across PVTs. devices should be kept to 240 Ω per the JEDEC standard.

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4.4.3 UHVIO Output Buffer Impedance

Table 19 shows the UHVIO output buffer impedance.

4.4.4 LVDS I/O Output Buffer Impedance

The LVDS interface complies with TIA/EIA 644-A standard. See, TIA/EIA STANDARD 644-A, “Electrical Characteristics of Low V oltage Differential Signaling (LVDS) Interface Circuits” for details.

4.5 I/O AC Parameters

This section includes the AC parameters of the following I/O types:  General Purpose I/O (GPIO)  Double Data Rate 3 I/O (DDR3) for DDR2/LVDDR2, LPDDR2 and DDR3 modes  Low V oltage I/O (LVIO)  Ultra High V oltage I/O (UHVIO)  LVDS I/O The load circuit and output transition time waveforms are shown in Figure 5 and Figure 6. Figure 5. Load Circuit for Output Figure 6. Output Transition Time Waveform Table 19. UHVIO Output Buffer Impedance

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4.5.1 GPIO I/O AC Electrical Characteristics

AC electrical characteristics for GPIO I/O in slow and fast modes are presented in the Table 20 and Table 21, respectively. Note that the fast or slow I/O behavior is determined by the appropriate control bit in the IOMUXC control registers. Table 20. GPIO I/O AC Parameters Slow Mode 1 tps is measured between VIL to VIH for rising edge and between VIH to VIL for falling edge. 2 Hysteresis mode is recommended for inputs with transition times greater than 25 ns. Table 21. GPIO I/O AC Parameters Fast Mode

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4.5.2 LPDDR2 I/O AC Electrical Characteristics

The DDR2/LVDDR2 interface mode fully complies with JESD79-2E DDR2 JEDEC standard release April, 2008. The DDR3 interface mode fully complies with JESD79-3D DDR3 JEDEC standard release April, 2008. Table 22 shows the AC parameters for LPDDR2 I/O operating in DDR2 mode. Output Pad T ransition Times (Low Drive) tr, tf 15 pF 35 pF — — 4.82/4.5 10.54/9.95 ns Output Pad Slew Rate (Max Drive)1 tps 15 pF 35 pF 0.69/0.78 0.36/0.39 —— V / n s Output Pad Slew Rate (High Drive) 1 tps 15 pF 35 pF 0.55/0.62 0.28/0.30 —— V / n s Output Pad Slew Rate (Medium Drive) 1 tps 15 pF 35 pF 0.39/0.44 0.19/0.20 —— V / n s Output Pad Slew Rate (Low Drive)1 tps 15 pF 35 pF 0.21/0.22 0.09/0.1 —— V / n s Output Pad di/dt (Max Drive) tdit — — — 70 mA/ns Output Pad di/dt (High Drive) tdit — — — 53 mA/ns Output Pad di/dt (Medium drive) tdit — — — 35 mA/ns Output Pad di/dt (Low drive) tdit — — — 18 mA/ns Input T ransition Times 2 trm — — — 25 ns 1 tps is measured between VIL to VIH for rising edge and between VIH to VIL for falling edge. 2 Hysteresis mode is recommended for inputs with transition time greater than 25 ns. Table 22. LPDDR2 I/O DDR2 mode AC Characteristics 1 Table 21. GPIO I/O AC Parameters Fast Mode (continued)

i.MX53 Applications Processors for Industrial Products, Rev. 6 Freescale Semiconductor 39 Table 23 shows the AC parameters for LPDDR2 I/O operating in LPDDR2 mode. Table 24 shows the AC parameters for LPDDR2 I/O operating in DDR3 mode. 2 Vid(ac) specifies the input differential voltage | Vtr - Vcp | required for switching, where Vtr is the “true” input signal and V cp is the “complementary” input signal. The Minimum value is equal to Vih(ac) - Vil(ac). 3 The typical value of Vix(ac) is expected to be about 0.5 x OVDD. and Vix(ac) is expected to track variation of OVDD. Vix(ac) indicates the voltage at which differential input signal must cross. 4 The typical value of Vox(ac) is expected to be about 0.5 x OVDD and Vox(ac) is expected to track variation in OVDD. Vox(ac) indicates the voltage at which differential output signal must cross. Table 23. LPDDR2 I/O LPDDR2 mode AC Characteristics 1 1 Note that the JEDEC LPDDR2 specification (JESD209_2B) supersedes any specification in this document. is the “complementary” input signal. The Minimum value is equal to Vih(ac) - Vil(ac). indicates the voltage at which differential input signal must cross. Single output slew rate tsr 50 Ω to Vref. 5pF load. Table 24. LPDDR2 I/O DDR3 mode AC Characteristics 1

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4.5.3 LVIO I/O AC Electrical Characteristics

AC electrical characteristics for LVIO I/O in slow and fast modes are presented in the Table 25 and Table 26, respectively. Note that the fast or slow I/O behavior is determined by the appropriate control bit in the IOMUXC control registers. Single output slew rate tsr At 25 Ω to Vref 2.5 — 5 V/ns Skew between pad rise/fall asymmetry + skew caused by SSN tSKD clk = 266 MHz clk = 400 MHz —— 0 . 2 0.1 ns 1 Note that the JEDEC JESD79_3C specification supersedes any specification in this document. 2 Vid(ac) specifies the input differential voltage |Vtr-Vcp| required for switching, where Vtr is the “true” input signal and Vcp is the “complementary” input signal. The Minimum value is equal to Vih(ac) - Vil(ac). 3 The typical value of Vix(ac) is expected to be about 0.5 x OVDD. and Vix(ac) is expected to track variation of OVDD. Vix(ac) indicates the voltage at which differential input signal must cross. 4 The typical value of Vox(ac) is expected to be about 0.5 x OVDD and Vox(ac) is expected to track variation in OVDD. Vox(ac) indicates the voltage at which differential output signal must cross. Table 25. LVIO I/O AC Parameters in Slow Mode 1 Hysteresis mode is recommended for inputs with transition times greater than 25 ns. Table 24. LPDDR2 I/O DDR3 mode AC Characteristics 1 (continued)

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4.5.4 UHVIO I/O AC Electrical Characteristics

Table 27 shows the AC parameters for UHVIO I/O operating in low output voltage mode. Table 28 shows the AC parameters for UHVIO I/O operating in high output voltage mode. Table 26. LVIO I/O AC Parameters in Fast Mode 1 Hysteresis mode is recommended for inputs with transition time greater than 25 ns. Table 27. AC Electrical Characteristics of UHVIO Pad (Low Output Voltage Mode) 1 tps is measured between VIL to VIH for rising edge and between VIH to VIL for falling edge. 2 Hysteresis mode is recommended for inputs with transition times greater than 25 ns. Table 28. AC Electrical Characteristics of UHVIO Pad (High Output Voltage Mode)

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4.5.5 LVDS I/O AC Electrical Characteristics

The differential output transition time waveform is shown in Figure 7. Figure 7. Differential LVDS Driver Transition Time Waveform Table 29 shows the AC parameters for LVDS I/O. 1 tps is measured between VIL to VIH for rising edge and between VIH to VIL for falling edge. 2 Hysteresis mode is recommended for inputs with transition times greater than 25 ns. Table 29. AC Electrical Characteristics of LVDS Pad 1 Measurement levels are 20–80% from output voltage. Table 28. AC Electrical Characteristics of UHVIO Pad (High Output Voltage Mode) (continued)

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4.6 System Modules Timing

This section contains the timing and electrical parameters for the modules in the i.MX53 processor.

4.6.1 Reset Timings Parameters

Figure 8 shows the reset timing and Table 30 lists the timing parameters. Figure 8. Reset Timing Diagram

4.6.2 WDOG Reset Timing Parameters

Figure 9 shows the WDOG reset timing and Table 31 lists the timing parameters. Figure 9. WATCHDOG_RST Timing Diagram CKIL is approximately 32 kHz. TCKIL is one period or approximately 30 μs.

4.6.3 Clock Amplifier Parameters (CKIH1, CKIH2)

or sinusoidal frequency source. No external series capacitors are required. Table 30. Reset Timing Parameters Table 31. WATCHDOG_RST Timing Parameters

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Table 32 shows the electrical parameters of CAMP.

4.6.4 DPLL Electrical Parameters

Table 33 shows the electrical parameters of digital phase-locked loop (DPLL). Table 32. CAMP Electrical Parameters (CKIH1, CKIH2) 1 NVCC_CKIH is the supply voltage of CAMP. Table 33. DPLL Electrical Parameters 1 Device input range cannot exceed the electrical specifications of the CAMP, see Table 32. the user has to enter a value “1” less than the desired value at the inputs of DPLL for PDF and MFD.

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4.6.5 NAND Flash Controller (NFC) Parameters

This section provides the relative timing requirements among various signals of NFC at the module level, in each operational mode. Timing parameters in Figure 10, Figure 11, Figure 12, Figure 13, Figure 15, and Table 35 show the default NFC mode (asymmetric mode) using two Flash clock cycles per one access of RE_B and WE_B. Timing parameters in Figure 10, Figure 11, Figure 12, Figure 14, Figure 15, and Table 35 show symmetric NFC mode using one Flash clock cycle per one access of RE_B and WE_B. With reference to the timing diagrams, a high is defined as 80% of signal value and low is defined as 20% of signal value. All parameters are given in nanoseconds. The BGA contact load used in calculations is 20 pF (except for NF16— 40 pF) and there is maximum drive strength on all contacts. All timing parameters are a function of T, which is the period of the flash_clk clock (“enfc_clk” at system level). This clock frequency can be controlled by the user, configuring CCM (SoC clock controller). The clock is derived from emi_slow_clk after single divider. Figure 34 demonstrates several examples of clock frequency settings. NOTE A potential limitation for minimum clock frequency may exist for some devices. When the clock frequency is too low, the data bus capturing might occur after the specified trhoh (RE_B high to output hold) period. Setting the clock frequency above 25.6 MHz (that is, T = 39 ns) guaranties a proper operation for devices having trhoh > 15 ns. It is also recommended that the NFC_FREQ_SEL Fuse be set accordingly to initiate the boot with 33.33 MHz clock. 4 Tdpdref is the time period of the reference clock after predivider. According to the specification, the maximum lock time in FOL mode is 398 cycles of divided reference clock when DPLL starts after full reset. 5 Tdck is the time period of the output clock, dpdck_2. Table 34. NFC Clock Settings Examples

1 Boot value NFC_FREQ_SEL Fuse High (burned)

2 Boot value NFC_FREQ_SEL Fuse Low

Reference Manual for details.

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Lower frequency operation can be supported for most available devices in the market, relying on data lines Bus-Keeper logic. This depends on device behavior on the data bus in the time interval between data output valid to data output high-Z state. In NAND device parameters this period is marked between t rhoh and trhz (RE_B high to output high-Z). In most devices, the data transition from valid value to high-Z occurs without going through other states. Setting the data bus pads to Bus-Keeper mode in the IOMUXC registers, keeps the data bus valid internally after the specified hold time, allowing proper capturing with slower clock. Figure 10. Command Latch Cycle Timing Figure 11. Address Latch Cycle Timing

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Figure 15. Other Timing Parameters

i.MX53 Applications Processors for Industrial Products, Rev. 6 Freescale Semiconductor 49 Table 35. NFC—Timing Characteristics symmetric mode the setup time will equal 1.5T + 0.95. EXTMC including I/O pad delay. DSR can be used to determine t REA max parameter with the following formula: t REA = 1.5T - tDSR. “emi_slow_clk” of the system, which default value is 7.5 ns (133 MHz).

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4.6.6 External Interface Module (EIM)

The following subsections provide information on the EIM.

4.6.6.1 EIM Signal Cross Reference

Table 36 is a guide intended to help the user identify signals in the External Interface Module Chapter of the Reference Manual which are identical to those mentioned in this data sheet.

4.6.6.2 EIM Interface Pads Allocation

EIM supports16-bit and 8-bit devices operating in address/data separate or multiplexed modes. In some of the modes the EIM and the NAND FLASH have shared data bus. Table 37 provides EIM interface pads allocation in different modes. 4 NF17 is defined only in asymmetric operation mode. NF17 max value is equivalent to max t RHZ value that can be used with NFC. Taclk is “emi_slow_clk” of the system. 5 NF18 is defined only in Symmetric operation mode. t DHR (MIN) is calculated by the following formula: Tdl 3 - (tREpd + tDpd) where tREpd is RE propogation delay in the chip including I/O pad delay, and tDpd is Data propogation delay from I/O pad to EXTMC including I/O pad delay. NF18 max value is equivalent to max t RHZ value that can be used with NFC. Taclk is “emi_slow_clk” of the system. Table 36. EIM Signal Cross Reference

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8 Bit 16 Bit 32 Bit 16 Bit 32 Bit

1 For 32-bit mode, the address range is A[24:0], due to address space allocation in memory map.

2 NANDF_D[7:0] multiplexed on ALT3 mode of PATA_DATA[7:0]

3 NANDF_D[15:8] multiplexed on ALT3 mode of PATA_DATA[15:8]

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4.6.6.3 General EIM Timing-Synchronous Mode

Figure 16, Figure 17, and Table 38 specify the timings related to the EIM module. All EIM output control signals may be asserted and deasserted by an internal clock synchronized to the BCLK rising edge according to corresponding assertion/negation control fields. Figure 16. EIM Outputs Timing Diagram Figure 17. EIM Inputs Timing Diagram Table 38. EIM Bus Timing Parameters 1

i.MX53 Applications Processors for Industrial Products, Rev. 6 Freescale Semiconductor 53 WE3 BCLK High Level Width 0.4 x t 0.8 x t 1.2 x t 1.6 x t WE4 Clock rise to address valid3 -0.5 x t - 1.25 -0.5 x t + 1.75 1.25 -1.5 x t +1.75 -2 x t - 1.25 -2 x t + 1.75 WE5 Clock rise to address invalid 0.5 x t - 1.25 1.25 1.5 x t + 1.75 2 x t - 1.25 2 x t + 1.75 WE6 Clock rise to CSx_B valid -0.5 x t - 1.25 -0.5 x t + 1.75 1.25 -1.5 x t + 1.75 -2 x t - 1.25 -2 x t + 1.75 WE7 Clock rise to CSx_B invalid 0.5 x t - 1.25 1.25 1.5 x t + 1.75 2 x t - 1.25 2 x t + 1.75 WE8 Clock rise to WE_B Valid -0.5 x t - 1.25 -0.5 x t + 1.75 1.25 -1.5 x t + 1.75 -2 x t - 1.25 -2 x t + 1.75 WE9 Clock rise to WE_B Invalid 0.5 x t - 1.25 1.25 1.5 x t + 1.75 2 x t - 1.25 2 x t + 1.75 WE10 Clock rise to OE_B Valid -0.5 x t - 1.25 -0.5 x t + 1.75 1.25 -1.5 x t + 1.75 -2 x t - 1.25 -2 x t + 1.75 WE11 Clock rise to OE_B Invalid 0.5 x t - 1.25 1.25 1.5 x t + 1.75 2 x t - 1.25 2 x t + 1.75 WE12 Clock rise to BEy_B Valid -0.5 x t - 1.25 -0.5 x t + 1.75 1.25 -1.5 x t + 1.75 -2 x t - 1.25 -2 x t + 1.75 WE13 Clock rise to BEy_B Invalid 0.5 x t - 1.25 1.25 1.5 x t + 1.75 2 x t - 1.25 2 x t + 1.75 WE14 Clock rise to ADV_B Valid -0.5 x t - 1.25 -0.5 x t + 1.75 1.25 -1.5 x t + 1.75 -2 x t - 1.25 -2 x t + 1.75 WE15 Clock rise to ADV_B Invalid 0.5 x t - 1.25 1.25 1.5 x t + 1.75 2 x t - 1.25 2 x t + 1.75 WE16 Clock rise to Output Data Valid -0.5 x t - 1.25 -0.5 x t + 1.75 1.25 -1.5 x t + 1.75 -2 x t - 1.25 -2 x t + 1.75 WE17 Clock rise to Output Data Invalid 0.5 x t - 1.25 1.25 1.5 x t + 1.75 2 x t - 1.25 2 x t + 1.75 WE18 Input Data setup time to Clock rise WE19 Input Data hold time from Clock rise WE20 WAIT_B setup time to Clock rise WE21 WAIT_B hold time from Clock rise Table 38. EIM Bus Timing Parameters (continued) 1

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4.6.6.4 Examples of EIM Synchronous Accesses

Figure 18 to Figure 21 provide few examples of basic EIM accesses to external memory devices with the timing parameters mentioned previously for specific control parameters settings. Figure 18. Synchronous Memory Read Access, WSC=1 3 For signal measurements “High” is defined as 80% of signal value and “Low” is defined as 20% of signal value.

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Figure 21. 16-Bit Muxed A/D Mode, Synchronous Read Access, WSC=7, RADVN=1, ADH=1, and OEA=0

4.6.6.5 General EIM Timing-Asynchronous Mode

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Figure 24. Asynchronous Memory Write Access Figure 25. Asynchronous A/D Muxed Write Access

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Table 39. EIM Asynchronous Timing Parameters Table Relative Chip Select internal driving FFs to CSx out.

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4.6.7 DDR SDRAM Specific Parameters (DDR2/LVDDR2, LPDDR2, and

DDR3) The DDR2/LVDDR2 interface fully complies with JESD79-2E – DDR2 JEDEC release April, 2008, supporting DDR2-800 and LVDDR2-800. The DDR3 interface fully complies with JESD79-3D – DDR3 JEDEC release April 2008 supporting DDR3-800. The LPDDR2 interface fully complies with JESD209-2B, supporting LPDDR2-800. WE43 Input Data Valid to CSx_B Invalid MAXCO - MAXCSO + MAXDI MAXCO - MAXCSO + MAXDI —n s WE44 CSx_B Invalid to Input Data invalid 00 — n s WE45 CSx_B Valid to BEy_B Valid (Write access) WE12 - WE6 + (WBEA - CSA) — 3 + (WBEA - CSA) ns WE46 BEy_B Invalid to CSx_B Invalid (Write access) WE7 - WE13 + (WBEN - CSN) — -3 + (WBEN - CSN) ns MAXDTI DT ACK MAXIMUM delay from chip dtack input to its internal FF + 2 cycles for synchronization —— — WE47 Dtack Active to CSx_B Invalid MAXCO - MAXCSO + MAXDTI MAXCO - MAXCSO + MAXDTI —n s WE48 CSx_B Invalid to Dtack invalid 0 0 — ns 1 Parameters WE4... WE21 value see column BCD = 0 in Table 38. 2 All config. parameters (CSA,CSN,WBEA,WBEN,ADVA,AD VN,OEN,OEA,RBEA & RBEN) are in cycle units. 3 CS Assertion. This bit field determines when CS signal is asserted during read/write cycles. 4 CS Negation. This bit field determines when CS signal is negated during read/write cycles. 5 t is axi_clk cycle time. 6 BE Assertion. This bit field determines when BE signal is asserted during read cycles. 7 BE Negation. This bit field determines when BE signal is negated during read cycles.

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Figure 28 and Table 40 show the address and control timing parameters for DDR2 and DDR3. Figure 28. DDR SDRAM Address and Control Parameters for DDR2 and DDR3 Table 40. DDR SDRAM Timing Parameter Table1 2 1 All timings are refer to Vref level cross point. 2 Reference load model is 25 Ω resistor from each of the DDR outputs to VDD_REF.

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Figure 31 and Table 43 show the data read timing parameters. Figure 31. DDR SDRAM DQ vs. DQS and SDCLK Read Cycle Table 42. DDR SDRAM Write Cycle 1 2 3 1 All timings are refer to Vref level cross point. 2 Reference load model is 25 Ω resistor from each of the DDR outputs to VDD_REF. Table 43. DDR SDRAM Read Cycle 1

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4.7 External Peripheral Interfaces Parameters

The following subsections provide information on external peripheral interfaces.

4.7.1 AUDMUX Timing Parameters

The AUDMUX provides a programmable interconnect logic for voice, audio and data routing between internal serial interfaces (SSIs) and external serial interfaces (audio and voice codecs). The AC timing of AUDMUX external pins is governed by the SSI module. For more information, see the respective SSI electrical specifications found within this document.

4.7.2 CSPI and ECSPI Timing Parameters

This section describes the timing parameters of the CSPI and ECSPI blocks. The CSPI and ECSPI have separate timing parameters for master and slave modes. The nomenclature used with the CSPI / ECSPI modules and the respective routing of these signals is shown in Table 44.

4.7.2.1 CSPI Master Mode Timing

Figure 32 depicts the timing of CSPI in master mode. Table 45 lists the CSPI master mode timing characteristics. Figure 32. CSPI/ECSPI Master Mode Timing Diagram Table 44. CSPI Nomenclature and Routing

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4.7.2.2 CSPI Slave Mode Timing

Figure 33 depicts the timing of CSPI in slave mode. Timing characteristics were not available at the time of publication. Figure 33. CSPI/ECSPI Slave Mode Timing Diagram Table 45. CSPI Master Mode Timing Parameters 2 SPI_RDY is sampled internally by ipg_clk and is asynchronous to all other CSPI signals.

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4.7.2.3 ECSPI Master Mode Timing

Figure 32 depicts the timing of ECSPI in master mode. Table 46 lists the ECSPI master mode timing characteristics.

4.7.2.4 ECSPI Slave Mode Timing

Figure 33 depicts the timing of ECSPI in slave mode. Table 47 lists the ECSPI slave mode timing characteristics. Table 46. ECSPI Master Mode Timing Parameters 2 SPI_RDY is sampled internally by ipg_clk and is asynchronous to all other CSPI signals. Table 47. ECSPI Slave Mode Timing Parameters

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4.7.3 Enhanced Serial Audio Interface (ESAI) Timing Parameters

The ESAI consists of independent transmitter and receiver sections, each section with its own clock generator. Table 48 shows the interface timing values. The number field in the table refers to timing signals found in Figure 34 and Figure 35. Table 48. Enhanced Serial Audio Interface (ESAI) Timing

62 Clock cycle 5 tSSICC 4 × Tc

63 Clock high period

64 Clock low period

65 SCKR rising edge to FSR out (bl) high —

66 SCKR rising edge to FSR out (bl) low —

67 SCKR rising edge to FSR out (wr) high 6 —

68 SCKR rising edge to FSR out (wr) low 6 —

69 SCKR rising edge to FSR out (wl) high —

70 SCKR rising edge to FSR out (wl) low —

71 Data in setup time before SCKR (SCK in synchronous

72 Data in hold time after SCKR falling edge —

73 FSR input (bl, wr) high before SCKR falling edge 6 —

74 FSR input (wl) high before SCKR falling edge —

75 FSR input hold time after SCKR falling edge —

78 SCKT rising edge to FST out (bl) high —

79 SCKT rising edge to FST out (bl) low —

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80 SCKT rising edge to FST out (wr) high 6 —

20.0 10.0 x ck i ck ns

81 SCKT rising edge to FST out (wr) low 6 —

22.0 12.0 x ck i ck ns

82 SCKT rising edge to FST out (wl) high —

19.0 9.0 x ck i ck ns

83 SCKT rising edge to FST out (wl) low —

20.0 10.0 x ck i ck ns

84 SCKT rising edge to data out enable from high

22.0 17.0 x ck i ck ns

86 SCKT rising edge to data out valid —

18.0 13.0 x ck i ck ns

87 SCKT rising edge to data out high impedance 77 —

21.0 16.0 x ck i ck ns

89 FST input (bl, wr) setup time before SCKT falling edge 6 —

2.0 18.0 x ck i ck ns

90 FST input (wl) setup time before SCKT falling edge —

2.0 18.0 x ck i ck ns

91 FST input hold time after SCKT falling edge —

4.0 5.0 x ck i ck ns

95 HCKR/HCKT clock cycle — 2 x T C 15 — — ns

96 HCKT input rising edge to SCKT output — — — 18.0 — ns 97 HCKR input rising edge to SCKR output — — — 18.0 — ns 1 VCORE_VDD= 1.00 ± 0.10V Tj = -40 °C to 125 °C CL= 50 pF 2 i ck = internal clock x ck = external clock i ck a = internal clock, asynchronous mode (asynchronous implies that SCKT and SCKR are two different clocks) i ck s = internal clock, synchronous mode (synchronous implies that SCKT and SCKR are the same clock) 3 bl = bit length wl = word length wr = word length relative

4 SCKT(SCKT pin) = transmit clock

SCKR(SCKR pin) = receive clock FST(FST pin) = transmit frame sync FSR(FSR pin) = receive frame sync HCKT(HCKT pin) = transmit high frequency clock HCKR(HCKR pin) = receive high frequency clock 5 For the internal clock, the external clock cycle is defined by Icyc and the ESAI control register. Table 48. Enhanced Serial Audio Interface (ESAI) Timing (continued)

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Figure 34. ESAI Transmitter Timing second-to-last bit clock of the first word in the frame. 7 Periodically sampled and not 100% tested.

i.MX53 Applications Processors for Industrial Products, Rev. 6 Freescale Semiconductor 71 Figure 35. ESAI Receiver Timing

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4.7.4 Enhanced Secured Digital Host Controller(eSDHCv2/v3) AC timing

This section describes the electrical information of the eSDHCv2/v3, which includes SD/eMMC4.3 (Single Data Rate) timing and eMMC4.4 (Dual Date Rate) timing. 4.7.4.1 SD/eMMC4.3 (Single Data Rate) AC Timing Figure 36 depicts the timing of SD/eMMC4.3, and Table 49 lists the SD/eMMC4.3 timing characteristics. Figure 36. SD/eMMC4.3 Timing Table 49. SD/eMMC4.3 Interface Timing Specification

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4.7.5 FEC AC Timing Parameters

This section describes the electrical information of the Fast Ethernet Controller (FEC) module. The FEC is designed to support both 10 and 100 Mbps Ethernet/IEEE 802.3 networks. An external transceiver interface and transceiver function are required to complete the interface to the media. The FEC supports the 10/100 Mbps MII (18 pins in total) and the 10 Mbps (only 7-wire interface, which uses 7 of the MII pins), for connection to an external Ethernet transceiver. For the pin list of MII and 7-wire, see the i.MX53 Reference Manual. This section describes the AC timing specifications of the FEC. The MII signals are compatible with transceivers operating at a voltage of 3.3 V .

4.7.5.1 MII Receive Signal Timing

The MII receive signal timing involves the FEC_RXD[3:0], FEC_RX_DV , FEC_RX_ER, and FEC_RX_CLK signals. The receiver functions correctly up to a FEC_RX_CLK maximum frequency of 25 MHz + 1%. There is no minimum frequency requirement but the processor clock frequency must exceed twice the FEC_RX_CLK frequency. Table 51 lists the MII receive channel signal timing parameters and Figure 38 shows MII receive signal timings. eSDHC Input / Card Outputs CMD, DAT (Reference to CLK) SD3 eSDHC Input Setup Time t ISU 2.5 — ns SD4 eSDHC Input Hold Time t IH 2.5 — ns Table 51. MII Receive Signal Timing 1 FEC_RX_DV, FEC_RX_CLK, and FEC_RXD0 have same timing in 10 Mbps 7-wire interface mode. 2 Test conditions: 25pF on each output signal. Table 50. eMMC4.4 Interface Timing Specification (continued)

i.MX53 Applications Processors for Industrial Products, Rev. 6 Freescale Semiconductor 75 Figure 38. MII Receive Signal Timing Diagram

4.7.5.2 MII Transmit Signal Timing

must exceed twice the FEC_TX_CLK frequency. diagram for the values listed in Table 52. Table 52. MII Transmit Signal Timing 1 FEC_TX_EN, FEC_TX_CLK, and FEC_TXD0 have the same timing in 10 Mbps 7-wire interface mode. 2 Test conditions: 25pF on each output signal.

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Figure 39. MII Transmit Signal Timing Diagram

4.7.5.3 MII Async Inputs Signal Timing (FEC_CRS and FEC_COL)

input timings listed in Table 53. Figure 40. MII Async Inputs Timing Diagram

4.7.5.4 MII Serial Management Channel Timing (FEC_MDIO and FEC_MDC)

Table 53. MII Async Inputs Signal Timing 1 Test conditions: 25pF on each output signal. 2 FEC_COL has the same timing in 10 Mbit 7-wire interface mode. Table 54. MII Transmit Signal Timing

i.MX53 Applications Processors for Industrial Products, Rev. 6 Freescale Semiconductor 77 Figure 41. MII Serial Management Channel Timing Diagram

4.7.5.5 RMII Mode Timing

FEC_TX_EN, FEC_TXD[1:0], FEC_RXD[1:0] and optional FEC_RX_ER. The RMII mode timings are shown in Table 55 and Figure 42. 1 Test conditions: 25pF on each output signal. Table 55. RMII Signal Timing Table 54. MII Transmit Signal Timing (continued)

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Figure 42. RMII Mode Signal Timing Diagram

4.7.6 Flexible Controller Area Network (FLEXCAN) AC Electrical

to see which pins expose Tx and Rx pins; these ports are named TXCAN and RXCAN, respectively. 1 Test conditions: 25pF on each output signal. Table 55. RMII Signal Timing (continued)

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4.7.7 I 2C Module Timing Parameters

This section describes the timing parameters of the I2C module. Figure 43 depicts the timing of I2C module, and Table 56 lists the I2C module timing characteristics. Figure 43. I2C Bus Timing Table 56. I2C Module Timing Parameters 2 The maximum hold time has only to be met if the device does not stretch the LOW period (ID no IC5) of the I2CLK signal. of 250 ns must be met. This automatically is the case if the device does not stretch the LOW period of the I2CLK signal. before the I2CLK line is released. 4 Cb = total capacitance of one bus line in pF.

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4.7.8 Image Processing Unit (IPU) Module Parameters

The purpose of the IPU is to provide comprehensive support for the flow of data from an image sensor and/or to a display device. This support covers all aspects of these activities:  Connectivity to relevant devices — cameras, displays, graphics accelerators, and TV encoders.  Related image processing and manipulation: sens or image signal processing, display processing, image conversions, and other related functions.  Synchronization and control capabilities, such as avoidance of tearing artifacts.

4.7.8.1 IPU Sensor Interface Signal Mapping

The IPU supports a number of sensor input formats. Table 57 defines the mapping of the Sensor Interface Pins used for various supported interface formats. Table 57. Camera Input Signal Cross Reference, Format and Bits Per Cycle 1 CSIx stands for CSI1 or CSI2.

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4.7.8.2 Sensor Interface Timings

There are three camera timing modes supported by the IPU. Smart camera sensors, which include imaging processing, usually support video mode transfer. They use an embedded timing syntax to replace the SENSB_VSYNC and SENSB_HSYNC signals. The timing syntax is defined by the BT.656/BT.1120 standards. This operation mode follows the recommendations of ITU BT.656/ ITU BT.1120 specifications. The only control signal used is SENSB_PIX_CLK. Start-of-frame and active-line signals are embedded in the data stream. An active line starts with a SAV code and ends with a EA V code. In some cases, digital blanking is inserted in between EA V and SA V code. The CSI decodes and filters out the timing-coding from the data stream, thus recovering SENSB_VSYNC and SENSB_HSYNC signals for internal use. On BT.656 one component per cycle is received over the SENSB_DATA bus. On BT.1120 two components per cycle are received over the SENSB_DATA bus.

4.7.8.2.2 Gated Clock Mode

The SENSB_VSYNC, SENSB_HSYNC, and SENSB_PIX_CLK signals are used in this mode. See Figure 44. Figure 44. Gated Clock Mode Timing Diagram 2 The MSB bits are duplicated on LSB bits implementing color extension. 3 The two MSB bits are duplicated on LSB bits implementing color extension. 4 YCbCr 8 bits—Supported within the BT.656 protocol (sync embedded within the data stream). processing, but only under some restrictions on the control protocol. 6 YCbCr 16 bits—Supported as a “generic data” input, with no on-the-fly processing. 7 YCbCr 16 bits—Supported as a sub-case of the YCbCr, 20 bits, under the same conditions (BT.1120 protocol). 8 YCbCr 20 bits—Supported only within the BT.1120 protocol (syncs embedded within the data stream).

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valid as long as SENSB_HSYNC is high. Data is latched at the rising edge of the valid pixel clocks. SENSB_HSYNC goes to low at the end of line. Pixel clocks then become invalid and the CSI stops receiving data from the stream. For next line the SENSB_HSYNC timing repeats. For next frame the SENSB_VSYNC timing repeats.

4.7.8.2.3 Non-Gated Clock Mode

The timing is the same as the gated-clock mode (described in Section 4.7.8.2.2, “Gated Clock Mode,”) except for the SENSB_HSYNC signal, which is not used (see Figure 45). All incoming pixel clocks are valid and cause data to be latched into the input FIFO. The SENSB_PIX_CLK signal is inactive (states low) until valid data is going to be transmitted over the bus. Figure 45. Non-Gated Clock Mode Timing Diagram active-high/low SENSB_HSYNC; and rising/falling-edge triggered SENSB_PIX_CLK.

4.7.8.3 Electrical Characteristics

the IPU. Table 58 lists the sensor interface timing characteristics. Figure 46. Sensor Interface Timing Diagram

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4.7.8.4 IPU Display Interface Signal Mapping

The IPU supports a number of display output video formats. Table 59 defines the mapping of the Display Interface Pins used during various supported video interface formats. Table 58. Sensor Interface Timing Characteristics

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Table 59. Video Signal Cross-Reference

24 Bit

Groups should not be overlapped.

i.MX53 Applications Processors for Industrial Products, Rev. 6 Freescale Semiconductor 85 DIx_DISP_CLK PixCLK — — DIx_PIN1 — VSYNC_IN May be required for anti-tearing DIx_PIN2 HSYNC — — DIx_PIN3 VSYNC — VSYNC out DIx_PIN4 — — Additional frame/row synchronous signals with programmable timing DIx_PIN5 — — DIx_PIN6 — — DIx_PIN7 — — DIx_PIN8 — — DIx_D0_CS — CS0 — DIx_D1_CS — CS1 Alternate mode of PWM output for contrast or brightness control DIx_PIN11 — WR — DIx_PIN12 — RD — DIx_PIN13 — RS1 Register select signal DIx_PIN14 — RS2 Optional RS2 DIx_PIN15 DRDY/DV DRDY Data validation/blank, data enable DIx_PIN16 — — Additional data synchronous signals with programmable features/timingDIx_PIN17 Q — 1 Signal mapping (both data and control/synchronization) is flexible. The table provides examples. 2 This mode works in compliance with recommendation ITU-R BT.656. The timing reference signals (frame start, frame end, line start, and line end) are embedded in the 8-bit data bus. Only video data is supported, transmission of non-video related data during blanking intervals is not supported. Table 59. Video Signal Cross-Reference (continued)

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Table 59 provides information for both the Disp0 and Disp1 ports. However, Disp1 port has reduced pinout depending on IOMUXC configuration and therefore may not support all the above configurations. See the IOMUXC table for details.

4.7.8.5 IPU Display Interface Timing

The IPU Display Interface supports two kinds of display accesses: synchronous and asynchronous. There are two groups of external interface pins to provide synchronous and asynchronous controls accordantly.

4.7.8.5.1 Synchronous Controls

The synchronous control changes its value as a function of a system or of an external clock. This control has a permanent period and a permanent wave form. There are special physical outputs to provide synchronous controls:  The ipp_disp_clk is a dedicated base synchronous si gnal that is used to generate a base display (component, pixel) clock for a display.  The ipp_pin_1– ipp_pin_7 are general purpose synchronous pins, that can be used to provide HSYNC, VSYNC, DRDY or any else independent signal to a display. The IPU has a system of internal binding counters for internal events (such as HSYNC/VSYCN and so on) calculation. The internal event (local start point) is synchronized with internal DI_CLK. A suitable control starts from the local start point with predefined UP and DOWN values to calculate control’s changing points with half DI_CLK resolution. A full description of the counters system can be found in the IPU chapter of the i.MX53 Reference Manual.

4.7.8.5.2 Asynchronous Controls

The asynchronous control is a data-oriented signal that changes its value with an output data according to additional internal flags coming with the data. There are special physical outputs to provide asynchronous controls, as follows:  The ipp_d0_cs and ipp_d1_cs pins are dedicated to pr ovide chip select signals to two displays.  The ipp_pin_11– ipp_pin_17 are general purpose asynchr onous pins, that can be used to provide WR. RD, RS or any other data oriented signal to display. NOTE The IPU has independent signal generators for asynchronous signals toggling. When a DI decides to put a new asynchronous data in the bus, a new internal start (local start point) is generated. The signals generators calculate predefined UP and DOWN values to change pins states with half DI_CLK resolution.

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4.7.8.6 Synchronous Interfaces to Standard Active Matrix TFT LCD Panels

4.7.8.6.1 IPU Display Operating Signals

The IPU uses four control signals and data to operate a standard synchronous interface:  IPP_DISP_CLK—Clock to display  HSYNC—Horizontal synchronization  VSYNC—Vertical synchronization  DRDY—Active data All synchronous display controls are generated on the base of an internally generated “local start point”. The synchronous display controls can be placed on time axis with DI’s offset, up and down parameters. The display access can be whole number of DI clock (Tdiclk) only. The IPP_DA TA can not be moved relative to the local start point. The data bus of the synchronous interface is output direction only.

4.7.8.6.2 LCD Interface Functional Description

Figure 47 depicts the LCD interface timing for a generic active matrix color TFT panel. In this figure signals are shown with negative polarity. The sequence of events for active matrix interface timing is:  DI_CLK internal DI clock, used for calculation of other controls.  IPP_DISP_CLK latches data into the panel on its negative edge (when positive polarity is selected). In active mode, IPP_DISP_CLK runs continuously.  HSYNC causes the panel to start a new line. (Usually IPP_PIN_2 is used as HSYNC.)  VSYNC causes the panel to start a new frame. It always encompasses at least one HSYNC pulse. (Usually IPP_PIN_3 is used as VSYNC.)  DRDY acts like an output enable signal to the CRT display. This output enables the data to be shifted onto the display. When disabled, the data is invalid and the trace is off. (DRDY can be used either synchronous or asynchronous generic purpose pin as well.) Figure 47. Interface Timing Diagram for TFT (Active Matrix) Panels

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4.7.8.6.3 TFT Panel Sync Pulse Timing Diagrams

Figure 48 depicts the horizontal timing (timing of one line), including both the horizontal sync pulse and the data. All the parameters shown in the figure are programmable. All controls are started by corresponding internal events—local start points. Th e timing diagrams correspond to inverse polarity of the IPP_DISP_CLK signal and active-low polarity of the HSYNC, VSYNC, and DRDY signals. Figure 48. TFT Panels Timing Diagram—Horizontal Sync Pulse Figure 49. TFT Panels Timing Diagram—Vertical Sync Pulse

i.MX53 Applications Processors for Industrial Products, Rev. 6 Freescale Semiconductor 89 Table 60 shows timing characteristics of signals presented in Figure 48 and Figure 49. Table 60. Synchronous Display Interface Timing Characteristics (Pixel Level) FW—with of active line in interface clocks. be built by suitable DI’s counter. built by suitable DI’s counter.

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The maximal accuracy of UP/DOWN edge of controls is: IP5o Offset of IPP_DISP_CLK Todicp DISP_CLK_OFFSET × Tdiclk DISP_CLK_OFFSET—offset of IPP_DISP_CLK edges from local start point, in DI_CLK×2 (0.5 DI_CLK Resolution) Defined by DISP_CLK counter ns IP13o Offset of VSYNC Tovs VSYNC_OFFSET × Tdiclk VSYNC_OFFSET—offset of Vsync edges from a local start point, when a Vsync should be active, in DI_CLK (0.5 DI_CLK Resolution).The VSYNC_OFFSET should be built by suitable DI’s counter. ns IP8o Offset of HSYNC T ohs HSYNC_OFFSET × Tdiclk HSYNC_OFFSET—offset of Hsync edges from a local start point, when a Hsync should be active, in DI_CLK (0.5 DI_CLK Resolution).The HSYNC_OFFSET should be built by suitable DI’s counter. ns IP9o Offset of DRDY Todrdy DRDY_OFFSET × Tdiclk DRDY_OFFSET—offset of DRDY edges from a suitable local start point, when a corresponding data has been set on the bus, in DI_CLK (0.5 DI_CLK Resolution) The DRDY_OFFSET should be built by suitable DI’s counter. ns 1 Display interface clock period immediate value. DISP_CLK_PERIOD—number of DI_CLK per one Tdicp. Resolution 1/16 of DI_CLK. DI_CLK_PERIOD—relation of between programing clock frequency and current system clock frequency Display interface clock period average value. 2 DI’s counter can define offset, period and UP/DOWN characteristic of output signal according to programed parameters of the counter. Same of parameters in the table are not defined by DI’s registers directly (by name), but can be generated by corresponding DI’s counter. The SCREEN_WIDTH is an input value for DI’s HSYNC generation counter. The distance between HSYNCs is a SCREEN_WIDTH. Table 60. Synchronous Display Interface Timing Characteristics (Pixel Level) (continued)

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4.7.8.7 Interface to a TV Encoder (TVDAC)

The interface has an 8-bit data bus, transferring a single 8-bit value (Y/U/V) in each cycle. The timing of the interface is described in Figure 51. NOTE  The frequency of the clock DISP_CLK is 27 MHz (within 10%)  The HSYNC, VSYNC signals are active low.  The DRDY signal is shown as active high.  The transition to the next row is marked by the negative edge of the HSYNC signal. It remains low for a single clock cycle.  The transition to the next field/fram e is marked by the negative edge of the VSYNC signal. It remains low for at least one clock cycles. — At a transition to an odd field (of the next frame), the negative edges of VSYNC and HSYNC coincide. — At a transition is to an even field (of the same frame), they do not coincide.  The active intervals—during which da ta is transferred—are marked by the HSYNC signal being high.

2 Display interface clock down time

3 Display interface clock up time where CEIL(X) rounds the elements of X to the nearest integers towards infinity. Tdicd 1 2---T diclk ceil× 2 DISP_CLK_DOWN× ⎛⎞= Tdicu 1 2---T diclk ceil× 2 DISP_CLK_UP× ⎛⎞=

i.MX53 Applications Processors for Industrial Products, Rev. 6 Freescale Semiconductor 93 Figure 51. TV Encoder Interface Timing Diagram

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4.7.8.7.1 TVEv2 TV Encoder Performance Specifications

The TV encoder output specifications are shown in Table 62. All the parameters in the table are defined under the following conditions: R set = 1.05 kΩ ±1%, resistor on TVDAC_VREF pin to GND R load = 37.5 Ω ±1%, output load to the GND Table 62. TV Encoder Video Performance Specifications

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4.7.8.8 Asynchronous Interfaces

The following sections describes the types of asynchronous interfaces.

4.7.8.8.1 Standard Parallel Interfaces

The IPU has four signal generator machines for asynchronous signal. Each machine generates IPU’s internal control levels (0 or 1) by UP and DOWN that are defined in registers. Each asynchronous pin has a dynamic connection with one of the signal generators. This connection is redefined again with a new display access (pixel/component). The IPU can generate control signals according to system 80/68 requirements. The burst length is received as a result from predefined behavior of the internal signal generator machines. The access to a display is realized by the following:  CS (IPP_CS) chip select  WR (IPP_PIN_11) write strobe  RD (IPP_PIN_12) read strobe  RS (IPP_PIN_13) Register select (A0) Both system 80 and system 68k interfaces are supported for all described modes as depicted in Figure 52, Figure 53, Figure 54, and Figure 55. The timing images correspond to active-low IPP_CS, WR and RD signals. Each asynchronous access is defined by an access size parameter. This parameter can be different between different kinds of accesses. This parameter defines a length of windows, when suitable controls of the current access are valid. A pause between two different display accesses can be guaranteed by programing suitable access sizes. There are no minimal/maximal hold/setup times hard defined by DI. Each control signal can be switched at any time during access size. Chroma/Luma Delay Inequality — — 1.0 — ±ns VIDEO PERFORMANCE IN HD MODE 2 Luma Frequency Response 0–30 MHz -0.2 — 0.2 dB Chroma Frequency Response 0–15 MHz, YCbCr 422 mode -0.2 — 0.2 dB Luma Nonlinearity — — 3.2 — % Chroma Nonlinearity — — 3.4 — % Luma Signal-to-Noise Ratio 0–30 MHz — 62 — dB Chroma Signal-to-Noise Ratio 0–15 MHz — 72 — dB 1 Guaranteed by design. 2 Guaranteed by characterization. Table 62. TV Encoder Video Performance Specifications (continued)

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Figure 52. Asynchronous Parallel System 80 Interface (Type 1) Timing Diagram

i.MX53 Applications Processors for Industrial Products, Rev. 6 Freescale Semiconductor 97 Figure 53. Asynchronous Parallel System 80 Interface (Type 2) Timing Diagram

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Figure 54. Asynchronous Parallel System 68k Interface (Type 1) Timing Diagram

i.MX53 Applications Processors for Industrial Products, Rev. 6 Freescale Semiconductor 99 Figure 55. Asynchronous Parallel System 68k Interface (Type 2) Timing Diagram IPP_WAIT release. Figure 56 shows timing of the parallel interface with IPP_WAIT control.

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Figure 56. Parallel Interface Timing Diagram—Read Wait States

4.7.8.8.2 Asynchronous Parallel Interface Timing Parameters

on active low control signals (signals polarity is controlled through the DI_DISP_SIG_POL register).

i.MX53 Applications Processors for Industrial Products, Rev. 6 Freescale Semiconductor 101 Figure 57. Asynchronous Parallel Interface Timing Diagram Table 63. Asynchronous Display Interface Timing Parameters (Pixel Level)

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Table 64. Asynchronous Parallel Interface Timing Parameters (Access Level) 1The exact conditions have not been finalized, but will likely match the current customer requirement for their specific display . These conditions may be chip specific. ACCESS_SIZE is predefined in REGISTER. DISP_DOWN is predefined in REGISTER. DISP_UP is predefined in REGISTER. DISP_DOWN is predefined in REGISTER. DISP_UP is predefined in REGISTER.

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4.7.9 LVDS Display Bridge (LDB) Module Parameters

The LVDS interface complies with TIA/EIA 644-A standard. For more details, see TIA/EIA STANDARD 644-A, “Electrical Characteristics of Low V oltage Differential Signaling (LVDS) Interface Circuits”.

4.7.10 One-Wire (OWIRE) Timing Parameters

Figure 58 depicts the RPP timing, and Table 65 lists the RPP timing parameters. Figure 58. Reset and Presence Pulses (RPP) Timing Diagram DISP_DOWN is predefined in REGISTER. DISP_UP is predefined in REGISTER. Table 65. RPP Sequence Delay Comparisons Timing Parameters 1 In order not to mask signaling by other devices on the 1-Wire bus, t RSTL + tR should always be less than 960 µs.

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Figure 59 depicts Write 0 Sequence timing, and Table 66 lists the timing parameters. Figure 59. Write 0 Sequence Timing Diagram lists the timing parameters. Figure 60. Write 1 Sequence Timing Diagram Figure 61. Read Sequence Timing Diagram Table 66. WR0 Sequence Timing Parameters

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4.7.11 Pulse Width Modulator (PWM) Timing Parameters

This section describes the electrical information of the PWM. The PWM can be programmed to select one of three clock signals as its source frequency. The selected clock signal is passed through a prescaler before being input to the counter. The output is available at the pulse-width modulator output (PWMO) external pin. Figure 62 depicts the timing of the PWM, and Table 68 lists the PWM timing parameters. Figure 62. PWM Timing Table 67. WR1 /RD Timing Parameters Table 68. PWM Output Timing Parameter

1 System CLK frequency 1

1 CL of PWMO = 30 pF

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4.7.12 PATA Timing Parameters

This section describes the timing parameters of the Parallel A TA module which are compliant with A TA/A TAPI-6 specification. Parallel A TA module can work on PIO/Multi-Word DMA/Ultra DMA transfer modes. Each transfer mode has different data transfer rate, Ultra DMA mode 4 data transfer rate is up to 100MB/s. Parallel A TA module interface consist of a total of 29 pins. Some pins act on different function in different transfer mode. There are different requirements of timing relationships among the function pins conform with A TA/A TAPI-6 specification and these requirements are configurable by the ATA module registers. Table 69 and Figure 63 define the AC characteristics of all the PATA interface signals in all data transfer modes. Figure 63. PATA Interface Signals Timing Diagram operation is needed, this may not be compatible with bus buffers. Another area of attention is the slew rate limit imposed by the ATA specification on the ATA bus. a 40 pF load. Not many vendors of bus buffers specify slew rate of the outgoing signals. signal is such that contention on the host and device tri-state busses is always avoided. Table 69. AC Characteristics of All Interface Signals amplitude with all capacitive loads from 15 –40 pF where all signals have the same capacitive load value.

i.MX53 Applications Processors for Industrial Products, Rev. 6 Freescale Semiconductor 107 In the timing equations, some timing parameters are used. These parameters depend on the implementation of the i.MX53 PATA interface on silicon, the bus buffer used, the cable delay and cable skew. Table 70 shows ATA timing parameters. Table 70. PATA Timing Parameters 1 Values provided where applicable.

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4.7.12.1 PIO Mode Read Timing

Figure 64 shows timing for PIO read. Table 71 lists the timing parameters for PIO read. Figure 64. PIO Read Timing Diagram Table 71. PIO Read Timing Parameters

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Figure 66 shows timing for MDMA read, Figure 67 shows timing for MDMA write, and Table 73 lists the timing parameters for MDMA read and write. Figure 66. MDMA Read Timing Diagram Figure 67. MDMA Write Timing Diagram Table 73. MDMA Read and Write Timing Parameters

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4.7.12.2 Ultra DMA (UDMA) Input Timing

Figure 68 shows timing when the UDMA in transfer starts, Figure 69 shows timing when the UDMA in host terminates transfer, Figure 70 shows timing when the UDMA in device terminates transfer, and Table 74 lists the timing parameters for UDMA in burst. Figure 68. UDMA in Transfer Starts Timing Diagram 1 tk1 in the MDMA figures ( Figure 66 and Figure 67) equals (tk - 2 x T). 2 tk1 in the MDMA figures equals (tk – 2 x T). Table 73. MDMA Read and Write Timing Parameters (continued)

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Figure 69. UDMA in Host Terminates Transfer Timing Diagram Figure 70. UDMA in Device Terminates Transfer Timing Diagram Table 74. UDMA in Burst Timing Parameters

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4.7.12.3 UDMA Output Timing

Figure 71 shows timing when the UDMA out transfer starts, Figure 72 shows timing when the UDMA out host terminates transfer, Figure 73 shows timing when the UDMA out device terminates transfer, and Table 75 lists the timing parameters for UDMA out burst. Figure 71. UDMA Out Transfer Starts Timing Diagram active edge on the DSTROBE signal. The equation given on this line tries to capture this constraint. 2 Make ton and toff big enough to avoid bus contention. Table 74. UDMA in Burst Timing Parameters (continued)

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Figure 72. UDMA Out Host Terminates Transfer Timing Diagram Figure 73. UDMA Out Device Terminates Transfer Timing Diagram Table 75. UDMA Out Burst Timing Parameters

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4.7.13 SATA PHY Parameters

This section describes SATA PHY electrical specifications.

4.7.13.1 Reference Clock Electrical and Jitter Specifications

The refclk signal is differential and supports frequencies of 25 MHz or 50-156.25 MHz (100 MHz and 125 MHz are common frequencies). The frequency is pin-selectable (for more information about the signal, see “Per-Transceiver Control and Status Signals” in the SA TA PHY chapter in the Reference Manual). Table 76 provides the SATA PHY reference clock specifications. trfs1 trfs trfs = 1.6 × T + tsui + tco + tbuf + tbuf — — tdzfs tdzfs = time_dzfs × T - (tskew1) time_dzfs tss tss tss = time_ss × T - (tskew1 + tskew2) time_ss tmli tdzfs_mli tdzfs_mli =max (time_dzfs, time_mli) × T - (tskew1 + tskew2) — tli tli1 tli1 > 0 — tli tli2 tli2 > 0 — tli tli3 tli3 > 0 — tcvh tcvh tcvh = (time_cvh ×T) - (tskew1 + tskew2) time_cvh —t o n toff ton = time_on × T - tskew1 toff = time_off × T - tskew1 Table 76. Reference Clock Specifications Table 75. UDMA Out Burst Timing Parameters (continued)

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4.7.13.1.1 Reference Clock Jitter Measurement

The total phase jitter on the reference clock is specified at 3 ps RMS. There are numerous ways to measure the reference clock jitter, one of which is as follows. Using a high-speed sampling scope (20 GSamples/s), 1 million samples of the differential reference clock are taken, and the zero-crossing times of each rising edge are calculated. From the zero-crossing data, an average reference clock period is calculated. This average reference clock period is subtracted from each sequential, instantaneous period to find the difference between each reference clock rising edge and the ideal placement to produce the phase jitter sequence. The power spectral density (PSD) of the phase jitter is calculated and integrated after being weighted with the transfer function shown in Figure 74. The square root of the resultant integral is the RMS total phase jitter. Figure 74. Weighting Function for RMS Phase Jitter Calculation

4.7.13.2 Transmitter and Receiver Characteristics

as provide information about parameters not defined in the standard.

4.7.13.2.1 SATA PHY Transmitter Characteristics

Table 77 provides specifications for SATA PHY transmitter characteristics. Table 77. SATA2 PHY Transmitter Characteristics

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4.7.13.2.2 SATA PHY Receiver Characteristics

Table 78 provides specifications for SATA PHY receiver characteristics.

4.7.13.3 SATA_REXT Reference Resistor Connection

The impedance calibration process requires connection of reference resistor 191 Ω. 1% precision resistor on SATA_REXT pad to ground. Resistor calibration consists of learning which state of the internal Resistor Calibration register causes an internal, digitally trimmed calibration resistor to best match the impedance applied to the SATA_REXT pin. The calibration register value is then supplied to all Tx and Rx termination resistors. During the calibration process (for a few tens of microseconds), up to 0.3 mW can be dissipated in the external SATA_REXT resistor. At other times, no power is dissipated by the SATA_REXT resistor.

4.7.13.4 SATA Connectivity When Not in Use

The Temperature Sensor is part of the SATA module. If SA TA IP is disabled, the Temperature Sensor will not work as well. Temperature Sensor functionality is important in supporting high performance applications without overheating the device (at high ambient temp). When both SA TA and thermal sensor are not required, connect VP and VPH supplies to ground. The rest of the ports, both inputs and outputs (SATA_REFCLKM, SA TA_REFCLKP, SATA_REXT, SATA_RXM, SA TA_RXP, SA TA_TXM) can be left floating. It is not recommended to turn off the VPH while the VP is active. When SA TA is not in use but thermal sensor is still required, both VP and VPH supplies must be powered on according to their nominal voltage levels. The reference clock input frequency must fall within the specified range of 25 MHz to 156.25 MHz. SA TA_REXT does not need to be connected, as the termination impedance is not of consequence. Table 78. SATA PHY Receiver Characteristics

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4.7.14 SCAN JTAG Controller (SJC) Timing Parameters

Figure 75 depicts the SJC test clock input timing. Figure 76 depicts the SJC boundary scan timing. Figure 77 depicts the SJC test access port. Signal parameters are listed in Table 79. Figure 75. Test Clock Input Timing Diagram Figure 76. Boundary Scan (JTAG) Timing Diagram

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4.7.15 SPDIF Timing Parameters

The Sony/Philips Digital Interconnect Format (SPDIF) data is sent using the bi-phase marking code. When encoding, the SPDIF data signal is modulated by a clock that is twice the bit rate of the data signal. Table 80 and Figures , show SPDIF timing parameters for the Sony/Philips Digital Interconnect Format (SPDIF), including the timing of the modulating Rx clock (SRCK) for SPDIF in Rx mode and the timing of the modulating Tx clock (STCLK) for SPDIF in Tx mode. SJ9 TMS, TDI data hold time 25 — ns SJ10 TCK low to TDO data valid — 44 ns SJ11 TCK low to TDO high impedance — 44 ns SJ12 TRST assert time 100 — ns SJ13 TRST set-up time to TCK low 40 — ns

1 TDC = target frequency of SJC

2 VM = mid-point voltage

Table 80. SPDIF Timing Parameters Table 79. JTAG Timing (continued)

i.MX53 Applications Processors for Industrial Products, Rev. 6 Freescale Semiconductor 121 Figure 79. SPDIF Timing Diagram Figure 80. STCLK Timing

4.7.16 SSI Timing Parameters

synchronous interfaces are summarized in Table 81. Word Length (WL) and Bit Length (BL). chapter as AUD3_TXC appears in the timing diagram as TXC. Table 81. AUDMUX Port Allocation

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4.7.16.1 SSI Transmitter Timing with Internal Clock

Figure 81 depicts the SSI transmitter internal clock timing and Table 82 lists the timing parameters for the SSI transmitter internal clock. Figure 81. SSI Transmitter Internal Clock Timing Diagram Table 82. SSI Transmitter Timing with Internal Clock

i.MX53 Applications Processors for Industrial Products, Rev. 6 Freescale Semiconductor 123 NOTE  All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync (TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures.  All timings are on Audiomux Pads when SSI is being used for data transfer.  The terms WL and BL refer to Word Length (WL) and Bit Length (BL).  “Tx” and “Rx” refer to the Transmit and Receive sections of the SSI.  For internal Frame Sync operation using external clock, the FS timing is same as that of Tx Data (for example, during AC97 mode of operation). SS17 (Tx) CK high to STXD high/low — 15.0 ns SS18 (Tx) CK high to STXD high impedance — 15.0 ns SS19 STXD rise/fall time — 6.0 ns Synchronous Internal Clock Operation SS42 SRXD setup before (Tx) CK falling 10.0 — ns SS43 SRXD hold after (Tx) CK falling 0.0 — ns SS52 Loading — 25.0 pF Table 82. SSI Transmitter Timing with Internal Clock (continued)

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4.7.16.2 SSI Receiver Timing with Internal Clock

Figure 82 depicts the SSI receiver internal clock timing and Table 83 lists the timing parameters for the receiver timing with the internal clock Figure 82. SSI Receiver Internal Clock Timing Diagram Table 83. SSI Receiver Timing with Internal Clock

i.MX53 Applications Processors for Industrial Products, Rev. 6 Freescale Semiconductor 125 NOTE  All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync (TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures.  All timings are on Audiomux Pads when SSI is being used for data transfer.  “Tx” and “Rx” refer to the Transmit and Receive sections of the SSI.  The terms WL and BL refer to Word Length (WL) and Bit Length (BL).  For internal Frame Sync operation using external clock, the FS timing is same as that of Tx Data (for example, during AC97 mode of operation). Oversampling Clock Operation SS47 Oversampling clock period 15.04 — ns SS48 Oversampling clock high period 6.0 — ns SS49 Oversampling clock rise time — 3.0 ns SS50 Oversampling clock low period 6.0 — ns SS51 Oversampling clock fall time — 3.0 ns Table 83. SSI Receiver Timing with Internal Clock (continued)

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4.7.16.3 SSI Transmitter Timing with External Clock

Figure 83 depicts the SSI transmitter external clock timing and Table 84 lists the timing parameters for the transmitter timing with the external clock Figure 83. SSI Transmitter External Clock Timing Diagram Table 84. SSI Transmitter Timing with External Clock

i.MX53 Applications Processors for Industrial Products, Rev. 6 Freescale Semiconductor 127 NOTE  All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync (TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures.  All timings are on Audiomux Pads when SSI is being used for data transfer.  “Tx” and “Rx” refer to the Transmit and Receive sections of the SSI.  The terms WL and BL refer to Word Length (WL) and Bit Length (BL).  For internal Frame Sync operation using external clock, the FS timing is same as that of Tx Data (for example, during AC97 mode of operation). SS39 (Tx) CK high to STXD high impedance — 15.0 ns Synchronous External Clock Operation SS44 SRXD setup before (Tx) CK falling 10.0 — ns SS45 SRXD hold after (Tx) CK falling 2.0 — ns SS46 SRXD rise/fall time — 6.0 ns Table 84. SSI Transmitter Timing with External Clock (continued)

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4.7.16.4 SSI Receiver Timing with External Clock

Figure 84 depicts the SSI receiver external clock timing and Table 85 lists the timing parameters for the receiver timing with the external clock. Figure 84. SSI Receiver External Clock Timing Diagram Table 85. SSI Receiver Timing with External Clock

i.MX53 Applications Processors for Industrial Products, Rev. 6 Freescale Semiconductor 129 NOTE  All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync (TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures.  All timings are on Audiomux Pads when SSI is being used for data transfer.  “Tx” and “Rx” refer to the Transmit and Receive sections of the SSI.  The terms WL and BL refer to Word Length (WL) and Bit Length (BL).  For internal Frame Sync operation using external clock, the FS timing is same as that of Tx Data (for example, during AC97 mode of operation).

4.7.17 UART I/O Configuration and Timing Parameters

4.7.17.1 UART RS-232 I/O Configuration in Different Modes

The i.MX53 UART interfaces can serve both as DTE or DCE device. This can be configured by the DCEDTE control bit (default 0 — DCE mode). Table 86 shows the UART I/O configuration based on the enabled mode.

4.7.17.2 UART RS-232 Serial Mode Timing

The following sections describe the electrical information of the UART module in the RS-232 mode.

4.7.17.2.1 UART Transmitter

Figure 85 depicts the transmit timing of UART in the RS-232 serial mode, with 8 data bit/1 stop bit format. Table 87 lists the UART RS-232 serial mode transmit timing characteristics. Table 86. UART I/O Configuration vs. Mode

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Figure 85. UART RS-232 Serial Mode Transmit Timing Diagram

4.7.17.2.2 UART Receiver

serial mode receive timing characteristics. Figure 86. UART RS-232 Serial Mode Receive Timing Diagram

4.7.17.3 UART IrDA Mode Timing

The following subsections give the UART transmit and receive timings in IrDA mode.

4.7.17.3.3 UART IrDA Mode Transmitter

the transmit timing characteristics. Table 87. RS-232 Serial Mode Transmit Timing Parameters 1 Fbaud_rate: Baud rate frequency. The maximum baud rate the UART can support is ( ipg_perclk frequency)/16. 2 Tref_clk: The period of UART reference clock ref_clk (ipg_perclk after RFDIV divider). Table 88. RS-232 Serial Mode Receive Timing Parameters 2 Fbaud_rate: Baud rate frequency. The maximum baud rate the UART can support is ( ipg_perclk frequency)/16.

i.MX53 Applications Processors for Industrial Products, Rev. 6 Freescale Semiconductor 131 Figure 87. UART IrDA Mode Transmit Timing Diagram

4.7.17.3.4 UART IrDA Mode Receiver

receive timing characteristics. Figure 88. UART IrDA Mode Receive Timing Diagram Table 89. IrDA Mode Transmit Timing Parameters 1 Fbaud_rate: Baud rate frequency. The maximum baud rate the UART can support is ( ipg_perclk frequency)/16. 2 Tref_clk: The period of UART reference clock ref_clk (ipg_perclk after RFDIV divider). Table 90. IrDA Mode Receive Timing Parameters 2 Fbaud_rate: Baud rate frequency. The maximum baud rate the UART can support is ( ipg_perclk frequency)/16.

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4.7.18 USB-OH-3 Parameters

This section describes the electrical parameters of the USB OTG port and USB HOST ports. For on-chip USB PHY parameters see Section 4.7.19, “USB PHY Parameters.”

4.7.18.1 Serial Interface

In order to support four serial different interfaces, the USB serial transceiver can be configured to operate in one of four modes:  DA T_SE0 bidirectional, 3-wire mode  DA T_SE0 unidirectional, 6-wire mode  VP_VM bidirectional, 4-wire mode  VP_VM unidirectional, 6-wire mode

4.7.18.1.1 DAT_SE0 Bidirectional Mode

Figure 89. USB Transmit Waveform in DAT_SE0 Bidirectional Mode Table 91. Signal Definitions — DAT_SE0 Bidirectional Mode

i.MX53 Applications Processors for Industrial Products, Rev. 6 Freescale Semiconductor 133 Figure 90. USB Receive Waveform in DAT_SE0 Bidirectional Mode Table 92. Definitions of USB Waveform in DAT_SE0 Bi — Directional Mode

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4.7.18.1.2 DAT_SE0 Unidirectional Mode

Figure 91. USB Transmit Waveform in DAT_SE0 Unidirectional Mode Table 93. Signal Definitions — DAT_SE0 Unidirectional Mode

i.MX53 Applications Processors for Industrial Products, Rev. 6 Freescale Semiconductor 135 Figure 92. USB Receive Waveform in DAT_SE0 Unidirectional Mode Table 94. USB Port Timing Specification in DAT_SE0 Unidirectional Mode

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4.7.18.1.3 VP_VM Bidirectional Mode

Figure 93. USB Transmit Waveform in VP_VM Bidirectional Mode Figure 94. USB Receive Waveform in VP_VM Bidirectional Mode Table 95. Signal Definitions — VP_VM Bidirectional Mode

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4.7.18.1.4 VP_VM Unidirectional Mode

Figure 95. USB Transmit Waveform in VP_VM Unidirectional Mode Table 96. USB Port Timing Specification in VP_VM Bidirectional Mode Table 97. Signal Definitions — VP_VM Unidirectional Mode

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Figure 96. USB Receive Waveform in VP_VM Unidirectional Mode Table 98. USB Timing Specification in VP_VM Unidirectional Mode

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4.7.18.2 Parallel Interface (Normal ULPI) Timing

Electrical and timing specifications of Parallel Interface (Normal ULPI) for Host Port2 and Port3 are presented in the subsequent sections. Figure 97. USB Transmit/Receive Waveform in Parallel Mode

4.7.19 USB PHY Parameters

This section describes the USB-OTG PHY and the USB Host port PHY parameters.

4.7.19.1 USB PHY AC Parameters

Table 101 lists the AC timing parameters for USB PHY . Table 99. Signal Definitions — Parallel Interface (Normal ULPI) USB_Clk In Interface clock. All interface signals are synchronous to Clock. ownership is determined by Dir. USB_Dir In Direction. Control the direction of the Data bus. data stream currently on the bus. USB_Nxt In Next. The PHY asserts this signal to throttle the data. Table 100. USB Timing Specification for Normal ULPI Mode

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4.7.19.2 USB PHY Additional Electrical Parameters

Table 102 lists the parameters for additional electrical characteristics for USB PHY .

4.7.19.3 USB PHY System Clocking (SYSCLK)

Table 103 lists the USB PHY system clocking parameters. Table 101. USB PHY AC Timing Parameters

12 Mbps

480 Mbps

Table 102. Additional Electrical Characteristics for USB PHY Table 103. USB PHY System Clocking Parameters

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4.7.19.4 USB PHY Voltage Thresholds

Table 104 lists the USB PHY voltage thresholds.

4.7.19.5 USB PHY Termination

USB driver impedance in FS and HS modes is 45 Ω ±10% (steady state). No external resistors required.

4.8 XTAL Electrical Specifications

Table 105 shows the XTALOSC electrical specifications. Table 106 shows the XTALOSC_32K electrical specifications.

4.9 Integrated LDO Voltage Regulators Parameters

The PLL supplies VDD_DIG_PLL and VDD_ANA_PLL can be powered ON from internal LDO voltage regulator (default case). In this case VDD_REG is used as internal regulator’s power source. The regulator’s output can be used as a supply for other domains such as VDDA and VDDAL1. Table 107 shows the VDD_DIG_PLL and VDD_ANA_PLL Integrated V oltage Regulators Parameters. Table 104. VBUS Comparators Thresholds

1 For VBUS maximum rating, see Table 4 on page 16

Table 105. XTALOSC Electrical Specifications Table 106. XTALOSC_32K Electrical Specifications 1 Recommended nominal frequency 32.768 kHz.

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5 Boot Mode Configuration

5.1 Boot Mode Configuration Pins

sampled at reset and can be used to override fuse values, depending on the value of BT_FUSE_SEL fuse. document and Boot chapter in i.MX53 reference manual. Table 107. LDO Voltage Regulators Electrical Specifications 2 The gain or attenuation from the input supply variation to the output of the LDO (by design). 3 The limitation is for sum of the VDD_DIG_PLL and VDD_ANA_PLL current. Table 108. Fuses and Associated Pins Used for Boot

5.2 Boot Devices Interfaces Allocation

which are configured during boot when appropriate. settings for BT_FUSE_SEL = ‘0’. Table 109. Interfaces Allocation During Boot Table 108. Fuses and Associated Pins Used for Boot (continued)

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5.3 Power Setup During Boot

programming the PLL1P2_VREG bits. Table 109. Interfaces Allocation During Boot (continued)

6 Package Information and Contact Assignments

This section includes the contact assignment information and mechanical package drawing. location) for the 19 × 19 mm, 0.8 mm pitch package. Figure 98. 19 x 19 mm Package Top View

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Figure 99. 19 x 19 mm Package, 529 Solder Balls, Bottom View Figure 100. 19 x 19 mm Package Side View

The following notes apply to Figure 98, Figure 99, and Figure 100.

1. All dimensions are in millimeters.
2. Dimensions and tolerancing per ASME Y14.5M1–994.

Table 110. 19 x 19 mm Ground, Power, Sense, and Reference Contact Assignments

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includes out of reset pad state. Table 111. 19 x 19 mm Signal Assignments, Power Rails, and I/O Instance Block I/O Direction Config. Table 110. 19 x 19 mm Ground, Power, Sense, and Reference Contact Assignments (continued)

Table 111. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued) Instance Block I/O Direction Config.

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Instance Block I/O Direction Config.

Instance Block I/O Direction Config.

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Instance Block I/O Direction Config.

Instance Block I/O Direction Config.

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Instance Block I/O Direction Config.

Instance Block I/O Direction Config.

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Instance Block I/O Direction Config.

Instance Block I/O Direction Config.

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Instance Block I/O Direction Config.

Instance Block I/O Direction Config.

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Instance Block I/O Direction Config.

Instance Block I/O Direction Config.

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Instance Block I/O Direction Config.

Instance Block I/O Direction Config.

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Instance Block I/O Direction Config.

1 The state immediately after reset and before ROM firmware or software has executed. 2 During power-on reset, this port acts as input for fuse override. See Section 5.1, “Boot Mode Configuration Pins” for details. For appropriate resistor values, see Chapter 1 of i.MX53 System Development User's Guide (MX53UG).

3 During power-on reset, this port acts as output for diagnostic signal INT_BOOT

4 During power-on reset, this port acts as output for diagnostic signal ANY_PU_RST

Instance Block I/O Direction Config.

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Table 112 shows the 19 × 19 mm, 0.8 mm pitch ball map. Table 112. 19 x 19 mm, 0.8 mm Pitch Ball Map

Table 112. 19 x 19 mm, 0.8 mm Pitch Ball Map (continued)

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Revision History

7 Revision History

Table 113 provides a revision history for this data sheet. Table 113. i.MX53 Data Sheet Document Revision History Rev. 6 03/2013 In Table 1, “Ordering Information” removed MCIMX535DVV2C, as it no longer exists. (NVCC_LVDS) and L VDS band gap supply (NVCC_LVDS_BG) to 2.375 volts. I n Section 1.2, “Features,” added a new bullet item to mention support for FlexCAN feature. this is not supported on i.MX53. I n Section 4.2.3, “Power Supplies Usage,” updated the fourth bullet item. and shifted its position to left. a footnote on “YCbCr 8 bits 2 cycles” column header. bulleted list after the second paragraph. GHz in the third bullet item of the first bulleted list. resolution, 8 Mbps bit rate” from VPU brief description. resolution, 8 Mbps bit rate” from VPU brief description.

i.MX53 Applications Processors for Industrial Products, Rev. 6 Freescale Semiconductor 171 Rev. 4 11/2011  In Section 1, “Introduction,” added a new bullet item, Applications processor, to the bulleted list that contains features of the i.MX53 processor. I n Section 1.2, “Features,” changed “T arget frequency” to “Maximum frequency” and added a new bullet item to mention support for the DVFS feature. I n Section 2.1, “Block Diagram,” added Figure 1, "i.MX53 System Block Diagram," on page 6 . I n Table 2, "i.MX53 Digital and Analog Blocks," on page 7, removed “Sorenson H.263 decode, 4CIF resolution, 8 Mbps bit rate” from VPU brief description.  Added a note after Section 4.2.1, “Power-Up Sequence,” cross-referencing i.MX53 System Development User’s Guide. I n Table 10, "GPIO I/O DC Electrical Characteristics," on page 27 : —Changed test condition “Iout = -1 mA” to “Iout = -0.8 mA” in the first row —Removed test condition “Iout= specified Ioh Drive” from the first row —Removed “0.8 x OVDD” from the Min column of the first row —Changed test condition “Iout = 1 mA” to “Iout = 0.8 mA” in the second row —Removed test condition “Iout= specified Iol Drive” from the second row —Removed “0.2 x OVDD” from the Max column of the second row —Removed rows 3–6 —Changed the max value for Iin at condition “Vin = OVDD or 0” in row 12 from 2 μA to 10 μA —Changed the max value for Iin at condition “Vin = OVDD” in rows 13–15 from 2 μA to 10 μA —Changed the max value for Iin at condition “Vin = 0 V” in row 15 from 36 μA to 40 μA —Changed the max value for Iin at condition “Vin = 0 V” in row 16 from 2 μA to 10 μA —Changed the max value for Iin at condition “Vin = OVDD” in row 16 from 36 μA to 40 μA I n Table 11, "DDR2 I/O DC Electrical Parameters," on page 28: —Added test condition “Ioh = -0.1 mA” in the first row —Added test condition “Iol = 0.1 mA” in the second row —Removed rows 3–4 I n Section 4, “Electrical Characteristics,” removed the note appearing after the first paragraph. I n Section 4.2.1, “Power-Up Sequence,” updated the fifth bullet item to specify that VDD_ANA_PLL can be used to power NVCC_CKIH and NVCC_RESET . I n Section 4.3.2.2, “LPDDR2 Mode I/O DC Parameters,” added the sentence “The parameters in Ta ble 12 are guaranteed per the operating ranges in Ta ble 6, unless otherwise noted.” before Ta ble 12. I n Table 12, "LPDDR2 I/O DC Electrical Parameters," on page 29 : —Added test condition “Ioh = -0.1 mA” in the first row —Added test condition “Iol = 0.1 mA” in the second row I n Table 13, "DDR3 I/O DC Electrical Parameters," on page 29: —Added test condition “Ioh = -0.1 mA” in the first row —Added test condition “Iol = 0.1 mA” in the second row I n Table 14, "LVIO DC Electrical Characteristics," on page 30: —Added test condition “Ioh = -0.8 mA” in the first row —Added test condition “Iol = 0.8 mA” in the second row I n Table 15, "UHVIO DC Electrical Characteristics," on page 31 : —Changed test condition “Iout = -1 mA” to “Iout = -0.8 mA” in the first row —Removed test condition “Iout= specified Ioh Drive” from the first row —Removed “0.8 x OVDD” from the Min column of the first row —Changed test condition “Iout = 1 mA” to “Iout = 0.8 mA” in the second row —Removed test condition “Iout= specified Iol Drive” from the second row —Removed “0.2 x OVDD” from the Max column of the second row —Removed rows 3–6 Table 113. i.MX53 Data Sheet Document Revision History (continued)

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Rev. 4 (continued) 11/2011  In Section 4.3.5, “LVDS I/O DC Parameters,” added the sentence “The parameters in Table 16 are guaranteed per the operating ranges in Table 6, unless otherwise noted.” before Ta bl e 1 6. I n T able 16, "LVDS DC Electrical Characteristics," on page 32, changed test condition “Rload=100Ω padP , –padN” to “Rload = 100Ω between padP and padN”. I n Table 35, " NFC—Timing Characteristics," on page 49 , corrected footnote number for Tdl. I n T able 49, "SD/eMMC4.3 Interface Timing Specification," on page 72, updated eSDHC output delay. I n Table 50, "eMMC4.4 Interface Timing Specification," on page 73 , updated eSDHC output delay. I n Table 62, "TV Encoder Video Performance Specifications," on page 94 , changed test condition “Fout = 9.28 MHz” for SFDR to “Fout = 8.3 MHz”. Rev. 3 06/2011  In T able 6, "i.MX53 Operating Ranges," on page 18, updated operating ranges of VDDGP and VCC. I n Section 4.1.1, “Absolute Maximum Ratings,” updated the caution note on page 16. Rev. 2 05/2011 Initial release.

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