IMX51

IMX51 FREESCALE | Alldatasheet

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Technical content

© Freescale Semiconductor, Inc., 2009. All rights reserved. Preliminary—Subject to Change Without Notice Freescale Semiconductor Data Sheet: Advance Information Document Number: IMX51CEC Rev. 1, 11/2009 IMX51

Package Information

Case 2058 13 x 13 mm, 0.5 mm pitch Case 2017 19 x 19 mm, 0.8 mm pitch

Ordering Information

See Ta ble 1 on page 3 for ordering information. This document contains information on a new product. Specifications and information herein are subject to change without notice.

1 Introduction

The i.MX51 multimedia applications processors represent Freescale Semiconductor’s latest addition to a growing family of multimedia-focused products offering high performance processing optimized for lowest power consumption. The i.MX51 processors feature Freescale’s advanced and power-efficient implementation of the ARM Cortex A8™ core, which operates at speeds as high as 800 MHz. Up to 200 MHz DDR2 and mobile DDR DRAM clock rates are supported. These devices are suitable for applications such as the following:  Netbooks (web tablets)  Nettops (internet desktop devices)  Mobile internet devices (MID)  Portable media players (PMP)  Portable navigation devices (PND)  High-end PDAs  Gaming consoles  Automotive navigation and entertainment (see automotive data sheet, IMX51AEC) i.MX51 Applications Processors for Consumer and Industrial Products

3.2 Supply Power-Up/Power-Down Requirements and

Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX512DVK8C, MCIMX513DVK8C, MCIMX515DVK8C, and MCIMX511DVK8C.

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Preliminary—Subject to Change Without Notice Introduction Features include the following:  Smart Speed Technology—The heart of the i.MX51 processors is a level of power management throughout the device that enables the rich suite of multimedia features and peripherals to achieve minimum system power consumption in both active and various low-power modes. Smart Speed Technology enables the designer to deliver a feature-rich product that requires levels of power that are far less than typical industry expectations.  Applications Processor—i.MX51 processors boost the capabilities of high-tier portable applications by providing for the ever-increasing MIPS needs of operating systems and games. Freescale’s Dynamic V oltage and Frequency Scaling (DVFS) allows the device run at much lower voltage and frequency with sufficient MIPS for tasks such as audio decode resulting in significant power reduction.  Multimedia Powerhouse—The multimedia performance of the i.MX51 processors is boosted by a multi-level cache system and further enhanced by a Multi-Standard Hardware Video Codec, autonomous Image Processing Unit, SD and HD720p Triple Video (TV) Encoder with triple video DAC, Neon (including Advanced SIMD, 32-bit Single-Precision floating point support and V ector Floating Point co-processor), and a programmable smart DMA (SDMA) controller.  Powerful Graphics Acceleration—Graphics is the key to m obile game navigation, web browsing, and other applications. The i.MX51 processors provide two independent, integrated Graphics Processing Units: OpenGL ES 2.0 3D graphics accelerator (27 Mtri/s, 166 Mpix/s) and OpenVG 1.1 2D graphics accelerator (166 Mpix/s).  Interface Flexibility—The i.MX51 processor interface supports connection to all popular types of external memories: DDR2, Mobile DDR, NOR Flash, PSRAM, Cellular RAM, NAND Flash (MLC and SLC) and OneNAND. Designers seeking to provide products that deliver a rich multimedia experience find a full suite of on-chip peripherals: LCD controller and CMOS sensor interface, High-Speed USB On-The-Go with PHY , and three High-Speed USB hosts, multiple expansion card ports (High-Speed MMC/SDIO Host and others), 10/100 Ethernet controller, and a variety of other popular interfaces (PA TA, UART, I 2C, I2S serial audio, and SIM card, among others).  Increased Security—Because the need for advanced secur ity for mobile devices continues to increase, the i.MX51 processors deliver hardware-enabled security features that enable secure e-commerce, digital rights management (DRM), information encryption, secure boot, and secure software downloads. For detailed information about the MX51 security features contact your Freescale representative. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX512DVK8C, MCIMX513DVK8C, MCIMX515DVK8C, and MCIMX511DVK8C.

1.1 Ordering Information

Table 1 provides the ordering information. Table 1. Ordering Information 2 Part numbers with a PC prefix indicate non-production engineering parts. 3 Case 2017 and Case 2058 are RoHS compliant, lead-free, MSL = 3.

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1.2 Block Diagram

Figure 1 shows the functional modules of the processor. Figure 1. Functional Block Diagram

3 HS Ports

Features

i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 1 Freescale Semiconductor 5 Preliminary—Subject to Change Without Notice 2F e a t u r e s The i.MX51 processor contains a large number of digital and analog modules that are described in Table 2. Table 2. i.MX51 Digital and Analog Modules battery interfaces, for example: Dallas DS2502. Non-Pipelined Vector Floating Point (VFP) co-processor (VFPv3). (SSI1-3), a Digital Audio Mux (AUDMUX), and Digital Audio Out (SPDIF TX). See the specific interface listings in this table. configuring two or more AUDMUX ports. a Frequency Pre-Multiplier (FPM). modes, four chip selects to support multiple peripherals. are locked to prevent further writing. comparators, cross-system triggers, counters, and sequencers.

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Preliminary—Subject to Change Without Notice The EMI is an external and internal memory interface. It performs arbitration between multi-AXI masters to multi-memory controllers, divided into four major channels: fast memories (Mobile DDR, DDR2) channel, slow memories (NOR-FLASH/PSRAM/NAND-FLASH etc.) channel, internal memory (RAM, ROM) channel and graphical memory (GMEM) Channel. In order to increase the bandwidth performance, the EMI separates the buffering and the arbitration between different channels so parallel accesses can occur. By separating the channels, slow accesses do not interfere with fast accesses. EMI features:  64-bit and 32-bit AXI ports  Enhanced arbitration scheme for fast channel, including dynamic master priority, and taking into account which pages are open or closed and what type (Read or Write) was the last access  Flexible bank interleaving  Supports 16/32-bit Mobile DDR up to 200 MHz SDCLK (mDDR400)  Supports 16/32-bit (Non-Mobile) DDR2 up to 200 MHz SDCLK (DDR2-400)  Supports up to 2 Gbit Mobile DDR memories  Supports 16-bit (in muxed mode only) PSRAM memories (sync and async operating modes), at slow frequency, for debugging purposes  Supports 32-bit NOR-Flash memories (only in muxed mode), at slow frequencies for debugging purposes  Supports 4/8-ECC, page sizes of 512 Bytes, 2 KBytes and 4 KBytes  NAND-Flash (including MLC)  Multiple chip selects  Enhanced Mobile DDR memory controller, supporting access latency hiding  Supports watermarking for security (Internal and external memories)  Supports Samsung OneNAND ™ (only in muxed I/O mode) EPIT -1 EPIT -2 Enhanced Periodic Interrupt Timer Timer Peripherals Each EPIT is a 32-bit “set and forget” timer that starts counting after the EPIT is enabled by software. It is capable of providing precise interrupts at regular intervals with minimal processor intervention. It has a 12-bit prescaler for division of input clock frequency to get the required time setting for the interrupts to occur, and counter values can be programmed on the fly. eSDHC-1 eSDHC-2 eSDHC-3 Enhanced Multi-Media Card/ Secure Digital Host Controller Connectivity Peripherals The features of the eSDHC module, when serving as host, include the following:  Conforms to SD Host Controller Standard Specification version 2.0  Compatible with the MMC System Specification version 4.2  Compatible with the SD Memory Card Specification version 2.0  Compatible with the SDIO Card Specification version 1.2  Designed to work with SD Memory, miniSD Memory, SDIO, miniSDIO, SD Combo, MMC and MMC RS cards  Configurable to work in one of the following modes: —SD/SDIO 1-bit, 4-bit —MMC 1-bit, 4-bit, 8-bit  Full-/high-speed mode  Host clock frequency variable between 32 kHz to 52 MHz  Up to 200 Mbps data transfer for SD/SDIO cards using four parallel data lines  Up to 416 Mbps data transfer for MMC cards using eight parallel data lines Table 2. i.MX51 Digital and Analog Modules (continued)

i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 1 Freescale Semiconductor 7 Preliminary—Subject to Change Without Notice eSDHC-4 (muxed with P-A TA) Enhanced Multi-Media Card/ Secure Digital Host Controller Connectivity Peripherals Can be configured as eSDHC (see above) and is muxed with the P-AT A interface. FEC Fast Ethernet Controller Connectivity Peripherals The Ethernet Media Access Controller (MAC) is designed to support both 10 Mbps and 100 Mbps ethernet/IEEE Std 802.3™ networks. An external transceiver interface and transceiver function are required to complete the interface to the media. FIRI Fast Infra-Red Interface Connectivity Peripherals Fast Infra-Red Interface GPIO-1 GPIO-2 GPIO-3 GPIO-4 General Purpose I/O Modules System Control Peripherals These modules are used for general purpose input/output to external ICs. Each GPIO module supports up to 32 bits of I/O. GPT General Purpose Timer Timer Peripherals Each GPT is a 32-bit “free-running” or “set and forget” mode timer with a programmable prescaler and compare and capture register. A timer counter value can be captured using an external event, and can be configured to trigger a capture event on either the leading or trailing edges of an input pulse. When the timer is configured to operate in “set and forget” mode, it is capable of providing precise interrupts at regular intervals with minimal processor intervention. The counter has output compare logic to provide the status and interrupt at comparison. This timer can be configured to run either on an external clock or on an internal clock. GPU Graphics Processing Unit Multimedia Peripherals The GPU provides hardware acceleration for 2D and 3D graphics algorithms with sufficient processor power to run desk-top quality interactive graphics applications on displays up to HD720 resolution. It supports color representation up to 32 bits per pixel. The GPU with its 128 KByte memory enables high performance mobile 3D and 2D vector graphics at rates up to 27 Mtriangles/sec, 166 M pixels/sec, 664 Mpixels/sec (Z). GPU2D Graphics Processing Unit-2D Ver. 1 Multimedia Peripherals The GPU2D provides hardware acceleration for 2D graphic algorithms with sufficient processor power to run desk-top quality interactive graphics applications on displays up to HD720 resolution. I 2C-1 I2C-2 HS-I2C I2C Interface Connectivity Peripherals I2C provides serial interface for controlling peripheral devices. Data rates of up to 400 Kbps are supported by two of the I2C ports. Data rates of up to 3.4 Mbps (I2C Specification v2.1) are supported by the HS-I 2C. Note: See the errata for the HS-I2C in the i.MX51 Chip Errata. The two standard I2C modules have no errata.

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Preliminary—Subject to Change Without Notice Security The IC Identification Module (IIM) provides an interface for reading, programming, and/or overriding identification and control information stored in on-chip fuse elements. The module supports electrically programmable poly fuses (e-Fuses). The IIM also provides a set of volatile software-accessible signals that can be used for software control of hardware elements not requiring non-volatility. The IIM provides the primary user-visible mechanism for interfacing with on-chip fuse elements. Among the uses for the fuses are unique chip identifiers, mask revision numbers, cryptographic keys, JT AG secure mode, boot characteristics, and various control signals requiring permanent non-volatility. The IIM also provides up to 28 volatile control signals. The IIM consists of a master controller, a software fuse value shadow cache, and a set of registers to hold the values of signals visible outside the module. IOMUXC IOMUX Control System Control Peripherals This module enables flexible I/O multiplexing. Each I/O pad has default as well as several alternate functions. The alternate functions are software configurable. IPU Image Processing Unit Multimedia Peripherals IPU enables connectivity to displays and image sensors, relevant processing and synchronization. It supports two display ports and two camera ports, through the following interfaces.  Legacy Interfaces  Analog TV interfaces (through a TV encoder bridge) The processing includes:  Support for camera control  Image enhancement: color adjustment and gamut mapping, gamma correction and contrast enhancement, sharpening and noise reduction  Video/graphics combining  Support for display backlight reduction  Image conversion—resizing, rotation, inversion and color space conversion  Synchronization and control capabilities, allowing autonomous operation.  Hardware de-interlacing support KPP Keypad Port Connectivity Peripherals The KPP supports an 8 × 8 external keypad matrix. The KPP features are as follows:  Open drain design  Glitch suppression circuit design  Multiple keys detection  Standby key press detection P-A TA (Muxed with eSDHC-4 Parallel AT A Connectivity Peripherals The P-A TA block is an AT attachment host interface. Its main use is to interface with hard disc drives and optical disc drives. It interfaces with the AT A-5 (UDMA-4) compliant device over a number of AT A signals. It is possible to connect a bus buffer between the host side and the device side. This is muxed with eSDHC-4 interfaces. PWM-1 PWM-2 Pulse Width Modulation Connectivity Peripherals The pulse-width modulator (PWM) has a 16-bit counter and is optimized to generate sound from stored sample audio images. It can also generate tones. The PWM uses 16-bit resolution and a 4x16 data FIFO to generate sound. RAM

128 Kbytes

Unified RAM, can be split between Secure RAM and Non-Secure RAM ROM

36 Kbytes

Supports secure and regular Boot Modes

i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 1 Freescale Semiconductor 9 Preliminary—Subject to Change Without Notice RTIC Real Time Integrity Checker Security Protecting read-only data from modification is one of the basic elements in trusted platforms. The Run-Time Integrity Checker v3 (RTICv3) module, is a data monitoring device responsible for ensuring that memory content is not corrupted during program execution. The RTICv3 mechanism periodically checks the integrity of code or data sections during normal OS run-time execution without interfering with normal operation. The RTICv3’s purpose is to ensure the integrity of the peripheral memory contents, protect against unauthorized external memory elements replacement, and assist with boot authentication. SAHARA Lite SAHARA security accelerator Lite Security SAHARA (Symmetric/Asymmetric Hashing and Random Accelerator) is a security co-processor. It implements symmetric encryption algorithms, (AES, DES, 3DES, and RC4), public key algorithms, hashing algorithms (MD5, SHA-1, SHA-224, and SHA-256), and a hardware random number generator. It has a slave IP bus interface for the host to write configuration and command information, and to read status information. It also has a DMA controller, with an AHB bus interface, to reduce the burden on the host to move the required data to and from memory . SCC Security Controller Security The Security Controller is a security assurance hardware module designed to safely hold sensitive data such as encryption keys, digital right management (DRM) keys, passwords, and biometrics reference data. The SCC monitors the system’s alert signal to determine if the data paths to and from it are secure—that is, cannot be accessed from outside of the defined security perimeter. If not, it erases all sensitive data on its internal RAM. The SCC also features a Key Encryption Module (KEM) that allows non-volatile (external memory) storage of any sensitive data that is temporarily not in use. The KEM utilizes a device-specific hidden secret key and a symmetric cryptographic algorithm to transform the sensitive data into encrypted data. SDMA Smart Direct Memory Access System Control Peripherals The SDMA is multi-channel flexible DMA engine. It helps in maximizing system performance by off loading various cores in dynamic data routing. The SDMA features list is as follows:  Powered by a 16-bit instruction-set micro-RISC engine  Multi-channel DMA supports up to 32 time-division multiplexed DMA channels  48 events with total flexibility to trigger any combination of channels  Memory accesses including linear, FIFO, and 2D addressing  Shared peripherals between ARM Cortex A8™ and SDMA  Very fast context-switching with two-level priority-based preemptive multi-tasking  DMA units with auto-flush and prefetch capability  Flexible address management for DMA transfers (increment, decrement, and no address changes on source and destination address)  DMA ports can handle unit-directional and bi-directional flows (copy mode)  Up to 8-word buffer for configurable burst transfers for EMI  Support of byte-swapping and CRC calculations  A library of scripts and API are available SIM Subscriber Identity Module Interface Connectivity Peripherals The SIM is an asynchronous interface with additional features for allowing communication with Smart Cards conforming to the ISO 7816 specification. The SIM is designed to facilitate communication to SIM cards or pre-paid phone cards.

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Preliminary—Subject to Change Without Notice JTAG manipulation is a known hacker’s method of executing unauthorized program code, getting control over secure applications, and running code in privileged modes. The JTAG port provides a debug access to several hardware blocks including the ARM processor and the system bus. The JT AG port must be accessible during platform initial laboratory bring-up, manufacturing tests and troubleshooting, as well as for software debugging by authorized entities. However, in order to properly secure the system, unauthorized JT AG usage should be strictly forbidden. In order to prevent JTAG manipulation while allowing access for manufacturing tests and software debugging, the i.MX51 processor incorporates a mechanism for regulating JT AG access. The i.MX51Secure JT AG Controller provides four different JT AG security modes that can be selected via e-fuse configuration. SPBA Shared Peripheral Bus Arbiter System Control Peripherals SPBA (Shared Peripheral Bus Arbiter) is a two-to-one IP bus interface (IP bus) arbiter. SPDIF Sony Philips Digital Interface Multimedia Peripherals A standard digital audio transmission protocol developed jointly by the Sony and Philips corporations. Only the transmitter functi onality is supported. SRTC Secure Real Time Clock Security The SRTC incorporates a special System State Retention Register (SSRR) that stores system parameters during system shutdown modes. This register and all SRTC counters are powered by dedicated supply rail NVCC_SRTC_POW. The NVCC_SRTC_POW can be energized even if all other supply rails are shut down. This register is helpful for storing warm boot parameters. The SSRR also stores the system security state. In case of a security violation, the SSRR mark the event (security violation indication). SSI-1 I2S/SSI/AC97 Interface Connectivity Peripherals The SSI is a full-duplex synchronous interface used on the i.MX51 processor to provide connectivity with off-chip audio peripherals. The SSI supports a wide variety of protocols (SSI normal, SSI network, I2S, and AC-97), bit depths (up to 24 bits per word), and clock/frame sync options. Each SSI has two pairs of 8x24 FIFOs and hardware support for an external DMA controller in order to minimize its impact on system performance. The second pair of FIFOs provides hardware interleaving of a second audio stream, which reduces CPU overhead in use cases where two timeslots are being used simultaneously. SSI-2 SSI-3 TVE TV Encoder Multimedia The TVE is implemented in conjunction with the Image Processing Unit (IPU) allowing handheld devices to display captured still images and video directly on a TV or LCD projector. It supports the following analog video outputs: composite, S-video, and component video up to HD720p/1080i. TZIC T rustZone Aware Interrupt Controller ARM/Control The TrustZone Interrupt Controller (TZIC) collects interrupt requests from all i.MX51A sources and routes them to the ARM core. Each interrupt can be configured as a normal or a secure interrupt. Software Force Registers and software Priority Masking are also supported.

i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 1 Freescale Semiconductor 11 Preliminary—Subject to Change Without Notice UART-1 UART-2 UART-3 UART Interface Connectivity Peripherals Each of the UART modules supports the following serial data transmit/receive protocols and configurations:  7 or 8 bit data words, 1 or 2 stop bits, programmable parity (even, odd, or none)  Programmable baud rates up to 4 MHz. This is a higher max baud rate relative to the 1.875 MHz, which is stated by the TIA/EIA-232-F standard and previous Freescale UART modules.  32-byte FIFO on Tx and 32 half-word FIFO on Rx supporting auto-baud  IrDA 1.0 support (up to SIR speed of 115200 bps)  Option to operate as 8-pins full UART , DCE, or DTE USB USB 2.0 High-Speed OTG and 3x Hosts Connectivity Peripherals USB-OTG contains one high-speed OTG module, which is internally connected to the on-chip HS USB PHY . There are an additional three high-speed host modules that require external USB PHYs. VPU Video Processing Unit Multimedia Peripherals A high-performing video processing unit (VPU), which covers many SD-level video decoders and SD-level encoders as a multi-standard video codec engine as well as several important video processing such as rotation and mirroring. VPU Features:  MPEG-4 decode: 720p, 30 fps, simple profile and advanced simple profile  MPEG-4 encode: D1, 25/30 fps, simple profile  H.263 decode: 720p, 30 fps, profile 3  H.263 encode: D1, 25/30 fps, profile 3  H.264 decode: 720p, 30 fps, baseline, main, and high profile  H.264 encode: D1, 25/30 fps, baseline profile  MPEG-2 decode: 720p, 30 fps, MP-ML  MPEG-2 encode: D1, 25/30 fps, MP-ML (in software with partial acceleration in hardware)  VC-1 decode: 720p, 30 fps, simple, main, and advanced profile  DivX decode: 720p, 30 fps versions 3, 4, and 5  RV10 decode: 720p, 30 fps  MJPEG decode: 32 Mpix/s  MJPEG encode: 64 Mpix/s WDOG-1 Watch Dog Timer Peripherals The Watch Dog Timer supports two comparison points during each counting period. Each of the comparison points is configurable to evoke an interrupt to the ARM core, and a second point evokes an external event on the WDOG line. WDOG-2 (TZ) Watch Dog (T rustZone) Timer Peripherals The TrustZone Watchdog (TZ WDOG) timer module protects against TrustZone starvation by providing a method of escaping normal mode and forcing a switch to the TZ mode. TZ starvation is a situation where the normal OS prevents switching to the TZ mode. This situation should be avoided, as it can compromise the system’s security. Once the TZ WDOG module is activated, it must be serviced by TZ software on a periodic basis. If servicing does not take place, the timer times out. Upon a time-out, the TZ WDOG asserts a TZ mapped interrupt that forces switching to the TZ mode. If it is still not served, the TZ WDOG asserts a security violation signal to the CSU. The TZ WDOG module cannot be programmed or deactivated by a normal mode SW. XT ALOSC Crystal Oscillator I/F Clocking The XTALOSC module allows connectivity to an external crystal.

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Preliminary—Subject to Change Without Notice

2.1 Special Signal Considerations

Table 3 lists special signal considerations for the i.MX51. The signal names are listed in alphabetical order. The package contact assignments are found in Section 4, “Package Information and Contact Assignments.” Signal descriptions are defined in the i.MX51 reference manual. Table 3. Special Signal Considerations chapter in the i.MX51 reference manual for details on the respective clock trees. tie CKIH1/CKIH2 to GND for best practice. not used, float the COMP contact and ensure the DACs are powered down. Note: Previous engineering samples required this reference to be bypassed to a positive supply. GPANAIO This signal is reserved for Freescale manufacturing use only. Users should float this output. GPIO_NAND This is a general-purpose input/output (GPIO3_12) on the NVCC_NANDF_A power rail. These signals are analog TV outputs that should be tied to GND when not being used. followed. For example, do not use an external pull down on an input that has on-chip pull-up. to GND through an external pull-down resistor (such as 1 k Ω) is allowed. NC These signals are No Connect (NC) and should be floated by the user.

i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 1 Freescale Semiconductor 13 Preliminary—Subject to Change Without Notice PMIC_INT_REQ When using the MC13892 power management IC, the PMIC_INT_REQ high-priority interrupt input on i.MX51 should be either floated or tied to NVCC_SRTC_POW with a 4.7 k Ω to 68 kΩ resistor. This avoids a continuous current drain on the real-time clock backup battery due to a 100 k Ω on-chip pull-up resistor. PMIC_INT_REQ is not used by the Freescale BSP (board support package) software. The BSP requires that the general-purpose INT output from the MC13892 be connected to i.MX51 GPIO input GPIO1_8 configured to cause an interrupt that is not high-priority. The original intent was for PMIC_INT_REQ to be connected to a circuit that detects when the battery is almost depleted. In this case, the I/O must be configured as alternate mode 0 (AL T0 = power fail). POR_B This cold reset negative logic input resets all modules and logic in the IC. Note: The POR_B input must be immediately asserted at power-up and remain asserted until after the last power rail is at its working voltage. RESET_IN_B This warm reset negative logic input resets all modules and logic except for the following:  Test logic (JTAG, IOMUXC, DAP) S R T C  Memory repair – Configuration of memory repair per fuse settings  Cold reset logic of WDOG – Some WDOG logic is only reset by POR_B. See WDOG chapter in i.MX51 Reference Manual for details. RREFEXT Determines the reference current for the USB PHY bandgap reference. An external 6.04 kΩ 1% resistor to GND is required. SGND, SVCC, and SVDDGP These sense lines provide the ability to sense actual on-chip voltage levels on their respective supplies. SGND monitors differentials of the on-chip ground versus an external power source. SVCC monitors on-chip VCC, and SVDDGP monitors VDDGP . Freescale recommends connection of the SVCC and SVDDGP signals to the feedback inputs of switching power-supplies or to test points. STR This signal is reserved for Freescale manufacturing use. The user should float this signal. TEST_MODE TEST_MODE is for Freescale factory use only. This signal is internally connected to an on-chip pull-down device. Users must either float this signal or tie it to GND. VREF When using VREF with DDR-2 I/O, the nominal 0.9 V reference voltage must be half of the NVCC_EMI_DRAM supply. The user must tie VREF to a precision external resistor divider. Use a 1 kΩ 0.5% resistor to GND and a 1 kΩ 0.5% resistor to NVCC_EMI_DRAM. Shunt each resistor with a closely-mounted 0.1 µF capacitor. To reduce supply current, a pair of 1.5 kΩ 0.1% resistors can be used. Using resistors with recommended tolerances ensures the ± 2% VREF tolerance (per the DDR-2 specification) is maintained when four DDR-2 ICs plus the i.MX51 are drawing current on the resistor divider. Note: When VREF is used with mDDR this signal must be tied to GND. VREFOUT This signal determines the T riple Video DAC (TVDAC) reference voltage. The user must tie VREFOUT to an external 1.18 kΩ 1% resistor to GND. Table 3. Special Signal Considerations (continued)

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Electrical Characteristics

3 Electrical Characteristics

This section provides the device and module-level electrical characteristics for the i.MX51 processor.

3.1 Chip-Level Conditions

This section provides the device-level electrical characteristics for the IC. See Table 5 for a quick reference to the individual tables and sections. VREG This regulator is no longer used and should be floated by the user. XT AL/EXTAL The user should tie a fundamental-mode crystal across XTAL and EXT AL. The crystal must be rated for a maximum drive level of 100 μW or higher. An ESR (equivalent series resistance) of 80 Ω or less is recommended. Freescale BSP (Board Support Package) software requires 24 MHz on EXTAL. The crystal can be eliminated if an external 24 MHz oscillator is available. In this case, EXTAL must be directly driven by the external oscillator and XTAL is floated. The EXT AL signal level must swing from NVCC_OSC to GND. If the clock is used for USB, then there are strict jitter requirements: < 50 ps peak-to-peak below 1.2 MHz and < 100 ps peak-to-peak above 1.2 MHz for the USB PHY . The COSC_EN bit in the CCM (Clock Control Module) must be cleared to put the on-chip oscillator circuit in bypass mode which allows EXTAL to be externally driven. COSC_EN is bit 12 in the CCR register of the CCM. Table 4. JTAG Controller Interface Summary Table 5. i.MX51 Chip-Level Conditions

i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 1 Freescale Semiconductor 15 Preliminary—Subject to Change Without Notice CAUTION Stresses beyond those listed under Table 6 may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated under Table 8, "i.MX51 Operating Ranges," on page 16 is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Table 7 provides the thermal resistance data. Table 6. Absolute Maximum Ratings T able 111 on page 141 and Table 114 on page 160. The maximum range can be superseded by the DC tables. Table 7. Thermal Resistance Data or bottom (B) of the package, with no board attached to the package.

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Preliminary—Subject to Change Without Notice Table 8. i.MX51 Operating Ranges (as needed). The DDR clock rate is 200 MHz. (as needed). The DDR clock rate is 200 MHz.

i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 1 Freescale Semiconductor 17 Preliminary—Subject to Change Without Notice NVCC_EMI NVCC_PER5 NVCC_PER10 NVCC_PER11 NVCC_PER12 NVCC_PER13 NVCC_PER14 GPIO EMI Supply and additional digital power supplies. 1.65 1.875 or 2.775 3.1 V NVCC_IPUx NVCC_PER3 NVCC_PER8 NVCC_PER9 GPIO IPU Supply and additional digital power supplies. 1.65 1.875 or 2.775 3.1 V NVCC_EMI_DRAM DDR and Fuse Read Supply 1.65 1.8 1.95 V VDD_FUSE 5 Fusebox Program Supply (Write Only) 3.0 — 3.3 V NVCC_NANDF_x6 NVCC_PER15 NVCC_PER17 Ultra High voltage I/O (UHVIO) supplies — V UHVIO_L 1.65 1.875 1.95 UHVIO_H 2.5 2.775 3.1 UHVIO_UH 3.0 3.3 3.6 NVCC_USBPHY NVCC_OSC USB_PHY analog supply, oscillator analog supply 2.25 2.5 2.75 V TVDAC_DHVDD, NVCC_TV_BACK, AHVDDRGB TVE-to-DAC level shifter supply, cable detector supply, analog power supply to RGB channel 2.69 2.75 2.91 V NVCC_HS4_1 NVCC_HS4_2 NVCC_HS6 NVCC_HS10 HS-GPIO additional digital power supplies 1.65 — 3.1 V NVCC_I2C I 2C and HS-I2C I/O Supply8 1.65 1.875 1.95 V 2.7 3.0 3.3 NVCC_SRTC_ POW SRTC Core and I/O Supply (L VIO) 1.1 1.2 1.3 V VDDA33 USB PHY I/O analog supply 3.0 3.3 3.6 V VBUS See Table 6 on page 15 and Table 109 on page 137 for details. This is not a power supply. —— — — T C Case T emperature –20 — 85 oC 1 Voltage at the package power supply contact must be maintained between the minimum and maximum voltages. The design must allow for supply tolerances and system voltage drops. 2 The nominal values for the supplies indicate the target setpoint for a tolerance no tighter than ± 50 mV . Use of supplies with a tighter tolerance allows reduction of the setpoint with commensurate power savings. 3 Voltage for STOP mode – final value to be determined by characterization. Higher voltage in STOP mode reduces amount of power savings. Table 8. i.MX51 Operating Ranges (continued)

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3.1.1 Supply Current

4 The NVCC_IPUx rails are isolated from one another. This allows the connection of different supply voltages for each one. For example, NVCC_IPU2 can operate at 1.8 V while NVCC_IPU4 operates at 3.0 V. 5 In Read mode, Freescale recommends VDD_FUSE be floated or grounded. T ying VDD_FUSE to a positive supply (3.0 V–3.3 V) increases the possibility of inadvertently blowing fuses and is not recommended. 6 The NAND Flash supplies are composed of three groups: A, B, and C. Each group can be powered with a different supply 7 The analog supplies should be isolated in the application design. Use of series inductors is recommended. 8 Operation of the HS-I2C and I2C is not guaranteed when operated between the supply voltages of 1.95 to 2.7 V . Table 9. Interface Frequency Table 10. Fuse Supply Current VDD_FUSE supply per Table 8. 1 The current Iprogram is only required during program time (t program).

i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 1 Freescale Semiconductor 19 Preliminary—Subject to Change Without Notice Table 11 shows the current core consumption (not including I/O) of the i.MX51. Table 11. i.MX51 Stop Mode Current and Power Consumption 1

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3.1.2 USB PHY Current Consumption

3.2 Supply Power-Up/Power-Down Requirements and Restrictions

The system design must comply with the power-up and power-down sequence guidelines as described in this section to guarantee reliable operation of the device. Any deviation from these sequences may result in the following situations:  Excessive current during power-up phase  Prevention of the device from booting  Irreversible damage to the i.MX51 processor (worst-case scenario) Stop Mode  External reference clocks enabled  No power gating for ARM and processing units  HPM voltage VDDGP = 1.1 V, VCC = 1.225 V, VDDA = 1.2 V All PLLs off, all CCM-generated clocks off CKIL input on with 32 kHz signal present All modules disabled USBPHY PLL off External (MHz) crystal and on-chip oscillator powered and generating reference clock No external resistive loads that cause current flow T A = 25°C VDDGP 50 mA VCC 2 VDDA 1.15 NVCC_OSC 1.5 To ta l 6 3 m W 1 The data in this table will be finalized after the complete characterization of the silicon. Table 12. USB PHY Current Consumption Table 11. i.MX51 Stop Mode Current and Power Consumption (continued) 1

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3.2.1 Power-Up Sequence

Figure 2 shows the power-up sequence. Figure 2. Power-Up Sequence asserted until after the last power rail is at its working voltage.

3.2.2 Power-Down Sequence

3.3 I/O DC Parameters

1. VDD_FUSE should only be powered when writing.
2. No power-up sequence dependencies exist between the supplies shown in the block diagram shaded in gray.
3. There is no requirement for VDDGP to be preceded by any other power supply other than NVCC_SRTC_POW.

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Preliminary—Subject to Change Without Notice The term ‘OVDD’ in this section refers to the associated supply rail of an input or output. The association is shown in Table 111 and Table 114.

3.3.1 GPIO/HSGPIO I/0 DC Parameters

The parameters in Table 13 are guaranteed per the operating ranges in Table 8, unless otherwise noted. Table 13. GPIO/HSGPIO DC Electrical Characteristics level through to the target DC level, VIL or VIH. Monotonic input transition time is from 0.1ns to 1s. 2 Hysteresis of 250 mV is guaranteed over all operating conditions when hysteresis is enabled.

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3.3.2 DDR2 I/O DC Parameters

The parameters in Table 14 are guaranteed per the operating ranges in Table 8, unless otherwise noted.

3.3.3 Low Voltage I/O (LVIO) DC Parameters

The parameters in Table 15 are guaranteed per the operating ranges in Table 8, unless otherwise noted. Table 14. DDR2 I/O DC Electrical Parameters

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3.3.4 Ultra-High Voltage I/O (UHVIO) DC Parameters

The parameters in Table 16 are guaranteed per the operating ranges in Table 8, unless otherwise noted. Input current (no pull-up/down) IIN VI = 0 or OVDD — — TBD μA Input current (22 kΩ Pull-up) IIN VI = 0 VI = OVDD —— 1 6 TBD μA Input current (47 kΩ Pull-up) IIN VI = 0 VI = OVDD —— 7 6 TBD μA Input current (100 kΩ Pull-up) IIN VI = 0 VI = OVDD —— 3 6 TBD μA Input current (100 kΩ Pull-down) IIN VI = 0 VI = OVDD —— T B D μA Keeper Circuit Resistance — OVDD = 1.875V OVDD = 2.775V kΩ 1 To maintain a valid level, the transition edge of the input must sustain a constant slew rate (monotonic) from the current DC level through to the target DC level, VIL or VIH. Monotonic input transition time is from 0.1 ns to 1 s. 2 Hysteresis of 250 mV is guaranteed over all operating conditions when hysteresis is enabled. Table 16. UHVIO DC Electrical Characteristics 1 Table 15. LVIO DC Electrical Characteristics (continued)

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3.3.5 I 2C I/O DC Parameters

NOTE: See the errata for HS-I2C in i.MX51 Chip Errata document. The two standard I2C modules have no errata The DC Electrical Characteristics listed below are guaranteed using operating ranges per Table 8, unless otherwise noted. Input Hysteresis VHYS low voltage mode high voltage mode 0.38 0.95 —0 . 4 3 1.33 V Schmitt trigger VT+2,4 VT+ — 0.5OVDD — — V Schmitt trigger VT– 2,4 VT– — — — 0.5 × OVDD V Input current (no pull-up/down) IIN VI = 0 VI = OVDD —— T B D μA Input current (22 kΩ Pull-up) IIN VI = 0 VI = OVDD — — 202 TBD μA Input current (47 kΩ Pull-up) IIN VI = 0 VI = OVDD —— 6 1 TBD μA Input current (100 kΩ Pull-up) IIN VI = 0 VI = OVDD —— 4 7 TBD μA Input current (360 kΩ Pull-down) IIN VI = 0 VI = OVDD —— T B D 5.7 μA Keeper Circuit Resistance — NA — 17 — k Ω 1 This table applies with VCC down to 0.9 V. UHVIO are functional down to 0.85 V with degraded performance. 2 T o maintain a valid level, the transitioning edge of the input must sustain a constant slew rate (monotonic) from the current DC level through to the target DC level, VIL or VIH. Monotonic input transition time is from 0.1 ns to 1 s. 3 Overshoot and undershoot conditions (transitions above OVDD and below OVSS) on switching pads must be held below 0.6 V, and the duration of the overshoot/undershoot must not exceed 10% of the system clock cycle. Overshoot/undershoot must be controlled through printed circuit board layout, transmission line impedance matching, signal line termination, or other methods. Non-compliance to this specification may affect device reliability or cause permanent damage to the device. 4 Hysteresis of 250 mV is guaranteed over all operating conditions when hysteresis is enabled. Table 17. I2C Standard/Fast/High-Speed Mode Electrical Parameters for Low/Medium Drive Strength Table 16. UHVIO DC Electrical Characteristics 1 (continued)

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Preliminary—Subject to Change Without Notice 3.3.6 eSDHCv2 Electrical I/O DC Parameters This module is designed to interface with both low and high-voltage cards. See Table 8 for UHVIO supply ranges. Table 18 lists the Module Name electrical DC characteristics. Schmitt trigger VT– 1,2 VT– — — — 0.5 × OVDD V I/O leakage current (no pull-up) I in VI = OVDD or 0 — — TBD μA 1 T o maintain a valid level, the transitioning edge of the input must sustain a constant slew rate (monotonic) from the current DC level through to the target DC level, VIL or VIH. Monotonic input transition time is from 0.1ns to 1s. 2 Hysteresis of 250 mV is guaranteed over all operating conditions when hysteresis is enabled. Table 18. MMC/SD Interface Electrical Specification

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3.3.7 USBOTG Electrical DC Parameters

3.3.8 USB Port Electrical DC Characteristics

Table 19 and Table 20 list the electrical DC characteristics. Table 19. USBOTG Interface Electrical Specification Table 20. USB Interface Electrical Specification

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3.4 Output Buffer Impedance Characteristics

This section defines the I/O Impedance parameters of the i.MX51 processor.

3.4.1 LVIO I/O Output Buffer Impedance

3.4.2 DDR Output Buffer Impedance

Table 21. LVIO I/O Output Buffer Impedance Table 22. DDR I/O Output Buffer Impedance

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3.4.3 UHVIO Output Buffer Impedance

Output driver impedance is measured with “long” transmission line of impedance Ztl attached to I/O pad and incident wave launched into transmission lime. Rpu/Rpd and Ztl form a voltage divider that defines specific voltage of incident wave relative to OVDD. Output driver impedance is calculated from this voltage divider (see Figure 3). Table 23. UHVIO Output Buffer Impedance

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Preliminary—Subject to Change Without Notice Figure 3. Impedance Matching Load for Measurement

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3.5 I/O AC Parameters

The load circuit and output transition time waveforms are shown in Figure 4 and Figure 5. AC electrical characteristics for slow and fast I/O are presented in the Table 24 and Table 25, respectively. Figure 4. Load Circuit for Output Figure 5. Output Transition Time Waveform

3.5.1 Slow I/O AC Parameters

Table 24. Slow I/O AC Parameters

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3.5.2 Fast I/O AC Parameters

3.5.3 I 2C AC Parameters

NOTE: See the errata for HS-I2C in i.MX51 Chip Errata document. The two standard I2C modules have no errata Figure 6 depicts the load circuit for output pads for standard- and fast-mode. Figure 7 depicts the output pad transition time definition. Figure 6 depicts pull-up current source measurement for HS-mode. Figure 8 Output Pad di/dt (Low drive) tdit — — — 7 mA/ns Input Transition Times1 trm — — — 25 ns 1 Hysteresis mode is recommended for inputs with transition times greater than 25 ns. Table 25. Fast I/O AC Parameters 1 Hysteresis mode is recommended for inputs with transition time greater than 25 ns. Table 24. Slow I/O AC Parameters (continued)

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Preliminary—Subject to Change Without Notice The electrical characteristics for I2C I/O are listed in the tables from the Table 26 to the Table 29 on page 35. Characteristics are guaranteed using operating ranges per Table 8, unless otherwise noted. Table 26. I2C Standard- and Fast-Mode Electrical Parameters Table 27. I2C Standard- and Fast-Mode Electrical Parameters Table 28. I2C High-Speed Mode Electrical Parameters

i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 1 Freescale Semiconductor 35 Preliminary—Subject to Change Without Notice Table 29. I2C High-Speed Mode Electrical Parameters Table 30. Low Voltage I2C I/O Parameters

1 Hysteresis mode is recommended for inputs with transition time greater than 25 ns

Table 31. High Voltage I2C I/O Parameters

1 Hysteresis mode is recommended for inputs with transition time > 25 ns

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3.6 Module Timing

This section contains the timing and electrical parameters for the modules in the i.MX51 processor.

3.6.1 Reset Timings Parameters

Figure 10 shows the reset timing and Table 32 lists the timing parameters. Figure 10. Reset Timing Diagram

3.6.2 WDOG Reset Timing Parameters

Figure 11 shows the WDOG reset timing and Table 33 lists the timing parameters. Figure 11. WATCHDOG_RST Timing Diagram CKIL is approximately 32 kHz. TCKIL is one period or approximately 30 μs.

3.6.3 AUDMUX Timing Parameters

AUDMUX external pins is hence governed by the SSI module. Table 32. Reset Timing Parameters Table 33. WATCHDOG_RST Timing Parameters

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3.6.4 Clock Amplifier Parameters (CKIH1, CKIH2)

The input to Clock Amplifier (CAMP) is internally ac-coupled allowing direct interface to a square wave or sinusoidal frequency source. No external series capacitors are required

3.6.5 DPLL Electrical Parameters

Table 34. CAMP Electrical Parameters (CKIH1, CKIH2) 1 VCC is the supply voltage of CAMP . 2 This value of the sinusoidal input will be determined during characterization. Table 35. DPLL Electrical Parameters 1 Device input range cannot exceed the electrical specifications of the CAMP , see Table 34. the user has to enter a value “1” less than the desired value at the inputs of DPLL for PDF and MFD.

3 Should be less than denominator –67108862 — 67108862 —

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3.6.6 NAND Flash Controller (NFC) Parameters

This section provides the relative timing requirements among different signals of NFC at the module level in the different operational modes. Timing parameters in Figure 12, through Figure 15, Figure 17, and Table 37 show the default NFC mode (asymmetric mode) using two Flash clock cycles per one access of RE_B and WE_B. Timing parameters in Figure 12, Figure 13, Figure 14, Figure 16, Figure 17, and Table 37 show symmetric NFC mode using one Flash clock cycle per one access of RE_B and WE_B. With reference to the timing diagrams, a high is defined as 80% of signal value and low is defined as 20% of signal value. All parameters are given in nanoseconds. The BGA contact load used in calculations is 20 pF (except for NF16 - 40 pF) and there is max drive strength on all contacts. All timing parameters are a function of T, which is the period of the flash_clk clock (“enfc_clk” at system level). This clock frequency can be controlled by the user, configuring CCM (SoC clock controller). The clock is derived from emi_slow_clk after single divider. Table 36 demonstrates few examples for clock frequency settings. 3 The maximum total multiplication factor (MFI + MFN/MFD) allowed is 15.Therefore, if the MFI value is 15, MFN value must be zero. 4 Tdpdref is the time period of the reference clock after predivider.According to the specification, the maximum lock time in FOL mode is 398 cycles of divided reference clock when DPLL starts after full reset. 5 Tdck is the time period of the output clock, dpdck_2. Table 36. NFC Clock Settings Examples 1 Rounded up to whole nanoseconds.

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Preliminary—Subject to Change Without Notice Figure 15. Read Data Latch Timing - asymmetric mode. Figure 16. Read Data Latch Timing - Symmetric Mode.

i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 1 Freescale Semiconductor 41 Preliminary—Subject to Change Without Notice Figure 17. Other Timing Parameters. Table 37. NFC—Timing Characteristics

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3.6.7 External Interface Module (WEIM)

3.6.7.1 WEIM Signal Cross Reference

Table 38 is a guide to help the user identify signals in the WEIM Chapter of the Reference Manual Chapter that are the same as those mentioned in this data sheet. NF21 WE high to RE low tWHR 14T -5.45 14T -5.45 NF22 WE high to busy t WB 6T 1 tDSR is calculated by the following formula: Asymmetric mode: tDSR = tREpd + tDpd + 1/2T - Tdl2 Symmetric mode: t DSR = tREpd + tDpd - Tdl2 tREpd + tDpd = 11.2 ns (including clock skew) where tREpd is RE propogation delay in the chip including IO pad delay, and tDpd is Data propogation delay from IO pad to EMI including IO pad delay. tDSR can be used to determine t REA max parameter with the following formula: t REA = 1.5T - tDSR. 2 Tdl is composed of 4 delay-line units each generates an equal delay with min 1.25 ns and max 1 aclk period (T aclk). Default is 1/4 aclk period for each delay-line unit, so all 4 delay lines together generates a total of 1 aclk period. Taclk is “emi_slow_clk” of the system, which default value is 7.5 ns (133MHz). 3 NF17 is defined only in asymmetric operation mode. NF17 max value is equivalent to max t RHZ value that can be used with NFC. Taclk is “emi_slow_clk” of the system. 4 NF18 is defined only in Symmetric operation mode. t DHR (MIN) is calculated by the following formula: Tdl 2 - (tREpd + tDpd) where tREpd is RE propogation delay in the chip including IO pad delay, and tDpd is Data propogation delay from IO pad to EMI including IO pad delay. NF18 max value is equivalent to max t RHZ value that can be used with NFC. Taclk is “emi_slow_clk” of the system. Table 38. WEIM Signal Cross Reference Table 37. NFC—Timing Characteristics (continued)

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3.6.7.2 WEIM Internal Module Multiplexing

Table 39 provides WEIM internal muxing information. DAT A EIM_NFC_D (Data bus shared with NAND Flash) EIM_Dx (dedicated data bus) WAIT_B EIM_WAIT Table 39. WEIM Internal Module Multiplexing Table 38. WEIM Signal Cross Reference (continued)

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Preliminary—Subject to Change Without Notice EIM_D22 — D6 D22 EIM_D23 — D7 D23 EIM_D24 — D8 D24 EIM_D25 — D9 D25 EIM_D26 — D10 D26 EIM_D27 — D11 D27 EIM_D28 — D12 D28 EIM_D29 — D13 D29 EIM_D30 — D14 D30 EIM_D31 — D15 D31 EIM_A16 A16 A16 A16 A16 EIM_A17 A17 A17 A17 A17 EIM_A18 A18 A18 A18 A18 EIM_A19 A19 A19 A19 A19 EIM_A20 A20 A20 A20 A20 EIM_A21 A21 A21 A21 A21 EIM_A22 A22 A22 A22 A22 EIM_A23 A23 A23 A23 A23 EIM_A24 A24 A24 A24 A24 EIM_A25 A25 A25 A25 A25 EIM_A26 A26 A26 A26 A26 EIM_A27 A27 A27 A27 A27 EIM_EB0 EB0 EB0 EB0 EB0 EIM_EB1 EB1 EB1 EB1 EB1 EIM_EB2 EB2 EB2 EB2 EB2 EIM_EB3 EB3 EB3 EB3 EB3 EIM_OE OE OE OE OE EIM_CS0 CS0 CS0 CS0 CS0 EIM_CS1 CS1 CS1 CS1 CS1 EIM_CS2 CS2 CS2 CS2 CS2 EIM_CS3 CS3 CS3 CS3 CS3 Table 39. WEIM Internal Module Multiplexing (continued)

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3.6.7.3 General WEIM Timing

The following diagrams and tables specify the timings related to the WEIM module. All WEIM output control signals may be asserted and deasserted by an internal clock synchronized to the BCLK rising edge according to corresponding assertion/negation control fields. Figure 18. WEIM Outputs Timing Diagram

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Preliminary—Subject to Change Without Notice Figure 19. WEIM Inputs Timing Diagram Table 40. WEIM Bus Timing Parameters 1

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3.6.7.4 Examples of WEIM Accesses

The following diagrams give few examples of basic WEIM accesses to external memory devices with the timing parameters mentioned previously for specific control parameters settings. Figure 20. Synchronous Memory Read Access, WSC=1 clocked from this source. See the CCM chapter of the i.MX51 Reference Manual for a detailed clock tree description. 3 For signal measurements “High” is defined as 80% of signal value and “Low” is defined as 20% of signal value. Table 40. WEIM Bus Timing Parameters (continued) 1

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Preliminary—Subject to Change Without Notice Figure 21. Synchronous Memory, Write Access, WSC=1, WBEA=1, WBEN=1, and WADVN=0 Figure 22. Synchronous 16-Bit Memory, Two Non-Sequential 32-bit Read Accesses, WSC=2, SRD=1, BCD=0

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Preliminary—Subject to Change Without Notice Figure 25. 16-Bit Muxed A/D Mode, Synchronous Read Access, WSC=7, RADVN=1, ADH=1, OEA=2 the timing parameters mentioned above. Figure 26. Asynchronous Memory Read Access

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Preliminary—Subject to Change Without Notice WE34 WE_B Invalid to CSx_B Invalid WE7 – WE9 + (WEN – CSN) — 3 – (WEN_CSN) ns WE35 CSx_B Valid to OE_B Valid WE10 – WE6 + (OEA – CSA) — 3 + (OEA – CSA) ns WE36 OE_B Invalid to CSx_B Invalid WE7 – WE11 + (OEN – CSN) — 3 – (OEN – CSN) ns WE37 CSx_B Valid to BEy_B Valid (Read access) WE12 – WE6 + (RBEA – CSA) — 3 + (RBEA4 – CSA) ns WE38 BEy_B Invalid to CSx_B Invalid (Read access) WE7 – WE13 + (RBEN – CSN) — 3 – (RBEN 5 – CSN) ns WE39 CSx_B Valid to ADV_B Valid WE14 – WE6 + (ADV – CSA) — 3 + (ADVA – CSA) ns WE40 ADV_B Invalid to CSx_B Invalid (ADVL is asserted) WE7 – WE15 – CSN — 3 – CSN ns WE41 CSx_B Valid to Output Data Valid WE16 – WE6 – WCSA — 3 – WCSA ns WE42 Output Data Invalid to CSx_B Invalid WE17 – WE7 – CSN — 3 – CSN ns WE43 Input Data Valid to CSx_B Invalid MAXCO + MAXDI MAXCO6 + MAXDI7 —n s WE44 CSx_B Invalid to Input Data invalid 00 — ns WE45 CSx_B Valid to BEy_B Valid (Write access) WE12 – WE6 + (WBEA – CSA) — 3 + (WBEA – CSA) ns WE46 BEy_B Invalid to CSx_B Invalid (Write access) WE7 – WE13 + (WBEN – CSN) — –3 + (WBEN – CSN) ns WE47 Dtack Valid to CSx_B Invalid MAXCO + MAXDTI MAXCO6 + MAXDTI8 —n s WE48 CSx_B Invalid to Dtack invalid 0 0 — ns 1 Parameters WE4... WE21 value see in the Ta ble 4 1. 2 CS Assertion. This bit field determines when CS signal is asserted during read/write cycles. 3 CS Negation. This bit field determines when CS signal is negated during read/write cycles. 4 BE Assertion. This bit field determines when BE signal is asserted during read cycles. 5 BE Negation. This bit field determines when BE signal is negated during read cycles. 6 Output maximum delay from internal driving the FFs to chip outputs. The Max. delay between all memory controls (addr, csx_b, oe_b, we_b, bey_b, and adv_b) 7 Maximum delay from chip input data to internal FFs. The max. delay between all data input pins. 8 DT ACK maximum delay from chip input data to internal FF . Table 41. WEIM Asynchronous Timing Parameters Table Relative Chip Select (continued)

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3.6.8 SDRAM Controller Timing Parameters

3.6.8.1 Mobile DDR SDRAM Timing Parameters

Figure 29. Mobile DDR SDRAM Basic Timing Parameters Table 42. Mobile DDR SDRAM Timing Parameter Table

200 MHz 166 MHz 133 MHz

this is true for medium and low drive strengths.

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Preliminary—Subject to Change Without Notice Figure 30. Mobile DDR SDRAM Write cycle Timing Diagram Table 43. Mobile DDR SDRAM Write Cycle Parameter Table 1

200 MHz2

166 MHz 133 MHz

3 This parameter is affected by pad timing. If the slew rate is < 1 V/ns, 0.1 ns should be increased to this value.

i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 1 Freescale Semiconductor 55 Preliminary—Subject to Change Without Notice Figure 31. Mobile DDR SDRAM DQ vs. DQS and SDCLK READ Cycle Timing Diagram Table 44. Mobile DDR SDRAM Read Cycle Parameter Table 1

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3.6.9 DDR2 SDRAM Specific Parameters

Figure 32 shows the timing parameters for DDR2. The timing parameters for this diagram appear in Table 45. Figure 32. DDR2 SDRAM Basic Timing Parameters Table 45. DDR2 SDRAM Timing Parameter Table

i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 1 Freescale Semiconductor 57 Preliminary—Subject to Change Without Notice DDR6 Address output setup time tIS1 0.35 — ns DDR7 Address output hold time tIH1 0.475 — ns 1 These values are for command/address slew rates of 1V/ns and SDCLK / SDCLK_B differential slew rate of 2 V/ns. For different values use the settings shown in Ta ble 4 6. Table 46. Derating Values for DDR2-400 (SDCLK = 200 MHz) Table 45. DDR2 SDRAM Timing Parameter Table (continued)

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Preliminary—Subject to Change Without Notice Figure 33. DDR2 SDRAM Write Cycle Table 47. DDR2 SDRAM Write Cycle

i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 1 Freescale Semiconductor 59 Preliminary—Subject to Change Without Notice Table 48. Derating values for DDR2 Differential DQS 1,2 Table 49. Derating values for DDR2 Single Ended DQS 3,4

1. T est conditions are: Capacitance 15 pF for DDR P ADS. Recommended drive strengths is medium for SDCLK and high for
2. SDRAM CLK and DQS related parameters are being measured from the 50% point. that is, high is defined as 50% of signal
3. T est conditions are: Capacitance 15 pF for DDR P ADS. Recommended drive strengths is medium for SDCLK and high for
4. SDRAM CLK and DQS related parameters are being measured from the 50% point. that is, high is defined as 50% of signal

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Preliminary—Subject to Change Without Notice Figure 34. DDR2 SDRAM DQ vs. DQS and SDCLK READ Cycle

3.7 External Peripheral Interfaces

3.7.1 CSPI Timing Parameters

signals is shown in Table 51 on page 61. Table 50. DDR2 SDRAM Read Cycle 1

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3.7.1.1 CSPI Master Mode Timing

Figure 35 depicts the timing of CSPI in Master mode and Table 52 lists the CSPI Master Mode timing characteristics. Figure 35. CSPI Master Mode Timing Diagram Table 51. CSPI Nomenclature and Routing

1 This set of BGA contacts is labeled CSPI, but is actually an eCSPI channel

Table 52. CSPI Master Mode Timing Parameters

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3.7.1.2 CSPI Slave Mode Timing

Figure 36 depicts the timing of CSPI in Slave mode. Table 53 lists the CSPI Slave Mode timing characteristics. Figure 36. CSPI Slave Mode Timing Diagram Table 53. CSPI Slave Mode Timing Parameters Table 52. CSPI Master Mode Timing Parameters (continued)

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Preliminary—Subject to Change Without Notice 3.7.2.2 eCSPI Slave Mode Timing Figure 37 depicts the timing of eCSPI in Slave mode and Table 54 lists the eCSPI Slave Mode timing characteristics. Figure 38. eCSPI Slave Mode Timing Diagram Table 55. eCSPI Slave Mode Timing Parameters

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3.7.4 FEC AC Timing Parameters

This section describes the electrical information of the Fast Ethernet Controller (FEC) module. The FEC is designed to support both 10 and 100 Mbps Ethernet/IEEE 802.3 networks. An external transceiver interface and transceiver function are required to complete the interface to the media. The FEC supports the 10/100 Mbps MII (18 pins in total) and the 10 Mbps-only 7-wire interface, which uses 7 of the MII pins, for connection to an external Ethernet transceiver. For the pin list of MII and 7-wire, refer to the i.MX51 Reference Manual. This section describes the AC timing specifications of the FEC. The MII signals are compatible with transceivers operating at a voltage of 3.3 V .

3.7.4.1 MII Receive Signal Timing

The MII receive signal timing involves the FEC_RXD[3:0], FEC_RX_DV , FEC_RX_ER, and FEC_RX_CLK signals. The receiver functions correctly up to a FEC_RX_CLK maximum frequency of 25 MHz + 1%. There is no minimum frequency requirement but the processor clock frequency must exceed twice the FEC_RX_CLK frequency. Table 57 lists the MII receive channel signal timing parameters and Figure 40 shows MII receive signal timings. SD7 eSDHC Input Setup Time tISU 2.5 — ns SD8 eSDHC Input Hold Time t IH4 2.5 — ns 1 In low speed mode, card clock must be lower than 400 kHz, voltage ranges from 2.7 to 3.6 V. 2 In normal speed mode for SD/SDIO card, clock frequency can be any value between 0 –25 MHz. In high-speed mode, clock frequency can be any value between 0 –50 MHz. 3 In normal speed mode for MMC card, clock frequency can be any value between 0 –20 MHz. In high-speed mode, clock frequency can be any value between 0 –52 MHz. 4 T o satisfy hold timing, the delay difference between clock input and cmd/data input must not exceed 2 ns. Table 57. MII Receive Signal Timing 1 FEC_RX_DV, FEC_RX_CLK, and FEC_RXD0 have same timing in 10 Mbps 7-wire interface mode. Table 56. eSDHCv2 Interface Timing Specification (continued)

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3.7.4.2 MII Transmit Signal Timing

and Figure 41 shows MII transmit signal timing diagram for the values listed in Table 58. Figure 41. MII Transmit Signal Timing Diagram Table 58. MII Transmit Signal Timing 1 FEC_TX_EN, FEC_TX_CLK, and FEC_TXD0 have the same timing in 10 Mbps 7-wire interface mode.

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3.7.4.3 MII Async Inputs Signal Timing (FEC_CRS and FEC_COL)

Table 59 lists MII asynchronous inputs signal timing information. Figure 42 shows MII asynchronous input timings listed in Table 59. Figure 42. MII Async Inputs Timing Diagram

3.7.4.4 MII Serial Management Channel Timing (FEC_MDIO and FEC_MDC)

Table 59. MII Async Inputs Signal Timing 1 FEC_COL has the same timing in 10 Mbit 7-wire interface mode. Table 60. MII Transmit Signal Timing

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3.7.5 Frequency Pre-Multiplier (FPM) Electrical Parameters (CKIL)

in the megahertz region. The output of the FPM provides the reference frequency for the on-chip DPLLs. Parameters of the FPM are listed in Table 61.

3.7.6 High-Speed I 2C (HS-I2C) Timing Parameters

following modes: Standard, Fast and High speed. two standard I2C modules that have no errata. Table 61. FPM Specifications

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3.7.6.1 Standard and Fast Mode Timing Parameters

Figure 44 depicts the standard and fast mode timings of HS-I2C module, and Table 62 lists the timing characteristics. Figure 44. HS-I2C Standard and Fast Mode Bus Timing Table 62. HS-I2C Timing Parameters—Standard and Fast Mode of 250 ns must then be met. This automatically is the case if the device does not stretch the LOW period of the SCLH signal. before the SCLH line is released. 4 Cb = total capacitance of one bus line in pF .

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3.7.6.2 High-Speed Mode Timing Parameters

Figure 45 depicts the high-speed mode timings of HS-I2C module, and Table 63 lists the timing characteristics. Figure 45. High-Speed Mode Timing Table 63. HS-I2C High-Speed Mode Timing Parameters

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3.7.7 I 2C Module Timing Parameters

This section describes the timing parameters of the I2C Module. Figure 46 depicts the timing of I2C module, and Table 64 lists the I2C Module timing characteristics. Figure 46. I2C Bus Timing Table 64. I2C Module Timing Parameters of 250 ns must be met. This automatically is the case if the device does not stretch the LOW period of the I2CLK signal. before the I2CLK line is released. 4 Cb = total capacitance of one bus line in pF .

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3.7.8 Image Processing Unit (IPU) Module Parameters

The purpose of the IPU is to provide comprehensive support for the flow of data from an image sensor and/or to a display device. This support covers all aspects of these activities:  Connectivity to relevant devices — cameras, displays, graphics accelerators, and TV encoders.  Related image processing and manipulation: sens or image signal processing, display processing, image conversions, and other related functions.  Synchronization and control capabilities such as avoidance of tearing artifacts.

3.7.8.1 Sensor Interface Timings

There are three camera timing modes supported by the IPU. Smart camera sensors, which include imaging processing, usually support video mode transfer. They use an embedded timing syntax to replace the SENSB_VSYNC and SENSB_HSYNC signals. The timing syntax is defined by the BT.656/BT.1120 standards. This operation mode follows the recommendations of ITU BT.656/ ITU BT.1120 specifications. The only control signal used is SENSB_PIX_CLK. Start-of-frame and active-line signals are embedded in the data stream. An active line starts with a SA V code and ends with a EA V code. In some cases, digital blanking is inserted in between EA V and SA V code. The CSI decodes and filters out the timing-coding from the data stream, thus recovering SENSB_VSYNC and SENSB_HSYNC signals for internal use. On BT.656 one component per cycle is received over the SENSB_DA TA bus. On BT.1120 two components per cycle are received over the SENSB_DATA bus.

3.7.8.1.2 Gated Clock Mode

The SENSB_VSYNC, SENSB_HSYNC, and SENSB_PIX_CLK signals are used in this mode. See Figure 47. Figure 47. Gated Clock Mode Timing Diagram

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Preliminary—Subject to Change Without Notice A frame starts with a rising edge on SENSB_VSYNC (all the timings correspond to straight polarity of the corresponding signals). Then SENSB_HSYNC goes to high and hold for the entire line. Pixel clock is valid as long as SENSB_HSYNC is high. Data is latched at the rising edge of the valid pixel clocks. SENSB_HSYNC goes to low at the end of line. Pixel clocks then become invalid and the CSI stops receiving data from the stream. For next line the SENSB_HSYNC timing repeats. For next frame the SENSB_VSYNC timing repeats.

3.7.8.1.3 Non-Gated Clock Mode

The timing is the same as the gated-clock mode (described in Section 3.7.8.1.2, “Gated Clock Mode”), except for the SENSB_HSYNC signal, which is not used. See Figure 48. All incoming pixel clocks are valid and cause data to be latched into the input FIFO. The SENSB_PIX_CLK signal is inactive (states low) until valid data is going to be transmitted over the bus. Figure 48. Non-Gated Clock Mode Timing Diagram active-high/low SENSB_HSYNC; and rising/falling-edge triggered SENSB_PIX_CLK.

3.7.8.2 Electrical Characteristics

Figure 49. Sensor Interface Timing Diagram

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3.7.8.3 IPU Display Interface Signal Mapping

The IPU supports a number of display output video formats. Table 66 defines the mapping of the Display Interface Pins used during various supported video interface formats. Table 65. Sensor Interface Timing Characteristics

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24 Bit

Groups should not be overlapped.

i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 1 Freescale Semiconductor 77 Preliminary—Subject to Change Without Notice DIx_DISP_CLK PixCLK — — DIx_PIN1 — VSYNC_IN May be required for anti-tearing DIx_PIN2 HSYNC — — DIx_PIN3 VSYNC — VSYNC out DIx_PIN4 — — Additional frame/row synchronous signals with programmable timing DIx_PIN5 — — DIx_PIN6 — — DIx_PIN7 — — DIx_PIN8 — — DIx_D0_CS — CS0 — DIx_D1_CS — CS1 Alternate mode of PWM output for contrast or brightness control DIx_PIN11 — WR — DIx_PIN12 — RD — DIx_PIN13 — RS1 Register select signal DIx_PIN14 — RS2 Optional RS2 DIx_PIN15 DRDY/DV DRDY Data validation/blank, data enable DIx_PIN16 — — Additional data synchronous signals with programmable features/timingDIx_PIN17 Q — 1 Signal mapping (both data and control/synchronization) is flexible. The table provides examples. 2 This mode works in compliance with recommendation ITU-R BT .656. The timing reference signals (frame start, frame end, line start, and line end) are embedded in the 8-bit data bus. Only video data is supported, transmission of non-video related data during blanking intervals is not supported. Table 66. Video Signal Cross-Reference (continued)

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3.7.8.4 IPU Display Interface Timing

The IPU Display Interface supports two kinds of display’s accesses: synchronous and asynchronous. There are two groups of external interface pins to provide synchronous and asynchronous controls accordantly.

3.7.8.4.1 Synchronous Controls

The synchronous control is a signal that changes its value as a function either of a system or of an external clock. This control has a permanent period and a permanent wave form. There are special physical outputs to provide synchronous controls:  The ipp_disp_clk is a dedicated base synchronous si gnal that is used to generate a base display (component, pixel) clock for a display.  The ipp_pin_1– ipp_pin_7 are general purpose synchronous pins, that can be used to provide HSYNC, VSYNC, DRDY or any else independent signal to a display. The IPU has a system of internal binding counters for internal events (like HSYNC/VSYCN etc.) calculation. The internal event (local start point) is synchronized with internal DI_CLK. A suitable control starts from the local start point with predefined UP and DOWN values to calculate control’s changing points with half DI_CLK resolution. A full description of the counters system is in the IPU chapter of the i.MX51 reference manual.

3.7.8.4.2 Asynchronous Controls

The asynchronous control is a data oriented signal that changes its a value with an output data according to an additional internal flags coming with the data. There are special physical outputs to provide asynchronous controls, as follows:  The ipp_d0_cs and ipp_d1_cspins are dedicated to pr ovide chip select signals to two displays  The ipp_pin_11– ipp_pin_17 are general purpose asynchr onous pins, that can be used to provide WR. RD, RS or any else data oriented signal to display. NOTE The IPU has independent signal generators for asynchronous signals toggling. When a DI decides to put a new asynchronous data in the bus, a new internal start (local start point) is generated. The signals generators calculate predefined UP and DOWN values to change pins states with half DI_CLK resolution.

3.7.8.5 Synchronous Interfaces to Standard Active Matrix TFT LCD Panels

3.7.8.5.1 IPU Display Operating Signals

The IPU uses four control signals and data to operate a standard synchronous interface:  IPP_DISP_CLK—Clock to display  HSYNC—Horizontal synchronization Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX512DVK8C, MCIMX513DVK8C, MCIMX515DVK8C, and MCIMX511DVK8C.

i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 1 Freescale Semiconductor 79 Preliminary—Subject to Change Without Notice  VSYNC—Vertical synchronization  DRDY—Active data All synchronous display controls are generated on base of an internal generated “local start point”. The synchronous display controls can be placed on time axis with DI’s offset, up and down parameters. The display access can be whole number of DI clock (Tdiclk) only. The IPP_DATA can not be moved relative to the local start point.

3.7.8.5.2 LCD Interface Functional Description

Figure 50 depicts the LCD interface timing for a generic active matrix color TFT panel. In this figure signals are shown with negative polarity. The sequence of events for active matrix interface timing is:  DI_CLK internal DI clock, used for calculation of other controls.  IPP_DISP_CLK latches data into the panel on its negative edge (when positive polarity is selected). In active mode, IPP_DISP_CLK runs continuously.  HSYNC causes the panel to start a new line. (Usually IPP_PIN_2 is used as HSYNC)  VSYNC causes the panel to start a new frame. It always encompasses at least one HSYNC pulse. (Usually IPP_PIN_3 is used as VSYNC)  DRDY acts like an output enable signal to the CRT display. This output enables the data to be shifted onto the display. When disabled, the data is invalid and the trace is off. (For DRDY can be used either synchronous or asynchronous generic purpose pin as well.) Figure 50. Interface Timing Diagram for TFT (Active Matrix) Panels

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3.7.8.5.3 TFT Panel Sync Pulse Timing Diagrams

Figure 51 depicts the horizontal timing (timing of one line), including both the horizontal sync pulse and the data. All shown on the figure parameters are programmable. All controls are started by corresponding internal events—local start points. The timing diagrams correspond to inverse polarity of the IPP_DISP_CLK signal and active-low polarity of the HSYNC, VSYNC and DRDY signals. Figure 51. TFT Panels Timing Diagram—Horizontal Sync Pulse Figure 52. TFT Panels Timing Diagram—Vertical Sync Pulse

i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 1 Freescale Semiconductor 81 Preliminary—Subject to Change Without Notice Table 67 shows timing characteristics of signals presented in Figure 51 and Figure 52. Table 67. Synchronous Display Interface Timing Characteristics (Pixel Level) FW—with of active line in interface clocks. be built by suitable DI’s counter. built by suitable DI’s counter.

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Preliminary—Subject to Change Without Notice The maximal accuracy of UP/DOWN edge of controls is IP5o Offset of IPP_DISP_CLK Todicp DISP_CLK_OFFSET × Tdiclk DISP_CLK_OFFSET— offset of IPP_DISP_CLK edges from local start point, in DI_CLK×2 (0.5 DI_CLK Resolution) Defined by DISP_CLK counter ns IP13o Offset of VSYNC Tovs VSYNC_OFFSET × Tdiclk VSYNC_OFFSET—offset of Vsync edges from a local start point, when a Vsync should be active, in DI_CLK (0.5 DI_CLK Resolution).The VSYNC_OFFSET should be built by suitable DI’s counter. ns IP8o Offset of HSYNC T ohs HSYNC_OFFSET × Tdiclk HSYNC_OFFSET—offset of Hsync edges from a local start point, when a Hsync should be active, in DI_CLK (0.5 DI_CLK Resolution).The HSYNC_OFFSET should be built by suitable DI’s counter. ns IP9o Offset of DRDY Todrdy DRDY_OFFSET × Tdiclk DRDY_OFFSET— offset of DRDY edges from a suitable local start point, when a corresponding data has been set on the bus, in DI_CLK (0.5 DI_CLK Resolution) The DRDY_OFFSET should be built by suitable DI’s counter. ns 1 Display interface clock period immediate value. DISP_CLK_PERIOD—number of DI_CLK per one Tdicp. Resolution 1/16 of DI_CLK DI_CLK_PERIOD—relation of between programing clock frequency and current system clock frequency Display interface clock period average value. 2 DI’s counter can define offset, period and UP/DOWN characteristic of output signal according to programed parameters of the counter. Same of parameters in the table are not defined by DI’s registers directly (by name), but can be generated by corresponding DI’s counter. The SCREEN_WIDTH is an input value for DI’s HSYNC generation counter. The distance between HSYNCs is a SCREEN_WIDTH. Table 67. Synchronous Display Interface Timing Characteristics (Pixel Level) (continued)

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3.7.8.6 Interface to a TV Encoder

The interface has an 8-bit data bus, transferring a single 8-bit value (Y/U/V) in each cycle. The timing of the interface is described in Figure 54. NOTE  The frequency of the clock DISP_CLK is 27 MHz (within 10%)  The HSYNC, VSYNC signals are active low.  The DRDY signal is shown as active high.  The transition to the next row is marked by the negative edge of the HSYNC signal. It remains low for a single clock cycle  The transition to the next field/fram e is marked by the negative edge of the VSYNC signal. It remains low for at least one clock cycles — At a transition to an odd field (of the next frame), the negative edges of VSYNC and HSYNC coincide. — At a transition is to an even field (of the same frame), they do not coincide.  The active intervals—during which da ta is transferred—are marked by the HSYNC signal being high.

2 Display interface clock down time

3 Display interface clock up time

where CEIL(X) rounds the elements of X to the nearest integers towards infinity. Tdicd 1 2---T diclk ceil× 2 DISP_CLK_DOWN× ⎛⎞= Tdicu 1 2---T diclk ceil× 2 DISP_CLK_UP× ⎛⎞= Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX512DVK8C, MCIMX513DVK8C, MCIMX515DVK8C, and MCIMX511DVK8C.

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3.7.8.6.1 TV Encoder Performance Specifications

The TV encoder output specifications are shown in Table 69. Table 69. TV Encoder Video Performance Specifications

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3.7.8.7 Asynchronous Interfaces

3.7.8.7.1 Standard Parallel Interfaces

The IPU has four signal generator machines for asynchronous signal. Each machine generates IPU’s internal control levels (0 or 1) by UP and DOWN are defined in Registers. Each asynchronous pin has a dynamic connection with one of the signal generators. This connection is redefined again with a new display access (pixel/component) The IPU can generate control signals according to system 80/68 requirements. The burst length is received as a result from predefined behavior of the internal signal generator machines. The access to a display is realized by the following:  CS (IPP_CS) chip select  WR (IPP_PIN_11) write strobe  RD (IPP_PIN_12) read strobe  RS (IPP_PIN_13) Register select (A0) Both system 80 and system 68k interfaces are supported for all described modes as depicted in Figure 55, Figure 56, Figure 57, and Figure 58. The timing images correspond to active-low IPP_CS, WR and RD signals. Each asynchronous access is defined by an access size parameter. This parameter can be different between different kinds of accesses. This parameter defines a length of windows, when suitable controls of the current access are valid. A pause between two different display accesses can be guaranteed by programing of suitable access sizes. There are no minimal/maximal hold/setup time hard defined by DI. Each control signal can be switched at any time during access size. Luma Frequency Response 0-30 MHz -0.7 0.1 dB Chroma Frequency Response 0-15 MHz, YCbCr 422 mode TBD TBD dB Luma Nonlinearity 2.6 % Chroma Nonlinearity 2.2 % Luma Signal-to-Noise Ratio 0-30 MHz TBD dB Chroma Signal-to-Noise Ratio 0-15 MHz TBD dB

1 Guaranteed by design

2 Guaranteed by characterization

3 Rset = 1.05 kOhm Table 69. TV Encoder Video Performance Specifications (continued)

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Preliminary—Subject to Change Without Notice Figure 55. Asynchronous Parallel System 80 Interface (Type 1) Timing Diagram

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Preliminary—Subject to Change Without Notice Figure 57. Asynchronous Parallel System 68k Interface (Type 1) Timing Diagram

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Preliminary—Subject to Change Without Notice Display operation can be performed with IPP_WAIT signal. The DI reacts to the incoming IPP_WAIT signal with 2 DI_CLK delay. The DI finishes a current access and a next access is postponed until IPP_WAIT release. Figure 59 shows timing of the parallel interface with IPP_WAIT control. Figure 59. Parallel Interface Timing Diagram—Read Wait States

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3.7.8.7.2 Asynchronous Parallel Interface Timing Parameters

Figure 60 depicts timing of asynchronous parallel interfaces based on the system 80 and system 68k interfaces. Table 71 shows timing characteristics at display access level. All timing diagrams are based on active low control signals (signals polarity is controlled via the DI_DISP_SIG_POL Register). Figure 60. Asynchronous Parallel Interface Timing Diagram Table 70. Asynchronous Display Interface Timing Parameters (Pixel Level)

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Preliminary—Subject to Change Without Notice IP32 RS hold Tdchrr DOWN# RS strobe release, predefined value in DI REGISTER IP33 Read start Tdcsr UP# read strobe switch, predefined value in DI REGISTER ns IP34 Read hold Tdchr DOWN# read strobe release signal, predefined value in DI REGISTER ns IP35 Write start Tdcsw UP# write strobe switch, predefined value in DI REGISTER ns IP36 Controls hold time for write Tdchw DOWN# write strobe release, predefined value in DI REGISTER ns IP37 Slave device data delay 1 T racc Delay of incoming data Physical delay of display’s data, defined from Read access local start point ns IP38 Slave device data hold time 3 T roh Hold time of data on the buss Time that display read data is valid in input bus ns IP47 Read time point 13 Tdrp Data sampling point Point of input data sampling by DI, predefined in DC Microcode 1This parameter is a requirement to the display connected to the IPU. Table 71. Asynchronous Parallel Interface Timing Parameters (Access Level) Table 70. Asynchronous Display Interface Timing Parameters (Pixel Level) (continued)

i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 1 Freescale Semiconductor 95 Preliminary—Subject to Change Without Notice IP39 Setup time for wait signal Tswait — — — — IP47 Read time point 13 Tdrp Tdrp–1.5 Tdrp Tdrp+1.5 ns 1The exact conditions have not been finalized, but will likely match the current customer requirement for their specific display . These conditions may be chip specific. 2Display period value for read ACCESS_SIZE is predefined in REGISTER 3Display period value for write ACCESS_SIZE is predefined in REGISTER 4Display control down for CS DISP_DOWN is predefined in REGISTER 5Display control up for CS DISP_UP is predefined in REGISTER 6Display control down for RS DISP_DOWN is predefined in REGISTER 7Display control up for RS DISP_UP is predefined in REGISTER 8Display control down for read DISP_DOWN is predefined in REGISTER Table 71. Asynchronous Parallel Interface Timing Parameters (Access Level) (continued)

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3.7.8.8 Standard Serial Interfaces

The IPU supports the following types of asynchronous serial interfaces: 1. 3-wire (with bidirectional data line). 2. 4-wire (with separate data input and output lines). 3. 5-wire type 1 (with sampling RS by the serial clock). 4. 5-wire type 2 (with sampling RS by the chip select signal). The IPU has four independent outputs and one input. The port can be configured to provide 3, 4, or 5-wire interfaces. Figure 61 depicts the timing diagram of the 3-wire serial interface. The timing diagrams correspond to active-low IPP#_CS signal and the straight polarity of the IPP_CLK signal. For this interface, a bidirectional data line is used outside the chip. The IPU still uses separate input and output data lines (IPP_IND_DISPB_SD_D and IPP_DO_DISPB_SD_D). The I/O mux should provide joining the internal data lines to the bidirectional external line according to the IPP_OBE_DISPB_SD_D signal provided by the IPU. 9Display control up for read DISP_UP is predefined in REGISTER 10Display control down for read DISP_DOWN is predefined in REGISTER 11Display control up for write DISP_UP is predefined in REGISTER 12This parameter is a requirement to the display connected to the IPU 13Data read point Note: DISP#_READ_EN—operand of DC’s MICROCDE READ command to sample incoming data 14Loop back delay Tlbd is the cumulative propagation delay of read controls and read data. It includes an IPU output delay, a chip-level output delay , board delays, a chip-level input delay, an IPU input delay. This value is chip specific. Tdicur 1 2---T DI_CLK ceil× 2 DISP_UP_#× ⎛⎞= Tdicdrw 1 2---T DI_CLK ceil× 2 DISP_DOWN_#× ⎛⎞= Tdicuw 1 2---T DI_CLK ceil× 2 DISP_UP_#× DI_CLK_PERIOD ⎛⎞= Tdrp T DI_CLK ceil× DISP#_READ_EN Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX512DVK8C, MCIMX513DVK8C, MCIMX515DVK8C, and MCIMX511DVK8C.

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Preliminary—Subject to Change Without Notice Figure 63 depicts timing of the 5-wire serial interface. For this interface, a separate RS line is added. Figure 63. 5-Wire Serial Interface Timing Diagram

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3.7.8.8.1 Asynchronous Serial Interface Timing Parameters

Figure 64 depicts timing of the serial interface. Table 72 shows timing characteristics at display access level. Figure 64. Asynchronous Serial Interface Timing Diagram Table 72. Asynchronous Serial Interface Timing Characteristics (Access Level)

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Preliminary—Subject to Change Without Notice IP52 Write clock low pulse width T wl Tdicdw–Tdicuw–1.5 Tdicdw 6–Tdicuw7 Tdicdw–Tdicuw+1.5 ns IP53 Write clock high pulse width T wh Tdicpw–Tdicdw+ Tdicuw–1.5 Tdicpw–Tdicdw+ Tdicuw Tdicpw–Tdicdw+ Tdicuw+1.5 ns IP54 Controls setup time for read Tdcsr Tdicur–1.5 Tdicur — ns IP55 Controls hold time for read Tdchr Tdicpr–Tdicdr–1.5 Tdicpr–Tdicdr — ns IP56 Controls setup time for write Tdcsw Tdicuw–1.5 Tdicuw — ns IP57 Controls hold time for write Tdchw Tdicpw–Tdicdw–1.5 Tdicpw–Tdicdw — ns IP58 Slave device data delay 8 T racc 0 — Tdrp 9–Tlbd10-Tdicur-1.5 ns IP59 Slave device data hold time 8 T roh Tdrp-Tlbd-Tdicdr+1.5 — Tdicpr-Tdicdr-1.5 ns IP60 Write data setup time Tds Tdicdw-1.5 Tdicdw — ns IP61 Write data hold time Tdh Tdicpw-Tdicdw-1.5 Tdicpw-Tdicdw — ns IP62 Read period 2 Tdicpr Tdicpr-1.5 Tdicpr Tdicpr+1.5 ns IP63 Write period 3 Tdicpw Tdicpw-1.5 Tdicpw Tdicpw+1.5 ns IP64 Read down time 4 Tdicdr Tdicdr-1.5 Tdicdr Tdicdr+1.5 ns IP65 Read up time 5 Tdicur Tdicur-1.5 Tdicur Tdicur+1.5 ns IP66 Write down time 6 Tdicdw Tdicdw-1.5 Tdicdw Tdicdw+1.5 ns IP67 Write up time 7 Tdicuw Tdicuw-1.5 Tdicuw Tdicuw+1.5 ns IP68 Read time point 9 Tdrp Tdrp-1.5 Tdrp Tdrp+1.5 ns IP69 Clock offset 11 Toclk Toclk-1.5 Toclk Toclk+1.5 ns IP70 RS up time 12 Tdicurs Tdicurs–1.5 Tdicurs Tdicurs+1.5 ns IP71 RS down time 13 Tdicdrs Tdicdrs -1.5 Tdicdrs Tdicdrs+1.5 ns IP72 CS up time 14 Tdicucs Tdicucs –1.5 Tdicucs Tdicucs+1.5 ns IP73 CS down time 15 Tdicdcs Tdicdcs –1.5 Tdicdcs Tdicdcs+1.5 ns 1The exact conditions have not been finalized, but will likely match the current customer requirement for their specific display . These conditions may be chip specific. 2Display interface clock period value for read 3Display interface clock period value for write Table 72. Asynchronous Serial Interface Timing Characteristics (Access Level) (continued)

i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 1 Freescale Semiconductor 101 Preliminary—Subject to Change Without Notice 4Display interface clock down time for read 5Display interface clock up time for read 6Display interface clock down time for write 7Display interface clock up time for write 8This parameter is a requirement to the display connected to the IPU 9Data read point DISP_RD_EN is predefined in REGISTER 10Loop back delay Tlbd is the cumulative propagation delay of read controls and read data. It includes an IPU output delay, a chip-level output delay, board delays, a chip-level input delay, an IPU input delay. This value is chip specific. 11Display interface clock offset value CLK_OFFSET is predefined in REGISTER 12Display RS up time DISP_RS_UP is predefined in REGISTER 13Display RS down time DISP_RS_DOWN is predefined in REGISTER 14Display RS up time DISP_CS_UP is predefined in REGISTER Tdicdr 1 2---T DI_CLK ceil× 2 DISP_DOWN_#× ⎛⎞= Tdicur 1 2---T DI_CLK ceil× 2 DISP_UP_#× ⎛⎞= Tdicdw 1 2---T DI_CLK ceil× 2 DISP_DOWN_#× ⎛⎞= Tdicuw 1 2---T DI_CLK ceil× 2 DISP_UP_#× DI_CLK_PERIOD ⎛⎞= Tdrp T DI_CLK ceil× DISP_READ_EN Toclk T DI_CLK ceil× DISP_CLK_OFFSET Tdicurs T DI_CLK ceil× DISP_RS_UP_# Tdicdrs T DI_CLK ceil× DISP_RS_DOWN_# Tdicucs T DI_CLK ceil× DISP_CS_UP_# Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX512DVK8C, MCIMX513DVK8C, MCIMX515DVK8C, and MCIMX511DVK8C.

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Preliminary—Subject to Change Without Notice 3.7.9 1-Wire Timing Parameters Figure 65 depicts the RPP timing, and Table 73 lists the RPP timing parameters. Figure 65. Reset and Presence Pulses (RPP) Timing Diagram Figure 66 depicts Write 0 Sequence timing, and Table 74 lists the timing parameters. Figure 66. Write 0 Sequence Timing Diagram DISP_CS_DOWN is predefined in REGISTER. Table 73. RPP Sequence Delay Comparisons Timing Parameters Table 74. WR0 Sequence Timing Parameters

i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 1 Freescale Semiconductor 103 Preliminary—Subject to Change Without Notice Figure 67 depicts Write 1 Sequence timing, Figure 68 depicts the Read Sequence timing, and Table 75 lists the timing parameters. Figure 67. Write 1 Sequence Timing Diagram Figure 68. Read Sequence Timing Diagram

3.7.10 Pulse Width Modulator (PWM) Timing Parameters

Table 75. WR1 /RD Timing Parameters

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Preliminary—Subject to Change Without Notice Figure 69 depicts the timing of the PWM, and Table 76 lists the PWM timing parameters. Figure 69. PWM Timing

3.7.11 P-ATA Timing Parameters

A TA/A TAPI-6 specification. A TA/A TAPI-6 specification and these requirements are configurable by the ATA module registers. Table 76. PWM Output Timing Parameter

1 System CLK frequency 1

1 CL of PWMO = 30 pF

i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 1 Freescale Semiconductor 105 Preliminary—Subject to Change Without Notice Figure 70. P-ATA Interface Signals Timing Diagram interface is 3.3 V compatible. UDMA mode operation is needed, this may not be compatible with bus buffers. Another area of attention is the slew rate limit imposed by the ATA specification on the ATA bus. a 40 pF load. Not many vendors of bus buffers specify slew rate of the outgoing signals. signal is such that contention on the host and device tri-state busses is always avoided. Table 77. AC Characteristics of All Interface Signals amplitude with all capacitive loads from 15 –40 pF where all signals have the same capacitive load value.

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Preliminary—Subject to Change Without Notice In the timing equations, some timing parameters are used. These parameters depend on the implementation of the i.MX51 P-ATA interface on silicon, the bus buffer used, the cable delay and cable skew. Table 78 shows ATA timing parameters. Table 78. P-ATA Timing Parameters 1 Values provided where applicable.

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3.7.11.1 PIO Mode Read Timing

Figure 71 shows timing for PIO read, and Table 79 lists the timing parameters for PIO read. Figure 71. PIO Read Timing Diagram Table 79. PIO Read Timing Parameters

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Preliminary—Subject to Change Without Notice Figure 72 shows timing for PIO write, and Table 80 lists the timing parameters for PIO write. Figure 72. Multi-word DMA (MDMA) Timing Table 80. PIO Write Timing Parameters

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Preliminary—Subject to Change Without Notice

3.7.11.2 Ultra DMA (UDMA) Input Timing

Figure 75 shows timing when the UDMA in transfer starts, Figure 76 shows timing when the UDMA in host terminates transfer, Figure 77 shows timing when the UDMA in device terminates transfer, and Table 82 lists the timing parameters for UDMA in burst. Figure 75. UDMA In Transfer Starts Timing Diagram Figure 76. UDMA In Host Terminates Transfer Timing Diagram Table 81. MDMA Read and Write Timing Parameters (continued)

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Preliminary—Subject to Change Without Notice

3.7.11.3 UDMA Output Timing

Figure 78 shows timing when the UDMA out transfer starts, Figure 79 shows timing when the UDMA out host terminates transfer, Figure 80 shows timing when the UDMA out device terminates transfer, and Table 83 lists the timing parameters for UDMA out burst. Figure 78. UDMA Out Transfer Starts Timing Diagram Figure 79. UDMA Out Host Terminates Transfer Timing Diagram

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Preliminary—Subject to Change Without Notice

3.7.12 SIM (Subscriber Identification Module) Timing

This section describes the electrical parameters of the SIM module. Each SIM module interface consists of 12 signals (two separate ports each containing six signals). Typically a a port uses five signals. The interface is designed to be used with synchronous SIM cards meaning the SIM module provides the clock used by the SIM card. The clock frequency is typically 372 times the Tx/Rxdata rate, however the SIM module can work with CLK frequencies of 16 times the Tx/Rx data rate. There is no timing relationship between the clock and the data. The clock that the SIM module provides to the SIM card is used by the SIM card to recover the clock from the data in the same manner as standard UART data exchanges. All six signals (5 for bi-directional Tx/Rx) of the SIM module are asynchronous to each other. There are no required timing relationships between signals in normal mode. The SIM card is initiated by the interface device; the SIM card responds with Answer to Reset. Although the SIM interface has no defined requirements, the ISO-7816 defines reset and power-down sequences. (For detailed information, see ISO-7816.) Table 84 defines the general timing requirements for the SIM interface. Figure 81. SIM Clock Timing Diagram Table 84. SIM Timing Parameters, High Drive Strength

2 With C = 50 pF

3 With C = 50 pF

4 With Cin = 30 pF , Cout = 30 pF

5 With Cin = 30 pF

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3.7.12.1 Reset Sequence

3.7.12.1.1 Cards with internal reset

The sequence of reset for this kind of SIM Cards is as follows (see Figure 82):  After power up, the clock signal is enabled on SIMx_CLKy(time T0)  After 200 clock cycles, RX must be high.  The card must send a response on RX acknowledging the reset between 400 and 40000 clock cycles after T0. Figure 82. Internal-Reset Card Reset Sequence

3.7.12.1.2 Cards with Active Low Reset

 After 200 clock cycles, SIMx_DA TAy_RX_TX must be high. received on SIMx_DA TAy_RX_TX between 400 and 40000 clock cycles after T1.

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Preliminary—Subject to Change Without Notice Figure 83. Active-Low-Reset Cards Reset Sequence

3.7.12.2 Power Down Sequence

timing requirements for this sequence, with Fckil = CKIL frequency value.

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Preliminary—Subject to Change Without Notice

3.7.13 SCAN JTAG Controller (SJC) Timing Parameters

Figure 85 depicts the SJC test clock input timing. Figure 86 depicts the SJC boundary scan timing. Figure 87 depicts the SJC test access port. Signal parameters are listed in Table 86. Figure 85. Test Clock Input Timing Diagram Figure 86. Boundary Scan (JTAG) Timing Diagram

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Preliminary—Subject to Change Without Notice

3.7.14 SPDIF Timing Parameters

Table 87 shows the timing parameters for the Sony/Philips Digital Interconnect Format (SPDIF).

3.7.15 SSI Timing Parameters

This section describes the timing parameters of the SSI module. The connectivity of the serial synchronous interfaces is summarized in Table 88. SJ9 TMS, TDI data hold time 25 — ns SJ10 TCK low to TDO data valid — 44 ns SJ11 TCK low to TDO high impedance — 44 ns SJ12 TRST assert time 100 — ns SJ13 TRST set-up time to TCK low 40 — ns

1 TDC = target frequency of SJC

2 VM = mid-point voltage

Table 87. SPDIF Timing Table 88. AUDMUX Port Allocation Table 86. JTAG Timing (continued)

i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 1 Freescale Semiconductor 121 Preliminary—Subject to Change Without Notice NOTE  The terms WL and BL used in the timing diagrams and tables refer to Word Length (WL) and Byte Length (BL).  The SSI timing diagrams use gene ric signal names wherein the names used in the i.MX51 reference manual are channel specific signal names. For example, a channel clock referenced in the IOMUXC chapter as AUD3_TXC appears in the timing diagram as TXC. Figure 89. SSI Transmitter Internal Clock Timing Diagram

3.7.15.1 SSI Transmitter Timing with Internal Clock

Table 89. SSI Transmitter Timing with Internal Clock Table 88. AUDMUX Port Allocation (continued)

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Preliminary—Subject to Change Without Notice  All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync (TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures.  All timings are on Audiomux Pads when SSI is being used for data transfer.  The terms WL and BL refer to Word Length (WL) and Byte Length (BL).  ”Tx” and “Rx” refer to the Transmit and Receive sections of the SSI.  For internal Frame Sync operation using external clock, the FS timing is same as that of Tx Data (for example, during AC97 mode of operation). SS4 (Tx/Rx) CK clock low period 36.0 — ns SS5 (Tx/Rx) CK clock fall time — 6.0 ns SS6 (Tx) CK high to FS (bl) high — 15.0 ns SS8 (Tx) CK high to FS (bl) low — 15.0 ns SS10 (Tx) CK high to FS (wl) high — 15.0 ns SS12 (Tx) CK high to FS (wl) low — 15.0 ns SS14 (Tx/Rx) Internal FS rise time — 6.0 ns SS15 (Tx/Rx) Internal FS fall time — 6.0 ns SS16 (Tx) CK high to STXD valid from high impedance — 15.0 ns SS17 (Tx) CK high to STXD high/low — 15.0 ns SS18 (Tx) CK high to STXD high impedance — 15.0 ns SS19 STXD rise/fall time — 6.0 ns Synchronous Internal Clock Operation SS42 SRXD setup before (Tx) CK falling 10.0 — ns SS43 SRXD hold after (Tx) CK falling 0.0 — ns SS52 Loading — 25.0 pF Table 89. SSI Transmitter Timing (continued)with Internal Clock (continued)

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3.7.15.2 SSI Receiver Timing with Internal Clock

Figure 90. SSI Receiver Internal Clock Timing Diagram Table 90. SSI Receiver Timing with Internal Clock

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Preliminary—Subject to Change Without Notice  All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync (TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures.  All timings are on Audiomux Pads when SSI is being used for data transfer.  “Tx” and “Rx” refer to the Transmit and Receive sections of the SSI.  The terms WL and BL refer to Word Length (WL) and Byte Length (BL).  For internal Frame Sync operation using external clock, the FS timing is same as that of Tx Data (for example, during AC97 mode of operation). SS48 Oversampling clock high period 6.0 — ns SS49 Oversampling clock rise time — 3.0 ns SS50 Oversampling clock low period 6.0 — ns SS51 Oversampling clock fall time — 3.0 ns Table 90. SSI Receiver Timing with Internal Clock (continued)

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3.7.15.3 SSI Transmitter Timing with External Clock

Figure 91. SSI Transmitter External Clock Timing Diagram Table 91. SSI Transmitter Timing with External Clock

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Preliminary—Subject to Change Without Notice  All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync (TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures.  All timings are on Audiomux Pads when SSI is being used for data transfer.  “Tx” and “Rx” refer to the Transmit and Receive sections of the SSI.  The terms WL and BL refer to Word Length (WL) and Byte Length (BL).  For internal Frame Sync operation using external clock, the FS timing is same as that of Tx Data (for example, during AC97 mode of operation).

3.7.15.4 SSI Receiver Timing with External Clock

Figure 92. SSI Receiver External Clock Timing Diagram Table 91. SSI Transmitter Timing with External Clock (continued)

i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 1 Freescale Semiconductor 127 Preliminary—Subject to Change Without Notice NOTE  All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync (TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures.  All timings are on Audiomux Pads when SSI is being used for data transfer.  “Tx” and “Rx” refer to the Transmit and Receive sections of the SSI.  The terms WL and BL refer to Word Length (WL) and Byte Length (BL).  For internal Frame Sync operation using external clock, the FS timing is same as that of Tx Data (for example, during AC97 mode of operation). Table 92. SSI Receiver Timing with External Clock

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Preliminary—Subject to Change Without Notice

3.7.16 UART

Table 93 shows the UART I/O configuration based on which mode is enabled.

3.7.17 USBOH3 Parameters

This section describes the electrical parameters of the USB OTG port and USB HOST ports. For on-chip USB PHY parameters see Section 3.7.19, “USB PHY Parameters.”

3.7.17.1 USB Serial Interface

In order to support four serial different interfaces, the USB serial transceiver can be configured to operate in one of four modes:  DA T_SE0 bidirectional, 3-wire mode  DA T_SE0 unidirectional, 6-wire mode  VP_VM bidirectional, 4-wire mode  VP_VM unidirectional, 6-wire mode The USB controller does not support ULPI Serial mode. Only the legacy serial mode is supported. Table 93. UART I/O Configuration vs. Mode Table 94. Serial Mode Signal Map for 6-pin FsLs Serial Mode

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3.7.17.1.1 USB DAT_SE0 Bi-Directional Mode

Figure 93. USB Transmit Waveform in DAT_SE0 Bi-Directional Mode Table 95. Serial Mode Signal Map for 3-pin FsLs Serial Mode Table 96. Signal Definitions—DAT_SE0 Bi-Directional Mode Table 94. Serial Mode Signal Map for 6-pin FsLs Serial Mode (continued)

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Preliminary—Subject to Change Without Notice Figure 94. USB Receive Waveform in DAT_SE0 Bi-Directional Mode

3.7.17.1.2 USB DAT_SE0 Unidirectional Mode

Table 97. Definitions of USB Receive Waveform in DAT_SE0 Bi-Directional Mode Table 98. Signal Definitions—DAT_SE0 Unidirectional Mode

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Preliminary—Subject to Change Without Notice

3.7.17.1.3 USB VP_VM Bi-Directional Mode

Figure 97. USB Transmit Waveform in VP_VM Bi-Directional Mode Figure 98. USB Receive Waveform in VP_VM Bi-Directional Mode Table 100. Signal Definitions—VP_VM Bi-Directional Mode

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3.7.17.1.4 USB VP_VM Uni-Directional Mode

Figure 99. USB Transmit Waveform in VP_VM Unidirectional Mode Table 101. USB Port Timing Specification in VP_VM Bi-directional Mode Table 102. USB Signal Definitions—VP_VM Uni-Directional Mode

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Preliminary—Subject to Change Without Notice Figure 100. USB Receive Waveform in VP_VM Unidirectional Mode Table 103. USB Timing Specification in VP_VM Unidirectional Mode

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3.7.18 USB Parallel Interface Timing

Electrical and timing specifications of Parallel Interface are presented in the subsequent sections. Figure 101. USB Transmit/Receive Waveform in Parallel Mode Table 104. Signal Definitions—Parallel Interface (Normal ULPI) USB_Clk In Interface clock. All interface signals are synchronous to Clock. ownership is determined by Dir. USB_Dir In Direction. Control the direction of the Data bus. stream currently on the bus. USB_Nxt In Next. The PHY asserts this signal to throttle the data. Table 105. USB Timing Specification for ULPI Parallel Mode

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Preliminary—Subject to Change Without Notice

3.7.19 USB PHY Parameters

3.7.19.1 USB PHY AC Parameters

3.7.19.2 USB PHY Additional Electrical Parameters

3.7.19.3 USB PHY System Clocking (SYSCLK)

Table 106. USB PHY AC Timing Parameters Table 107. Additional Electrical Characteristics for USB PHY Table 108. USB PHY System Clocking Parameters

3.7.19.4 USB PHY Voltage Thresholds

4 Package Information and Contact Assignments

This section includes the contact assignment information and mechanical package drawing. location) for the 13 × 13 mm, 0.5 mm pitch package. Table 109. VBUS Comparators Thresholds

1 For VBUS maximum rating, see Ta ble 6 on page 15

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Figure 102. Package: Case 2058—0.5 mm Pitch The following notes apply to Figure 102. 1 All dimensions in millimeters. 2 Dimensioning and tolerancing per ASME Y14.5M-1994. 3 Maximum solder ball diameter measured parallel to Datum A. 4 Datum A, the seating plane, is determined by the spherical crowns of the solder balls. 5 Parallelism measurement shall exclude any effect of mark on top surface of package.

a listing of the no-connect contacts. Table 110. 13 × 13 mm Ground, Power, Sense, and Reference Contact Assignments

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Table 110. 13 × 13 mm Ground, Power, Sense, and Reference Contact Assignments (continued)

on page 172 lists the contacts that can be overridden with fuse settings. Table 111. 13 × 13 mm Signal Assignments, Power Rails, and I/O

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Table 111. 13 × 13 mm Signal Assignments, Power Rails, and I/O (continued)

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1 The state immediately after reset and before ROM firmware or software has executed.

Table 112 shows the device No Connect assignment list. Table 112. 13 × 13 mm No Connect Assignments

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Table 112. 13 × 13 mm No Connect Assignments (continued)

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location) for the 19 × 19 mm, 0.8 mm pitch package.

Figure 103. 19x 19 mm Package: Case 2017-01—0.8 mm Pitch

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The following notes apply to Figure 103. 1 All dimensions in millimeters. 2 Dimensioning and tolerancing per ASME Y14.5M-1994. 3 Maximum solder ball diameter measured parallel to Datum A. 4 Datum A, the seating plane, is determined by the spherical crowns of the solder balls. 5 Parallelism measurement shall exclude any effect of mark on top surface of package. assignments including associated power supplies. Table 113. 19 × 19 mm Ground, Power, Sense, and Reference Contact Assignments

Table 113. 19 × 19 mm Ground, Power, Sense, and Reference Contact Assignments (continued)

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Table 114 displays an alpha-sorted list of the signal assignments including power rails. Table 114. 19 x 19 mm Signal Assignments, Power Rails, and I/O

Table 114. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued)

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1 The state immediately after reset and before ROM firmware or software has executed.

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4.2.2.3 Fuse Override Considerations

Table 115 lists the contacts that can be overridden with fuse settings. Table 115. Fuse Override Contacts

during product development. In production, the boot configuration is controlled by fuses. 2 Consider using an external 68 k Ω pull-up if system constraints indicate that the on-chip 100 k Ω pull-up is too weak. Table 115. Fuse Override Contacts (continued)

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Table 116 shows the 13 x 13 mm, 0.5 pitch ball map. Table 116. 13 × 13 mm, 0.5 mm Pitch Ball Map

Table 116. 13 × 13 mm, 0.5 mm Pitch Ball Map (continued)

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Table 117 shows the 19 × 19 mm, 0.8 pitch ball map. Table 117. 19 × 19 mm, 0.8 Pitch Ball Map

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Table 117. 19 × 19 mm, 0.8 Pitch Ball Map (continued)

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Revision History

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5 Revision History

Table 118 provides a revision history for this data sheet. Table 118. i.MX51 Data Sheet Document Revision History 1 11/4/2009 Initial public release.

Document Number: IMX51CEC Rev. 1 How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. Technical Information Center, EL516

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