IMX35_1 FREESCALE | Alldatasheet
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Data Sheet: Advance Information Document Number: MCIMX35SR2CEC Rev. 6, 10/2009 © Freescale Semiconductor, Inc., 2008, 2009. All rights reserved. This document contains information on a product under development. Freescale reserves the right to change or discontinue this product without notice. IMX35
Package Information
Case 5284 17 x 17 mm, 0.8 mm Pitch
Ordering Information
See Table 1 on page 3 for ordering information.
1 Introduction
The i.MX353 and the i.MX357 multimedia applications processors represent the next generation of ARM11 products with the right performance and integration to address applications within the industrial and consumer markets for applications such as HMI and display controllers. Unless otherwise specified, the material in this data sheet is applicable to both the i.MX353 and i.MX357 devices and referred to singularly throughout this document as i.MX35 or MCIMX35. The i.MX353 devices do not include a graphics processing unit (GPU). For information on i.MX35 devices for automotive applications, please refer to document number, MCIMX35SR2AEC. The i.MX35 processor takes advantage of the ARM1136JF-S™ core running at 532 MHz that is boosted by a multi-level cache system and integrated features such as LCD controller, Ethernet, and graphics acceleration for creating rich user interfaces. i.MX35 Applications Processors for Industrial and Consumer Products Silicon Revisions 2.0 and 2.1 3 Signal Descriptions: Special Function Related Pins . . . . 11
4.3 Supply Power-Up/Power-Down Requirements and
5.1 MAPBGA Production Package 1568-01, 17 × 17 mm,
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B.
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 6 Freescale Semiconductor2 The i.MX35 supports connections to various types of external memories, such as SDRAM, mobile DDR, and DDR2, SLC and MCL NAND Flash, NOR Flash and SRAM. The devices can be connected to a variety of external devices such as USB 2.0 OTG, A TA, MMC/SDIO, and Compact Flash.
1.1 Features
It provides low-power solutions for applications demanding high-performance multimedia and graphics. The i.MX35 is based on the ARM1136 platform, which has the following features: ARM1136JF-S processor, version r1p3 16-Kbyte L1 instruction cache 16-Kbyte L1 data cache 128-Kbyte L2 cache, version r0p4 128 Kbytes of internal SRAM V ector floating point unit (VFP11) To boost multimedia performance, the following hardware accelerators are integrated: Image processing unit (IPU) OpenVG 1.1 graphics processing unit (GPU) The MCIMX35 provides the following interfaces to external devices (some of these interfaces are muxed and not available simultaneously): 2 controller area network (CAN) interfaces 2 SDIO/MMC interfaces, 1 SDIO/CE-ATA interface 32-bit mobile DDR, DDR2 (4-bank architecture), and SDRAM (up to 133 MHz) 2 configurable serial peripheral interfaces (CSPI) (up to 52 Mbps each) Enhanced serial audio interface (ESAI) 2 synchronous serial interfaces (SSI) Ethernet MAC 10/100 Mbps 1 USB 2.0 host with ULPI interface or internal full-speed PHY . Up to 480 Mbps if external HS PHY is used. 1 USB 2.0 OTG (up to 480 Mbps) controller with internal high-speed OTG PHY Flash controller—MLC/SLC NAND and NOR GPIO with interrupt capabilities 3 I 2C modules (up to 400 Kbytes each) J T A G Key pin port Asynchronous sample rate converter (ASRC) 1 - W i r e Parallel camera sensor (4/8/10/16-bit data port for video color models: YCC, YUV , 30 Mpixels/s) Parallel display (primary up to 24-bit, 1024 x 1024) Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B.
1.2 Ordering Information
each revision is not compatible, so it is important that the correct ballmap be used to implement the layout. Table 1. Ordering Information 2 Case 5284 is RoHS-compliant, lead-free, MSL = 3, 1.
1.3 Block Diagram
Figure 1 is the i.MX35 simplified interface block diagram. Figure 1. i.MX35 Simplified Interface Block Diagram
2 Functional Description and Application Information
2.1 Application Processor Domain Overview
3 FuseBox
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 6 Freescale Semiconductor 5 The i.MX35 core is intended to operate at a maximum frequency of 532 MHz to support the required multimedia use cases. Furthermore, an image processing unit (IPU) is integrated into the AP domain to offload the ARM11 core from performing functions such as color space conversion, image rotation and scaling, graphics overlay, and pre- and post-processing. The functionality of AP Domain peripherals includes the user interface; the connectivity, display, security, and memory interfaces; and 128 Kbytes of multipurpose SRAM.
2.2 Shared Domain Overview
The shared domain is composed of the shared peripherals, a smart DMA engine (SDMA) and a number of miscellaneous modules. For maximum flexibility, some peripherals are directly accessible by the SDMA engine. The i.MX35 has a hierarchical memory architecture including L1 caches and a unified L2 cache. This reduces the bandwidth demands for the external bus and external memory. The external memory subsystem supports a flexible external memory system, including support for SDRAM (SDR, DDR2 and mobile DDR) and NAND Flash.
2.3 Advanced Power Management Overview
To address the continuing need to reduce power consumption, the following techniques are incorporated in the i.MX35: Clock gating Power gating Power-optimized synthesis Well biasing The insertion of gating into the clock paths allows unused portions of the chip to be disabled. Because static CMOS logic consumes only leakage power, significant power savings can be realized. “Well biasing” is applying a voltage that is greater than V DD to the nwells, and one that is lower than VSS to the pwells. The effect of applying this well back bias voltage reduces the subthreshold channel leakage. For the 90-nm digital process, it is estimated that the subthreshold leakage is reduced by a factor of ten over the nominal leakage. Additionally, the supply voltage for internal logic can be reduced from 1.4 V to 1.22 V .
2.4 ARM11 Microprocessor Core
The CPU of the i.MX35 is the ARM1136JF-S core, based on the ARM v6 architecture. This core supports the ARM Thumb ® instruction sets, features Jazelle® technology (which enables direct execution of Java byte codes) and a range of SIMD DSP instructions that operate on 16-bit or 8-bit data values in 32-bit registers. The ARM1136JF-S processor core features are as follows: Integer unit with integral EmbeddedICE ™ logic Eight-stage pipeline Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B.
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 6 Freescale Semiconductor6 Branch prediction with return stack Low-interrupt latency Instruction and data memory ma nagement units (MMUs), managed using micro TLB structures backed by a unified main TLB Instruction and data L1 caches, including a non-blocking data cache with hit-under-miss Virtually indexed/physically addressed L1 caches 64-bit interface to both L1 caches Write buffer (bypassable) High-speed Advanced Micro Bus Architecture (AMBA) ™ L2 interface V ector floating point co-processor (VFP) for 3D graphics and hardware acceleration of other floating-point applications E T M ™ and JTAG-based debug support Table 2 summarizes information about the i.MX35 core.
2.5 Module Inventory
Table 3 shows an alphabetical listing of the modules in the MCIMX35. For extended descriptions of the modules, see the MCIMX35 reference manual. Table 2. i.MX35 Core
Features
The ARM1136™ platform consists of the ARM1136JF-S core, the ETM real-time debug modules, a 6 × 5 multi-layer AHB crossbar switch (MAX), and a vector floating processor (VFP). The i.MX35 provides a high-performance ARM11 microprocessor core and highly integrated system functions. The ARM Application Processor (AP) and other subsystems address the needs of the personal, wireless, and portable product market with integrated peripherals, advanced processor core, and power management capabilities. 16-Kbyte instruction cache 16-Kbyte data cache 128-Kbyte L2 cache 32-Kbyte ROM 128-Kbyte RAM Table 3. Digital and Analog Modules memory. the interface can send or receive 1 bit at a time.
interfaces with the A TA device over a number of AT A signals. appropriate internal and external ports. serial data bus running at 1 Mbps. communication with fewer software interrupts. access to the external memory. NANDFC—provides an interface to NAND Flash memories. WEIM—interfaces to NOR Flash and PSRAM. Table 3. Digital and Analog Modules (continued)
sections, each section with its own clock generator. interface) with low power consumption. module supports 32 bits of I/O. interrupts at regular intervals with minimal processor intervention. on an external clock or on an internal clock. This module accelerates OpenVG and GDI graphics.
and various control signals requiring a fixed value. external 24.576-MHz crystal.
from stored sample audio images; it can also generate tones. interface, and the peripherals. transfer between internal buffers and system memory. signal, depending on the software configuration.
3 Signal Descriptions: Special Function Related Pins
and the corresponding pin names are listed in Table 4.
4 Electrical Characteristics
to the individual tables and sections.
1 ARM = ARM1136 platform, SDMA = SDMA platform
Table 4. Special Function Related Pins External ARM Clock EXT_ARMCLK AL T0 External clock input for ARM clock. External Peripheral Clock I2C1_CLK AL T6 External peripheral clock source. and can also be used for debug. impossible to disable it until the next reset. Table 5. i.MX35 Chip-Level Conditions
periods may affect device reliability. associated supply rail of an input or output. Table 6. Absolute Maximum Ratings 1 VDD is also known as QVCC.
2 HBM ESD classification level according to the AEC-Q100-002 standard
Table 7. i.MX35 Operating Ranges
4.1.2 Interface Frequency Limits
Table 8 provides information on interface frequency limits. to 1.8 or 3.3 V . NVCC_MLB can be left floating. recommended that FUSE_VDD be connected to ground when not being used for programming. Table 8. Interface Frequency
1 JT AG TCK Frequency fJTAG DC 5 10 MHz
Table 7. i.MX35 Operating Ranges (continued)
4.2 Power Modes
Table 9 provides descriptions of the power modes of the i.MX35 processor. Table 9. i.MX35 Power Modes ARM is in wait for interrupt mode. configured by CGR register). OSC audio is off (can be configured). ARM is in wait for interrupt mode. PER PLL is off (can be configured). configured by CGR register). ARM is in wait for interrupt mode.
4.3 Supply Power-Up/Power-Down Requirements and Restrictions
This section provides power-up and power-down sequence guidelines for the i.MX35 processor. irreversible damage to the i.MX35 processor (worst-case scenario).
4.3.1 Powering Up
- Assert Power on Reset (POR ).
- Turn on digital logic domain and IO power supply: VDD n, NVCCx
- Wait until VDD n and NVCCx power supplies are stable + 32 μs.
- Turn on all other power supplies: PHY1_VDDA, USBPHY1_VDDA_BIAS, PHY2_VDD,
USBPHY1_UPLLVDD, OSC24M_VDD, OSC_AUDIO_VDD, MVDD, PVDD, FUSEVDD. ARM is in wait for interrupt mode. Table 9. i.MX35 Power Modes (continued)
- Wait until PHY1_VDDA, USBPHY1_VDDA_BIAS, PHY2_VDD, USBPHY1_UPLLVDD,
Figure 2 shows the power-up sequence and timing. Figure 2. i.MX35 Power-Up Sequence and Timing
4.3.2 Powering Down
can be shut down at the same time.
4.4 Reset Timing
4.4.1 Power On Reset
of resetting the i.MX35 can also be supported by tying the POR_B and RESET_IN_B pins together. Figure 3. Timing Between POR_B and CKIL for Complete Reset of i.MX35
4.4.2 System Reset
RESET_IN_B. The following modules are not reset upon system reset: RTC, PLLs, CCM, and IIM. POR_B pin must be deasserted all the time. Figure 4. Timing Between RESET_IN_B and CKIL for i.MX35 System Reboot
4.5 Power Characteristics
- Measure worst case power consumption on individual rails using directed test on i.MX35.
- Correlate worst case power consumption power measurements with worst case power
- Combine common voltage rails based on power supply sequencing requirements
- Guard band worst case numbers for temperature and process variation. Guard band is based on
process data and correlated with actual data measured on i.MX35.
- The sum of individual rails is greater than real world power consumption, as a real system does
not typically maximize power consumption on all peripherals simultaneously.
4.6 Thermal Characteristics
Core via I.D: 0.168 mm, Core via plating 0.016 mm. Full array map design, but nearly all balls under die are power or ground. Table 10. Power Consumption
Table 11. Thermal Resistance Data
4.7 I/O Pin DC Electrical Characteristics
customized at three drive strength levels: normal, high, and max. Table 12 shows currents for the different DDR pin drive strength modes. specification for this package. for the case temperature. Reported value includes the thermal resistance of the interface layer. Table 12. DDR Pin Drive Strength Mode Current Levels Table 11. Thermal Resistance Data (continued)
NVCC for the SD/MMC interface refers to NVCC_SDIO. Table 13. I/O Pin DC Electrical Characteristics
3.3 V NVCC (for digital
Table 13. I/O Pin DC Electrical Characteristics (continued)
4.8 I/O Pin AC Electrical Characteristics
Figure 5 shows the load circuit for output pins. Figure 5. Load Circuit for Output Pin
Figure 6 shows the output pin transition time waveform. Figure 6. Output Pin Transition Time Waveform
4.8.1 AC Electrical Test Parameter Definitions
The zero voltage source is connect ed between pin and load capacitance. The current (through this source) derivative is calculated during output transitions. Table 14. AC Electrical Characteristics of GPIO Pins in Slow Slew Rate Mode Rise/Fall Typ. Rise/Fall Max. Table 15. AC Electrical Characteristics of GPIO Pins in Slow Slew Rate Mode Parameter Symbol Test Condition Min.
Table 16. AC Electrical Characteristics of GPIO Pins in Fast Slew Rate Mode for Parameter Symbol Test Condition Min. Table 17. AC Electrical Characteristics, GPIO Pins in Fast Slew Rate Mode Parameter Symbol Test Condition Min. Parameter Symbol Test Condition Min.
Table 18. AC Electrical Characteristics of GPIO Pins in Slow Slew Rate Mode Parameter Symbol Test Condition Min. Table 19. AC Electrical Characteristics of GPIO Pins in Fast Slew Rate Mode Parameter Symbol Test Condition Min.
4.8.2 AC Electrical Characteristics for DDR Pins (DDR2, Mobile DDR, and
Table 20. AC Electrical Characteristics of DDR Type IO Pins in DDR2 Mode Parameter Symbol Test Condition Min. Table 21. AC Requirements of DDR2 Pins indicates the voltage at which the differential output signal must cross. Cload = 25 pF .
Table 22. AC Electrical Characteristics of DDR Type IO Pins in mDDR Mode Parameter Symbol Test Condition Min. Table 23. AC Electrical Characteristics of DDR Type IO Pins in SDRAM Mode Parameter Symbol Test Condition Min. Table 24. AC Electrical Characteristics of DDR Type IO Pins in SDRAM Mode Max Drive (1.8 V) Parameter Symbol Test Condition Min.
4.9 Module-Level AC Electrical Specifications
the i.MX35. The modules are listed in alphabetical order.
4.9.1 AUDMUX Electrical Specifications
AUDMUX external pins is hence governed by the SSI module. See the electrical specification for SSI.
4.9.2 CSPI AC Electrical Specifications
the “External Signals and Multiplexing” chapter of the reference manual for more details. VIH to VIL for falling edge. 2 Max. condition for tdit: bcs model, 1.3 V, IO 1.95 V , and –40 °C. and –40 °C. Input transition time from pad is 5 ns (20%–80%). Table 24. AC Electrical Characteristics of DDR Type IO Pins in SDRAM Mode Max Drive (1.8 V) (continued) Parameter Symbol Test Condition Min.
4.9.3 DPLL Electrical Specifications
EXTAL24M, bypassing the internal oscillator. DPLL specifications are listed in Table 26.
4.9.4 Embedded Trace Macrocell (ETM) Electrical Specifications
access (TPA) that supports TRACECLK frequencies up to 133 MHz. Figure 9 depicts the TRACECLK timings of ETM, and Table 27 lists the timing parameters. Figure 9. ETM TRACECLK Timing Diagram Table 26. DPLL Specifications
2 Tdck1
1 There are two PLL are used in the i.MX35, MPLL and PPLL. Both are based on same DPLL design. Table 25. CSPI Interface Timing Parameters (continued)
Table 28 lists the timing parameters. Figure 10. Trace Data Timing Diagram
4.9.4.1 Half-Rate Clocking Mode
falling edges of TRACECLK, where TRACECLK is half the frequency of the clock shown in Figure 10.
4.9.5 EMI Electrical Specifications
This section provides electrical parametrics and timing for the EMI module.
4.9.5.1 NAND Flash Controller Interface (NFC)
Table 27. ETM TRACECLK Timing Parameters Table 28. ETM Trace Data Timing Parameters
which are not NFC clock related.
4.9.5.2 Wireless External Interface Module (WEIM)
in muxed mode where both rising and falling edge may be used according to control register configuration. 1 The flash clock maximum frequency is 50 MHz. 2 Subject to DPLL jitter specification listed in Table 26, "DPLL Specifications," on page 31. Table 29. NFC Timing Parameters1 (continued)
timing of the WEIM module, and Table 30 lists the timing parameters. Figure 15. WEIM Bus Timing Diagram
all controls, address, and BCLK is set to maximum drive. Table 30. WEIM Bus Timing Parameters 1 1 “High” is defined as 80% of signal value, and “low” is defined as 20% of signal value. 3 Parameters W18, W20, W22, and W24 are tested when FCE=1. i.MX35 does not support FCE=0.
Figure 26. DTACK Read Access Table 31. WEIM Asynchronous Timing Parameters Relative Chip Select Table
1 For the value of parameters WE4–WE21, see column BCD = 0 in Ta bl e 3 0. 2 CS Assertion. This bit field determines when the CS signal is asserted during read/write cycles. 3 CS Negation. This bit field determines when the CS signal is negated during read/write cycles. 4 BE Assertion. This bit field determines when the BE signal is asserted during read cycles. 5 BE Negation. This bit field determines when the BE signal is negated during read cycles. 6 Output maximum delay from internal driving ADDR/control FFs to chip outputs. 7 Output maximum delay from CS[x] internal driving FFs to CS[x] out. 8 DAT A maximum delay from chip input data to its internal FF . 9 DTACK maximum delay from chip dtack input to its internal FF . Note: All configuration parameters (CSA, CSN, WBEA, WBEN, LBA, LBN, OEN, OEA, RBEA, and RBEN) are in cycle units. Table 31. WEIM Asynchronous Timing Parameters Relative Chip Select Table (continued)
4.9.5.3 ESDCTL Electrical Specifications
mobile DDR or SDR SDRAM. Table 32 through Table 41 list the timing parameters. Figure 27. SDRAM Read Cycle Timing Diagram Table 32. DDR/SDR SDRAM Read Cycle Timing Parameters Note: CKE is high during the read/write cycle.
value. SD1 + SD2 does not exceed 7.5 ns for 133 MHz. parameters are measured at maximum memory frequency. Table 32. DDR/SDR SDRAM Read Cycle Timing Parameters (continued)
Figure 28. SDR SDRAM Write Cycle Timing Diagram Table 33. SDR SDRAM Write Timing Parameters
defined as 80% of signal value and “low” is defined as 20% of signal value. The timing parameters are similar to the ones used in SDRAM data sheets. measured at maximum memory frequency. Figure 29. SDRAM Refresh Timing Diagram Table 34. SDRAM Refresh Timing Parameters
The timing parameters are similar to the ones used in SDRAM data sheets. measured at maximum memory frequency. Figure 30. SDRAM Self-Refresh Cycle Timing Diagram 1 SD10 and SD11 are determined by SDRAM controller register settings. Table 34. SDRAM Refresh Timing Parameters (continued)
will be stopped in low state. Figure 31. DDR2 SDRAM Basic Timing Parameters Table 35. SDRAM Self-Refresh Cycle Timing Parameters Table 36. DDR2 SDRAM Timing Parameter Table
Table 37. Derating Values for DDR2–400, DDR2–533
Table 38. DDR Single-ended Slew Rate drive strength is Medium for SDCLK and High for Address and controls. Figure 34. DDR2 SDRAM DQ vs. DQS and SDCLK READ Cycle Timing Diagram
drive strength is Medium for SDCLK and High for Address and controls. Figure 35. Mobile DDR SDRAM Write Cycle Timing Diagram Table 39. DDR2 SDRAM Read Cycle Parameter Table read cycles related to DQS). Table 40. Mobile DDR SDRAM Write Cycle Timing Parameters 1 1 T est condition: Measured using delay line 5 programmed as follows: ESDCDLY5[15:0] = 0x0703.
The timing parameters are similar to the ones used in SDRAM data sheets. measured at maximum memory frequency. Figure 36. Mobile DDR SDRAM DQ versus DQS and SDCLK Read Cycle Timing Diagram defined as 50% of signal value. The timing parameters are similar to the ones used in SDRAM data sheets. measured at maximum memory frequency. Table 41. Mobile DDR SDRAM Read Cycle Timing Parameters
4.9.6 Enhanced Serial Audio Interface (ESAI) Timing Specifications
found in Figure 37 and Figure 38. Table 42. Enhanced Serial Audio Interface Timing
62 Clock cycle 4 tSSICC 4 × Tc
63 Clock high period
64 Clock low period
65 SCKR rising edge to FSR out (bl) high —
66 SCKR rising edge to FSR out (bl) low —
67 SCKR rising edge to FSR out (wr) high
68 SCKR rising edge to FSR out (wr) low
69 SCKR rising edge to FSR out (wl) high —
70 SCKR rising edge to FSR out (wl) low —
71 Data in setup time before SCKR (SCK in synchronous
72 Data in hold time after SCKR falling edge —
73 FSR input (bl, wr) high before SCKR falling edge
74 FSR input (wl) high before SCKR falling edge —
75 FSR input hold time after SCKR falling edge —
78 SCKT rising edge to FST out (bl) high —
79 SCKT rising edge to FST out (bl) low —
80 SCKT rising edge to FST out (wr) high 5 —
81 SCKT rising edge to FST out (wr) low
82 SCKT rising edge to FST out (wl) high —
83 SCKT rising edge to FST out (wl) low —
84 SCKT rising edge to data out enable from high
86 SCKT rising edge to data out valid —
87 SCKT rising edge to data out high impedance
89 FST input (bl, wr) setup time before SCKT falling edge
90 FST input (wl) setup time before SCKT falling edge —
91 FST input hold time after SCKT falling edge —
3 SCKT(SCKT pin) = transmit clock
4 For the internal clock, the external clock cycle is defined by Icyc and the ESAI control register. second-to-last bit clock of the first word in the frame. 6 Periodically sampled and not 100% tested. Table 42. Enhanced Serial Audio Interface Timing (continued)
Figure 37. ESAI Transmitter Timing
Figure 39. eSDHCv2 Timing Table 43. eSDHCv2 Interface Timing Specification 1 In low-speed mode, the card clock must be lower than 400 kHz, voltage ranges from 2.7 to 3.6 V. clock frequency can be any value between 0–50 MHz. frequency can be any value between 0–52 MHz. 4 To satisfy hold timing, the delay difference between clock input and cmd/data input must not exceed 2 ns.
4.9.8 Fast Ethernet Controller (FEC) AC Electrical Specifications
rate uses seven of the MII pins for connection to an external Ethernet transceiver.
4.9.8.1 FEC AC Timing
transceivers operating at a voltage of 3.3 V .
4.9.8.2 MII Receive Signal Timing
must exceed twice the FEC_RX_CLK frequency. Table 44 lists MII receive channel timings. 1 FEC_RX_DV , FEC_RX_CLK, and FEC_RXD0 have the same timing when in 10 Mbps 7-wire interface mode. Figure 40 shows the MII receive signal timings listed in Table 44. Figure 40. MII Receive Signal Timing Diagram Table 44. MII Receive Signal Timing
4.9.8.3 MII Transmit Signal Timing
must exceed twice the FEC_TX_CLK frequency. Table 45 lists MII transmit channel timings. 1 FEC_TX_EN, FEC_TX_CLK, and FEC_TXD0 have the same timing when in 10 Mbps 7-wire interface mode. Figure 41 shows the MII transmit signal timings listed in Table 45. Figure 41. MII Transmit Signal Timing Diagram
4.9.8.4 MII Asynchronous Inputs Signal Timing
1 FEC_COL has the same timing in 10 Mbit 7-wire interface mode. Table 45. MII Transmit Signal Timing Table 46. MII Asynch Inputs Signal Timing
Figure 42 shows MII asynchronous input timings listed in Table 46. Figure 42. MII Asynch Inputs Timing Diagram
4.9.8.5 MII Serial Management Channel Timing
specification. However the FEC can function correctly with a maximum MDC frequency of 15 MHz. Table 47. MII Transmit Signal Timing M11 FEC_MDC falling edge to FEC_MDIO output valid (max.
Figure 43 shows MII serial management channel timings listed in Table 47. Figure 43. MII Serial Management Channel Timing Diagram
4.9.9 FIR Electrical Specifications
Association). Refer to the IrDA® website for details on FIR and MIR protocols.
4.9.10 FlexCAN Module AC Electrical Specifications
4.9.11 I 2C AC Electrical Specifications
This section describes the electrical characteristics of the I2C module.
4.9.11.1 I 2C Module Timing
Figure 44 depicts the timing of the I2C module. Table 48 lists the I2C module timing parameters. Figure 44. I2C Bus Timing Diagram Table 48. I2C Module Timing Parameters 2 The maximum hold time has to be met only if the device does not stretch the LOW period (ID IC6) of the I2CLK signal. 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the I2CLK signal. specification) before the I2CLK line is released.
4.9.12 IPU—Sensor Interfaces
4.9.12.1 Supported Camera Sensors
Table 49 lists the known supported camera sensors at the time of publication.
4.9.12.2 Functional Description
There are three timing modes supported by the IPU. signals. The timing syntax is defined by the BT.656 standard. signal used is SENSB_PIX_CLK. Start-of-frame and active-line signals are embedded in the data stream. Table 49. Supported Camera Sensors 1 2 These sensors have not been validated at the time of publication.
stream, thus recovering SENSB_VSYNC and SENSB_HSYNC signals for internal use.
4.9.12.2.2 Gated Clock Mode
Figure 45. Gated Clock Mode Timing Diagram is valid as long as SENSB_HSYNC is high. Data is latched at the rising edge of the valid pixel clocks. the SENSB_VSYNC timing repeats.
4.9.12.2.3 Non-Gated Clock Mode
low) until valid data is going to be transmitted over the bus. Figure 46. Non-Gated Clock Mode Timing Diagram
active-high/low SENSB_HSYNC; and rising/falling-edge triggered SENSB_PIX_CLK.
4.9.12.3 Electrical Characteristics
Figure 47 depicts the sensor interface timing, and Table 50 lists the timing parameters. Figure 47. Sensor Interface Timing Diagram
4.9.13 IPU — Display Interfaces
Table 50. Sensor Interface Timing Parameters
4.9.13.1 Synchronous Interfaces
4.9.13.1.4 Interface to Active Matrix TFT LCD Panels, Functional Description
selected). In active mode, DISPB_D3_CLK runs continuously. DISPB_D3_HSYNC causes the panel to start a new line. data to be shifted to the display. When disabled, the data is invalid and the trace is off. Figure 48. Interface Timing Diagram for TFT (Active Matrix) Panels
4.9.13.1.5 Interface to Active Matrix TFT LCD Panels, Electrical Characteristics
DI_DISP3_TIME_CONF Register. Figure 51. Synchronous Display Interface Timing Diagram—Access Level
1 Display interface clock period immediate value
Display interface clock period average value. Table 51. Synchronous Display Interface Timing Parameters—Pixel Level (continued)
4.9.13.2 Interface to Sharp HR-TFT Panels
Table 52. Synchronous Display Interface Timing Parameters—Access Level 1 The exact conditions have not been finalized, but will likely match the current customer requirement for their specific display. These conditions may be device specific.
2 Display interface clock down time
3 Display interface clock up time
where CEIL(X) rounds the elements of X to the nearest integers toward infinity.
images correspond to straight polarity of the Sharp signals. Figure 52. Sharp HR-TFT Panel Interface Timing Diagram—Pixel Level Table 53. Sharp Synchronous Display Interface Timing Parameters—Pixel Level
1 DISPB_D3_CLK period
Example is drawn with FW + 1 = 320 pixel/line, FH + 1 = 240 lines. SPL pulse width is fixed and aligned to the first data of the line. REV toggles every HSYNC period.
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 6 Freescale Semiconductor74
4.9.13.3 Synchronous Interface to Dual-Port Smart Displays
Functionality and electrical characteristics of the synchronous interface to dual-port smart displays are TFT LCD Panels, Electrical Characteristics.”
4.9.13.3.6 Interface to a TV Encoder—Functional Description
The interface has an 8-bit data bus, transferring a single 8-bit value (Y/U/V) in each cycle. The bits D7–D0 of the value are mapped to bits LD17–LD10 of the data bus, respectively. Figure 53 depicts the interface timing. The frequency of the clock DISPB_D3_CLK is 27 MHz. The DISPB_D3_HSYNC, DISPB_D3_VSYNC and DISPB_D3_DRDY signals are active low. The transition to the next row is marked by th e negative edge of the DISPB_D3_HSYNC signal. It remains low for a single clock cycle. The transition to the next field/frame is marked by the negative edge of the DISPB_D3_VSYNC signal. It remains low for at least one clock cycle. — At a transition to an odd field (of the next frame), the negative edges of DISPB_D3_VSYNC and DISPB_D3_HSYNC coincide. — At a transition to an even field (of the same frame), they do not coincide. The active intervals—during which data is transferred—are marked by the DISPB_D3_HSYNC signal being high. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B.
Figure 53. TV Encoder Interface Timing Diagram
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 6 Freescale Semiconductor76
4.9.13.3.7 Interface to a TV Encoder, Electrical Characteristics
The timing characteristics of the TV encoder interface are identical to the synchronous display Characteristics.”
4.9.13.4 Asynchronous Interfaces
This section discusses the asynchronous parallel and serial interfaces.
4.9.13.4.8 Parallel Interfaces, Functional Description
The IPU supports the following asynchronous parallel interfaces: System 80 interface — Type 1 (sampling with the chip select signal) with and without byte enable signals. — Type 2 (sampling with the read and write si gnals) with and without byte enable signals. System 68k interface — Type 1 (sampling with the chip select signal) with or without byte enable signals. — Type 2 (sampling with the read and write si gnals) with or without byte enable signals. For each of four system interfaces, there are three burst modes: 1. Burst mode without a separate clock—The burst length is defined by the corresponding parameters of the IDMAC (when data is transferred from the system memory) or by the HBURST signal (when the MCU directly accesses the display via the slave AHB bus). For system 80 and system 68k type 1 interfaces, data is sampled by the CS signal and other control signals change only when transfer direction is changed during the burst. For type 2 interfaces, data is sampled by the WR/RD signals (system 80) or by the ENABLE signal (system 68k), and the CS signal stays active during the whole burst. 2. Burst mode with the separate clock DISPB_BCLK—In this mode, data is sampled with the DISPB_BCLK clock. The CS signal stays active during whole burst transfer. Other controls are changed simultaneously with data when the bus state (read, write or wait) is altered. The CS signals and other controls move to non-active state after burst has been completed. 3. Single access mode—In this mode, slave AHB and DMA burst are broken to single accesses. The data is sampled with CS or other controls according to the interface type as described above. All controls (including CS) become non-active for one display interface clock after each access. This mode corresponds to the ATI single access mode. Both system 80 and system 68k interfaces are supported for all described modes as depicted in Figure 54, Figure 55, Figure 56, and Figure 57. These timing images correspond to active-low DISPB_Dn_CS, DISPB_Dn_WR and DISPB_Dn_RD signals. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B.
accesses to different displays. The range of this pause is from 4 to 19 HSP_CLK cycles. Figure 54. Asynchronous Parallel System 80 Interface (Type 1) Burst Mode Timing Diagram
Figure 55. Asynchronous Parallel System 80 Interface (Type 2) Burst Mode Timing Diagram
Figure 56. Asynchronous Parallel System 68k Interface (Type 1) Burst Mode Timing Diagram
Figure 57. Asynchronous Parallel System 68k Interface (Type 2) Burst Mode TIming Diagram
Figure 58. Parallel Interface Timing Diagram—Read Wait States
4.9.13.4.9 Parallel Interfaces, Electrical Characteristics
Figure 59. Asynchronous Parallel System 80 Interface (Type 1) Timing Diagram
Figure 60. Asynchronous Parallel System 80 Interface (Type 2) Timing Diagram
Figure 61. Asynchronous Parallel System 68k Interface (Type 1) Timing Diagram
Figure 62. Asynchronous Parallel System 68k Interface (Type 2) Timing Diagram Table 54. Asynchronous Parallel Interface Timing Parameters—Access Level
8 T racc 0 — Tdrp 9 –T l b d10 –T d i c u r–
1The exact conditions have not been finalized, but will likely match the current customer requirement for their specific display. These conditions may be device-specific.
2 Display interface clock period value for read:
3 Display interface clock period value for write:
4 Display interface clock down time for read:
5 Display interface clock up time for read:
6 Display interface clock down time for write:
7 Display interface clock up time for write:
8 This parameter is a requirement to the display connected to the IPU
Table 54. Asynchronous Parallel Interface Timing Parameters—Access Level (continued)
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 6 Freescale Semiconductor 87 The following parameters are programmed via the DI_DISP#_TIME_CONF_1, DI_DISP#_TIME_CONF_2, and DI_HSP_CLK_PER registers: HSP_CLK_PERIOD DISP#_READ_EN
4.9.13.5 Serial Interfaces, Functional Description
The IPU supports the following types of asynchronous serial interfaces: 3-wire (with bidirectional data line) 4-wire (with separate data input and output lines) 5-wire type 1 (with sampling RS by the serial clock) 5-wire type 2 (with sampling RS by the chip select signal) Figure 63 depicts timing of the 3-wire serial interface. The timing images correspond to active-low DISPB_D#_CS signal and the straight polarity of the DISPB_SD_D_CLK signal. For this interface, a bidirectional data line is used outside the device. The IPU still uses separate input and output data lines (IPP_IND_DISPB_SD_D and IPP_DO_DISPB_SD_D). The I/O mux connects the internal data lines to the bidirectional external line according to the IPP_OBE_DISPB_SD_D signal provided by the IPU. Each data transfer can be preceded by an optional preamble with programmable length and contents. The preamble is followed by read/write (RW) and address (RS) bits. The order of the these bits is programmable. The RW bit can be disabled. The following data can consist of one word or of a whole burst. The interface parameters are controlled by the DI_SER_DISPn_CONF registers (n = 1, 2).
9 Data read point
10 Loopback delay Tlbd is the cumulative propagation delay of read controls and read data. It includes an IPU output delay, a device – level output delay, board delays, a device – level input delay, an IPU input delay. This value is device specific. Tdrp T HSP_CLK ceil DISP#_READ_EN Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B.
4.9.13.5.10 Serial Interfaces, Electrical Characteristics
Figure 67 depicts timing of the serial interface. Table 55 lists the timing parameters at display access level. Figure 67. Asynchronous Serial Interface Timing Diagram Table 55. Asynchronous Serial Interface Timing Parameters—Access Level
8 T racc 0 — Tdrp 9 –T l b d10 –T d i c u r
1 The exact conditions have not been finalized, but will likely match the current customer requirement for their specific display. These conditions may be device specific. 8 This parameter is a requirement to the display connected to the IPU. Table 55. Asynchronous Serial Interface Timing Parameters—Access Level (continued)
4.9.14 Memory Stick Host Controller (MSHC)
Figure 68. MSHC_CLK Timing Diagram
9 Data read point:
device-level output delay, board delays, a device-level input delay, and an IPU input delay. This value is device specific.
Figure 69. Transfer Operation Timing Diagram (Serial)
Figure 70. Transfer Operation Timing Diagram (Parallel) modes, and not the i.MX35 timing. Table 56. Serial Interface Timing Parameters 1
4.9.15 MediaLB Controller Electrical Specifications
This section describes the electrical information of the MediaLB Controller module. restrictions described in Table 57. Table 57. Parallel Interface Timing Parameters 1 restrictions described in Table 7. Table 58. MLB 256/512 Fs Timing Parameters Table 56. Serial Interface Timing Parameters 1 (continued)
specified from the valid voltage threshold as listed below unless otherwise noted. 1 The MLB controller can shut off MLBCLK to place MediaLB in a low-power state. time period. Therefore, coupling must be minimized while meeting the maximum capacitive load listed. Table 59. MLB Device 1024Fs Timing Parameters Table 58. MLB 256/512 Fs Timing Parameters (continued)
Figure 72 depicts write 0 sequence timing, and Table 61 lists the timing parameters. Figure 72. Write 0 Sequence Timing Diagram Figure 73. Write 1 Sequence Timing Diagram Figure 74. Read Sequence Timing Diagram
4.9.17 Parallel ATA Module AC Electrical Specifications
mode has a different data transfer rate, Ultra DMA mode 4 data transfer rate is up to 100 MBps. Table 61. WR0 Sequence Timing Parameters Table 62. WR1/RD Timing Parameters
4.9.17.1 General Timing Requirements
Table 63 and Figure 75 define the AC characteristics of the interface signals on all data transfer modes. Figure 75. ATA Interface Signals Timing Diagram
4.9.17.2 ATA Electrical Specifications (ATA Bus, Bus Buffers)
This section discusses A TA parameters. For a detailed description, refer to the ATA-6 specification. Level shifters are required for 3.3-V or 5.0-V compatibility on the A TA interface. of bus buffers is not recommended if fast UDMA mode is required. specify the slew rate of the outgoing signals. on the host and device tri-state buses is always avoided. Table 63. AC Characteristics of All Interface Signals all capacitive loads from 15 pF through 40 pF , where all signals have the same capacitive load value.
4.9.17.3 Timing Parameters
implementation of the A TA interface on silicon, the bus buffer used, the cable delay, and the cable skew. Table 64. ATA Timing Parameters 1 Values provided where applicable.
4.9.17.4 PIO Mode Timing
Figure 76 shows timing for PIO read, and Table 65 lists the timing parameters for PIO read. Figure 76. PIO Read Timing Diagram Table 65. PIO Read Timing Parameters
4.9.17.5 UDMA-In Timing
Table 68 lists the timing parameters for the UDMA-in burst. Figure 80. UDMA-In Transfer Starts Timing Diagram Figure 81. UDMA-In Host Terminates Transfer Timing Diagram Table 67. MDMA Read and Write Timing Parameters (continued)
4.9.17.6 UDMA-Out Timing
Table 69 lists the timing parameters for the UDMA-out burst. Figure 83. UDMA-Out Transfer Starts Timing Diagram Figure 84. UDMA-Out Host Terminates Transfer Timing Diagram
4.9.18 Parallel Interface (ULPI) Timing
Electrical and timing specifications of the parallel interface are presented in the subsequent sections. Figure 86. USB Transmit/Receive Waveform in Parallel Mode
4.9.19 PWM Electrical Specifications
Table 70. Signal Definitions—Parallel Interface USB_Clk In Interface clock. All interface signals are synchronous to the clock. USB_Data[7:0] I/O Bidirectional data bus, driven low by the link during idle. Bus ownership is determined by Dir. USB_Dir In Direction. Control the direction of the data bus. USB_Stp Out Stop. The link asserts this signal for 1 clock cycle to stop the data stream currently on the bus. USB_Nxt In Next. The PHY asserts this signal to throttle the data. Table 71. USB Timing Specification in VP_VM Unidirectional Mode
periods with duty cycle of 50 percent.
4.9.20 SJC Electrical Specifications
Figure 90 depicts the SJC TRST timing, and Table 72 lists the SJC timing parameters. Figure 87. Test Clock Input Timing Diagram Figure 88. Boundary Scan (JTAG) Timing Diagram
4.9.21 SPDIF Timing
a clock that is twice the bit rate of the data signal. SPDIF in Rx mode and the timing of the modulating Tx clock (STCLK). for SPDIF in Tx mode.
2 VM = mid point voltage
Table 73. SPDIF Timing Parameters Table 72. SJC Timing Parameters (continued)
Figure 91. SRCK Timing Figure 92. STCLK Timing
4.9.22 SSI Electrical Specifications
This section describes electrical characteristics of the SSI.
4.9.22.1 SSI Transmitter Timing with Internal Clock
Figure 93 depicts the SSI transmitter timing with internal clock, and Table 74 lists the timing parameters. Figure 93. SSI Transmitter with Internal Clock Timing Diagram
Table 74. SSI Transmitter with Internal Clock Timing Parameters
4.9.22.2 SSI Receiver Timing with Internal Clock
Figure 94. SSI Receiver with Internal Clock Timing Diagram
Table 75. SSI Receiver with Internal Clock Timing Parameters
4.9.22.3 SSI Transmitter Timing with External Clock
Figure 95 depicts the SSI transmitter timing with external clock, and Table 76 lists the timing parameters. Figure 95. SSI Transmitter with External Clock Timing Diagram
Table 76. SSI Transmitter with External Clock Timing Parameters
4.9.22.4 SSI Receiver Timing with External Clock
Figure 96 depicts the SSI receiver timing with external clock, and Table 77 lists the timing parameters. Figure 96. SSI Receiver with External Clock Timing Diagram Table 77. SSI Receiver with External Clock Timing Parameters
4.9.23 UART Electrical
This section describes the electrical information of the UART module.
4.9.23.1 UART RS-232 Serial Mode Timing
The following subsections give the UART transmit and receive timings in RS-232 serial mode.
4.9.23.1.11 UART Transmitter
Figure 97 depicts the transmit timing of UART in RS-232 serial mode, with 8 data bit/1 stop bit format. Table 78 lists the UART RS-232 serial mode transmit timing characteristics. Figure 97. UART RS-232 Serial Mode Transmit Timing Diagram Table 77. SSI Receiver with External Clock Timing Parameters (continued)
4.9.23.1.12 UART Receiver
serial mode receive timing characteristics. Figure 98. UART RS-232 Serial Mode Receive Timing Diagram
4.9.23.2 UART IrDA Mode Timing
The following subsections give the UART transmit and receive timings in IrDA mode.
4.9.23.2.13 UART IrDA Mode Transmitter
the transmit timing characteristics. Figure 99. UART IrDA Mode Transmit Timing Diagram Table 78. RS-232 Serial Mode Transmit Timing Parameters 1 Fbaud_rate: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16. 2 Tref_clk: The period of UART reference clock ref_clk (ipg_perclk after RFDIV divider). Table 79. RS-232 Serial Mode Receive Timing Parameters 2 Fbaud_rate: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency) ÷ 16.
4.9.23.2.14 UART IrDA Mode Receiver
the receive timing characteristics. Figure 100. UART IrDA Mode Receive Timing Diagram
4.9.24 USB Electrical Specifications
Table 80. IrDA Mode Transmit Timing Parameters 1 Fbaud_rate: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16. 2 Tref_clk: The period of UART reference clock ref_clk (ipg_perclk after RFDIV divider). Table 81. IrDA Mode Receive Timing Parameters 2 Fbaud_rate: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency) ÷ 16.
4.9.24.1 DAT_SE0 Bidirectional Mode
transmit and receive waveforms respectively. Figure 101. USB Transmit Waveform in DAT_SE0 Bidirectional Mode Figure 102. USB Receive Waveform in DAT_SE0 Bidirectional Mode Table 82. Signal Definitions—DAT_SE0 Bidirectional Mode
Table 83 describes the port timing specification in DAT_SE0 bidirectional mode.
4.9.24.2 DAT_SE0 Unidirectional Mode
transmit and receive waveforms respectively. Figure 103. USB Transmit Waveform in DAT_SE0 Unidirectional Mode Table 83. Port Timing Specification in DAT_SE0 Bidirectional Mode Table 84. Signal Definitions—DAT_SE0 Unidirectional Mode
Figure 104. USB Receive Waveform in DAT_SE0 Unidirectional Mode Table 85 describes the port timing specification in DAT_SE0 unidirectional mode.
4.9.24.3 VP_VM Bidirectional Mode
and receive waveforms respectively. Table 85. USB Port Timing Specification in DAT_SE0 Unidirectional Mode Table 86. Signal Definitions—VP_VM Bidirectional Mode
4.9.24.4 VP_VM Unidirectional Mode
transmit and receive waveforms respectively. Figure 107. USB Transmit Waveform in VP_VM Unidirectional Mode Table 88. Signal Definitions—VP_VM Unidirectional Mode Table 87. USB Port Timing Specification in VP_VM Bidirectional Mode (continued)
Figure 108. USB Receive Waveform in VP_VM Unidirectional Mode Table 89 describes the port timing specification in VP_VM unidirectional mode. Table 89. USB Timing Specification in VP_VM Unidirectional Mode
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 6 Freescale Semiconductor130
5 Package Information and Pinout
This section includes the following: Mechanical package drawing Pin/contact assignment information Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B.
See Figure 109 for the package drawing and dimensions of the production package. Figure 109. Production Package: Mechanical Drawing
5.2 MAPBGA Signal Assignments
ballmap be used to implement the layout. Table 90. Silicon Revision 2.0 Signal Ball Map Locations
Table 90. Silicon Revision 2.0 Signal Ball Map Locations (continued)
Table 91. Silicon Revision 2.1 Signal Ball Map Locations
Table 91. Silicon Revision 2.1 Signal Ball Map Locations (continued)
Table 92. Silicon Revision 2.0 Ball Map—17 x 17, 0.8 mm Pitch
Table 93. Silicon Revision 2.1 Ball Map—17 x 17, 0.8 mm Pitch
6 Product Documentation
All related product documentation for the i.MX35 processor is located at http://www.freescale.com/imx.
7 Revision History
Table 94 shows the revision history of this document. Table 94. i.MX35 Data Sheet Revision History Filled in TBDs in Ta ble 13. Revised Figure 15 and Ta ble 30 by removing FCE = 0 and FCE = 1. Added footnote 3 to the table. SDRAM Mode,” to exclude mention of slew rate. 3 03/2009 In Section 4.3.1, “Powering Up,” reverse positions of steps 5 and 6. SDRAM timing. Inserted DDR2 SDRAM timing.
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