IMX27L

MCIMX27VOP4A FREESCALE | Alldatasheet

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© Freescale Semiconductor, Inc., 2008. All rights reserved. Preliminary—Subject to Change Without Notice Freescale Semiconductor Data Sheet, Advance Information This document contains information on a product under development. Freescale reserves the right to change or discontinue this product without notice. Document Number: MCIMX27 Rev. 1, 1/2008 This document contains information on a new product. Specifications and information herein are subject to change without notice. i.MX27 and i.MX27L

Package Information

(MAPBGA–404)

Ordering Information

See Table 1 on page 4 for ordering information.

1 Introduction

The MCIMX27/MCIMX27L (i.MX27 and i.MX27L) Multimedia Applications Processors represent the next step in low-power, high-performance applications processors. Unless otherwise specified, the material in this data sheet is applicable to both the i.MX27 and i.MX27L processors and is referred to singularly throughout this document as i.MX27. The i.MX27L does not include the following features: ATA-6 HDD Interface, Memory Stick Pro, VPU, MPEG-4/ H.263/H.264 HW encoder/decoder, and eMMA (PrP processing, CSC, deblock, dering). Based on an ARM926EJ-S™ microprocessor core, the i.MX27/i.MX27L processor provides the performance with low-power consumption required by modern digital devices such as the following:

• Feature-rich cellular phones
• Portable media players and mobile gaming machines
• Personal digital assistants (PDAs) and wireless PDAs i.MX27 and i.MX27L Data Sheet Multimedia Applications Processor

Contents

2 Functional Description and

2.1 ARM926 Microprocessor Core Platform . . . 4 3.5 Module-Level Electrical Specifications . . . 44

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• Portable DVD players
• Digital cameras The i.MX27/MX27L processor features the advanced and power-efficient ARM926EJ-S core operating at speeds up to 400 MHz, and is optimized for minimal power consumption using the most advanced techniques for power saving (for example, DPTC, power gating, and clock gating). With 90 nm technology and dual Vt, the i.MX27/MX27L device provides the optimal performance vs. leakage current balance. The performance of the i.MX27/MX27L processors are both boosted by an on-chip cache system, and features peripheral devices, such as an MPEG-4, H.263, an H.264 video codec (up to D1—720 x 486—@ 30 FPS), LCD, eMMA_lt, and CMOS Sensor Interface controllers. The i.MX27/MX27L processors supports connections to various types of external memories, such as 266-MHz DDR, NAND Flash, NOR Flash, SDRAM, and SRAM. The i.MX27/MX27L devices can be connected to a variety of external devices using technology, such as high-speed USBOTG 2.0, the Advanced Technology Attachment (ATA), Multimedia/Secure Data (MMC/SDIO), and CompactFlash. NOTE The i.MX27L does not support the ATA-6 HDD interface.

1.1 Features

The MX27/MX27L processors are targeted for video and voice over-IP (V2IP) and smart remote controllers. It also provides low-power solutions for any high-performance and demanding multimedia and graphics applications. The systems include the following features:

• Multi-standard video codec (i.MX27 only) — MPEG-4 part-II simple profile encoding/decoding — H.264/A VC baseline profile encoding/decoding — H.263 P3 encoding/decoding — Multi-party call: one stream encoding and two streams decoding simultaneously — Multi-format: encodes MPEG-4 bitstream, and decodes H.264 bitstream simultaneously — On-the-fly video processing that reduces system memory load (for example, the power-efficient viewfinder application with no involvement of either the memory system or the ARM CPU)
• Advanced power management (i.MX27/27L) — Dynamic process and te mperature compensation — Multiple clock and power domains — Independent gating of power domains
• Multiple communication and expansion ports

1.2 Block Diagram

Figure 1 shows the i.MX27 simplified interface block diagram. Figure 1. i.MX27/MX27L Simplified Interface Block Diagram

• ATA-6 HDD Interface
• Memory Stick Pro
• VPU: MPEG-4/ .263/H.264 HW encoder/decoder
• eMMA (PrP processing, CSC, deblock, dering)

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1.3 Ordering Information

Table 1 provides ordering information for the MAPBGA, lead-free packages.

2 Functional Description and Application Information

2.1 ARM926 Microprocessor Core Platform

crossbar switch (MAX), and a “primary AHB” complex.

• The instruction bus (I-AHB) of the ARM926EJ-S pr ocessor is connected directly to MAX Master Port 0.
• The data bus (D-AHB) of the ARM926EJ-S processo r is connected directly to MAX Master Port 1. Four alternate bus master interfaces are connected to MAX Master Ports 2–5. Three slave ports of the MAX are AHB-Lite compliant buses. Slave Port 0 is designated as the “primary” AHB. The primary AHB is internal to the platform and has five slaves connected to it: the AITC interrupt module, the MCTL memory controller, and two AIPI peripheral interface gaskets. Slave Ports 1 and 2 of the MAX are referred to as “secondary” AHBs. Each of the secondary AHB interfaces is only accessible off platform. The ARM926EJ-S processor supports the 32-bit and 16-bit ARM Thumb instruction sets, enabling the user to trade off between high performance and high-code density. The ARM926EJ-S processor includes features for efficient execution of Java byte codes, providing Java performance similar to the just-in-time (JIT) compiler—which is a type of Java comp iler—but without the associated code overhead. The ARM926EJ-S processor supports the ARM debug architecture and includes logic to assist in both hardware and software debugging. The ARM926EJ-S processor has a Harvard cached architecture and provides a complete high-performance processor subsystem, including the following:
• An ARM9EJ-S integer core
• A memory management unit (MMU)
• Separate instruction and data AMBA AHB bus interfaces
• ETM and JTAG-based debug support The ARM926EJ-S processor provides support for external coprocessors enabling floating-point or other application-specific hardware acceleration to be added. The ARM926EJ-S processor implements ARM architecture version 5TEJ. The four alternate bus master ports on the ARM926 Platform, which are connected directly to master ports of the MAX, are designed to support connections to multiple AHB masters external to the platform. An external arbitration AHB control module is needed if multiple external masters are desired to share an

Table 1. Ordering Information

support seamless connection to a single master with no external interface logic required. implementation of several clock synchronization circuits.

2.1.1 Memory System

applications. There is also a 24-Kbyte ROM for bootstrap code.

2.2 Module Inventory

module description for additional information. Table 2. Digital and Analog Modules peripherals that conforms to the IP Bus specification, Rev 2.0. with IDE hard disc drives and ATAPI optical disc drives. Note: This feature is not available on MX27L. point-to-multipoint configurations.

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The i.MX27/MX27L processors have three CSPI modules. resizing, and color space conversions. Note: This feature is not available on MX27L.

• Multi-Master Memory Interface (M3IF)
• Enhanced SDRAM/MDDR memory controller (ESDRAMC)
• PCMCIA memory controller (PCMCIA)
• NAND Flash Controller (NFC)
• Wireless External Interface Module (WEIM) ESDRAMC Enhanced SDRAM Controller External Memory Interface The ESDRAMC provides interface and control for synchronous DRAM memories for the system. 2.3.12/15 FEC Fast Ethernet Controller Connectivity Peripheral The FEC performs the full set of IEEE Std 802.3™/Ethernet CSMA/CD media access control and channel interface functions. The FEC supports connection and functionality for the 10/100 Mbps 802.3 media independent interface (MII). It requires an external transceiver (PHY) to complete the interface to the media. 2.3.13/15 GPIO General Purpose I/O Module Pins The GPIO provides 32 bits of bidirectional, general purpose I/O. This peripheral provides dedicated general-purpose pins that can be configured as either inputs or outputs. 2.3.14/16 GPT General Purpose Timer Timer Peripheral The GPT is a multipurpose module used to measure intervals or generate periodic output. 2.3.15/16 I 2C Inter IC Communicatio n Connectivity Peripheral The I2C provides serial interface to control the sensor interface and other external devices. Data rates of up to 100 Kbits/s are supported. 2.3.16/16 IIM IC Identification Module Security The IIM provides an interface for reading—and in some cases, programming, and overriding identification and control information stored in on-chip fuse elements. 2.3.17/17 JTAGC JTAG Controller Debug The JTAGC provides debug access to the ARM926 core, built-in self-test (BIST), and boundary scan test control. 2.3.18/17

Table 2. Digital and Analog Modules (continued)

to the customer memory stick. Note: This feature is not available on MX27L. interface to standard NAND Flash memory devices. external analog power switching logic and buffering. memory and assists with boot authentication.

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used on cell phone baseband processors or wireless PDAs. blocks—the Secure RAM module, and the Security Monitor. and performing data accesses to and from the cards. buffer to the external display device. 2S) and Intel AC97 standard.

• USB Host 1 is designed to support transceiverless connection to the on-board peripherals in Low Speed and Full Speed mode, and connection to the ULPI (UTMI+Low-Pin Court) and Legacy Full Speed transceivers
• USB Host 2 is designed to support transceiverless connection to the Cellular Modem Baseband Processor
• The USBOTG controller offers HS/FS/LS capabilities in Host mode and HS/FS in device mode. In Host mode, the controller supports direct connection of a FS/LS device (without external hub). In device (bypass) mode, the OTG port functions as gateway between the Host 1 Port and the OTG transceiver. 2.3.36/24 Video Codec Video Codec Hardware Acceleration Video Codec module supports full duplex video codec with 25 fps VGA image resolution, integrates H.264 BP, MPEG-4 SP and H.263 P3 video processing standard together. Note: This feature is not available on MX27L. 2.3.39/26

2.3 Module Descriptions

arranged in alphabetical order. register to send and receive bits over the 1-Wire bus.

2.3.2 AHB-Lite IP Interface Module (AIPI)

• All peripheral read transactions require a minimum of two system clocks (R-AHB side) and all write transactions require a minimum of three system clocks (R-AHB side).
• The AIPI supports 8-bit, 16-bit, and 32-bit IP bus peripherals. Byte, half word, and full word reads and writes are supported.
• The AIPI supports multi-cycle accesses by provi ding 16-bit to 8-bit peripherals operations and 32-bit to both 16-bit and 8-bit peripherals operations.
• The AIPI supports 31 external IP bus periphera ls each with a 4-Kbyte memory map (a slot). WDOG Watchdog Timer Module Timer Peripheral The WDOG module protects against system failures by providing a method for the system to recover from unexpected events or programming errors. 2.3.37/26 WEIM Wireless External Interface Module External Memory Interface The Wireless External Module (WEIM) handles the interface to devices external to chip, including generation of chip selects, clock and control for external peripherals and memory. It provides asynchronous and synchronous access to devices with SRAM-like interface. 2.3.38/26

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Functional Description and Application Information

2.3.3 ARM926EJ-S Interrupt Controller (AITC)

The ARM926EJ-S Interrupt Controller (AITC) is a 32-bit peripheral that collects interrupt requests from up to 64 sources and provides an interface to the ARM926EJ-S core. The AITC includes software controlled priority levels for normal interrupts. The AITC performs the following functions:

• Supports up to 64 interrupt sources
• Supports fast and normal interrupts
• Selects normal or fast interrupt request for any interrupt source
• Indicates pending interrupt sources via a register for normal and fast interrupts
• Indicates highest priority interrupt number vi a register. (Can be used as a table index.)
• Independently can enable or disable any interrupt source
• Provides a mechanism for software to schedule an interrupt
• Supports up to 16 software controlled priority le vels for normal interrupts and priority masking
• Can single-bit disable all normal interrupts and a ll fast interrupts. (Used in enabling of secure operations.)

2.3.4 ARM926EJ-S Platform

The ARM926EJ-S (ARM926) is a member of the ARM9 family of general-purpose microprocessors targeted at multi-tasking applications. The ARM926 supports the 32-bit ARM and 16-bit Thumb instructions sets. The ARM926 includes features for efficient execution of Java byte codes. A JTAG port is provided to support the ARM Debug Architecture, along with associated signals to support the ETM9 real-time trace module. The ARM926EJ-S is a Harvard cached architecture including an ARM9EJ-S integer core, a Memory Management Unit (MMU), separate instruction and data AMBA AHB interfaces, separate instruction and data caches, and separate instruction and data tightly coupled memory (TCM) interfaces. The ARM926 co-processor, instruction TCM, and data TCM interfaces are tied off within the ARM926 Platform and is not available for external connection. The ARM926EJ-S processor is a fully synthesizable macrocell, with a configurable memory system. Both instruction and data caches are 16 Kbytes on the platform. The cache is virtually accessed and virtually tagged. The data cached has physical tags as well. The MMU provides virtual memory facilities, which are required to support various platform operating systems, such as Symbian OS, Windows CE, and Linux. The MMU contains eight fully associative TLB entries for lockdown and 64 set associative entries. Refer to the ARM926EJ-S Technical Reference Manual for more information.

2.3.5 Advanced Technology Attachment (ATA)

The advanced technology attachment (ATA) host controller is compatible with the ATA/ATAPI-6 specification. The primary use of the ATA host controller is to interface with IDE hard disc drives and advanced technology attachment packet interface (ATAPI) optical disc drives. It interfaces with the ATA device over a number of ATA signals.

Functional Description and Application Information i.MX27/i.MX27L Data Sheet, Advance Information, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 11 This host controller supports interface protocols as specified in ATA/ATAPI-6 standard:

• PIO mode 0, 1, 2, 3, and 4
• Multiword DMA mode 0, 1, and 2
• Ultra DMA modes 0, 1, 2, 3, and 4 with bus clock of 50 MHz or higher
• Ultra DMA mode 5 with bus clock of 80 MHz or higher Before accessing the ATA bus, the host must program the timing parameters to be used on the ATA bus. The timing parameters control the timing on the ATA bus. Most timing parameters are programmable as a number of clock cycles (1 to 255). Some are implied. All of the ATA device-internal registers are visible to users, and they are defined as mirror registers in ATA host controller. As specified in ATA/ATAPI-6 standard, all the features/functions are implemented by reading/writing to the device’s internal registers. The protocols that can be active at the same time on the ATA bus are as follows:
• The first and simplest protocol (PIO mode acce ss) can be started at any time by the ARM926 to the ATA bus. The PIO mode is a slow protocol, mainly intended to be used to program an ATA disc drive, but also can be used to transfer data to/from the disc drive.
• The second protocol is the DMA mode access. DMA mode is started by the ATA interface after receiving a DMA request from the drive, and only if the ATA interface has been programmed to accept the DMA request. In DMA mode, either multiword-DMA or ultra-DMA protocol is used on the ATA bus. All transfers between FIFO and the host IP or DMA IP bus are zero wait states transfer, so a high-speed transfer between FIFO and DMA/host bus is possible.

2.3.6 Digital Audio MUX (AUDMUX)

The digital audio MUX (AUDMUX) provides programmable interconnecting for voice, audio, and synchronous data routing between host serial interfaces—for example, SSI, SAP, and peripheral serial interfaces—such as, audio and voice codecs. The AUDM UX allows audio system connectivity to be modified through programming, as opposed to altering the design of the system into which the chip is designed. The design of the AUDMUX allows multiple simultaneous audio/voice/data flows between the ports in point-to-point or point-to-multipoint configurations. Included in the AUDMUX are two types of interfaces. The internal ports connect to the processor serial interfaces, and the external ports connect to off-chip audio devices and serial interfaces of other processors. A desired connectivity is achieved by configuring the appropriate internal and external ports. The module includes full 6-wire SSI interfaces for asynchronous receive and transmit, as well as a configurable 4-wire (synchronous) or 6-wire (asynchronous) peripheral interface. The AUDMUX allows each host interface to be connected to any other host or peripheral interface in a point-to-point or point-to-multipoint (network mode).

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Functional Description and Application Information

2.3.7 Clock and Reset Module (CRM)

The clock and reset module (CRM) generates clock and reset signals used throughout the i.MX27/MX27L processor and for external peripherals. It also enables system software to control, customize, or read the status of the following functions:

• Chip ID
• Multiplexing of I/O signals
• I/O Driving Strength
• I/O Pull Enable Control
• Well-Bias Control
• System boot mode selection
• DPTC Control

2.3.8 CMOS Sensor Interface (CSI)

The CMOS sensor interface (CSI) is a logic interface that enables the i.MX27/MX27L processors to connect directly to external CMOS sensors and CCIR656 video source. The capabilities of the CSI include the following:

• Configurable interface logic to support popular CMOS sensors in the market
• Support traditional sensor timing interface
• Support CCIR656 video interface, progressive mode for smart sensor, interlace mode for PAL and NTSC input
• 8-bit input port for YCC, YUV , Bayer, or RGB data
• 3 2 × 32 FIFO storing image data supporting Core data read and DMA data burst transfer to system memory
• Full control of 8-bit and 16-bi t data to 32-bit FIFO packing
• Direct interface to eMMA-lt Pre-Processing block (PrP)—Not available on the i.MX27L
• Single interrupt source to interrupt controller fro m maskable sensor interrupt sources: Start of Frame, End of Frame, Change of Field, FIFO full
• Configurable master clock frequency output to sensor
• Asynchronous input logic design. Sensor master cl ock can be driven by either the i.MX27/MX27L processor or by external clock source.
• Statistic data generation for auto exposure (AE) and auto white balance (AWB) control of the camera (for Bayer data only)

2.3.9 Configurable Serial Peripheral Interface (CSPI)

The configurable serial peripheral interface (CSPI) is used for fast data communication with fewer software interrupts. There are three CSPI modules in the i.MX27/MX27L processors, which provide a full-duplex synchronous serial interface, capable of interfacing to the SPI master and slave devices. CSPI1 and CSPI2 are master/slave configurable and include three chip selects to support multiple peripherals.

Functional Description and Application Information i.MX27/i.MX27L Data Sheet, Advance Information, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 13 CSPI3 is only a master and has one chip-select signal. The transfer continuation function of the CSPI enables unlimited length data transfers using 32-bit wide by 8-entry FIFO for both TX and RX data DMA support. The CSPI ready (SPI_RDY) and chip select (SS) control signals enable fast data communication with fewer software interrupts. When the CSPI module is configured as a master, it uses a serial link to transfer data between the CSPI and an external device. A chip-enable signal and a clock signal are used to transfer data between these two devices. When the CSPI module is configured as a slave, the user can configure the CSPI Control register to match the external SPI master’s timing.

2.3.10 Direct Memory Access Controller (DMAC)

The direct memory access controller (DMAC) provides 16 channels to support linear memory, 2D memory, FIFO, and end-of-burst enable FIFO transfers to support a wide variety of DMA operations. Features include the following:

• Support of 16 channels linear memory, 2D memory , and FIFO for both source and destination
• Support of 8-bit, 16-bit, or 32-bit FIFO port size and memory port size data transfer
• Configurability of DMA burst length of up to a maximum of 16 words, 32 half-words, or 64 bytes for each channel
• Bus utilization control for a channel that is not triggered by DMA request
• Interrupts that are provided to interrupt handler on bulk data transfer complete or transfer error
• DMA burst time-out error to terminate DMA cycle when the burst cannot be completed in a programmed timing period
• Dedicated external DMA request and grant signal
• Support of increment, decrement, and no incr ement for source and destination addressing
• Support of DMA chaining 2.3.11 enhanced MultiMedia Accelerator Light (eMMA_lt) The enhanced MultiMedia Accelerator Light (eMMA_lt) consists of the video pre-processor (PrP) and post-processor (PP). In contrast with i.MX21 processor’s components, this eMMA does not include the video codec. A more powerful video codec is included as a separate module. NOTE The i.MX27L does not have a eMMA_lt module. Each module has individual control and configuration registers that are accessed via the IP interface, and are capable of bus mastering the AMBA bus to independently access system memory without any CPU intervention. This enables each module to be used independently of each other, and enables the pre-processor and post-processor modules to provide acceleration features for other software codec implementations and image processing software. These blocks work together to provide video acceleration, and to off-load the CPU from computation intensive tasks. The PrP and PP can be used for generic video pre- and post-processing, such as scaling, resizing, and color space conversions. A 32-bit-to-64-bit AHB gasket is used to convert a PrP AHB bus from a 32-bit to 64-bit protocol. A bypass function is implemented to bypass this 64-bit gasket if it is not needed.

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Functional Description and Application Information eMMA_lt supports the following image/video processing features:

• Pre-processor: — Data input: – System memory – Private DMA between CMOS Sensor Interface module and pre-processor — Data input formats: – Arbitrarily formatted RGB pixels (16 or 32 bits) – YUV 4:2:2 (Pixel interleaved) – YUV 4:2:0 (IYUV , YV12) — Input image size: 32 × 32 to 2044 × 2044 — Image scaling: – Programmable independent CH-1 and CH-2 re sizer. Can program to be in cascade or parallel. – Each resizer supports downscaling ratios from 1:1 to 8:1 in fractional steps. — Channel-1 output data format – Channel 1 – RGB 16 and 32 bpp – YUV 4:2:2 (YUYV , YVYU, UYVY , VYUY) — Channel-2 output data format – YUV 4:2:2 (YUYV) – YUV 4:4:4 – YUV 4:2:0 (IYUV , YV12) – RGB data and YUV data format can be generated concurrently — 32/64-bit AHB bus
• Post-processor — Input data: – From system memory — Input format: – YUV 4:2:0 (IYUV , YV12) — Image Size: 32 × 32 to 2044 × 2044 — Output format: – YUV 4:2:2 (YUYV) – RGB16 and RGB32 bpp — Image Resize – Upscaling ratios ranging from 1:1 to 1:4 in fractional steps – Downscaling ratios ranging from 1:1 to 2:1 in fractional steps and a fixed 4:1 – Ratios provide scaling between QCIF, CIF, QVGA (320 × 240, 240 × 320)

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2.3.12 Enhanced Synchronous Dy namic RAM Controller (ESDRAMC)

The enhanced synchronous dynamic RAM controller (ESDRAMC) provides an interface and control for synchronous DRAM memories for the system. SDRAM memories use a synchronous interface with all signals registered on a clock edge. A command protocol is used for initialization, read, write, and refresh operations to the SDRAM, and is generated on the signals by the controller (when required due to external or internal requests). It has support for both single data rate RAMs and double data rate SDRAMs. It supports 64 Mbits, 128 Mbits, 256 Mbits, and 512 Mbits, 1 Gbit, 2 Gbits, four bank synchronous DRAM by two independent chip selects and with up to 256 Mbytes addressable memory per chip select.

2.3.13 Fast Ethernet Controller (FEC)

The fast ethernet controller (FEC) is designed to support both 10 and 100 Mbps Ethernet/IEEE 802.3 networks. An external transceiver interface and transceiver function are required to complete the interface to the media. The FEC supports the 10/100 Mbps MII and the 10 Mbps-only 7-wire interface, which uses a subset of the MII pins for connection to an external Ethernet transceiver. The FEC incorporates the following features:

• Support for three different Ethernet physical interfaces: — 100-Mbps IEEE 802.3 MII — 10-Mbps IEEE 802.3 MII — 10-Mbps 7-wire interface (industry standard)
• IEEE 802.3 full duplex flow control
• Programmable max frame length suppor ts IEEE 802.1 VLAN tags and priority
• Support for full-duplex operation (200 Mbps throughput ) with a minimum system clock rate of

50 MHz

• Support for half-duplex operation (100 Mbps thr oughput) with a minimum system clock rate of

25 MHz

• Retransmission from transmit FIFO following a collision (no processor bus utilization)
• Automatic internal flushing of the receive FIFO for runts (collision fragments) and address recognition rejects (no processor bus utilization)
• Address recognition — Frames with broadcast a ddress may be always accepted or always rejected — Exact match for single 48-bit individual (unicast) address — Hash (64-bit hash) check of individual (unicast) addresses — Hash (64-bit hash) check of group (multicast) addresses — Promiscuous mode
• Independent DMA engine with multiple channels allowing transmit data, transmit descriptor, receive data, and receive descriptor accesses to provide high performance
• Independent RISC-based controller that provides the following functions in the FEC: — Initialization (those internal registers not initialized by the user or hardware) — High level control of the DMA channels (initiating DMA transfers)

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Functional Description and Application Information — Interpreting buffer descriptors — Address recognition for receive frames — Random number generation for transmit collision backoff timer

• The message information block (MIB) in FEC main tains counters for a variety of network events and statistics. The counters supported are the RMON (RFC 1757) Ethernet Statistics group and some of the IEEE 802.3 counters.

2.3.14 General Purpose I/O Module (GPIO)

The general-purpose input/output (GPIO) module provides dedicated general-purpose pins that can be configured as either inputs or outputs. When it is configured as an output, you can write to an internal register to control the state driven on the output pin. When configured as an input, you can detect the state of the input by reading the state of an internal register. The GPIO includes all of the general purpose input/output logic necessary to drive a specific data to the pad and control the direction of the pad using registers in the GPIO module. The ARM926 is able to sample the status of the corresponding pads by reading the appropriate status register. The GPIO supports up to 32 interrupts and has the ability to identify interrupt edges as well as generate three active high interrupts.

2.3.15 General Purpose Timer (GPT)

The i.MX27/MX27L processors contains six identical 32-bit general purpose timers (GPT) with programmable prescalers and compare and capture registers. Each timer’s counter value can be captured using an external event, and can be configured to trigger a capture event on the rising or/and falling edges of an input pulse. Each GPT can also generate an event on the TOUT pin, and an interrupt when the timer reaches a programmed value. Each GPT has an 11-bit prescaler that provides a programmable clock frequency derived from multiple clock sources, including ipg_clk_32k, ipg_clk_perclk, ipg_clk_perclk/4, and external clock from the TIN pin. The counter has two operation modes: free-run and restart mode. The GPT can work in low-power mode.

2.3.16 Inter IC Communication (I 2C)

Inter IC communication (I2C) is a two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange, minimizing the interconnection between devices. This bus is suitable for applications requiring occasional communications over a short distance between many devices. The flexible I2C enables additional devices to be connected to the bus for expansion and system development. The I2C operates up to 400 kbps dependent on pad loading and timing. (For pad requirement details, refer to Phillips I2C Bus Specification, Version 2.1.) The I2C system is a true multiple-master bus, including arbitration and collision detection that prevents data corruption if multiple devices attempt to control the bus simultaneously. This feature supports complex applications with multiprocessor control and can be used for rapid testing and alignment of end products through external connections to an assembly-line computer.

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2.3.17 IC Identification Module (IIM)

The IC identification module (IIM) provides an interface for reading and in some cases programming and/or overriding identification and control information stored in on-chip fuse elements. The module supports laser fuses (L-Fuses) or electrically-programmable poly fuses (e-Fuses) or both. The IIM also provides a set of volatile software-accessible signals, which can be used for software control of hardware elements not requiring non-volatility. The IIM provides the primary user-visible mechanism for interfacing with on-chip fuse elements. Among the uses for the fuses are unique chip identifiers, mask revision numbers, cryptographic keys, and various control signals requiring permanent non-volatility. The IIM also provides up to 28 volatile control signals and an ability to generate a second 168-bit SCC key. The IIM consists of a master controller, a software fuse value shadow cache, and a set of registers to hold the values of signals visible outside the module. Up to eight arrays of fuses (L-Fuses and/or e-Fuses) are associated with the IIM, but are instantiated outside of it. The IIM is accessible via an 8-bit IP bus interface. An 8-bit interface is used because it matches the natural width of the fuse arrays. All registers are 32-bit aligned to enable the module to be instantiated on IP buses supporting only 32-bit peripherals. A subset of fuses, as well as the software-controlled volatile signals, are capable of driving top-level nets within the SoC. These signals are hereinafter referred to as Hardware-Visible Signals, or HW-Visible Signals. These signals are intended for feature enablement and disablement and similar uses within the device. Laser fuses can only be blown during chip manufacturing (at the wafer level). The e-Fuses may be blown under software or JTAG control during the IC final test, in the customer’s factory, or in the field. They include a mechanism to inhibit further blowing of fuses (write-protect) to support secure computing environments. The fuse values may also be overridden by software without modifying the fuse element. Similar to the write-protect functionality, the override functionality can also be permanently disabled. Fuse banks may also be scan-inhibited on a per-bank basis to prevent reading and programming of fuses through the JTAG interface.

2.3.18 JTAG Controller (JTAGC)

The JTAG controller (JTAGC) module supports debug access to the ARM926 Platform and tristate enable of the I/O pads. The overall strategy is to achieve good test and debug features without increasing the pin count and reducing the complexity of I/O muxing. The JTAG Controller is compatible with IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture.

2.3.19 Keypad Port (KPP)

The keypad port (KPP) is designed to interface with a keypad matrix with 2-contact or 3-point contact keys. KPP is designed to simplify the software task of scanning a keypad matrix. With appropriate software support, the KPP is capable of detecting, debouncing, and decoding one or multiple keys pressed simultaneously in the keypad. The KPP supports up to 8 × 8 external key pad matrix. Its port pins can be used as general purpose I/O. Using an open drain design, the KPP includes glitch suppression circuit design, multiple keys, long key, and standby key detection.

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Functional Description and Application Information

2.3.20 Liquid Crystal Display Controller (LCDC)

The liquid crystal display controller (LCDC) provides display data for external gray-scale or color LCD panels. The LCDC is capable of supporting black-and-white, gray-scale, passive-matrix color (passive color or CSTN), and active-matrix color (active color or TFT) LCD panels. The LCDC provides the following features:

• Configurable AHB bus width (32-bit/64-bit).
• Support for single (non-split) screen monochrome or color LCD panels and self-refresh type LCD panels
• 16 simultaneous gray-scale levels from a palette of 16 for monochrome display
• Support for: — Maximum resolution of 800 × 600 — Passive color panel: – 4 (mapped to RGB444) / 8 (mapped to RGB444) / 12 (RGB444) bits per pixel (bpp) — TFT panel: – 4 (mapped to RGB666) / 8 (mapped to RGB666) / 12 (RGB444) / 16 (RGB565) / 18 (RGB666) bpp — 16 and 256 colors out of a palette of 4096 colors for 4 bpp and 8 bpp CSTN display, respectively — 16 and 256 colors out of a palette of 256 colo rs for 4 bpp and 8 bpp TFT display, respectively — True 4096 colors for a 12 bpp display — True 64K colors for 16 bpp — True 256K colors for 18 bpp — 16-bit AUO TFT LCD Panel — 24-bit AUO TFT LCD Panel

2.3.21 Multi-Master Memory Interface (M3IF)/M3IF-ESDCTL/MDDRC

The M3IF-ESDCTL/MDDRC interface is optimized and designed to reduce access latency by generating multiple accesses through the dedicated ESDCTL/MDDRC arbitration (MAB) module, which controls the access to and from the enhanced SDRAM/MDDR memory controller. For the other port interfaces, the M3IF only arbitrates and forwards the master requests received through the master port gasket (MPG) interface and M3IF Arbitration (M3A) module toward the respective memory controller. The masters that interface with the M3IF include the ARM Platform, FEC, LCDC, H.264, and the USB. The controllers are the ESDCTL/MDDRC, PCMCIA, NFC, and WEIM.

2.3.22 Multi-Layer AHB Crossbar Switch (MAX)

The ARM926EJ-S processor’s instruction and data buses—and all alternate bus master interfaces—arbitrate for resources via a 6 × 34 Multi-Layer AHB Crossbar Switch (MAX). There are six

Functional Description and Application Information i.MX27/i.MX27L Data Sheet, Advance Information, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 19 (M0–M5) fully functional master ports and three (S0–S2) fully functional slave ports. The MAX is uni-directional. All master and slave ports are AHB-Lite compliant. The design of the crossbar switch enables concurrent transactions to proceed from any master port to any slave port. That is, it is possible for all three slave ports to be active at the same time as a result of three independent master requests. If a particular slave port is simultaneously requested by more than one master port, arbitration logic exists inside the crossbar to allow the higher priority master port to be granted the bus, while stalling the other requestor(s) until that transaction has completed. The slave port arbitration schemes supported are fixed, programmable fixed, programmable default input port parking, and a round robin arbitration scheme. The crossbar switch also monitors the ccm_br input (clock control module bus request), which requests a bus grant from all four slave ports. The priority of ccm_br is programmable and defaults to the highest priority. Upon receiving bus grants for all four output ports, the ccm_bg output asserts. At this point, the clock control and reset module (CRM) can turn off hclk and be assured there are no outstanding AHB transactions in progress. Once the CRM is granted a port, no other master receives a grant on that port until the CRM bus request (ccm_br) negates.

2.3.23 Memory Stick Host Controller (MSHC)

The memory stick host controller (MSHC) is located between the AIPI and the Sony Memory Stick and provides support for data transfers between the i.MX27 processor and the Memory Stick (MS). The MSHC consists of two sub-modules; the MSHC gasket and the Sony memory stick host controller (SMSC). The SMSC module, which is the actual memory stick host controller, is compatible with Sony Memory Stick Ver 1.x and Memory Stick PRO. The gasket connects the AIPI IP bus to the SMSC interface to allow communication and data transfers via the IP Bus. NOTE The i.MX27L does not include the MSHC feature. The MSHC gasket uses a reduced IP Bus interface that supports the IP bus read/write transfers that include a back-to-back read or write. DMA transfers also take place via the IP Bus interface. A transfer can be initiated by the DMA or the host (through the AIPI) response to an MSHC DMA request or interrupt. The SMSC has two DMA address modes—a single address mode and a dual address mode. The MSHC is set to dual-address mode for transfers with the DMA. In dual-address mode, when the MSHC requests a transfer with the DMA request (XDRQ), the DMA initiates a transfer to the MSHC. NOTE Details regarding the operation of the MSHC module can be found separately in Memory Stick/Memory Stick PRO Host Controller IP Specification 1.3.

2.3.24 NAND Flash Controller (NFC)

NAND flash controller (NFC) interfaces standard NAND Flash devices to the i.MX27/MX27L processors and hides the complexities of accessing the NAND Flash. It provides a glueless interface to both 8-bit and

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Functional Description and Application Information 16-bit NAND Flash parts with page sizes of 512 Bytes or 2 Kbytes. Its addressing scheme enables it to access flash devices of almost limitless capacity. The 2-Kbyte RAM buffer of the NAND Flash is used as the boot RAM during a cold reset (if the i.MX27/MX27L device is configured for a boot to be carried out from the NAND Flash device). After the boot procedure completes, the RAM is available as buffer RAM. In addition, the NAND Flash controller provides an X16-bit and X32-bit interface to the AHB bus on the chip side, and an X8/X16 interface to the NAND Flash device on the external side.

2.3.25 Personal Computer Memory Card International Association

(PCMCIA) The Personal Computer Memory Card International Association (PCMCIA) provides the PCMCIA 2.1 standard, which defines the usage of memory and I/O devices as insertable and exchangeable peripherals for personal computers or PDAs. Examples of these types of devices include CompactFlash and WLAN adapters. The pcmcia_if host adapter module provides the control logic for PCMCIA socket interfaces, and requires some additional external analog power switching logic and buffering. The additional external buffers allow the pcmcia_if host adapter module to support one PCMCIA socket. The pcmcia_if shares its chip level I/O with the external interface to memory (EIM) pins. Additional logic is required to multiplex the EIM and the pcmcia_if on the same pins.

2.3.26 Digital Phase Lock Loop (DPLL)

Two on-chip digital phase lock loop (DPLLs) provide clock generation in digital and mixed analog/digital chips designed for wireless communication and other applications. The DPLLs produce a high-frequency chip clock signals with a low frequency and phase jitter.

2.3.27 Pulse-Width Modulator (PWM)

The pulse-width modulator (PWM) has a 16-bit counter and is optimized to generate sounds from stored sample audio images; it can also generate tones. The PWM uses 16-bit resolution and a 4 × 16 data FIFO to generate sound. The 16-bit up-counter has a source selectable clock with 4 × 16 FIFO to minimize interrupt overhead. Clock-in frequency is controlled by a 12-bit prescaler for the division of a clock. Capable of sound and melody generation, the PWM has an active-high or active-low configurable output, and can be programmed to be active in low-power and debug modes. The PWM can be programmed to generate interrupts at compare and rollover events.

2.3.28 Real Time Clock (RTC)

The real time clock module (RTC) maintains the system clock, provides stopwatch, alarm, and interrupt functions, and supports the following features:

• Full clock—days, hours, minutes, seconds
• Minute countdown timer with interrupt
• Programmable daily alarm with interrupt
• Sampling timer with interrupt

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• Once-per-day, once-per-hour, once-per- minute, and once-per-second interrupts
• Operation at 32.768 kHz or 32 kHz, or 38.4 kH z (determined by reference clock crystal) The prescaler converts the incoming crystal reference clock to a 1 Hz signal, which is used to increment the seconds, minutes, hours, and days TOD counters. The alarm functions, when enabled, generate RTC interrupts when the TOD settings reach programmed values. The sampling timer generates fixed-frequency interrupts, and the minute stopwatch allows for efficient interrupts on very small boundaries.

2.3.29 Run-TIme Integrity Checker (RTIC)

The run-time integrity checker (RTIC) is one of the security components in the i.MX27/MX27L processors. Its purpose is to ensure the integrity of the peripheral memory contents and assist with boot authentication. The RTIC has the ability to verify the memory contents during system boot and during run-time execution. If the memory contents at runtime fail to match the hash signature, an error in the security monitor is triggered. The RTIC provides SHA-1 message authentication and receives input via the DMA (AMBA-AHB Lite bus master) interface. It uses segmented data gathering to support non-contiguous data blocks in memory (up to two segments per block) and works during and with high assurance boot (HAB) process. It provides Secure-scan DFT security and support for up to four independent memory blocks. The RTIC has both a Programmable DMA bus duty cycle timer and its own watchdog timer. The RTIC operates in two primary modes:

• One-time hash mode—One-time hash mode is used during HAB for code authentication or one-time integrity checking, during which it stores the hash result internally and signals the ARM926 using an interrupt.
• Continuous-hash mode—In continuous-hash mode, the RTIC is used continuously to verify integrity of memory contents by checking re-generated hash against internally stored values and interrupts host only if error occurs.

2.3.30 Symmetric/Asymmetric Hashing and Random Accelerator

(SAHARA2) SAHARA2 is a security co-processor and implements encryption algorithms (AES, DES, and 3DES), hashing algorithms (MD5, SHA-1, SHA_224, and SHA-256), stream cipher algorithm (ARC4), and a hardware random number generator. SAHARA2 offer features:

• AES encryption/decryption — ECB, CBC, CTR, and CRM modes — 128-bit key
• D E S / 3 D E S — EBC, CBC, and CTR modes — 56-bit key with parity (DES)

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Functional Description and Application Information — 112-bit or 168-bit key with parity (3DES)

• ARC4 (RC4-compatible cipher) — 5–16-byte key — Host accessible S-box
• MD5, SHA-1, SHA-224, and SHA-256 hashing algorithms — Messages lengths which are multiples of bytes — Autopadding supported — HMAC (support for IPAD and OPAD via descriptors) — Up to 2 32 byte message length
• Random number generator (based NIST approved PRNG - FIPS 186-2) — Entropy is generated via an inde pendent free running ring oscillators

2.3.31 Security Controller Module (SCC)

The security controller module (SCC) is a hardware security component composed of two subblocks, the Secure RAM and the Security Monitor. Overall, its primary functionality is associated with establishing a centralized security state controller and hardware security state with a hardware configured, unalterable security policy. It also provides an uninterruptedly hardware mechanism to detect and respond to threat detection signals (specifically, platform test access signals). It also serves as a device unique data protection/encryption resource to enable off-chip storage of security sensitive data and an internal storage resource, which automatically and irrevocably destroys plain text security sensitive data upon threat detection. Security and security services in an embedded or data processing platform, refer to the i.MX27/MX27L processors’ ability to provide mandatory and optional information protection services. Information in this context refers to all embedded data, both program store and data load. Therefore, a secure platform is intended to protect information/data from unauthorized access in the form of inspection (read), modification (write), or execution (use). Security assurance refers to the degree of confidence that security claims are actually met and is therefore associated with the resources available to, and the integrity of, a given security design.

2.3.32 Secure Digital Host Controller (SDHC)

The secure digital host controller (SDHC) controls the MultiMedia card (MMC), secure digital memory (SD), and I/O cards by sending commands to cards and performing data accesses to/from the cards. The Multimedia card/Secure digital host (MMC/SD) module integrates both MMC support along with SD memory and I/O functions. The SDHC is fully compatible with the MMC System Specification Version 3.0, as well as with the SD Memory Card Specification 1.0, and SD I/O Specification 1.0 with 1/4 channel(s). The maximum data rate in 4-bit mode is 100 Mbps. The SDHC uses a built-in programmable frequency counter for the SDHC bus, and provides a maskable hardware interrupt for an SDIO interrupt, internal status, and FIFO status. It has a pair of 32 × 16-bit data FIFO buffers built in. The MultiMedia card (MMC) is a universal, low-cost data storage and communication media that is designed to cover a wide area of applications, including, for example, electronic toys, organizers, PDAs,

Functional Description and Application Information i.MX27/i.MX27L Data Sheet, Advance Information, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 23 and smart phones. The MMC communication is based on an advanced 7-pin serial bus designed to operate in a low-voltage range. The secure digital card (SD) is an evolution of MMC technology, with two additional pins in the form factor. It is specifically designed to meet the security, capacity, performance, and environment requirements inherent in newly emerging audio and video consumer electronic devices. The physical form factor, pin assignment, and data transfer protocol are forward-compatible with the MultiMedia Card with some additions. Under SD, it can be categorized into Memory and I/O. The memory card invokes a copyright protection mechanism that complies with the security of the SDMI standard, which is faster and provides the capability for a higher memory capacity. The I/O card provides high-speed data I/O with low-power consumption for mobile electronic devices.

2.3.33 Smart Liquid Cr ystal Display Controller Module (SLCDC)

The smart liquid crystal display controller (SLCDC) module transfers data from the display memory buffer to the external display device. Direct Memory Access (DMA) transfers the data transparently with minimal software intervention. Bus utilization of the DMA is controllable and deterministic. As cellular phone displays become larger and more colorful, demands on the processor increase. More CPU power is needed to render and manage the image. The role of the display controller is to reduce the CPU’s involvement in the transfer of data from memory to the display device so the CPU can concentrate on image rendering. DMA is used to optimize the transfer. Embedded control information needed by the display device is automatically read from a second buffer in system memory and inserted into the data stream at the proper time to completely eliminate the CPU’s role in the transfer. A typical scenario for a cellular phone display is to have the display image rendered in main system memory. After the image is complete, the CPU triggers the SLCDC module to transfer the image to the display device. Image transfer is accomplished by burst DMA, which steals bus cycles from the CPU. Cycle-stealing behavior is programmable so bus use is kept within predefined bounds. After the transfer is complete, a maskable interrupt is generated indicating the status. For animated displays, it is suggested that a two-buffer ping-pong scheme be implemented so that the DMA is fetching data from one buffer while the next image is rendered into the other. Several display sizes and types are used in the various products that use the SLCDC. The SLCDC module has the capability of directly interfacing to the selected display devices. Both serial and parallel interfaces are supported. The SLCDC module only supports writes to the display controller. SLCDC read operations from the display controller are not supported.

2.3.34 Synchronous Serial Interface (SSI)

The synchronous serial interface (SSI) is a full-duplex serial port that allows the chip to communicate with a variety of serial devices. These serial devices can be standard codecs, digital signal processors (DSPs), microprocessors, peripherals, and popular industry audio codecs that implement the inter-IC sound bus standard (I2S) and Intel AC97 standard. The SSI is typically used to transfer samples in a periodic manner. It consists of independent transmitter and receiver sections with independent clock generation and frame synchronization.

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Functional Description and Application Information The SSI contains independent (asynchronous) or shared (synchronous) transmit and receive sections with separate or shared internal/external clocks and frame syncs, operating in Master or Slave mode. The SSI can work in Normal mode operation using frame sync, and in Network mode operation allowing multiple devices to share the port with as many as thirty-two time slots. The SSI provides two sets of Transmit and Receive FIFOs. Each of the four FIFOs is 8× 24 bits. The two sets of Tx/RX FIFOs can be used in Network mode to provide two independent channels for transmission and reception. It also has programmable data interface modes such as I2S, LSB, and MSB aligned and programmable word lengths. Other program options include frame sync, clock generation, and programmable I2S modes (Master, Slave, or Normal). Oversampling clock, ccm_ssi_clk is available as output from SRCK in I2S Master mode. In addition to AC97 support, the SSI has completely separate clock and frame sync selections for the receive and transmit sections. In the AC97 standard, the clock is taken from an external source and frame sync is generated internally. The SSI also has a programmable internal clock divider and Time Slot Mask registers for reduced CPU overhead (for Tx and RX both).

2.3.35 Universal Asynchronous Receiver/Transmitter (UART)

The i.MX27/MX27L processors contain six UART modules. Each UART module is capable of standard RS-232 non-return-to-zero (NRZ) encoding format and IrDA-compatible infrared modes. The UART provides serial communication capability with external devices through an RS-232 cable or through use of external circuitry that converts infrared signals to electrical signals (for reception); or it transforms electrical signals to signals that drive an infrared LED (for transmission) to provide low-speed IrDA compatibility. The UART transmits and receives characters that are either 7 or 8 bits in length (program selectable). To transmit, data is written from the peripheral data bus to a 32-byte transmitter FIFO (TxFIFO). This data is passed to the shift register and shifted serially out on the transmitter pin (TXD). To receive, data is received serially from the receiver pin (RXD) and stored in a 32-half-word-deep receiver FIFO (RxFIFO). The received data is retrieved from the RxFIFO on the peripheral data bus. The RxFIFO and TxFIFO generate maskable interrupts as well as DMA requests when the data level in each of the FIFO reaches a programmed threshold level. The UART generates baud rates based on a programmable divisor and input clock. The UART also contains programmable auto baud detection circuitry to receive 1 or 2 stop bits as well as odd, even, or no parity. The receiver detects framing errors, idle conditions, BREAK characters, parity errors, and overrun errors.

2.3.36 Universal Serial Bus (USB)

The i.MX27/MX27L processors provide three USB ports. The USB module provides high performance USB On-The-Go (OTG) functionality, compliant with the USB 2.0 specification, the OTG supplement, and the ULPI 1.0 Low Pin Count specification. The module consists of three independent USB cores, each controlling one USB port. In addition to the USB cores, the USB module provides for transceiverless link (TLL) operation on host Ports 1 and 2, and provides the ability of routing the OTG transceiver interface to Host Port 1 such that

Functional Description and Application Information i.MX27/i.MX27L Data Sheet, Advance Information, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 25 this transceiver can be used to communicate with a USB peripheral connected to Host Port 1. The USB module has two connections to the CPU bus—one IP -bus connection for register accesses and one AHB-bus connection for the DMA transfer of data to and from the FIFOs. The USB module includes the following features:

• Full Speed/Low speed Host only core (HOST 1)
• Transceiverless link logic (TLL) for on board connection to a FS/LS USB peripheral
• Bypass mode to route Host Port 1 signals to OTG I/O port
• High Speed /Full Speed/Low Speed Host Only core (Host 2)
• Full Speed/Low Speed interface for Serial transceiver
• TLL function for direct connection to US B peripheral in FS/LS (serial) operation
• High-speed OTG core The USB module has two main modes of operation: Normal mode and Bypass mode. Furthermore, the USB interfaces can be configured for high-speed operation (480 Mbps) and/or full/low speed operation (12/1.5 Mbps). In Normal mode, each USB core controls its corresponding port. In additional to th4e major operational modes, each port can work in one or more modes, as follows: PHY mode In PHY mode, an external serial transceiver is connected to the port. This is used for off-board USB connections. TLL mode In TLL mode, internal logic is enabled to emulate the functionality of two back-to-back connected transceivers. This mode is typically used for on-board USB connections to USB-capable peripherals. Host Port 2 supports ULPI and Serial Transceivers. The OTG port requires a transceiver and is intended for off-board USB connections. Serial Interface mode In serial mode, a serial OT G transceiver must be connected. The port does not support dedicated signals for OTG signaling. Instead, a transceiver with built-in OTG registers must be used. Typically, the Transceiver registers are accessible over an I2C or SPI interface. ULPI mode In this mode, a ULPI transceiver is connected to the port pins to support high-speed off board USB connection. Bypass mode Bypass mode affects the operation of the OTG port and Host Port 1. This mode is only available when a serial transceiver is used on the OTG port, and the peripheral device on Port 1 is using a TLL connection. Bypass mode is activated by setting the bypass bit in the USBCONTROL register. In this mode, the USB OTG port connections are internally routed to the USB Host 1 port, such that the transceiver on the OTG port connects to a peripheral USB device on Host Port 1. The OTG core and the Host 1 core are disconnected from their ports when bypass is active. Low Power mode Each of the three USB cores has an associated power control module that is controlled by the USB core and clocked on a 32-kHz clock. When a USB bus is idle, the transceiver can be placed in low-power mode (suspend), after which the clocks to the USB core can be stopped. The 32-kHz low power clock must remain active as it is needed for walk-up detection.

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2.3.37 Watchdog Timer Module (WDOG)

The watchdog timer module (WDOG) protects against system failures by providing a method of escaping from unexpected events or programming errors. Once the WDOG module is activated, it must be serviced by software on a periodic basis. If servicing does not take place, the timer times out. Upon a time-out, the WDOG Timer module either asserts the wdog signal or a system reset signal wdog_rst, depending on software configuration. The WDOG Timer module also generates a system reset via a software write to the Watchdog Control Register (WCR) when there is a detection of a clock monitor event, an external reset, an external JTAG reset signal, or if a power-on-reset has occurred.

2.3.38 Wireless External Interface Module (WEIM)

The wireless external interface module (WEIM) handles the interface to devices external to the chip, including generation of chip selects, clocks and controls for external peripherals and memory. It provides asynchronous and synchronous access to devices with an SRAM-like interface. The WEIM includes six chip selects for external devices, with two CS signals covering a range of 128 Mbytes, and the other four each covering a range of 32 Mbytes. The 128-Mbyte range can be increased to 256 Mbytes when combined with the two signals. The WEIM offers selectable protection for each chip select as well as programmable data port size. There is a programmable wait-state generator for each chip select and support for big- and little-endian modes of operation per access.

2.3.39 Video Codec

The video codec module is the video processing module in the i.MX27 processor. It supports full duplex video codec with 25 fps VGA resolution, supports multi-party calls, and integrates multiple video processing standards, including H.264 BP, MPEG-4 SP, and H.263 P3 (including annex I, J, K, and T), D1 resolution, 30 fps—half-duplex. NOTE The video codec feature is not available on the i.MX27L. It has three 64-bit AHB-Lite master bus interfaces connecting to the EMI, which includes two read channels and one write channel. Its 32-bit AHB-Lite master bus is connected to ARM Platform to access system-internal SRAM. The video codec module contains three major architectural components: video codec processing IP, AXI-to-AHB bus protocol transfer module, and a 32-bit to 64-bit AHB master bus protocol transfer module. The Video Codec module supports following video stream processing features:

• Multi-standard video codec — MPEG-4 part-II simple profile encoding/decoding — H.264/A VC baseline profile encoding/decoding — H.263 P3 encoding/decoding — Multi-party call: max processing four im age/bitstream encoding and/or decoding simultaneously

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• Coding tools — High-performance motion estimation – Single reference frame for bo th MPEG-4 and H.264 encoding – Support 16 reference frame for H.264 decoding – Quarter-pel and half-pel accuracy motion estimation – [+/-16, +/-16] Search range – Unrestricted motion vector — All variable block sizes are supported (in case of encoding, 8 × 4, 4 × 8, and 4 × 4 block sizes are not supported). — MPEG-4 AC/DC prediction and H.264 Intra prediction — H.263 Annex I, J, K(RS = 0 and ASO =0), and T are supported. In case of encoding, the Annex I and K(RS=1 or ASO=1) are not supported. — CIR (Cyclic Intra Refresh)/AIR (Adaptive Intra Refresh) — Error resilience tools – MPEG-4 re-synchronize marker and data-partitioning with RVLC (fixed number of bits/macroblocks between macroblocks) – H.264/A VC FMO and ASO – H.263 slice structured mode — Bit-rate control (CBR and VBR)
• Pre/post rotation/mirroring — 8 rotation/mirroring modes for image to be encoded — 8 rotation/mirroring modes fo r image to be displayed
• Programmability — Embeds 16-bit DSP processor that is dedicated to processing bitstream and driving codec hardware — General purpose registers and interrupt gene ration for communication between system and video codec module

3 Signal Descriptions

This section discusses the following:

• Identifies and defines all device si gnals in text, tables, and (as appropriate) figures. Signals can be organized by group, as applicable.
• Contains pin-assignment/contact-connection diagrams , if the sequence of information in the data sheet requires them to be included here.

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Table 3 shows the i.MX27/MX27L signal descriptions. Table 3. i.MX27/MX27L Signal Descriptions SDRAM/MDDR is not the address but the pre-charge bank select signal. EB0 Active low external enable byte signal that controls D [15:8], shared with PCMCIA PC_REG. EB1 Active low external enable byte signal that controls D [7:0], shared with PCMCIA PC_IORD. CSD [1:0] is selected. DTACK is multiplexed with CS4. CS[5:4] are multiplexed with ETMTRACECLK and ETMTRACESYNC; PF22, 21. an on-going burst sequence and initiate a new (long first access) burst sequence. BCLK Clock signal sent to external synchronous memories (such as burst flash) during burst mode. is also shared with the PCMCIA PC_WE.

EXT_60M This is a special factory test signal. To ensure proper operation, connect this signal to ground. EXT_266M This is a special factory test signal. To ensure proper operation, connect this signal to ground. modules (except the reset module, SDRAMC module, and the clock control module) are reset. source: power on reset, system reset (RESET_IN), and watchdog reset. by an external RC circuit designed to detect a power-up event. oscillator circuit is shut down. Table 3. i.MX27/MX27L Signal Descriptions (continued)

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handshake signals to PMIC(VSTBY). TRST Test Reset Pin—External active low signal used to asynchronously initialize the JTAG controller. TDO Serial Output for test instructions and data. Changes on the falling edge of TCK. TDI Serial Input for test instructions and data. Sampled on the rising edge of TCK. TCK Test Clock to synchronize test logic and control register access through the JTAG port. multiplexed with 1-Wire; thus, utilizing 1-Wire renders RTCK unusable and vice versa; PE16. added. This signal is multiplexed with CSPI3_MOSI; PE22. SD1_CLK SD Output Clock. This signal is multiplexed with CSPI3_SCLK; PE23. pull-up, via the Pull-up enable register, a 50 K–69 K external pull up resistor must be added. SD1_D[3] is muxed with CSPI3_SS while SD1_D[0] is muxed with CSPI3_MISO PE21–18. multiplexed with SLCDC1_CS; PB8. GPIO SD2_1:0] multiplexed with SLCDC1_RS and SLDCD1_D0; PB7–PB4.

through GPIO PD1 multiplexed with FEC_TXD1. SD3_CLK SD Output Clock signal. This signal is through GPIO PD0 multiplexed with FEC_TXD0. Note: SD3_DATA is multiplexed with ATA_DATA3–0. UART2_RXD Receive Data input signal. This signal is multiplexed with KP_ROW6 signal from KPP; PE7. UART2_TXD Transmit Data output signal. This signal is multiplexed with KP_COL6 signal from KPP; PE6. UART2_RTS Request to Send input signal. This signal is multiplexed with KP_ROW7 signal from KPP; PE4. UART2_CTS Clear to Send output signal. This signal is multiplexed with KP_COL7 signal from KPP; PE3. Note: UART 4, 5, and 6 are multiplexed with COMS Sensor Interface signals. signal multiplexing) to choose which signal KP_COL6 is available. Note: KP_COL[7:6] and KP_ROW[7:6] are multiplexed with UART2 signals as show above, also see UARTs table. TOUT3 of the General Purpose Timer module; PE5.

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USBH2_DATA5/RCV; and CSPI1_SS1 is multiplexed with EXT_DMAGRANT; PD26–28. Note: CSPI3 CSPI3_MOSI, CSPI3_MISO, CSPI3_SS, andCSPI3_SCLK are multiplexed with SD1 signals.

SLCDC2_CLK; through GPIO multiplexed with PC_WAIT_B; PC31. SLCDC2_D0; through GPIO multiplexed with PC_VS1; PC28. Clock, and Reset Controller module, and is also multiplexed with GPT6_TOUT; PC15. TOUT, and is also multiplexed with GPT6_TIN; PC14. Note: TOUT2, TOUT3 are multiplexed with PWMO pad; GPT4 and GPT5 signals are multiplexed with SSI2 pads.

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driver (dedicated signal SPS for Sharp panel HR-TFT); PA29. signal). This signal is multiplexed with the SLCDC1_RS; PA25.

signal is multiplexed with SLCDC1_D0; PA24. LD[15:0] signals are multiplexed with SLCDC1_DAT[15:0], SLCDC. PA23–PA6. Note: SLCDC signals are multiplexed with LCDC signals. Through GPIO also are multiplexed with SLCDC 15–0, and FEC signals; PF23, PD16–PD2. NVDD1–15, AVDD Noisy Supply for the I/O pins. There are 16 I/O voltage pads, NVDD1 through NVDD15 + AVDD.

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3.1 Power-Up Sequence

of power and resets to ensure proper operation. do not appear in this list. The signals are listed below with the named signal that they are multiplexed. The 1-Wire input and output signal is multiplexed with JTAG RTCK pad, PE16. Note: The Rest ATA signals are multiplexed with PCMCIA Pads.

3.2 EMI Pins Multiplexing

EMI. Table 4 lists the i.MX27 pin names, pad types, and the memory devices’ equivalent pin names. Table 4. EMI Multiplexing

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Table 4. EMI Multiplexing (continued)

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3.3 Electrical Characteristics

• Section 3.4, “i.MX27/iMX27L Chip-Level Conditions” — Section 3.4.1, “Current Consumption” — Section 3.4.2, “Test Conditions and Recommended Settings”
• Section 3.5, “Module-Level Electrical Specifications” — Section 3.5.1, “Pads IO (PADIO) Electricals” — Section 3.5.2, “1-Wire Electrical Specifications” D9 regular D9 — D9 — D9 D8 regular D8 — D8 — D8 D7 regular D7 — D7 — D7 D6 regular D6 — D6 — D6 D5 regular D5 — D5 — D5 D4 regular D4 — D4 — D4 D3 regular D3 — D3 — D3 D2 regular D2 — D2 — D2 D1 regular D1 — D1 — D1 D0 regular D0 — D0 — D0 PC_CD1 regular — — CD1 —— PC_CD2 regular — — CD2 —— PC_WAIT regular — — WAIT —— PC_READY regular — — READY — — PC_PWRON regular — — PC_PWRON — — PC_VS1 regular — — VS1 — — PC_VS2 regular — — VS2 — — PC_BVD1 regular — — BVD1 — — PC_BVD2 regular — — BVD2 — — PC_RST regular — — RST — — IOIS16 regular — — IOIS16/WP — — PC_RW regular — — RW —— PC_POE regular — — POE — — M _ R E Q U E S T r e g u l a r ————— M _ G R A N T r e g u l a r —————

to the individual tables and sections. Table 6 provides the DC absolute maximum operating conditions. for extended periods may affect device reliability. Table 5. i.MX27/iMX27L Chip-Level Conditions

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Table 7 provides the DC recommended operating conditions. Table 6. DC Absolute Maximum Conditions

4 Storage Temperature Range T storage –20 125 oC

Table 7. DC Operating Conditions

4 I/O Supply Voltage, Fast (7, 11, 12, 14, 15) 1

1 Segments 11, 14, 15 are mixture of Fast and Slow GPIO.

5 I/O Supply Voltage, Slow (5, 6, 8, 9, 10, 13, AV DD)

for equipment rated above 5 years.

6 I/O Supply Voltage, DDR (1, 2, 3, 4) 3

3 Segments 1, 3, 4 are mixture of DDR and Fast GPIO.

8 Fusebox read Supply Voltage FUSEV DD

9 Fusebox Program Supply Voltage FUSEV DD

12 Operating Ambient Temperature T A –20 — 85 oC

Table 8 provides information for interface frequency limits.

3.4.1 Current Consumption

per the temperature range shown in Table 7. Table 10 shows the power consumption for the i.MX27/iMX27L device. Table 8. Interface Frequency Table 9. Frequency Definition for Power Consumption Measurement

1 MCU core f MCUmeas@266 266 MHz

2 MCU core f MCUmeas@400 400 MHz

3 MCU AHB bus f MCU-AHBmeas 133 MHz

4 MCU IP bus f MCU-IPmeas 66 MHz

Table 10. Current Consumption

1 RUN Current

• N VDD = 1.75 V
• ARM is in wait for interrupt mode.
• ARM well bias is enabled.
• MCU PLL is on.
• SPLL is off.
• FPM is on.
• 26MHz oscillator is on.
• 32 kHz oscillator is on.
• Other modules are off. A = 25ºC. IddDOZE 11 mA

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3.4.2 Test Conditions and Recommended Settings

strength setting and 25 pF loads. SDHC timing has also been verified with high drive strength setting. Unless otherwise noted, AC/DC parameters are guaranteed at operating conditions shown in Table 7.

3.5 Module-Level Electrical Specifications

in alphabetical order by module name. 3 Sleep Current • QV DD = 1.2 V.

• N VDD = 1.75 V.
• Both PLLs are off.
• FPM is off.
• ARM well bias is enabled.
• 32 kHz oscillator is on.
• 26MHz oscillator is off.
• All the modules are off. A = 25ºC. IddSLEEP 900 μA 4 Power Gate • NV DD13 = 2.9 V
• R T CVDD, = 1.3 V
• All other VDD = 0 V
• T A = 25ºC. IddPG 75 μA

Table 10. Current Consumption (continued)

3.5.1 Pads IO (PADIO) Electricals

3.5.1.1 DC Electrical Characteristics

(DDR) pads (unless otherwise noted). Table 11. GPIO Pads DC Electrical Parameters

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1 Max High strength should be avoided due to excessive overshoot and ringing. Table 12. DDR (Double Data Rate) I/O Pads DC Electrical Parameters 1 Max High and DDR Drive strengths should be avoided due to excessive overshoot and ringing. Table 11. GPIO Pads DC Electrical Parameters (continued)

3.5.1.2 AC Electrical Characteristics

Figure 2 depicts the load circuit for output pads. Figure 3 depicts the output pad transition time waveform. and Table 15 for DDR I/O (unless otherwise noted). Figure 2. Load Circuit for Output Pad Figure 3. Output Pad Transition Time Waveform Table 13. AC Electrical Characteristics of Slow General I/O Pads 1 Hysteresis mode is recommended for input with transition time greater than 25 ns. Table 14. AC Electrical Characteristics of Fast General I/O Pads 1 Hysteresis mode is recommended for input with transition time greater than 25 ns.

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Figure 4 depicts the RPP timing, and Table 16 lists the RPP timing parameters. Figure 4. Reset and Presence Pulses (RPP) Timing Diagram Figure 5 depicts Write 0 Sequence timing, and Table 17 lists the timing parameters. Figure 5. Write 0 Sequence Timing Diagram Table 15. AC Electrical Characteristics of DDR I/O Pads Table 16. RPP Sequence Delay Comparisons Timing Parameters

Figure 6. Write 1 Sequence Timing Diagram Figure 7. Read Sequence Timing Diagram

3.5.3 ATA Electrical Specifications

The parallel ATA module is not available on the i.MX27L. Table 17. WR0 Sequence Timing Parameters Table 18. Write 1/Read Timing Parameters

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ATA/ATAPI-6 specification and these requirements are configurable by the ATA module registers.

3.5.3.1 General Timing Requirements

Table 19 and Figure 8 show the general timing requirements for the ATA interface signals. amplitude with all capacitive loads from 15 pf through 40 pf where all signals have the same capacitive load value. Figure 8. ATA interface Signals Timing Diagram

3.5.4 Digital Audio Mux (AUDMUX)

Table 19. AC Characteristics of All Interface Signals

3.5.5 CMOS Sensor Interface (CSI)

This section describes the electrical information (AC timing) of the CSI.

3.5.5.1 Gated Clock Mode Timing

Figure 9. CSI Timing Diagram, Gated, PIXCLK—Sensor Data at Falling Edge,

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Figure 10. CSI Timing Diagram, Gated, PIXCLK—Sensor Data at Rising Edge, Table 20 lists the gated clock mode timing parameters. Table 20. Gated Clock Mode Timing Parameters

For example: Given pixel clock period = 10 ns, duty cycle = 50/50, hold time = 1 ns, setup time = 1 ns.

3.5.5.2 Non-Gated Clock Mode Timing

lists the timing parameters. Figure 11. CSI Timing Diagram, Non-Gated, PIXCLK—Sensor Data at Falling Edge,

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Figure 12. CSI Timing Diagram, Non-Gated, PIXCLK—Sensor Data at Rising Edge, Table 21 lists the non-gated clock mode timing parameters.

3.5.6 Configurable Serial Peripheral Interface (CSPI)

This section describes the electrical information of the CSPI.

3.5.6.1 CSPI Timing

Table 21. Non-Gated Clock Mode Parameters

3.6 Timing Diagrams

voltage of 1.1 V , slow pad voltage of 2.68 V , and fast pad voltage of 1.65 V . Figure 13. CSPI Master Mode Timing Diagram Figure 14. CSPI Slave Mode Timing Diagram Table 22. CSPI Interface Timing Parameters

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3.6.1 Direct Memory Access Controller (DMAC)

1 The output SCLK transition time is tested with 25pF drive.

2 Tsclk = CSPI clock period

3 Twait = Wait time as per the Sample Period Control Register value.

4 Tper = CSPI reference baud rate clock period (PERCLK2)

5 Tipg = CSPI main clock IPG_CLOCK period

Table 22. CSPI Interface Timing Parameters (continued)

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3.6.2 Fast Ethernet Controller (FEC)

are compatible with transceivers operating at a voltage of 3.3 V .

3.6.2.1 MII Receive Signal Timing (FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER,

Figure 17 shows the MII receive signal timings, and Table 24 lists the timing parameters. Figure 17. MII Receive Signal Timing Diagram Table 23. DMAC Timing Parameters

3.6.2.2 MII Transmit Signal Timing (FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER,

Figure 18 shows the MII transmit signal timings, and Table 25 lists the timing parameters. Figure 18. MII Transmit Signal Timing Diagram

3.6.2.3 MII Asynchronous Inputs Signal Timing (FEC_CRS and FEC_COL)

Figure 19 shows the MII asynchronous input timings, and Table 26 lists the timing parameters. Table 24. MII Receive Signal Timing Parameters 1 FEC_RX_DV, FEC_RX_CLK, and FEC_RXD0 have the same timing in 10 Mbps 7-wire interface mode. Table 25. MII Transmit Signal Timing Parameters 1 FEC_TX_EN, FEC_TX_CLK, and FEC_TXD0 have the same timing in 10 Mbps 7-wire interface mode.

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Figure 19. MII Asynchronous Inputs Signal Timing Diagram

3.6.2.4 MII Serial Management Channel Timing (FEC_MDIO and FEC_MDC)

can function correctly with a maximum MDC frequency of 15 MHz. Figure 20 shows the MII serial management channel timings, and Table 27 lists the timing parameters. Figure 20. MII Serial Management Channel Timing Diagram Table 26. MII Asynchronous Inputs Signal Timing Parameter 1 FEC_COL has the same timing in 10 Mbit 7-wire interface mode.

3.6.3 Inter IC Communication (I 2C)

This section describes the electrical information of the I2C module.

3.6.3.1 I 2C Module Timing

module. Table 28 lists the I2C module timing parameters. Figure 21. I2C Bus Timing Diagram Table 27. MII Serial Management Channel Timing Parameters

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3.6.4 JTAG Controller (JTAGC)

access port, Figure 25 shows the JTAGC TRST timing, and Table 29 lists the JTAGC timing parameters. Figure 22. Test Clock Input Timing Diagram Table 28. I2C Module Timing Parameters

Figure 23. Boundary Scan Timing Diagram

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Figure 24. Test Access Port (TAP) Diagram Figure 25. TRST Timing Diagram Table 29. JTAGC Timing Parameters

3.6.5 Liquid Crystal Display Controller Module (LCDC)

Figure 26. LCDC Non-TFT Mode Timing Diagram

1 Midpoint voltage

Table 30. LCDC Non-TFT Mode Timing Parameters Table 29. JTAGC Timing Parameters (continued)

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Figure 27. LCDC TFT Mode Timing Diagram Table 31. LCDC TFT Mode Timing Parameters Table 30. LCDC Non-TFT Mode Timing Parameters (continued)

3.6.6 Memory Stick Host Controller (MSHC)

The i.MX27L does not contain an MSHC module. Figure 28. Transfer Operation Timing Diagram (Serial)

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Figure 29. Transfer Operation Timing Diagram (Parallel) Figure 30. MSHC_CLK Timing Diagram

3.6.7 NAND Flash Controller Interface (NFC)

timing parameters of the NFC is provided in Table 34. Table 32. Serial Interface Timing Parameters Table 33. Parallel Interface Timing Parameters

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divide-by-12 to generate a 22.17 MHz NFC clock and divide-by-8 to generate a 33.25 MHz NFC clock. should also be noted that the default NFC clock on power up is 16.63 MHz. Figure 31. Command Latch Cycle Timing Diagram Figure 32. Address Latch Cycle Timing Diagram

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Table 34. NFC Target Timing Parameters (continued)

3.6.8 Personal Computer Memory Card International Association

of one clock of strobe setup time and one clock of strobe hold time. Table 35 lists the timing parameters. Figure 35. Write Accesses Timing Diagram—PSHT=1, PSST=1

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Figure 36. Read Accesses Timing Diagram—PSHT=1, PSST=1 Table 35. PCMCIA Write and Read Timing Parameters

3.6.9 SDRAM (DDR and SDR) Memory Controller

Table 40, and Table 41 list the timing parameters. Figure 37. SDRAM Read Cycle Timing Diagram Table 36. DDR/SDR SDRAM Read Cycle Timing Parameters Note: CKE is high during the read/write cycle.

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50% of signal value. SD1 + SD2 does not exceed 7.5 ns for 133 MHz. parameters are measured at maximum memory frequency. parameters, see Table 40 and Table 41. Table 36. DDR/SDR SDRAM Read Cycle Timing Parameters (continued)

Figure 38. SDR SDRAM Write Cycle Timing Diagram Table 37. SDR SDRAM Write Timing Parameters

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1 SD11 and SD12 are determined by SDRAM controller register settings. Table 38. SDRAM Refresh Timing Parameters Table 37. SDR SDRAM Write Timing Parameters (continued)

parameters are measured at maximum memory frequency. 1 SD10 and SD11 are determined by SDRAM controller register settings. Table 38. SDRAM Refresh Timing Parameters (continued)

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Figure 40. SDRAM Self-Refresh Cycle Timing Diagram Table 39. SDRAM Self-Refresh Cycle Timing Parameters

Figure 41. Mobile DDR SDRAM Write Cycle Timing Diagram defined as 50% of signal value. parameters are measured at maximum memory frequency. Table 40. Mobile DDR SDRAM Write Cycle Timing Parameters1 1 Test condition: Measured using delay line 5 programmed as follows: ESDCDLY5[15:0] = 0x0703.

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Figure 42. Mobile DDR SDRAM DQ versus DQS and SDCLK Read Cycle Timing Diagram defined as 50% of signal value. parameters are measured at maximum memory frequency.

3.6.9.1 SDHC Electrical DC Characteristics

Table 42 lists the SDHC electrical DC characteristics. Table 41. Mobile DDR SDRAM Read Cycle Timing Parameters Table 42. SDHC Electrical DC Characteristics

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3.6.10 Smart Liquid Crystal Display Controller (SLCDC)

Figure 43. SLCDC Timing Diagram—Serial Transfers to LCD Device

Figure 44. SLCDC Timing Diagram—Parallel Transfers to LCD Device Table 43. SLCDC Serial Interface Timing Parameters Table 44. SLCDC Parallel Interface Timing Parameters

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3.6.11 Synchronous Serial Interface (SSI)

This section describes the electrical information of SSI.

3.6.11.1 SSI Transmitter Timing with Internal Clock

Figure 45. SSI Transmitter with Internal Clock Timing Diagram Table 44. SLCDC Parallel Interface Timing Parameters (continued)

Figure 46. SSI Transmitter with Internal Clock Timing Diagram Table 45. SSI Transmitter with Internal Clock Timing Parameters

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• All the timings for the SSI are given for a non-inve rted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync (TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures.
• All timings are on AUDMUX pads when SSI is being used for data transfer.
• “Tx” and “Rx” refer to the Transmit and Receive sections of the SSI.
• For internal frame sync operation using external clock, the FS timing is the same as that of Tx Data (for example, during AC97 mode of operation).

3.6.11.2 SSI Receiver Timing with Internal Clock

Figure 47. SSI Receiver with Internal Clock Timing Diagram Table 45. SSI Transmitter with Internal Clock Timing Parameters (continued)

Figure 48. SSI Receiver with Internal Clock Timing Diagram Table 46. SSI Receiver with Internal Clock Timing Parameters

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sync STFS/SRFS shown in the tables and in the figures. All timings are on AUDMUX pads when SSI is being used for data transfer. “Tx” and “Rx” refer to the Transmit and Receive sections of the SSI. same as that of Tx Data, for example, during the AC97 mode of operation. Table 46. SSI Receiver with Internal Clock Timing Parameters (continued)

3.6.11.3 SSI Transmitter Timing with External Clock

Figure 49. SSI Transmitter with External Clock Timing Diagram Figure 50. SSI Transmitter with External Clock Timing Diagram

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sync STFS/SRFS shown in the tables and in the figures. “Tx” and “Rx” refer to the Transmit and Receive sections of the SSI. same as that of Tx Data, for example, during the AC97 mode of operation. Table 47. SSI Transmitter with External Clock Timing Parameters

3.6.11.4 SSI Receiver Timing with External Clock

Figure 51. SSI Receiver with External Clock Timing Diagram Figure 52. SSI Receiver with External Clock Timing Diagram Table 48. SSI Receiver with External Clock Timing Parameters

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sync STFS/SRFS shown in the tables and in the figures. “Tx” and “Rx” refer to the Transmit and Receive sections of the SSI. same as that of Tx Data, for example, during the AC97 mode of operation.

3.6.12 Wireless External Interface Module (WEIM)

WEIM module, and Table 49 lists the timing parameters. Table 48. SSI Receiver with External Clock Timing Parameters (continued)

Figure 53. WEIM Bus Timing Diagram Table 49. WEIM Bus Timing Parameters

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Test conditions: pad voltage, 1.7 V–1.95 V; pad capacitance, 25 pF.

1 BCLK parameters are being measured from the 50% point—that is, high is defined as 50% of

signal value and low is defined as 50% of signal value. Table 49. WEIM Bus Timing Parameters (continued)

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Figure 56. Synchronous Memory Timing Diagram for Two Non-Sequential Figure 57. Synchronous Memory TIming Diagram for Burst

Figure 58. Muxed A/D Mode Timing Diagram for Asynchronous Figure 59. Muxed A/D Mode Timing Diagram for Asynchronous

3.6.13 USBOTG Electricals

This section describes the electrical information of the USB OTG port and host ports.

3.6.14 Serial Interface

• DAT_SE0 bidirectional, 3-wire mode
• DAT_SE0 unidirectional, 6-wire mode Write BCLK ADDR/ RW LBA OE EB[y] CS[x] Address V1 Write DataLast Valid AddrM_DATA WE1 WE2 WE3 WE4 WE6WE5 WE9 WE10 WE11 WE12 WE13 WE14 BCLK ADDR/ RW LBA OE EB[y] CS[x] Address V1 Read DataLast Valid AddrM_DATA WE2 WE3 WE4 WE11 WE12 WE7 WE8 WE9 WE10 WE15 WE16WE1

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• VP_VM bidirectional, 4-wire mode
• VP_VM unidirectional, 6-wire mode

3.6.14.1 DAT_SE0 Bidirectional Mode

Figure 60. USB Transmit Waveform in DAT_SE0 Bidirectional Mode Figure 61. USB Receive Waveform in DAT_SE0 Bidirectional Mode Table 50. Signal Definitions—DAT_SE0 Bidirectional Mode

• TX data when USB_TXOE_B is low
• Differential RX data when USB_TXOE_B is high USB_SE0_VM Out In
• SE0 drive when USB_TXOE_B is low
• SE0 RX indicator when USB_TXOE_B is high

Table 51. OTG Port Timing Specification in DAT_SE0 Bidirectional Mode

3.6.14.2 DAT_SE0 Unidirectional Mode

Figure 62. USB Transmit Waveform in DAT_SE0 Unidirectional Mode Table 52. Signal Definitions—DAT_SE0 Unidirectional Mode Table 51. OTG Port Timing Specification in DAT_SE0 Bidirectional Mode (continued)

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Figure 63. USB Receive Waveform in DAT_SE0 Unidirectional Mode

3.6.14.3 VP_VM Bidirectional Mode

Table 53. OTG Port Timing Specification in DAT_SE0 Unidirectional Mode Table 54. Signal Definitions—VP_VM Bidirectional Mode

• TX VP data when USB_TXOE_B is low
• RX VP data when USB_TXOE_B is high USB_SE0_VM Out (Tx) In (Rx)
• TX VM data when USB_TXOE_B low
• RX VM data when USB_TXOE_B high USB_RCV In • Differential RX data VP, VM, RCV USB_DAT_VP/ USB_SE0_VM

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3.6.14.4 VP_VM Unidirectional Mode

Table 55. OTG Port Timing Specification in VP_VM Bidirectional Mode Table 56. Signal Definitions—VP_VM Unidirectional Mode

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Table 57. USB Timing Specification in VP_VM Unidirectional Mode

4 Package Information and Pinout

4.1 Full Package Outline Drawing

Figure 68 shows package drawings and dimensions of the production package. Figure 68. i.MX27/MX27L Full Package MAPBGA: Mechanical Drawing

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4.2 Pin Assignments

• CLKMODE[1:0]: To ensure proper operation, leave these signals as no connects.
• OSC26M_TEST: To ensure proper operation, leave this signal as no connect.
• EXT_60M: To ensure proper operation, connect this signal to ground.
• EXT_266M: To ensure proper operation, connect this signal to ground.
• Most of the signals shown in Table 58 are multiplexed with other signals. For ease of reference, all of the signals at a particular pad are shown in the form of a compound signal name. Please refer to Table 3 for complete information on the signal multiplexing schemes of these signals. Table 58 shows the device pin list, sorted by signal identification, including pad locations for ground and power supply voltages.

Table 58. i.MX27 24 x 24 BGA (Signal ID by Ball Grid Location)

Table 58. i.MX27 24 x 24 BGA (Signal ID by Ball Grid Location) (continued)

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1. GND and QVSS contacts are tied together inside the BGA package
2. Freescale recommends tying GND and QVSS contacts to a single plane.

5 Product Documentation

This Data Sheet is labeled as a particular type: Product Preview, Advance Information, or Technical Data. Definitions of these types are available at: http://www.freescale.com.

6 Revision History

Table 59 provides a revision history for this document. Table 59. Document Revision History 1 1/2008 This release includes the MCIMX27L device.

Document Number: MCIMX27 Rev. 1 Preliminary—Subject to Change Without Notice How to Reach Us: Home Page: www.freescale.com E-mail: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7

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Tai Po, N.T., Hong Kong +800 2666 8080 support.asia@freescale.com For Literature Requests Only: Freescale Semiconductor Literature Distribution Center P.O. Box 5405 Denver, Colorado 80217 1-800-521-6274 or 303-675-2140 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”, must be validated for each customer application by customer’s technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. ARM and the ARM Powered Logo are registered trademarks of ARM Limited. ARM926EJ-S is a trademark of ARM Limited. IEEE 802.3, 802.1, and 1149.1 are registered trademarks of the Institute of Electrical and Electronics Engineers, Inc. (IEEE). This product is not endorsed or approved by the IEEE. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2008. Printed in the United States of America. All rights reserved.