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IMST805-F20E

STMicroelectronics

32-bit floating-point transputer - xtended temperature Feb-1997

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Datasheet sections

6.7 Memory configuration - : :
10.3 Thermal specification

IE, iicROELECTROMCS IMS T805E 32-bit floating-point transputer — Extended temperature

FEATURES

® 32 bit architecture @ 50 ns internal cycle time @ 20 MIPS (peak) instruction rate @ 2.8 Mflops (peak) instruction rate Pin compatible with IMS T800 Floating Point Unit ® Debugging support ® 64 bit on-chip floating point unit conforming to IEEE 754 @ 4Kkbytes on-chip static RAM ™ 120 Mbytes/sec sustained data rate to internal memory @ 4 Gbytes directly addressable external memory System 32 bit ® 26,7 Mbytes/sec sustained data rate to external memory Services [| Processor ® 950 ns response to interrupts @ Four INMOS serial links 5/10/20 Mbits/sec @ Bi-directional data rate of 2.4 Mbytes/sec per link ® High performance graphics support with block move instructions Services ® Boot from ROM or communication links Timers @ = Single 5 MHz clock input Link B Single +5V +5% power supply 4 Kbytes a) is | @ Packaging 84 pin PGA / 100 pin CQFP of ® Extended operating temperature —55_C to +125_C On-chip [ 32_| (a) ttc APPLICATIONS RAM Interface ®@ Scientific and mathematical applications Link ® High speed multi processor systems [32 | Interface ® High performance graphics processing — HUD/HDD displays External 32 ® Supercomputers Memory Interface ™@ Workstations and workstation clusters Interface ® Digital signal processing [2] ® Accelerator processors ® Distributed databases ®@ System simulation @ Telecommunications ® Robotics ® Fault tolerant systems @ Image processing @ Pattern recognition ®@ Artificial intelligence February 1997 42 1533 05

1 Introduction

The IMS T805E transputer is a 32 bit CMOS microcomputer with a 64 bit floating point unit and graphics support. It has 4 Kbytes on-chip RAM for high speed processing, a configurable memory interface and four standard INMOS communication links. The instruction set achieves efficient implementation of high level languages such as ANSIC and provides direct support for the OCCamM model of concurrency when using either a single transputer or a network. Procedure calls, process switching and typical interrupt latency are sub-microsecond. For convenience of description, the IMS T805E operation is split into the basic blocks shown in figure 1.1 Floating Point Unit VDD GND CapPlus . CapMinus System AN 32bit Reset Services 32] Processor Analyse Errorlin ——| Error BootFromROM Clockin LinkSpecial ProcSpeedSelect0-2 Link LinkOSpecial Services || Link123Special S| Interface LinkOutO

4 Kbytes

DisableIntRAM onhip 32 orm Link Linkint RAM \\-4) Interface LinkOut te Link Linkin2 ProcClockOut <4] Interface LinkOut2 notMemS0-4 «—_} notMemWrB0-3 ~ notMemRd «—| loom Link Linkin3 notMemRf <——| External N 3 Interface }—» LinkOut3 RefreshPending < Memory MemWait Interface [35 EventReq MemContig Event EventAck MemReq — EventWaiting MemGranted MemnotWrDO <2 Memnothtot MemAD2-31 Figure 1.1 IMS T805E block diagram {yz Ss: 3/71

The IMS T805E provides high performance arithmetic and floating point operations. The 64 bit floating point unit provides single and double length operation to the ANSI-IEEE 754-1985 standard for floating point arithmetic. It is able to perform floating point operations concurrently with the processor, sustaining a rate of 2.2 Mflops at a processor speed of 20 MHz. High performance graphics support is provided by microcoded block move instructions which operate at the speed of memory. The two-dimensional block move instructions provide for contiguous block moves as well as block copying of either non-zero bytes of data only or zero bytes only. Block move instructions can be used to provide graphics operations such as text manipulation, windowing, panning, scrolling and screen updating. Cyclic redundancy checking (CRC) instructions are available for use on arbitrary length serial data streams, to provide error detection where data integrity is critical. Another feature of the IMS T805E, useful for pattern recognition, is the facility to count bits set in a word. The IMS T805E can directly access a linear address space of 4 Gbytes. The 32 bitwide memory interface uses multiplexed data and address lines. Aconfigurable memory controller provides all timing, control and DRAM refresh signals for a wide variety of mixed memory systems. System Services include processor reset and bootstrap control, together with facilities for error analysis. Error signals may be daisy-chained in multi-transputer systems. The standard INMOS communication links allow networks of transputer family products to be constructed by direct point to point connections with no external logic. The IMS T805E links support the standard operating speed of 10 Mbits/sec, but also operate at 5 or 20 Mbits/sec. Each link can transfer data bi-directionally at up to 2.35 Mbytes/sec. The transputer is designed to efficiently implement high level languages such as ANSI C and occam. Access to the transputer at machine level is seldom required, but if necessary refer to the Transputer In- struction Set — A Compiler Writer's Guide. A summary of the transputer instruction set can be found in section 12. The IMS T805E instruction set contains a number of instructions to facilitate the implementation of break- points. For further information about breakpointing, refer to Support for debugging/breakpointing in trans- puters (technical note 61). Figure 1.2 shows the internal datapaths for the IMS T805E. 4/71 SCS")

Areg [yn [at Areg [ "> bata bus Dout | interface) out Breg bus bus Greg fl FPopcode instruction streamer ouna laid =a

4 Kbyte

bus i _T¥ Data B bus Address} [T_T data out reg Channel data |Configuration [TT] register and ming control ke U bus| External CPU memory interface ink oL__Ptrea unk ° eta ~ Lv ml [al [data reg | —»j output lin soa Wie Link 1 i Links ane Co Address aS registers instruction fetch addr channel address data address Figure 1.2 IMS T805E internal datapaths —__sSSSSSséSF7'SES-' e790 77, 2eS THOMSON

2 Pin designations

Signal names are prefixed by not if they are active low, otherwise they are active high. Pinout details for various packages are given in section 10. [Fin rot VDD, GND Power supply and return CapPlus, CapMinus External capacitor for internal clock power supply Clockin Input clock ProcSpeedSelect0-2 Processor speed selectors Reset System reset Error Error indicator Errorin Error daisychain input Analyse Error analysis BootFromROM Boot from external ROM or from link DisableIntRAM Disable internal RAM Table 2.1 IMS T805E system services ee ProcClockOut out Processor clock MemnotWrDO in/out Multiplexed data bit 0 and write cycle warning MemnotRfD1 in/out Multiplexed data bit 1 and refresh warning MemAD2-31 in/out Multiplexed data and address bus notMemRd out Read strobe notMemWrB0-3 out Four byte-addressing write strobes notMemS0-4 out Five general purpose strobes notMemRf out Dynamic memory refresh indicator RefreshPending out Dynamic refresh is pending MemWait in Memory cycle extender MemReq in Direct memory access request MemGranted out Direct memory access granted MemConfig in Memory configuration data input Table 2.2 IMS T805E external memory interface jin Strut EventReq Event request EventAck Event request acknowledge EventWaiting Event input requested by software Table 2.3 IMS T805E event [Pin SSC*dYCiwt ST SCSC*~*~S ration SSCSC~*d LinkIn0-3 in Four serial data input channels LinkOuto-3 out Four serial data output channels LinkSpecial in Select non-standard speed as 5 or 20 Mbits/sec LinkOSpecial in Select special speed for Link 0 Link123Special in Select special speed for Links 1,2,3 Table 2.4 IMS T805E link 6/71 {yz Ses:

3 Floating point unit

The 64 bit FPU provides single and double length arithmetic to floating point standard ANSI-IEEE 754-1985. Itis able to perform floating point arithmetic concurrently with the central processor unit (CPU). All data communication between memory and the FPU occurs under control of the CPU The FPU consists of a microcoded computing engine with a three deep floating point evaluation stack for manipulation of floating point numbers. These stack registers are FA, FB and FC, each of whichcan hold either 32 bit or 64 bit data; an associated flag, set when a floating point value is loaded, indicates which. The stack behaves in a similar manner to the CPU stack. As with the CPU stack, the FPU stack is not saved when rescheduling occurs. The FPU can be used in both low and high priority processes. When a high priority process interrupts a low priority one the FPU state is saved inside the FPU. The CPU will service the interrupt immediately on completing its current operation. The high priority process will not start, however, before the FPU has completedits current oper- ation. Points in an instruction stream where data need to be transferred to or from the FPU are called synchroni- sation points. At a synchronisation point the first processing unit to become ready will wait until the other is ready. The data transfer will then occur and both processors will proceed concurrently again. In order to make full use of concurrency, floating point data source and destination addresses can be calculated by the CPU whilst the FPU is performing operations on a previous set of data. Device performance is thus optimised by minimising the CPU and FPU idle times. The FPU has been designed to operate on both single length (32 bit) and double length (64 bit) floating point numbers, and returns results which fully conform to the ANSI-IEEE 754-1985 floating point arithmetic standard. Denormalised numbers are fully supported in the hardware. All rounding modes defined by the standard are implemented, with the default being rounded to the nearest. The basic addition, subtraction, multiplication and division operations are performed by single instructions. However, certain less frequently used floating point instructions are selected by a value in register A (when allocating registers, this should be taken into account). A /oad constantinstruction /dcis used to load regis- ter A; the floating point entry instruction fpentry then uses this value to select the floating point operation. This pair of instructions is termed a selector sequence. Names of operations which use fpentry begin with fou. A typical usage, returning the absolute value of a floating point number, would be fpuabs; ldc fpentry; Since the indirection code for fpuabs is OB, it would be encoded as Mnemonic Function Memory code code Ide fpuabs #4 #4B fpentry (op. code #AB) #2AFB is coded as pfix #A #2 HOA opr #B #F #FB Table 3.1 fpentry coding The remainderand square rootinstructions take considerably longer than other instructions to complete. In order to minimise the interrupt latency period of the transputer they are split up to form instruction se- quences. As an example, the instruction sequence for a single length square root is fpusartfirst; fpusqrtstep; — fpusqrtstep; —_fpusqrtlast; {yz Ss: 7/71

The FPU has its own error flag FP_Error. This reflects the state of evaluation within the FPU and is set in circumstances where invalid operations, division by zero or overflow exceptions to the ANSI-IEEE 754-1985 standard would be flagged. FP_Erroris also set if an inputto a floating point operation is infinite or is nota number (NaN). The FP_Errorflag can be set, tested and cleared without affecting the main Error flag, but can also set Errorwhen required Depending on how a program is compiled, itis possible for both unchecked and fully checked floating point arithmetic to be performed. Further details about the operation of the FPU can be foundin the ‘Transputer Instruction Set— A Compiler Writer's Guide’. T805-20E Operation Single length Double length add 350 ns 350 ns subtract 350 ns 350 ns multiply 550 ns 1000 ns divide 850 ns 1600 ns Timing is for operations where both operands are nor- malised fp numbers. Table 3.2 Typical floating point operation times for IMS T805E 8/71 SCS")

4 System services

System services include all the necessary logic to initialise and sustain operation of the device. They also include error handling and analysis facilities.

41 Power

Power is supplied to the device via the VDD and GND pins. Several of each are provided to minimise induc- tance within the package. All supply pins must be connected. The supply must be decoupled close to the chip by at least one 100 nF low inductance (e.g. ceramic) capacitor between VDD and GND. Four layer boards are recommended; if two layer boards are used, extra care should be taken in decoupling. Input voltages must not exceed specification with respect to VDD and GND, even during power-up and power-down ramping, otherwise /atchup can occur. CMOS devices canbe permanently damaged by ex- cessive periods of latchup.

42 CapPlus, CapMinus

The internally derived power supply for internal clocks requires an external low leakage, low inductance 1nF capacitor to be connected between CapPlus and CapMinus. A ceramic capacitor is preferred, with an impedance less than3 Ohms between 100 KHz and 10 MHz. Ifa polarised capacitor is used the nega- tive terminal should be connected to CapMinus. Total PCB track length should be less than 50 mm. The connections must not touch power supplies or other noise sources. vob = J CapPlus P.C.B track Phasesocked Decoupling loops capacitor 1 nF ] CapMinus _P.C.B track GND 7 Figure 4.1 Recommended PLL decoupling

4.3 Clockin

Transputer family components use a standard clock frequency, supplied by the user on the ClockIn input. The nominal frequency of this clock for all transputer family components is 5 MHz, regardless of device type, transputer word length or processor cycle time. High frequency internal clocks are derived from Clockin, simplifying system design and avoiding problems of distributing high speed clocks externally. Anumber of transputer devices may be connected to acommon clock, or may have individual clocks pro- viding each one meets the specified stability criteria. In a multi-clock system the relative phasing of Clock- In clocks is not important, due to the asynchronous nature of the links. Mark/space ratio is unimportant provided the specified limits of ClockIn pulse widths are met. Oscillator stability is important. Clockin must be derived from a crystal oscillator; RC oscillators are not sufficiently stable. ClockIn must not be distributed through a long chain of buffers. Clock edges must be monotonic and remain within the specified voltage and time limits. {yz Ss: 9/71

Parameter [min [Nom [ ax | TDCLDCH | Clockin pulse width low 40 TDCHDCL | Clockin pulse width high 40 TDCLDCL | Clockin period 200 1,3 TDCerror Clockin timing error 05 2 TDC1DC2_ | Difference in Clockin for 2 linked devices 400 3 TDCr Clockin rise time 10 4 TDCf Clockin fall time 8 4 Notes 1 Measured between corresponding points on consecutive falling edges. 2 Variation of individual falling edges from their nominal times.

3 This value allows the use of 200ppm crystal oscillators for two devices connected together by

a link. 4 Clock transitions must be monotonic within the range VIH to VIL (table 9.3). Table 4.1 Input clock TDCerror TDCerror -»| TDCerror TDCerror 15V ===NN a SS ——E ov IS IN TDCLDCH TDCHDCL TDCLDCL <— TDCf TDCr. Figure 4.2 Clockln timing

44 ProcSpeedSelect0-2

For the 20 MHz T805E the three speed select lines ProcSpeedSelect0-2 are tied low, according to table 4.2. The pins are arranged so that the IMS T805E can be plugged directly into a board designed for a IMS T425. The frequency of Clockin is 5 MHz. ProcSpeed- ProcSpeed- ProcSpeed- Processor Processor Select2 Select1 SelectO Clock Cycle Speed MHz Time ns A Table 4.2 Processor speed selection 10/71 {yz Ses:

45 Bootstrap

The transputer can be bootstrapped either from a link or from external ROM. Tofacilitate debugging, Boot- FromROM may be dynamically changed but must obey the specified timing restrictions. Itis sampled once only by the transputer, before the first instruction is executed after Reset is taken low. If BootFromROM is connected high (e.g. to VDD) the transputer starts to execute code from the top two bytes in external memory, at address #7FFFFFFE. This location should contain a backward jump to a pro- gram in ROM. Following this access, BootFromROM may be taken low if required. The processor is in the low priority state, and the W register points to MemStart (page 15). If BootFromROM is connected low (e.g. to GND) the transputer will wait for the first bootstrap message to arrive on any one ofits links. The transputer is ready to receive the first byte ona link within two processor cycles TPCLPCL after Reset goes low. If the first byte received (the control byte) is greater than 1 it is taken as the quantity of bytes to be input. The following bytes, to that quantity, are then placed in internal memory starting atlocation MemStart. Fol- lowing reception of the last byte the transputer will start executing code at MemStartas a low priority pro- cess. BootFromROM may be taken high after reception of the last byte, if required. The memory space immediately above the loaded code is used as work space. A byte arriving on other links after the control byte has been received and on the bootstrapping link after the last bootstrap byte, will be retained and no acknowledge will be sent until a process inputs from them

46 Peek and poke

Any location in internal or external memory can be interrogated and altered when the transputer is waiting for a bootstrap from link. If the control byte is 0 then eight more bytes are expected on the same link. The first four byte word is taken as an internal or external memory address at which to poke (write) the second four byte word. If the control byte is 1 the next four bytes areused as the address from which to peek (read) a word of data; the word is sent down the output channel of the same link. Following such a peek or poke, the transputer returns to its previously held state. Any number of accesses may be made in this way until the control byte is greater than 1, when the transputer will commence read- ing its bootstrap program. Any link can be used, but addresses and data must be transmitted via the same link as the control byte. {yz Ss: W/71 TT 7, See TTT

47 Reset

Reset can go high with VDD, but must at no time exceed the maximum specified voltage for VIH. After VDD is valid ClockIn shouldbe running fora minimum period TDCVRL before the end of Reset. The falling edge of Reset initialises the transputer, triggers the memory configuration sequence and starts the boot- strap routine. Link outputs are forced low during reset; link inputs and EventReq should be held low. Memory request(DMA) must not occur whilst Reset is high but can occur before bootstrap (page 32). After the end of Reset there will be a delay of 144 periods of Clockin (figure 4.3). Following this, the MemWrDO, MemR{D1 and MemAD2-31 pins will be scanned to check forthe existence of a pre-programmed memory interface configuration (page 35). This lasts for a further 144 periods of ClockIn. Regardless of whether aconfiguration was found, 36 configuration read cycles will then be performed on external memory using the default memory configuration (page 37), in an attempt to access the external configuration ROM. A delay will then occur, its period depending on the actual configuration. Finally eight complete and consecu- tive refresh cycles will initialise any dynamic RAM, using the new memory configuration. If the memory configuration does not enable refresh of dynamic RAM the refresh cycles will be replaced by an equivalent delay with no external memory activity. |f BootFromROM is high bootstrapping will then take place immediately, using data from external memory; otherwise the transputer will await an input from any link. The processor will be in the low priority state. Reset | Action tet nena oH ' 5 i internal xternal Delay configuration configuration Delay Refresh Boot Figure 4.3 IMS T805E post-reset sequence

48 Analyse

If Analyse is taken high when the transputer is running, the transputer will halt at the next descheduling point (point at which a context switch can occur). From Analyse being asserted, the processor will halt within three time slice periods plus the time taken for any high priority process to complete. As much of the transputer status is maintained as is necessary to permit analysis of the halted machine. Processor flags Error, HaltOnError and EnableJOBreak are normally cleared at reset on the IMS T805E; however, if Analyse is asserted the flags are not altered. Memory refresh continues. Input links will continue with outstanding transfers. Output links will not make another access to memory for data but will transmit only those bytes already in the link buffer. Providing there is no delay in link ac- knowledgement, the links should be inactive within a few microseconds of the transputer halting. Reset should not be asserted before the transputer has halted and link transfers have ceased. When Re- set is taken low whilst Analyse is high, neither the memory configuration sequence nor the block of eight refresh cycles will occur; the previous memory configuration will be used for any external memory ac- cesses. If BootFromROM is high the transputer will bootstrap as soon as Analyse is taken low, otherwise it will await a control byte on any link. If Analyse is taken low without Reset going high the transputer state and operation are undefined. After the end of a valid Analyse sequence the registers have the values giv- en in table 4.3. [ MemStart if bootstrapping from a link, or the external memory bootstrap address if bootstrapping from ROM. W | MemStart if bootstrapping from ROM, or the address of the first free word after the bootstrap program if bootstrapping from link. A_ | The value of I when the processor halted B_ | The value of W when the processor halted, together with the priority of the process when the transputer was halted (i.e. the W descriptor) C | The ID of the bootstrapping link if bootstrapping from link. Table 4.3 Register values after Analyse 12/71 SCS") a £97, STON TT

Symbol Parameter | Min | Nom | Max | TPVRH Power valid before Reset 10 ms TRHRL Reset pulse width high 8 Clockin 1 TDCVRL | Clockin running before Reset end 10 ms 2 TAHRH Analyse setup before Reset 3 ms TRLAL Analyse hold after Reset end 1 Clockin 1 TBRVRL BootFromROM setup 0 ms TRLBRX BootFromROM hold after Reset 50 ms 3 TALBRX BootFromROM hold after Analyse 50 ms 3 Notes 1 Full periods of ClockIn TDCLDCL required.

2 At power-on reset

3 Must be stable until after end of bootstrap period. See Bootstrap section 4.5. Table 4.4 Reset , Analyse and BootFromROM timing Clockin | TDCVRL } i i vpD am 14 TPVRHE ff Ef TRHRL | j i Reset i i } j TBAVA' TRLBRX, BootFromROM j }} Figure 4.4 Transputer Reset timing with Analyse low TRHRL /j Reset i TAHRH TRIAL | Analyse TBRVA TALBRX/ BootFromROM j a Figure 4.5 Transputer Reset, Analyse and BootFromROM timing {yz Ss: 13/71

49 Error, Errorin

The Error pin carries the OR’ed output of the internal Error flag and the Errortn input. If Error is high it indicates either that Errorin is high or that an error was detected in one of the processes. An internal error can be caused, for example, by arithmetic overflow, divide by zero, array bounds violation or software set- ting the flag directly. It can also be set from the floating point unit under certain circumstances (page 8) Once set, the Error flag is only cleared by executing the instruction testerr. The error is not cleared by pro- cessor reset, in order that analysis can identify any errant transputer (page 12). A process can be pro- grammed to stop if the Error flag is set; it cannot then transmit erroneous data to other processes, but pro- cesses which do not require that data can still be scheduled. Eventually all processes which rely, directly or indirectly, on data from the process in error will stop through lack of data. Errorin does not directly affect the status of a processor in any way. By setting the HaltOnErrorflag the transputer itself can be programmed to haltif Errorbecomes set. If Error becomes setafter HaltOnErrorhas been set, all processes on that transputer will cease but will not neces- sarily cause other transputers in a network to halt. Setting HaltOnErroratter Error will not cause the trans- puter to halt; this allows the processor reset and analyse facilities to function with the flags in indeterminate states. An alternative method of error handling is to have the errant process or transputer cause all transputers to halt. This can be done by ‘daisy-chaining’ the ErrorIn and Error pins of a number of processors and applying the final Error output signal to the EventReq pin of a suitably programmed master transputer. Since the process state is preserved when stopped by an error, the master transputer can then use the analyse function to debug the fault. When using such a circuit, note that the Errorflag is in an indeterminate state on power up; the circuit and software should be designed with this in mind. Error checks can be removed completely to optimise the performance of a proven program; any unex- pected error then occurring will have an arbitrary undefined effect. If a high priority process pre-empts a low priority one, status of the Error and HaltOnError flags is saved for the duration of the high priority process and restored at the conclusion of it. Status of both flags is trans- mitted to the high priority process. Either flag can be altered in the process without upsetting the error sta- tus of any complex operation being carried out by the pre-empted low priority process. In the event ofa transputer halting because of HaltOnError, the links will finish outstanding transfers before shutting down. If Analyse is asserted then all inputs continue but outputs will not make another access to memory for data. Memory refresh will continue to take place After halting due to the Error flag changing from 0 to 1 whilst Ha/tOnErroris set, register | points two bytes past the instruction which set Error. After halting due to the Analyse pin being taken high, register I points one byte past the instruction being executed. In both cases | will be copied to register A. Master seeee Transputer Latch{ PO Looe Event = = vented T805E T805E T805E slave 0 slave 1 slave n GND Errorin Error;—|Errorin Error: - - -- >Errorin_ Error (transputer links not shown) Figure 4.6 Error handling in a multi-transputer system 14/71 SCS") — £97, STON TT

5 Memory

The IMS T805E has 4 Kbytes of fast internal static memory for high rates of data throughput. Eachinternal memory access takes one processor cycle ProcClockOut (page 20). The transputer can also access 4 Gbytes of external memory space. Internal and external memory are part of the same linear address space. Internal RAM can be disabled by holding DisableIntRAM high. All internal addresses are then mapped to external RAM. This pin should not be altered after Reset has been taken low. IMS T805E memory is byte addressed, with words aligned on four-byte boundaries. The least significant byte of a word is the lowest addressed byte. The bits in a byte are numbered 0 to 7, with bit 0 the least significant. The bytes are numbered from 0, with byte 0 the least significant. In general, wherever a value is treated as a number of component values, the components are numbered in order of increasing numerical significance, with the least significant compo- nent numbered 0. Where values are stored in memory, the least significant component value is stored at the lowest (most negative) address. Internal memory starts at the most negative address #80000000 and extends to #80000FFF. User memory begins at #80000070; this location is given the name MemStart. An instruction dmemstartvalis provided to obtain the value of MemStart. The context of a process in the transputer model involves a workspace descriptor (WPtr) and an instruc- tion pointer (IPtr). WPtris a word address pointer to a workspace in memory. IPtr points to the next instruc- tion to be executed for the process which is the currently executing process. The context switch performed by the breakpoint instruction swaps the WPtr and IPtr of the currently executing process with the WPtr and IPtr held above MemStart. Two contexts are held above MemStart, one for high priority and one for low priority; this allows processes at both levels to have breakpoints. Note that on bootstrapping from a link, these contexts are overwritten by the loaded code. If this is not acceptable, the values should be peeked from memory before bootstrapping from a link. The reserved area of internal memory below MemStart is used to implement link and event channels. Two words of memory are reserved for timer use, TPtrLoc0 for high priority processes and TPtrLoct for low priority processes. They either indicate the relevant priority timer is not in use or point to the first pro- cess on the timer queue at that priority level. Values of certain processor registers for the current low priority process are saved in the reserved IntSave- Loc locations when a high priority process pre-empts a low priority one. Other locations are reserved for extended features such as block moves and floating point operations. External memory space starts at #80001000 and extends up through #00000000 to #7F FFFFFF. Memory configuration data and ROM bootstrapping code must be in the most positive address space, starting at #7FFFFF6C and #7FFFFFFE respectively. Address space immediately below this is conventionally used for ROM based code. {yz Ss: 15/71

hi Machine map lo Byte address Word offsets occam map Po cag #7FFFFF6C L | . #80001000 — Start of external memory —#0400 b_F¢s0000070 Memstart Memstat sich Reserved for #8000006C extended functions #80000048 ERegintSaveLoc | #80000044 STATUSIntSaveLoc |#80000040 CRegIntSaveLoc #8000003C ARegintSaveLoc | #80000034 IptrintSaveLoc #80000030 WdescintSaveLoc | #8000002C TPtrLoct #80000028 Note 1 TPtrLocO #80000024 Link 3 Input #8000001C #07 Link 3 Input Link 0 Input #80000010 #04 Link 0 Input Link 3 Output #8000000C #03 Link 3 Output Link 2 Output #80000008 #02 Link 2 Output #80000004 #01| Link 1 Output Link 0 Output —_|#80000000 (Base of memory) #00 Link 0 Output Notes

1 These locations are used as auxiliary processor registers and should not be manipulated by the

user. Like processor registers, their contents may be useful for implementing debugging tools (Analyse, page 12). For details see Transputer Instruction Set — A Compiler Writers’ Guide. Figure 5.1 IMS T805E memory map 16/71 SCS")

6 External memory interface

The External Memory Interface (EMI) allows access to a 32 bit address space, supporting dynamic and static RAM as well as ROM and EPROM. EMI timing can be configured at Reset to cater for most memory types and speeds, and aprogram is suppliedwith the Transputer Development System to aid inthis config- uration. There are 17 internal configurations which can be selected by a single pin connection (page 35). If none are suitable the user can configure the interface to specific requirements, as shown on page 37. The external memory cycle is divided into six Tstates with the following functions: T1 Address setup time before address valid strobe. T2 Address hold time after address valid strobe. T3 Read cycle tristate or write cycle data setup. T4 Extendable data setup time. T5 Read or write data. T6 Data hold Under normal conditions each Tstate may be from one to four periods Tm long, the duration being set during memory configuration. The default condition on Resetis that all Tstates are the maximum four peri- ods Tm long to allow external initialisation cycles to read slow ROM. Period T4 can be extended indefinitely by adding externally generated wait states. An external memory cycle is always an even number of periods Tm in length and the start of T1 always coincides with a rising edge of ProcClockOut. If the total configured quantity of periods Tm is anodd num- ber, one extra period Tm will be added at the end of T6 to force the start of the next T1 to coincide with arising edge of ProcClockOut. This period is designated E in configuration diagrams (figure 6.19). During an internal memory access cycle the external memory interface bus MemAD2-31 reflects the word address used to access internal RAM, MemnotWrD0 reflects the read/write operation and MemnotRfD1 is high; all control strobes are inactive. This is true unless and until a memory refresh cycle or DMA (memory request) activity takes place, when the bus will carry the appropriate external address or data. The bus activity is not adequate to trace the internal operation of the transputer in full, but may be used for hardware debugging in conjunction with peek and poke (page 11). ProcClockOut —f \\ Sf YS VY S/S Yi. MemnotWrDO Write / Read Read X MemnotRfD1 y X MemAD2-31 Address Figure 6.1 IMS T805E bus activity for internal memory cycle {yz Ss: 17/71

6.1 Pin functions

6.1.1 MemAD2-31

External memory addresses and data are multiplexed on one bus. Only the top 30 bits of address are out- put on the external memory interface, using pins MemAD2-31. They are normally output only during Tstates T1 and T2, and should be latched during this time. The data bus is 32 bits wide. It uses Me- mAD2-31 for the top 30 bits and MemnotRfD1 and MemnotWrD0 for the lower two bits 6.1.2 notMemRd For a read cycle the read strobe notMemRg is low during T4 and TS. Data is read by the transputer on the rising edge of this strobe, and may be removed immediately afterward. If the strobe duration is insuffi- cient it may be extended by adding extra periods Tm to either or both of the Tstates T4 and T5. Further extension may be obtained by inserting wait states at the end of T4.

6.1.3 MemnotWrDO

During T1 and T2 this pin will be low if the cycle is a write cycle, otherwise it will be high. During Tstates T3 to T6 it becomes bit 0 of the data bus. In both cases it follows the general timing of MemAD2-31. 6.1.4 notMemWrB0-3 Because the transputer uses word addressing, four write strobes are provided; one to write each byte of the word. notMemWrB0 addresses the least significant byte. 6.1.5 notMemS0-4 To facilitate control of differenttypes of memory and devices, the EMI is provided with five strobe outputs, four of which can be configured by the user. The strobes are conventionally assigned the functions shown in the read and write cycle diagrams, although there is no compulsion to retain these designations.

6.1.6 MemWait

Wait states can be selected by taking MemWait high. Externally generated wait states can be added to extend the duration of T4 indefinitely.

6.1.7 MemnotRfD1

During T1 and T2, this pin is low if the address on MemAD2-31 is a refresh address, otherwise it is high. During Tstates T3 to T6 it becomes bit 1 of the data bus. Inboth cases it follows the general timing of Me- mAD2-31. 6.1.8 notMemRf The IMS T805E can be operated with memory refresh enabled or disabled. The selection is made during memory configuration, when the refresh interval is also determined.

6.1.9 RefreshPending

When high, this pin signals that a refresh cycle is pending. 18/71 SCS")

i faz 2: Clockin CapMinus FTC OE (6MHz) GND LinkOIn 100K | GND 56K 4 notMemWrB3.- = Dynamic LinkOut img | notMemWrB2 [456K AT RAM Linkin 4 T805 |-notMemwrB1__| Bek 4) As LinkO notMemWrBO i Link1Out Dynamic} notMemRd—— notOE ~256K 4] RAM notMemS3—— notCAS— Dynamic Link2in notMemS2— RAM Link2Out notMemS1 notRAS: 56R notMemSO Link3In + Link30ut 43 Linkd sow sourese|_ | column address| address MemContig latch multiplexo! a5 9 2 8s,| |e) § 18 o| BEd a Sea; ja} $| [8 a 600 a a 60a a fa) a E EEE E E EEE E E E oa ooo oa o 2oo @ o o = 222 = = i = = = Figure 6.2 IMS T805E application

6.1.10 MemReq, MemGranted

Direct memory access (DMA) can be requested at any time by driving the asynchronous MemReg input high. MemGranted follows the timing of the bus being tristated and can be used to signal to the device requesting the DMA that it has control of the bus. Note that MemGranted changes on the falling edge of ProcClockOut and can therefore be sampled to establish control of the bus on the rising edge of ProcClockOut 6.1.11. MemConftig MemConfig is an input pin used to read configuration data when setting external memory interface (EMI) characteristics.

6.1.12 ProcClockOut

This clock is derived from the internal processor clock, which is in turn derived from Clockin. Its period is equal to one internal microcode cycle time, and can be derived from the formula TPCLPCL = TDCLDCL / PLLx where TPCLPCL is the ProcClockOut Period, TDCLDCL is the Clockin Period and PLLx is the phase lock loop factor for the relevant speed part, obtained from the ordering details (Ordering section). {yz Ss: 19/71 TT 7, See TTT

The time value Tm is used to define the duration of Tstates and, hence, the length of external memory cycles; its value is exactly half the period of one ProcClockOut cycle (0.5*TPCLPCL), regardless of mark/ space ratio of ProcClockOut. Edges of the various external memory strobes coincide with rising or falling edges of ProcClockOut. It should be noted, however, that there is a skew associated with each coincidence. The value of skew de- pends on whether coincidence occurs when the ProcClockOut edge and strobe edge are both rising, when both are falling or if either is rising when the other is falling. Timing values given in the strobe tables show the best and worst cases. If a more accurate timing relationship is required, the exact Tstate timing and strobe edge to ProcClockOut relationships should be calculated and the correct skew factors applied from the edge skew timing table 6.4. T805-20E Parameter [ Min | Max | Notes TPCLPCL | ProcClockOut period 48 52 ns TPCHPCL | ProcClockOut pulse width high 13.5 28.5 ns TPCLPCH | ProcClockOut pulse width low a ns 2,3 Tm ProcClockOut half cycle 24 26 ns TPCstab | ProcClockOut stability 8 % 1 Notes

1 Stability is the variation of cycle periods between two consecutive cycles, measured at corre-

sponding points on the cycles. 2 ais TPCLPCL — TPCHPCL. 3 This is a nominal value. Table 6.1 ProcClockOut 1.5V TPCLPCH TPCHPCL TPCLPCL Figure 6.3 IMS T805E ProcClockOut timing 20/71 SCS")

6.2 Read cycle

Byte addressing is carried out internally by the transputer for read cycles. For a read cycle the read strobe notMemRd is low during T4 and T5. Read cycle data may be set up onthe data bus at any time after the start of T3, but must be valid when the transputer reads it at the end of T5. Datamay be removed any time during T6, but must be off the bus no later than the end of that period. notMemSO is afixed format strobe. Its leading edge is always coincident with the start of T2 and its trailing edge always coincident with the end of T5. The leading edge of notMemS1 is always coincident with the start of T2, butits duration may be configured to be from zero to 31 periods Tm. Regardless of the configured duration, the strobe will terminate no later than the endof T6. The strobe is sometimes programmed to extend beyond the normal end of Tmx. When wait states are inserted into an EMI cycle the end of Tmx is delayed, but the potential active duration of the strobe is not altered. Thus the strobe can be configured to terminate relatively early under certain con- ditions (page 27). If notMemS1 is configured to be zero it will never go low. notMemS2, notMemS3 and notMemS4 are identical in operation. They all terminate at the end of T5, but the start of each can be delayed from one to 31 periods Tm beyond the start of T2. If the duration of one of these strobes would take it past the end of T5 it will stay high. This can be used to cause a strobe to become active only when wait states are inserted. If one of these strobes is configured to zero it will never go low. Figure 6.6 shows the effect of Wait on strobes in more detail; each division on the scale is one period Tm. Inthe read cycle timing diagrams ProcClockOut is included as a guide only; it is shown with each Tstate configured to one period Tm. T805-20E Symbol | Parameter [| Min | Max | TaZdV Address tristate to data valid 0 TdVRdH _ | Data setup before read 25 TRdHdX | Data hold after read 0 TSOLRdL | notMemS0 before start of read a4 a+4 1 TSOHRGdH | End of read from end of notMemSO 4 4 TRdLRdH | Read period b-3 b+5 2 Notes 1 ais total of T2+T3 where T2, T3 can be from one to four periods Tm each in length. 2. bis total of T4+Twait+T5 where T4, T5 can be from one to four periods Tm each in length and Twait may be any number of periods Tm in length. Table 6.2 Read {yz Ss: 21/71

mer 11 | T2 | T3 T4 | 5 T6 T1 | ProcClockOut iA \\ ( ; ‘ \\ | WW MemnotWrD0 (CCC Data) ) MemnotRiD1 | oe ( MemAD2-31 (CCCUK Data} ) ‘TaZdV ‘TRdHdX ‘aVSOL, TSOLaX| TavedH TSOLRdL || TRdLRdH notMemRd TSOHRdH TSOLSOH notMemSO (CE) TSOLS1LM 2 TSOHS1H® ) Hi } notMemS1 (ALE) Figure 6.4 IMS T805E external read cycle: static memory 22/71 .

svat |v romney | | | TaVSOL Address setup before notMemSO a8 1 TSOLax Address hold after notMemSO b-8 b+8 2 TSOLSOH notMemS0 pulse width low c-5 e+6 3 TSOLS1L 1 |notMemS1 from notMemSO 4 4 TSOLS1H | 5 |notMemS1 end from notMemSO d-3 d+7 46 TSOHS1H | 9 |notMemS1 end from notMemS0 end e-8 e+4 5.6 TSOLS2L | 2 |notMemS2 delayed after notMemSO 1-6 5 7 TSOLS2H | 6 |notMemS2 end from notMemSO c-5 +7 3 TSOHS2H | 10 | notMemS2 end from notMemSO0 end 4 7 TSOLS3L 3 | notMemS3 delayed after notMemSO £-6 +5 7 TSOLS3H | 7 |notMemS3 end from notMemSO c5 +7 3 TSOHS3H | 11 | notMemS3 end from notMemSO end 4 7 TSOLS4L 4 |notMemS4 delayed after notMemSO 1-6 5 7 TSOLS4H | 8 |notMemS4 end from notMemSO c5 c+7 3 TSOHS4H | 12 |notMemS4 end from notMemS0 end 4 7 Tmx Complete external memory cycle 8 Notes 1 ais T1 where T1 can be from one to four periods Tm in length. 2 bis T2 where T2 can be from one to four periods Tm in length. 3 cis total of T2+T3+T4+Twait+T5 where T2, T3, T4, T5 can be from one to four periods Tm each in length and Twait may be any number of periods Tm in length. 4 dcan be from zero to 31 periods Tm in length. 5 ecan be from -27 to +4 periods Tm in length.

6 If the configuration would cause the strobe to remain active past the end of T6 it will go high at

the end of T6. If the strobe is configured to zero periods Tm it will remain high throughout the complete cycle Tmx. 7 fcan be from zero to 31 periods Tm in length. If this length would cause the strobe to remain active past the end of TS5 it will go high at the end of TS. If the strobe value is zero periods Tm it will remain low throughout the complete cycle T1 to T5, going high only for first Tm of T6.

8 Tmx is one complete external memory cycle comprising the total of

71+T2+T3+T4+ Twait+T5+T6 where T1, T2, T3, T4, T5 can be from one to four periods Tm each in length, T6 can be from one to five periods Tm in length and Twait may be zero or any number of periods Tm in length. Table 6.3 IMS T805E strobe timing

Symbol Parameter [ Min | Max | TPCHSOH notMemS0 rising from ProcClockOut rising 6 4 TPCLSOH notMemSO0 rising from ProcClockOut falling 5 10 TPCHSOL notMemS0 falling from ProcClockOut rising -8 3 TPCLSOL notMemS0 falling from ProcClockOut falling -5 7 All timings in nanoseconds (ns). Table 6.4 Strobe SO to ProcClockOut skew ProcClockOut + \\__ t TPCHSOH ~ TPCHSOL Pr TPCLSOH creas notMemSO \\ Figure 6.7 IMS T805E skew of notMemSO to ProcClockOut {yz Ss: 25/71

6.3 Write cycle

For write cycles the relevant bytes in memory are addressed by the write strobes notMemWrB0-3. If a particular byte is not to be written, then the corresponding data outputs are tristated. For a write cycle pin MemnotWrDO will be low during T1 and T2. Write data is placed on the bus at the start of T3 and removed at the end of T6. If T6 is extended to force the next cycle Tmx (page 18) to start on a rising edge of ProcClockOut, data will be valid during this time also. The transputer has both early and late write cycle modes. For a late write cycle the relevant write strobes notMemWrB0-3 are low during T4 and TS5; for an early write they are also low during T3. Data should be latched into memory on the rising edge of the strobes in both cases, although itis valid until the end of T6. If the strobe duration is insufficient, it may be extended at configuration time by adding extra periods Tm to either or both of Tstates T4 and T5 for both early and late modes. For an early cycle they may also be added to T3. Further extension may be obtained by inserting wait states at the end of T4. If the data hold time is insufficient, extra periods Tm may be added to T6 to extend it. In the write cycle timing diagram ProcClockOut is included as a guide only; itis shown with each Tstate configured to one period Tm. The strobe is inactive during internal memory cycles. T805-20E TdVWrH | Data setup before write d7 d+10 15 TWrHdX | Data hold after write a0 at+5 1,2 TSOLWrL | notMemSO before start of early write b-5 b+5 1,3 notMemS0 before start of late write c5 e+5 1,4 TSOHWHH | End of write from end of notMemSO 5 4 1 TWrLWrH | Early write pulse width d4 d+7 15 Late write pulse width e4 e+7 1,6 All timings in nanoseconds (ns). Notes 1 Timing is for all write strobes notMemWrB0-3. 2 ais T6 where T6 can be from one to five periods Tm in length. 3 bis T2 where T2 can be from one to four periods Tm in length 4 cis total of T2+T3 where T2, T3 can be from one to four periods Tm each in length. 5 dis total of T3+T4+Twait+T5 where T3, T4, T5 can be from one to four periods Tm each in length and Twait may be zero or any number of periods Tm in length. 6 eis total of T4+Twait+T5 where T4, T5 can be from one to four periods Tm each in length and Twait may be zero or any number of periods Tm in length. Table6.5 Write 26/71 SCS")

Tstate | Tt | T2 | 13 | T4 | TS | T6 1 | ProcClockOut Tmx MemnotWrDo ) ss \\——?s8 ( MemnotRtD1 — MemAD2-31 {Address Data) TdVWrH TWrHDX TaVSOU TSOLax TSOLWrl TWrLWrH (Late write) TSOHWrH (CE) TSOLS1L®@ TSOHS1H@) notMemS1 TSOLS1H@) ra ee Figure 6.8 IMS T805E external write cycle

6.4 Wait

Taking MemWait high with the timing shown (figure 6.9) will extend the duration of T4. MemWait is sampled close to the falling edge of ProcClockOut prior to, but not at, the end of T4. By convention, not- MemS4 is used to synchronize wait state insertion. If this or another strobe is used, its delay should be such as to take the strobe low an even number of periods Tm after the start of T1, to coincide with a rising edge of ProcClockOut. MemWait may be kept high indefinitely, although if dynamic memory refresh is used it should not be kept high long enough to interfere with refresh timing. MemWait operates normally during all cycles, including refresh and configuration cycles. It does not affect internal memory access in any way. Ifthe start of T5 would coincide with a falling edge of ProcClockOut an extra wait period Tm (EW) is gener- ated by the EMI to force coincidence with a rising edge. Rising edge coincidence is only forced ifwait states are added, otherwise coincidence with a falling edge is permitted. {yz Ss: 27/71

TPCLWIH | Wait setup 8 1,2,3 TPCLWItL | Wait hold 10 1,2,3 TWILWIH | Delay before re-assertion of Wait 50 Notes 1 ProcClockOut load should not exceed 50pf. 2. If wait period exceeds refresh interval, refresh cycles will be lost. 3 The setup and hold times apply to both the assertion and deassertion of MemWait. Therefore, if MemWait changes within these times relative to the falling edge of ProcClockOut, before the start of T5, metastability may occur. Table 6.6 IMS T805E memory wait me T2 | T3 | T4 Ww TS | Té | 1 | ProcClockOut TPCLWtH P Memwait 7/77 NNN le TWtLWtH MemAD0-31 address )((((((((((((({ (Data )){_ Address notMemRd ee Ge Tstate | T3 | 14 | T4 Ww Ww | EW TS | T6 ProcClockOut MemWait Tstate | T3 | T4 | T4 Ww | EW Ww | EW 15 ProcClockOut \\ MemWait Figure 6.9 IMS T805E memory wait timing 28/71 SCS")

6.5 Memory refresh

The RefreshPending pin is asserted high when the external memory interface is about to perform a re- fresh cycle. It remains high until the refresh cycle is started by the transputer. The minimum time for the RefreshPending pin to be high is for one cycle of ProcClockOut (two periods Tm), when the EMI was. not about to perform a memory read or write. If the EMI was heldin the tristate condition with MemGranted asserted, then RefreshPending will be asserted when the refresh controller in the EMI is ready to perform a refresh. MemReq may be re-asserted any time after the commencement of the refresh cycle. Refresh- Pending changes state near the rising edge of ProcClockOut and can therefore be sampled by the falling edge of ProcClockOut. If no DMA is active then refresh will be performed following the end of the current internal or external memory cycle. If DMA is active the transputer will wait for DMA to terminate before commencing the re- fresh cycle. Unlike MemnotRfD1, RefreshPending is never tristated and can thus be interrogated by the DMA device; the DMA cycle can then be suspended, at the discretion of the DMA device, to allow refresh to take place The simple circuit of Figure 6.10 will suspend DMA requests from the external logic when RefreshPend- ing is asserted, so that a memory refresh cycle can be performed. DMA is restored on completion of the refresh cycle. The transputer will not perform an external memory cycle other than a refresh cycle, using this method, until the requesting device removes its DMA request. DMA Request | > MemReq <| RefreshPending Figure 6.10 IMS T805E refresh with DMA When refresh is disabled no refresh cycles occur. During the post-Reset period eight dummy refresh cycles will occur with the appropriate timing but with no bus or strobe activity. Arefresh cycle uses the same basic external memory timing as a normal external memory cycle, except that it starts two periods Tm before the start of T1. If a refresh cycle is due during an external memory access, it will be delayed until the end of that external cycle. Two extra periods Tm (periods R in the dia- gram) will then be inserted between the end of T6 of the external memory cycle and the start of T1 of the refresh cycle itself. The refresh address and various external strobes become active approximately one period Tm before T1. Bus signals are active until the end of T2, whilst notMemRf remains active until the end of T6. For arefresh cycle, MemnotRfD1 goes low before notMemRf goes low and MemnotWrD0 goes high with the same timing as MemnotRfD1. All the address lines share the same timing, but only MemAD2-11 give the refresh address. MemAD12-30 stay high during the address period, whilst MemAD31 remains low. Refresh cycles generate strobes notMemS0-4 with timing as for a normal external cycle, but notMemRd and notMemWrB0-3 remain high. MemWait operates normally during refresh cycles. Refresh cycles do not interrupt internal memory accesses, although the internal addresses cannot be re- flected on the external bus during refresh. {yz Ss: 29/71 TT 7, See TT ""

Parameter [in [Wor TRELRFH | Refresh pulse width low a-2 a+9 1 TRaVSOL | Refresh address setup before notMemSO b-12 TRfLSOL | Refresh indicator setup before notMemSO b4 b+6 2 Notes 1 ais total Tmx+Tm. 2 bis total T1+Tm where T1 can be from one to four periods Tm in length. Table 6.7 Memory refresh Tstate | T4 | 15 | Te | Tt | T2 | T3 | T4 | 15 | Te | TH | normal cycle Vv MemAD2-31 XX Address X_— Data) Tstate| Te | AR | R | 11 | 12 | 13 | 14] 15 | Te | TH | MemAD2-11 Refresh address notMemSO air: iso] TRILAIH notMemRt — MemnotWrDO MemnotRfD1 cso P MemAD31 Figure 6.11 IMS T805E refresh cycle timing 30/71 SCS") ee £97, STON TT

| a] R| 1] Procciockout — /\\_/\\_/\\ Sf \\S VSN notMemSO \\ MemReq \\ \\ \\ \\ MemGranted \\ — RefreshPending / / \\ notMemRt \\ MemAD2-11 Xx X_ Refresh Address Figure 6.12 IMS T805E refresh pending timing diagram {yz Ss: 31/71

6.6 Direct memory access

Direct memory access (DMA) can be requested at any time by driving the asynchronous MemRegq input high. The transputer samples MemReg just before falling edges of ProcClockOut. To guarantee taking over the bus immediately following either a refresh or external memory cycle, MemReq must be sampled at least four periods Tm before the end of T6. In the absence of an external memory cycle, the address bus is tristated two periods Tm after the ProcClockOut rising edge which follows the sample. Removal of MemReq is sampled just before falling edges of ProcClockOut and MemGranted is removed synchronously with the second falling edge of ProcClockOut which follows the sample. If accurate timing of DMA is required, the setup time relative to ProcClockOut must be met. Further external bus activity, either refresh, external cycles or reflection of internal cycles, willcommence atthe next butone rising edge of ProcClockOut. The strobes (notMemS0-4 and notMemWrB0-3) are left in their inactive states during DMA. DMA cannot interrupt a refresh or external memory cycle, and outstanding refresh cycles will occur before the bus is released to DMA. DMA does not interfere with internal memory cycles in any way, although a program running in internal memory would have to wait for the end of DMA before accessing external memory. DMA cannot access internal memory. If DMA extends longer than one refresh interval (Memory Refresh Config- uration Coding, table 6.11), the DMA user becomes responsible for refresh (see section 6.5). DMA may also inhibit an internally running program from accessing external memory. DMA allows a bootstrap program to be loaded into external RAM ready for execution after reset. If Mem- Req is held high throughout reset, MemGranted will be asserted before the bootstrap sequence begins. MemReq must be high at least one period TDCLDCL of Clockin before Reset. The circuit should be de- signed to ensure correct operation if Reset could interrupt a normal DMA cycle. T805-20E Parameter | Min [Max | TMRHPCL | MemReg setup before ProcClockOut falling 3 14 ns 1 TPCLMGH | MemReg response time 96 110 ns 2 TMRLPCL | Memreq removal before ProcClockOut falling 4 16 TPCLMGL | MemReg end response time 50 66 ns TADZMGH | Bus tristate before MemGranted 0 27 ns TMGLADV | Bus active after end of MemGranted 0 32 ns Notes 1 Setup time need only be met to guarantee sampling on this edge. 2. If an external cycle is active, maximum time could be (1 EMI cycle Tmx)+(1 refresh cycle TRELRfH)+(6 periods Tm). Table 6.8 Memory request 32/71 SCS")

T6 | ProcClockOut TMRHPC! MemReq TPCLMGH TPCLMGL MemGranted MemnotWrDO TADZMGH fr ~ TMGLADV | MomnotRfO1 MemAD2-31 Figure 6.13 IMS T805E memory request timing f Are MemReq | } i MemGranted | | Reset i | j Configuration i Dy TEL OLR | [Bl sequence }}) }) D _Pre— and post-configuration delays (figure 4.3)

1 Internal configuration sequence

E External configuration sequence R Initial refresh sequence B Bootstrap sequence Figure 6.14 IMS T805E DMA sequence at reset MemReq LTITT/ \\ cartaog oyeles interface cycles Read or write} Refresh Read or writj— MemGranted / \\ MemnotRID1 “Memab2 3 MemAD2-31 Figure 6.15 IMS T805E operation of MemReq, MemGranted with external, refresh memory cycles {yz Ss: 33/71

MemReq LTETTLELTL/ \\ [] \\ Internal memory cycles terface activity eS eagos | —{etgne(} —{ [___EMloycle _ | interface activity EMI cycle EMI cycle L_ MemGranted / \\ / \\ MemnotWrDO MemAD2-31 Figure 6.16 IMS T805E operation of MemReq, MemGranted with external, internal memory cycles 34/71 {yz Ses:

6.7. Memory configuration MemConfig is an input pin used to read configuration data when setting external memory interface (EMI) characteristics. It is read by the processor on two occasions after Reset goes low; first to check if one of the preset internal configurations is required, then to determine a possible external configuration.

6.7.1 Internal configuration

The internal configuration scan comprises 64 periods TDCLDCL of Clockin during the internal scan peri- od of 144 Clockin periods. MemnotWrDO0, MemnotRfD1 and MemAD2-32 are all high at the beginning of the scan. Starting with MemnotWrDO, each of these lines goes low successively at intervals of two Clockin periods and stays low until the end of the scan. If one of these lines is connected to MemConfig the presetinternal configuration mode associated with that line will be used as the EMI configuration. The default configuration is that defined in the table for MemAD31; connecting MemConfig to VDD will also produce this default configuration. Note that only 17 of the possible configurations are valid, all others re- main at the default configuration Duration of each Tstate Strobe Write | Refresh | Cycle periods Tm coefficient cycle | interval | time T1 | T2 | T3 | T4 | T5 | T6 type | Clockin | Proc cycles | cycles MemnotWrDO 144 1] 1 1] 1 |30)] 1 3 5 late 72 3 MemnotRfD1 1)2)1)41 1] 2 |30] 1 2 7 late 72 4 MemAD2 1/2/14 ]1)2)31)30) 1 2 7 late 72 5 MemAD3 2/3 )}1/)1/)/2]3 )30) 1 3 8 late 72 6 MemAD4 on 141 3 1 2 3 | early 72 3 MemAD5 1/1 );2)14 2/1 5 1 2 3 | early 72 4 MemAD6 2/1 2/1 3/1 6 1 2 3 early 72 5 MemAD7 2/2);2)1 3/2) 7 1 3 4 | early 72 6 MemAD8 1 1 1 1 1 1 | 30 1 2 3 early { 3 MemAD9 1)1)2)1)2)]1 ]30] 2 5 9 | early { 4 MemAD10 2/2)2/)2/4]2)30] 2 3 8 late 72 7 MemAD11 3/3 )}3)3)/3]3 | 30) 2 4 | 13 | late 72 9 MemAD12 Tyr }2);1)2 41 4 1 2 3 | early 72 4 MemAD13 2/1);2);1/2)2]5 1 2 3 | early 72 5 MemAD14 2/2);2/);1/3/2)]6 1 3 4 | early 72 6 MemAD31 4/4 |41]4 | 414 | 31 | 30 | 30] 18 late 72 12 { Provided for static RAM only. Table 6.9 IMS T805E internal configuration coding {yz Ss: 35/71

notMemso | TL TL notMemso | notMemS1 30 notMemS1 30 a notMems2 1__[ LJ notMems2. LE LL notMems3 = Ll LI notMems3. 21 CL notMemS4 notMemS4 notMemWr iae Ll LJ | notMemwr late LJ L_ MemConfig=MemnotWrDO MemConfig=MemnotRID1 notMemso. L_._ dT” notMemso. LT notMemS1 L__30 notMemS1 L 7 notMemss 3 LJ. notMemS3 rr re notMemS4__ SSS notMems4—— 4] notMemRd OL notMemRd SSCL notMemWr late LJ notMemWr Tey LJ. MemConfig=MemAD3 MemConfig=MemAD7 Figure 6.17 IMS T805E internal configuration Sit —___ 97, S68 Mots

Delay Internal configuration External configuration 64 16 periods Periods of ClockIn periods | Read at Read at of of 7FFFFF6C7FFFFF/0 Clockin| | 1 Clockin ol | / { 0.00:011 5666 a MemnotWrDo pidelaoe B02l4 f | Vy [ i | ee MemnotRfD1 | | | | | | — fo ff MemAD2 i -— {| FL] MemAD3 | | a | in | | { ly | | | | | MemAD31 | | | i | | — i | | MemConfig@) | FLL ET lemConfig | t— MemConfig ® } | / @ Internal configuration: MemConfig connected to MemAD2 ® External configuration: MemConfig connected to inverse of MemAD3 Figure 6.18 IMS T805E internal configuration scan

6.7.2 External configuration

If MemConfig is held low until MemnotWrDO0 goes low the internal configuration is ignoredand an external configuration will be loaded instead. An external configuration scan always follows an internal one, but if an internal configuration occurs any external configuration is ignored. The external configuration scan comprises 36 successive external read cycles, using the default EMI con- figuration preset by MemAD31. However, instead of data being read on the data bus as for a normal read cycle, only a single bit of data is read on MemConfig at each cycle. Addresses put out on the bus for each read cycle are shown intable 6.10, and are designed to address ROM atthe top of the memory map. The table shows the data to be held in ROM; data required at the MemConfig pin is the inverse of this. MemContfig is typically connected via an inverter to MemnotWrDO. Data bit zero of the least significant byte of each ROM word then provides the configuration data stream. By switching MemContfig between various data bus lines up to 32 configurations canbe stored in ROM, one per bit of the databus. MemCon- fig can be permanently connected to a data line or to GND. Connecting MemConfig to GND gives all Tstates configured to four periods; notMemS1 pulse of maximum duration; notMemS2-4 delayed by maximum; refresh interval 72 periods of Clockin; refresh enabled; late write. The external memory configuration table 6.10 shows the contribution of each memory address to the 13 configuration fields. The lowest 12 words (#7FFFFF6C to#7FFFFF98, fields 1 to 6) define the number of extra periods Tm to be added to each Tstate. If field 2 is 3 then three extra periods will be added to T2 to extend it to the maximum of four periods. {yz Ss: 37/71

The next five addresses (field 7) define the duration of notMemS1 and the following fifteen (fields 8 to 10) define the delays before strobes notMemS2-4 become active. The five bits allocated to each strobe allow durations of from 0 to 31 periods Tm, as described in strobes page 18. Addresses #7FFFFFEC to #7FFFFFF4 (fields 11 and 12) define the refresh interval and whether refresh is to be used, whilst the final address (field 13) supplies a high bit to MemContfig if a late write cycle is required. The columns to the right of the coding table show the values of each configuration bit for the four sample external configuration diagrams. Note the inclusion of period E at the end of T6 in some diagrams. This is inserted to bring the start of the next Tstate T1 to coincidewith a rising edge of ProcClockOut (page 20). Wait states W have been added to show the effect of them onstrobe timing; they are not part of a configura- tion. In each case which includes wait states, two wait periods are defined. This shows that if a wait state would cause the start of TS to coincide with a falling edge of ProcClockOut, another period Tm is gener- ated by the EMI to force it to coincide with a rising edge of ProcClockOut. This coincidence is only neces- sary if wait states are added, otherwise coincidence with a falling edge is permitted. Any configuration memory access is only permitted to be extended using wait, up to a total of 14 Clockin periods. 38/71 SCS")

notMemso LL notMemso | FL notMems2—— Lf SSC Moms LLL notMems3 TL notMems3—i“’CL notMemwr ely] EL notMemwr late | MemWait@ Cis Meat LL Example 1 Example 2 Tstate| 1 |2|3,3|4|Ww,W|5| 6,6, E|1 |2 Tstatd 1) 2) 2|3,3|4|wiw/5|6,6,E| 1/2 notMemso |_- L notMemso | EL notMems2_' 0 L___—SsnotMems2-—S—SSCS notMems3 Ss notMemss—S SCL notMems4—2-L__[_notMemsa 3 Ls notMemRd LC” notMemRd =i notMemwr 2] Of notMemwr early MemWait@ [Ls Memwait@ PL Example 3 Example 4 © No wait states inserted ©® One wait state inserted ® Two wait states inserted ® Three wait states inserted Figure 6.19 IMS T805E external configuration

configuration External configuration Delay ir rm i im i mm ma ir rm i m7 ir ms i ms L ir ms Address bt ££ fF £& tor fF w wu we uw w uw uw we uw ROR RR Ry ROR OR OR MemnotWrDO | : : : A ’ : L_— MemnotRiD1 __ : : Sooo : : : iI : : : Meman2 1: ITT TAT oo : fo : MemAD3 _/' : : : L : ' a 4 4 t MemContig @ uJ LL on i Vif notMemRd | L] LU u LI u U Lu LI LI @ MemContfig connected to inverse of MemnotWrDO @) Configuration field 1; 71 configured for 2 periods Tm @) Configuration field 2; T2 configured for 2 periods Tm @ _ Configuration field 10; most significant bit of notMemS4 configured high ® Configuration field 11; refresh interval configured for 36 periods ClockIn ® Configuration field 12; refresh enabled @® Configuration field 13; early write cycle Figure 6.20 IMS T805E external configuration scan 40/71 SCS")

Refresh Interval Field 11 Complete interval inns encoding cycle (ms) 18 3.6 00 0.922 36 7.2 01 1.843 54 10.8 10 2.765 72 14.4 11 3.686 Table 6.11 IMS T805E memory refresh configuration coding Refresh intervals are in periods of ClockIn and Clockin frequency is 5 MHz: Interval = 18 * 200 = 3600 ns Refresh interval is between successive incremental refresh addresses. Complete cycles are shown for 256 row DRAMS. T805-20E TMCVRdH | MemConfig data setup 25 TRdHMCX | MemConfig data hold 0 TSOLRdH | notMemS60 to configuration data read 388 412 Table 6.12 Memory configuration Tstate; T1 | T2 | T3 | T4 ) T5 | T6 1 wa teeth tee bert tre MemnotWrDO (CCC Cat) )) MemnotR{D1 (CCC data) )) MemAD2-31 Cate) notMemSO TSOLRdH notMemRd TMCVRd |< TRGHMCX MemConfig CCC data) > Figure 6.21 IMS T805E external configuration read cycle timing 42/71 SCS")

7 Events

EventReq and EventAck provide an asynchronous handshake interface between an external event and an internal process. When an external event takes EventReg high the external event channel (additional to the external link channels) is made ready to communicate with a process. When both the event channel and the process are ready the processor takes EventAck high and the process, if waiting, is scheduled. EventAck is removed after EventReq goes low. EventWaiting is asserted high by the transputer when a process executes an inputon the event channel; typically with the occam EVENT ? AwNy instruction. It remains high whilst the transputer is waiting for or servicing EventReq and is returned low when EventAck goes high. The EventWaiting pin changes near the falling edge of ProcClockOut and can therefore be sampled by the rising edge of ProcClockOut. The EventWaiting pin can only be asserted by executing an in instruction on the event channel. The EventWaiting pin is not asserted high when an enable channel (enbc) instruction is executed onthe Event channel (during an ALT construct in occam, for example). The EventWaiting pin can be asserted by ex- ecuting the occam input on the event channel (such as Event ? ANY), provided that this does not occur as a guard in analternative process. The EventWaiting pin can not be used to signify that an alternative process (ALT) is waiting on an input from the event channel. EventWaiting allows a process to control external logic; for example, to clock a number of inputs into a memory mapped data latch so that the event request type can be determined. Only one process may use the event channel at any given time. If no process requires an event to occur EventAck will never be taken high. Although EventReq triggers the channel on a transition from low to high, it must not be removed before EventAck is high. EventReq should be low during Reset; if not it will be ignored until it has gone low and returned high. EventAck is taken low when Reset occurs. If the process is a high priority one and no other high priority process is running, typical latency is 19 full processor cycles TCPLCPL (38 Tm), and maximum latency (assuming all memory accesses are internal) is 78 full processor cycles (156 Tm) with the FPU in use, and 58 full processor cycles (116 Tm) with the FPU notin use. Setting a high priority task to wait for an event input allows the user to interrupta transputer program running at low priority. The time taken from asserting EventReq to the execution of the microcode interrupt handler in the CPU is four cycles. The following functions take place during the four cycles: Cycle 1 Sample EventReq at pad on the rising edge of ProcClockOut and synchronise. Cycle 2 Edge detect the synchronised EventReq and form the interrupt request Cycle3 Sample interrupt vector for microcode ROM in the CPU. Cycle 4 Execute the interrupt routine for Event rather than the next instruction. T805-20E Symbol | Parameter [| Min | Max | TVHKH _ | EventReq response 0 TKHVL | EventReq hold 0 TVLKL Delay before removal of EventAck 0 157 TKLVH Delay before re-assertion of EventReq 0 TKHEWL | EventAck to end of EventWaiting 0 Table 7.1 Event {yz Ss: 43/71 TT 7, See oT

EventReq — NN TVHKH me TVLKL TKHVL. TKLVI EventAck TKHEWL EventWaiting t :] \\ Process waiting for Event Event waiting for Process Figure 7.1 IMS T805E event timing 44/71 Th SCS")

8 Links

Four identical INMOS bi-directional serial links provide synchronised communication between processors and with the outside world. Each link comprises an input channel and output channel. A link between two transputers is implemented by connecting a link interface on one transputer to a link interface on the other transputer. Every byte of data sent on a link is acknowledged on the input of the same link, thus each signal line carries both data and control information The quiescent state of a link output is low. Each data byte is transmitted as a high start bit followed by a one bit followed by eight data bits followed by a low stop bit. The least significant bit of data is transmitted first. After transmitting a data byte the sender waits for the acknowledge, which consists of a high start bit followed by a zero bit. The acknowledge signifies both that a process was able to receive the acknowl- edged data byte and that the receiving link is able to receive another byte. The sending link reschedules the sending process only after the acknowledge for the final byte of the message has been received. The IMS T805E links support the standard INMOS communication speed of 10 Mbits/sec. In addition they can be used at 5 or 20 Mbits/sec for 20 MHz and 25 MHz devices, and 20 Mbits/sec for faster devices. Links are not synchronised with ClockIn or ProcClockOut and are insensitive to their phases. Thus links from independently clocked systems may communicate, providing only that the clocks are nominally iden- tical and within specification. Links are TTL compatible and intended to be used in electrically quiet environments, between devices on a single printed circuit board or between two boards via a backplane. Direct connection may be made be- tween devices separated by a distance of less than 300 millimetres. For longer distances a matched 100 ohm transmission line should be used with series matching resistors RM. When this is done the line delay should be less than 0.4 bit time to ensure that the reflection returns before the next data bit is sent. Buffers may be used for very long transmissions. If so, their overall propagation delay should be stable within the skew tolerance of the link, although the absolute value of the delay is immaterial Link speeds can be set by LinkSpecial, LinkOSpecial and Link123Special. The link 0 speed can be set independently. Table 8.1 shows uni-directional and bi-directional data rates in Kbytes/sec for each link speed; LinknSpecial is to be read as LinkOSpecial when selecting link 0 speed and as Link123Special for the others. Data rates are quoted for a transputer using internal memory, and willbe affectedby a factor depending on the number of external memory accesses and the length of the external memory cycle. Link Linkn Kbytes/sec Special | Special | Mbits/sec [ Uni [| Bi 0 0 10 910 1250 0 1 5 450 670 1 0 10 910 1250 1 1 20 1740 2350 Table 8.1 Speed Settings for Transputer Links wWLolte] 3] 4] 5] 6] 7] Pale | Data | | Ack | Figure 8.1 IMS T805E link data and acknowledge packets {yz Ss: 45/71 TT 7, See TT

[Symbot [Parameter «in| Nom [ax [ Unit Notes | TJQr LinkOut rise time 20 ns TJOQF LinkOut fall time 10 ns TJDr Linkin rise time 20 ns TJDF Linkin fall time 20 ns TJQJD Buffered edge delay ns TJBskew | Variation in TJQUD 20 Mbits/s 3 ns 1

10 Mbits/s 10 ns 1

5 Mbits/s 30 ns 1

CLIZ Linkin capacitance @ f=1MHz 7 pF CLL LinkOut load capacitance 50 pF RM Series resistor for 100W transmission line 56 ohms Notes

1 This is the variation in the total delay through buffers, transmission lines, differential receivers

etc., caused by such things as short term variation in supply voltages and differences in delays for rising and falling edges. Table 8.2. Link LinkOut 10% === TJQr. |< TJQf 90% Linkin 10% SS ee TJDr. TJDt Figure 8.2 IMS T805E link timing LinkOut 15V Latest TJQUD Earliest TJQUD TJBskew Figure 8.3 IMS T805E buffered link timing 46/71 {yz Ses:

Transputer family device A LinkOut Linkin Linkin LinkOut Transputer family device B Figure 8.4 Links directly connected Transputer family device A LinkOut — €) Linkin RM Zo=100 ohms = RM Z0=100 ohms Transputer family device B Figure 8.5 Links connected by transmission line Transputer family device A LinkOut > Linkin Linkin <] LinkOut Transputer family device B Figure 8.6 Links connected by buffers {yz Ss: 47/71

9 Electrical specifications

9.1 DC electrical characteristics

[Svweot | PARAWETER [WIN [WAX [UNITS [NOTES] VDD DC supply voltage 0 7.0 V 1,23 Vi, Vo Voltage on input and output pins -0.5 VDD+0.5 Vv 1,23 ii} Input current +25 mA 4 tosc Output short circuit time (one pin) 1 s 2 Ts Storage temperature -65 150 °C 2 TA Ambient temperature under bias -55 125 °C 2 Ppmax Maximum allowable dissipation 2 Ww 2 Notes 1 All voltages are with respect to GND. 2. This is astress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operating sections of this specification is not implied. Stresses greater than those listed may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

3 This device contains circuitry to protect the inputs againstdamage caused by high static voltages

or electrical fields. However, it is advised that normal precautions be taken to avoid application of any voltage higher than the absolute maximum rated voltages to this high impedance circuit. Unused inputs should be tied to an appropriate logic level such as VDD or GND.

4 The input current applies to any input or output pin and applies when the voltage on the pin is

between GND and VDD. Table 9.1 Absolute maximum ratings [SvMBOL[_PARANETER———=«[_~MIN | WAX [UNITS [NOTES] VDD DC supply voltage 4.75 5.25 Vv 1 Vi, Vo Input or output voltage 0 VDD Vv 1,2 CL Load capacitance on any pin 60 pF 3 TA Operating temperature range -55 125 °C Notes 1 All voltages are with respect to GND. 2 Excursions beyond the supplies are permitted but not recommended; see DC characteristics.

3 Excluding LinkOut load capacitance

Table 9.2 Operating conditions

[SyeOL[ PARAMETER [WIN [WAX [UNITS [NOTES] Vin High level input voltage 20 | vdDD+05 | V 1,2 ViL Low level input voltage -0.5 08 Vv 1,2 i Input current @ GND<VI<VDD +10 pA 1,2 VoH Output high voltage @ |OH=2mA VDD-1 v 1,2 VOL Output low voltage @ |OL=4mA 0.4 Vv 1,2 loz Tristate output current @ GND<V0<VDD 410 pA 1,2 Po Power dissipation 1.2 WwW 2,3 CIN Input capacitance @ f=1MHz 7 pF Coz Output capacitance @ f=1MHz 10 pF Notes 1 All voltages are with respect to GND. 2 Parameters for IMS T805E measured at 4.75V<VDD<5.25V and —55°C<TA<125°C. Input clock frequency = 5 MHz. 3 Power dissipation varies with output loading and program execution. Power dissipation for processor operating at 20 MHz. Table 9.3 DC characteristics

9.2 Equivalent circuits

| lou 1.5V D.U.T. 1Mohm 50pF | S (oH) GND Note: This circuit represents the device sinking IOL and sourcing IOH with a 50pF capacitive load. Figure 9.1 Load circuit for AC measurements {yz Ss: 49/71

Outputs 1.5V ov tpLH VDD Outputs 1.5V ov Figure 9.2 AC measurements timing waveforms 9.3. AC timing characteristics [Symbot | Pavaretor «in [Wax [Units [Not TDr Input rising edges 2 20 1,2 TDF Input falling edges 2 20 1,2 Tar Output rising edges 25 1 TOr Output falling edges 15 1 TSOLaxX Address hold after notMemSO a-8 | a+8 3 Notes 1 Non-link pins; see section on links. 2 Allinputs except Clockin; see section on Clockin. 3 ais T2 where T2 can be from one to four periods Tm in length Address lines include MemnotWrDO, MemnotRfD1, MemAD2-31 Table 9.4 Input and output edges 50/71 {yz Ses:

TDF TDr __» Taf TQr —_» Figure 9.3 IMS T805E input and output edge timing TSOLax. 10% a Figure 9.4 IMS T805E tristate timing relative to notMemSO 30 - 30 Rise time

7 Rise time

10 - ee Fall time ns 40 ee She ae ee We — @ TTT tr 40 60 80 100 40 60 80 100 Load capacitance pF Load capacitance pF Link EMI Notes

1 Skewis measured between ProcClockOut with a load of 2 Schottky TTLinputs and 30pF

and notMemSO0 with a load of 2 Schottky TTL inputs and varying capacitance. Figure 9.5 Typical rise/fall times {yz Ss: 51/71

9.4 Power rating

Internal power dissipation (Piyt) of transputer and peripheral chips depends on VDD, as shown in figure 9.6. Pir is substantially independent of temperature. 800 T805-20E 700 rower 600 INT (mW) 500 44 46 48 50 52 54 56 VDD (Volts) Figure 9.6 IMS T805E internal power dissipation vs VDD Total power dissipation (Pp) of the chip is Pp =Pint +Pio where Pig is the power dissipation in the input and output pins; this is application dependent. Internal working temperature Ty of the chip is Ty =Ta +8Ja x Pp where Ta is the external ambient temperature in °C and @ ya is the junction-to-ambient thermal resistance in °C/W. Further information about device thermal characteristics can be found in section 10.3. 52/71 SCS")

10.1 84 pin grid array package 1 2 3 4 5 6 7 8 9 10 A| Refresh] Link és, Link123| Link Link Link | Event Mem Pending] Special| “Qui | Speciol| Ind | out | in2 | Ack Wait Proc] Clockin{ Event | LinkO | Link Link Link | Event not

8 Stes, Asst Sorel) me) mt) a Req Amd Mem

Cop | Cop Link | Link | Mem not c Minus | Plus int | in3_ | Config Mem S— oe WrB1 Proc not | not not D]| Error | Speed | Errorin Index Mem | Mem | Mem geet . Rf S WrB2 > WrBO Disable Boot not | not E} int From | Reset IMS T805E Mem | Mem RAW <> ROM re 84 pin grid array Rd <> $0 <> Proc top view not not F | Speed | Analyse a Pp Mem | Mem see dS $3 > S2 es g| Mem Mem Mem GND pet no jem me 4 AD27 wood, }& St H| Mem Mem Mem | Mem | Mem | Mem | Mem Mem A029 AD23 Ap16 | ADI2 | ADB | AD4 | AD3 | pipy J Mem Mem Mem Mem Mem Mem Mem Mem Mem AD28 | AD24 | AD22 | ADI9 | ADI7 | ADI ADs | ADS | AD2Z x| Mem ] Mem | Mem | Mem | Mem | Mem | Mem Mem | Mem AD26 | AD21 | AD20 | AD18 | ADI5 | ADI4 | ADI1 ADS | AD7 Figure 10.1 IMS T805E 84-pin grid array package pinout {yz Ss: 53/71

PA] O155 | 0147 | O60 T 5.429 | 3.754 | 4.064 | ee ee | PAI] = |OOSOREF[ = [= | 7.270REF[ = J Per — Toosorer| aro [Di] - TO900REF] - J - 22. BREF] — fel — | a.1oopsc] — ft 2540escy SS ee | LL Orzo T6150 TOT SOT 5.502 T5556 |) A | ° ul 4 | al wab 7098765432 1 L COR OMOROMOMOMOROM EN ©©0KOOOOOO|s (CROROM MOM OMOMOMOMOM IG e200 CORON) ~|9e°e @ee6le ®@00 @O0|F eee ©O@lc OR OMOMCROMOMOROMCROM IT ROR OM OMOMOMOROMOROM Et] 110900000000 |x ky7 SGS-THOMSON = Fi STF iiicROELECTROMICS PACKAGE OUTLINE:

84 CERAMIC PIN GRID ARRAY

[PEMMatyald 26 uorsf Aap 99-6602 Figure 10.2 IMS T805E 84-pin grid array package dimensions 54/71 G7 ses: 7/1, SON TT

10.2 100 pin cavity-down ceramic quad flat pack (CQFP) package ° N = 3 3 8 2 2 s s2 8 8 8 3 3 € =o <Om ONO & .8 & S89888 S35 & Ea Los BOSeee <i SoS 28o 28h 2925 § SOE ES AZOuwaZ2worzo00<SsSsSz022= NAA vo <4 95 90 85 BOD NC CapMinus Cr =I MemAD25 NC co E—= MemAD24 Clockin Ho Er MemAD23 EventWaiting SO 5 E> MemAD22 RefreshPending =o 75 =r MemAD21 CopPlus SoS F== MemAD20 LinkSpecial Oo -— VDD LinkOSpecial ——— -—3 MemAD19 ProcClockOut Ct 10 F=™ MemAD18 Link125Special —— 70 1 Mem ADI — E> Mem Py == ee =P inkOutd Cr . . F=5 Mem rkinklnd = 15 100 pin ceramic 65 = VO os inkOut) == E> Mem in SS iow a MEME inkOut2. Co E> Mem LinkIn2. Co op view -F— MemAD10 LinkOut3 Go 20 E— GND Linking Go 60-15 MemAD9 EventAck Cro F—=5 MemAD8 GND cr -— MemAD?7 EventReq =O -—I MemAD6 Ne co 25 -—3 MemAD5S NC cco 55-19 MemAD4 NC cS -—™ MemAD3 NC cr 4 -=™ MemAD2 NC cS E> MemnotRfD1 NC co—130 35 40 45 50 ~—X MemnotWrDO UUUUUUUUUUUUUUUUUUUU DPIVO=ZOSMNOHOTOONTNNGZO gore EEE EEC IST ENS o58 € g ECLD G90 E25 2 2§€ s€Ss SES SO 2 Fao Lote FEES ® £ Oss 2300 OO0C 3 § cee Qeee ee = ec Ce Figure 10.3 IMS T805E 100-pin cavity-down ceramic quad flat pack (CQFP) package pinout {yz Ss: 55/71

pw [ CONTROL DIMENSIONS mm] ALTERNATIVE DIMENSIONS INCH] —____REVISIONS a XT fazt [= sors = =o cToiso | 10.230 0.005 |= T-9.009 | K for }19.800 | 70.000 120-200-0780 10.787 —|-0.795 | oMIN fes[— It 3soner| ~~ T.aBerer | _ ee a ee eee a Al alos 2 | et [ES] 6 (Seating Plane Coplanarity) NOO00NROAQOoOnonAooA ra LUT TT) (54 SS 8 9 8 he = ==— ES Eee = == = | =o nee L Si | S20 == =e = => = S05 = =o = —— = i S09 5 wo ss =o AGAGAPUPAGL AAUP TAHUGLYAPANHG A - QUGUCOUUCUOCOOOCoOoo E A Notes; 1. Moximum leod splacement from ITZ SGS-THOMSON notional centre line = +0.125mm. S/ A MICROELECTRONICS PACKAGE OUTLINE: CAVITY DOWN

100 CERAMIC QUAD FLATPACK

Pe Rakyat si wer'ss[ Aa 99-6804 Figure 10.4 IMS T805E 100-pin cavity-down ceramic quad flat pack (CQFP) package dimensions 56/71 SCS")

10.3 Thermal specification

The IMS T805E is tested to amaximum silicon temperature of 140°C. For operation withinthe given speci- fications, the case temperature should not exceed 135°C. For temperatures above 135°C the operation of the device cannot be guaranteed and reliability may be impaired. For further information on reliability refer to the S€S-THOMSON Microelectronics Quality and Reliability Program. {yz Ss: 57/71

Ordering This section indicates the designation of speed and package selections for the various devices. Speed of Clockin is 5 MHz for all parts. Transputer processor cycle time is nominal; it can be calculated more exactly using the phase lock loop factor PLLx, as detailed in the external memory section. For availability contact your local SGS-THOMSON sales office or authorized distributor. SGS-THOMSON Processor Processor PLLx Package designation clock speed cycle time IMS T805-G20E 20.0 50 40 84 pin ceramic pin grid array IMS T805-F20E 20.0 50 40 100 pin ceramic quad flat pack Table 11.1 IMS T805E ordering details 58/71 SCS")

12 Transputer instruction set summary

12.1 Introduction

The Function Codes table 12.9 (page 63) gives the basic function code set. Where the operand value is less than 16, a single byte encodes the complete instruction. If the operand value is greater than 15, one prefix instruction (pfix) is required for each additional four bits of the operand. If the operand is negative the first prefix instruction will be nfix. Examples of prefix coding are given in table 12.1. Ide #35 is coded as pfix #3 #2 #23 Ide #5 #4 #45 ldc #987 is coded as ptix #9 #2 #29 ptix #8 #2 #28 Ide #7 #4 #47 ldc -31 9 (dc #FFFFFFE1) (Ide #FFE1) t is coded as nfix #1 #6 #61 Ide #1 #4 #41 Table 12.1 prefix coding Tables 12.10 to 12.30 (pages 63-70) give details of the operation codes. Where an operation code is less than 16 (e.g. add: operation code 05), the operation can be stored as a single byte comprising the operate function code F and the operand (5 in the example). Where an operation code is greater than 15 (e.g. /ada: operation code 16), the prefix function code 2 is used to extend the instruction. add (op. code #5) #F5 is coded as opr add #F #F5 ladd (op. code #16) #21F6 is coded as pfix #1 #2 #21 opr #6 #F #F6 Table 12.2 operate coding

12.1.1. Product identity numbers The load device identity (/ddevia) instruction (table 12.10) pushes the device type identity into the A regis- ter. Each productis allocated a unique group of numbers foruse with the /ddevidinstruction. Product identi- ty numbers are given in table 12.3 | Product | Identity numbers IMS T425 0 to 9 inclusive IMS T805 10 to 19 inclusive IMS T225 40 to 49 inclusive IMS T400 50 to 59 inclusive Table 12.3 Product identity numbers

12.1.2 Floating point unit

In the floating point unit (FPU) basic addition, subtraction, multiplication and division operations are per- formed by single instructions. However, certain less frequently used floating point instructions are selected by a value in register A (when allocating registers, this should be taken into account). A /oad constant in- struction /dc is used to load register A; the floating point entry instruction fpentry then uses this value to select the floating point operation. This pair of instructions is termed a selector sequence. In the Floating Point Operation Codes tables 12.23 to 12.29, a selector sequence code is indicated in the Memory Codecolumnby s. The code given inthe Operation Code column is the indirection code, the oper- and for the /dc instruction. The FPU and processor operate concurrently, so the actual throughput of floating point instructions is bet- ter than that implied by simply adding up the instruction times. For full details see Transputer Instruction Set — A Compiler Writer's Guide.

12.1.3 Notation

The Processor Cycles column refers to the number of periods TPCLPCL (refer to ProcClockOut) taken by aninstruction executing in internal memory. The number of cycles is given for the basic operation only; where the memory code for an instruction is two bytes, the time for the prefix function (one cycle) should be added. Some instruction times vary. Where a letter is included in the cycles column itis interpreted from table 12.4. [ Ident | Interpretation b | Bit number of the highest bit set in register A. Bit 0 is the least significant bit. mt_ | Bit number of the highest bit set in the absolute value of register A. Bit 0 is the least signifi- cant bit n Number of places shifted. w___| Number of words in the message. Part words are counted as full words. If the message is not word aligned the number of words is increased to include the part words at either end of the message. pt | Number of words per row. rt Number of rows. + does not apply to IMS T225 Table 12.4 Instruction set interpretation 60/71 SCS")

The DEF column of the tables indicates the descheduling/error features of an instruction as described in table . [ident [Feature i Se section | D The instruction is a descheduling point 12.2 E The instruction will affect the Error flag 12.3 Ft The instruction will affect the FP_Error flag 12.6 t applies to IMS T805 only Table 12.5 Instruction features

12.2 Descheduling points

The instructions in table 12.6 are the only ones at which a process may be descheduled. They are also the ones at which the processor will halt if the Analyse pin is asserted (refer to Analyse section) input message output message output byte output word timer alt wait timer input stop on error alt wait jump loop end end process start process Table 12.6 Descheduling point instructions 12.3. Error instructions The instructions in table 12.7 are the only ones which can affectthe Error flag directly. Note, however, that the floating point unit error flag FP_Erroris set by certain floating point instructions (section 12.6), and that Error can be set from this flag by focheckerror. add add constant subtract multiply fractional multiply + divide remainder long add long subtract long divide set error testerr fpcheckerror check word check subscript from 0 check single check count from 1 + does not apply to IMS T225 + applies to IMS T805 only Table 12.7 Error setting instructions

12.4 Debugging support

Table 12.20 (page 67) contains a number of instructions to facilitate the implementation of breakpoints. These instructions overload the operation of j0. Normally j0 is a no-op which might cause descheduling. SetjObreak enables the breakpointing facilities and causes j0 to act as a breakpointing instruction. When breakpointing is enabled, j0 swaps the current Iptr and Wptr with an Iptr and Wptr stored above MemS- tart. The break instruction does not cause descheduling, and preserves the state of the registers. Itis pos- sible to single step the processor at machine level using these instructions. Refer to Support for debug- ging/breakpointing in transputers (technical note 61) for more detailed information regarding debugger support.

12.5 Block move

The block move instructions (Table 12.21) move any number of bytes from any byte boundary in memory, to any other byte boundary, using the smallest possible number of word read, and wordor part-word writes. Sz SGSs- 61/71

A block move instruction can be interrupted by a high priority process. On interrupt, block move is com- pleted toa wordboundary, independent of start position. When restarting after interrupt, the last word writ- ten is written again. This appears as an unnecessary read and write in the simplest case of word aligned block moves, and may cause problems with FIFOs. This problem can be overcome by incrementing the saved destination (BregIntSaveLoc) and source pointer (CregIntSaveLoc) values by BytesPerWord during the high priority process.

12.6 Floating point errors (IMS T805 only)

The FPU has its own error flag FP_Error. This reflects the state of evaluation within the FPU and is set in circumstances where invalid operations, division by zero or overflow exceptions to the ANSI-IEEE 754-1985 standard would be flagged. FP_Erroris also set if an inputto a floating point operation is infinite or is not a number (NaN). The FP_Errorflag canbe set, tested and cleared without affecting the main Error flag, butcan also set Errorwhen required. Depending on how a program is compiled, it is possible for both unchecked and fully checked floating point arithmetic to be performed. The instructions in table 12.8 are the only ones which can affect the floating point error flag FP_Error. Error is set from this flag by focheckerror if FP_Error is set. fpadd fpsub fpmul fpdiv fpldniaddsn fpldniadddb fpldnimulsn fpldnimuldb fpremfirst fpusqrtfirst fpgt fpeq fpuseterror fpuclearerror fptesterror fpuexpincby32 fpuexpdecby32 fpumulby2 fpudivby2 fpur32tor64 fpur64tor32 fpucki32 fpucki64 fprtoi32 fpuabs fpint Table 12.8 Floating point error setting instructions

12.7 General instructions

The following tables list the complete instruction set which is common to all variants of the transputer. Ex- ceptions are noted at the bottom of each table by f or +. 62/71 SCS")

["esie” | Meas” | Mrwmons | Peyece | Mere Code Code Cycles 0 0x j 3 jump D 1 1X Idip 1 load local pointer 2 2x pfix 1 prefix 3 3X Idnl 2 load non-local 4 4x Ide 1 load constant 5 5X Idnip 1 load non-local pointer 6 6X nfix 1 negative prefix 7 7X Id 2 load local 8 8X adc 1 add constant E 9 9x call 7 call A AX oj 2 conditional jump (not taken) 4 conditional jump (taken) B BX ajw 1 adjust workspace Cc cx eqe 2 equals constant D Dx stl 1 store local E EX stnl 2 store non-local F FX opr - operate Table 12.9 Function codes reeia” | Meas’ | Mrvmons | Meee | Mere Code Code Cycles 2A 22FA | testpranal 2 test processor analyzing 3E 23FE |saveh 4 save high priority queue registers 3D 23FD savel 4 save low priority queue registers 18 21F8 sthf 1 store high priority front pointer 50 25F0 sthb 1 store high priority back pointer 1c 21FC stlf 1 store low priority front pointer 17 21F7 — |stlb 1 store low priority back pointer 54 25F4 sttimer 1 store timer 17C 2127FC_ | Iddevid 1 load device identity 7E 27FE __||dmemstartval 1 load value of memstart address Table 12.10 Processor initialisation operation codes

05 FS add 1 1 add E

09 FQ gt 2 2 greater than

04 F4 diff 1 1 difference

52 25F2 | sum 1 1 sum

08 F8 prod b+4 b+4 | product for positive register A

08 F8 prod m+5 m+5__| product for negative register A

Operation | Memory Processor Code Code Cycles

00 FO rev 1 reverse

3A 23FA xword 4 extend to word 56 25F6 =| cword 5 check word E 1D 21FD xdble 2 extend to double 4c 24FC cesngl 3 check single E 42 24F2 mint 1 minimum integer 5A 25FA | dup 1 duplicate top of stack 79 27F9 —|pop 1 pop processor stack Table 12.13 General operation codes Operation | Memory Processor Cycles Code Code 16-bit 32-bit devices | devices

02 F2 |bsub 1 1 byte subscript

yy FA wsub 2 2 word subscript ait 28F1 | wsubdb 3 3 form double word subscript 34 23F4 =| bent 2 2 byte count 3F 23FF | went 4 5 word count

01 FA Ib 5 5 load byte

3B 23FB |sb 4 4 store byte 4A 24FA |move 2w+8 2w+8 | move message t does not apply to IMS T225 Table 12.14 Indexing/array operation codes Operation | Memory Processor Name Code Code Cycles 22 22F2 Idtimer 2 load timer 2B 22FB tin 30 timer input (time future) D 4 timer input (time past) D 4E 24FE talt 4 timer alt start 51 25F1 taltwt 15 timer alt wait (time past) D 48 timer alt wait (time future) D 47 24F7 enbt 8 enable timer 2E 22FE dist 23 disable timer Table 12.15 Timerhandling operation codes STA SGSs- 65/71

Operation | Memory Processor Name Code Code Cycles

07 F7 in 2w+19 input message D

0B FB out 2w+19 output message D OF FF outword 23 output word D OE FE outbyte 23 output byte D 43 24F3 alt 2 alt start 44 24F4 | altwt 5 alt wait (channel ready) D 17 alt wait (channel not ready) D 45 24F5 altend 4 alt end 49 24F9 enbs 3 enable skip 30 23F0 ‘| diss 4 disable skip 12 21F2 resetch 3 reset channel 48 24F8 | enbe 7 enable channel (ready) 5 enable channel (not ready) 2F 22FF disc 8 disable channel Table 12.16 Input/output operation codes Operation | Memory Processor Name Code Code Cycles 20 22F0 ret 5 return 1B 21FB Idpi 2 load pointer to instruction 3c 23FC | gajw 2 general adjust workspace

06 F6 geall 4 general call

21 22F1 lend 10 loop end (loop) 5 loop end (exit) Table 12.17 Control operation codes Operation | Memory Processor Code Code Cycles 0D FD startp 12 start process

03 F3 endp 13 end process

39 23F9 | runp 10 run process 15 21F5 | stopp i) stop process 1E 21FE Idpri 1 load current priority Table 12.18 Scheduling operation codes 66/71 Th SCS")

Preaia” | Meas” | Mrvmons | Peyecer | Me Code Code Cycles 13 21F3 csub0 2 check subscript from 0 E 4D 24FD cent1 3 check count from 1 E 29 22F9 | testerr 2 test error false and clear (no error) 3 test error false and clear (error) 10 21F0 seterr 1 set error E 55 25F5 stoperr 2 stop on error (no error) D 57 25F7 | clrhalterr 1 clear halt-on-error 58 25F8 | sethalterr 1 set halt-on-error 59 25F9 _|testhalterr 2 test halt-on-error Table 12.19 Error handling operation codes Préaia” | Neos’ | Mrwmons | Pecan | me Code Code Cycles 0 00 jump 0 3 jump 0 (break not enabled) 11 jump 0 (break enabled, high priority) 13 jump 0 (break enabled, low priority) B1 2BF1 break 9 break (high priority) 14 break (low priority) B2 2BF2 | clrjObreak 1 clear jump 0 break enable flag B3 2BF3 setjObreak 1 set jump 0 break enable flag B4 2BF4 | testj0break 2 test jump 0 break enable flag set 7A 27FA timerdisableh 1 disable high priority timer interrupt 7B 27FB timerdisablel 1 disable low priority timer interrupt 7C 27FC timerenableh 6 enable high priority timer interrupt 7D 27FD timerenablel 6 enable low priority timer interrupt Table 12.20 Debugger support codes Prenia” | “ease” | Mmmens | Peeeer | me Code Code Cycles S5Bt 25FB moved2dinit 8 initialise data for 2D block move 5c t 25FC move2dall (2p+23) x r_ | 2D block copy 5Dt 25FD move2dnonzero (2p+23) x r_ | 2D block copy non-zero bytes 5Et 25FE (2p+23) x r_ | 2D block copy zero bytes Table 12.21 2D block move operation codes —— SL, SGS-THOMSON IT

Operation | Memory Processor Name Code Code Cycles 74 27F4 creword 35 calculate crc on word 75 27F5 | crebyte aa) calculate cre on byte 76 27F6 bitent b+2 count bits set in word 77 27F7 bitrevword 36 reverse bits in word 78 27F8 bitrevnbits n+4 reverse bottom n bits in word Table 12.22 CRC and bit operation codes

12.8 Floating point instructions

12.9 Floating point instructions for IMS T805 only

Operation | Memory Processor Code Code Cycles 8E 28FE fpldnisn 2 fp load non-local single 8A 28FA fpldnidb 3 fp load non-local double 86 28F6 —_| fpldnisni 4 fp load non-local indexed single 82 28F2 fpldnidbi 6 fp load non-local indexed double OF 29FF fpldzerosn 2 load zero single AO 2AFO fpldzerodb 2 load zero double AA 2AFA fpldniaddsn 8/11 fp load non local & add single F AG 2AF6 fpldniadddb 9/12 fp load non local & add double F AC 2AFC fpldnimulsn 13/20 fp load non local & multiply single F A8& 2AF8 fpldnimuldb 21/30 fp load non local & multiply double F 88 28F8 —_| fpstnisn 2 fp store non-local single 84 28F4 fpstnidb 3 fp store non-local double 9E 29FE fpstnli32 4 store non-local int32 Table 12.23 Floating point load/store operation codes Operation | Memory Processor Name Code Code Cycles AB 2AFB fpentry 1 floating point unit entry A4 2AF4 fprev 1 fp reverse FX) 2AF3 | fpdup 1 fp duplicate Table 12.24 Floating point general operation codes 68/71 {yz Ses:

Preaia” | Meas’ | Mrvmons | Peyecer | re Code Code Cycles 22 s fpurn 1 set rounding mode to round nearest 06 s fpurz 1 set rounding mode to round zero 04 s fpurp 1 set rounding mode to round positive 05 s fpurm 1 set rounding mode to round minus Table 12.25 Floating point rounding operation codes Preaie” | MéassY | Mrvmons | Peyecer | Mere Code Code Cycles 83 28F3 | fpchkerror 1 check fp error E 9c 29FC | fptesterror 2 test fp error false and clear F 23 s fpuseterror 1 set fp error F 9C s fpuclearerror 1 clear fp error F Table 12.26 Floating point error operation codes Preeie” | NéaseY | Mrwmons | Peyece | Me Code Code Cycles 94 29F4 fpgt 4/6 fp greater than F 95 29F5 | fpeq 3/5 fp equality F 92 29F2 fpordered 3/4 fp orderability 91 29F1 fpnan 2/3 fp NaN 93 29F3 fpnotfinite 2/2 fp not finite OE s fpuchki32 3/4 check in range of type int32 F OF s fpuchki64 3/4 check in range of type int64 F Table 12.27 Floating point comparison operation codes ae =e Code Code Cycles 07 s fpur32tor64 3/4 real32 to real64 F 08 s fpur64tor32 6/9 real64 to real32 F 9D 29FD fprtoi32 7/9 real to int32 F 96 29F6 | fpi32tor32 8/10 int32 to real32 98 29F8 fpi32tor64 8/10 int32 to real64 9A 29FA fpb32tor64 8/8 bit32 to real64 0D s fpunoround 2/2 real64 to real32, no round Al 2AF1 fpint 5/6 round to floating integer F Table 12.28 Floating point conversion operation codes

Operation | Memory rcs” | “cow | wrenone [Shae [Dome tine [oer 87 28F7 fpadd 6/9 6/9 fp add F 89 28F9 fpsub 6/9 6/9 fp subtract F 8B 28FB | fpmul 11/18 18/27 | fp multiply F 8c 28FC fpdiv 16/28 31/43 fp divide F 0B s fpuabs 2/2 2/2 fp absolute F 8F 28FF fpremfirst 36/46 36/46 fp remainder first step F 90 29F0 fpremstep 32/36 32/36 fp remainder iteration 01 s fpusqrtfirst 27/29 27/29 ‘| fp square root first step F 02 s fpusqrtstep 42/42 42/42 fp square root step 03 s fpusqrtlast 8/9 8/9 fp square root end OA s fpuexpinc32 6/9 6/9 multiply by 232 F 09 s fpuexpdec32 6/9 6/9 divide by 252 F 12 s fpumulby2 6/9 6/9 multiply by 2.0 F an s fpudivby2 6/9 6/9 divide by 2.0 F Table 12.29 Floating point arithmetic operation codes

12.10 Floating point instructions for IMS T400 and IMS T425 only

ren” | Mens” | Mwrons | Peycee” | Mme PE Code Code Cycles 73 27F3 | cflerr 3 check floating point error 9c 29FC | fptesterr 1 load value true (FPU not present) 63 26F3 | unpacksn 15 unpack single length fp number 6D 26FD roundsn 12/15 round single length fp number 6C 26FC | postnormsn 5/30 post-normalise correction of single length fp number 71 27F1 Idinf 1 load single length infinity Table 12.30 Floating point support operation codes

Product Information

IMST805-F20E specifications and overview.

Summary

32-bit floating-point transputer - xtended temperature Feb-1997

Description

32-bit floating-point transputer - xtended temperature Feb-1997

Source title IMST805-F20E Datasheet(PDF) - STMicroelectronics

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