IMST801

IMST801 ETC1 | Alldatasheet

Document overview

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Technical content

“deal Preliminary Data a nel

FEATURES

30 MIPS (peak) instruction rate

4.3 Mflops (peak) instruction rate . . . Debugging support Floating Point Unit 64 bit on-chip floating point unit which conforms to 1EEE 754

4 Kbytes on-chip static RAM

120 Mbytes/sec sustained data rate to internal memory bi

4 Gbytes directly addressable external memory System pee it

60 Mbytes/sec sustained data rate to external memory Services [ 32] jocessor

630 ns response to interrupts Four INMOS serial links 10/20 Mbits/sec Bi-directional data rate of 2.4 Mbytes/sec per link High performance graphics support with biock move Link instructions . Services Boot from ROM or communication links Timers Single 5 MHz clock input Link Single +5V +5% power supply (32 | Interface MIL-STD-883C processing will be available 4k bytes Link APPLICATIONS onctnip (22 (eT is | RAM Scientific and mathematical applications Link High speed multi processor systems =a Interface High performance graphics processing Supercomputers i Workstations and workstation clusters [32 | inte Digital signal processing External Accelerator processors Menor [32 Distributed databases interface System simulation Telecommunications Robotics Fault tolerant systems Image processing Pattern recognition Artificial intelligence 42 1441 00 May 1989

1 Introduction

The IMS T801 transputer is a 32 bit CMOS microcomputer with a 64 bit floating point unit and graphics support. It has 4 Kbytes on-chip RAM for high speed processing, a 32 bit non-multiplexed external memory interface and four standard INMOS communication links. The instruction set achieves efficient implementation of high level languages and provides direct support for the OCcam model of concurrency when using either a single transputer or a network. Procedure calls, process switching and typical interrupt latency are sub-microsecond. For convenience of description, the IMS T801 operation is split into the basic blocks shown in figure 1.1. Floating Point Unit vcc GND CapPlus CapMinus - Reset —>) eee ystem ‘sor Analyse services ErrorOut BootFromROM Clockin ProcSpeedSelect0-2 Link LinkSpeed Link LinkInO [2] Interface LinkOutO 4k bytes Link Linkin1 of [ 32 | [=] Interface LinkOut1 On-chip RAM Link Linkin2 32] Interface LinkOut2 ProcClockOut Link Linkin3 notMemWrB0-3 [2] Interface LinkOut3 notMemCE EventReq vel External Interface vert Waiting MemWait KS Mem 0-31 MemReq MemGranted a MemA2-31 Figure 1.1 IMS T801 block diagram The processor speed of a device can be pin-selected in stages from 17.5 MHz up to the maximum allowed for the part. A device running at 30 MHz achieves an instruction throughput of 30 MIPS peak and 15 MIPS. sustained. The extended temperature version of the device complies with MIL-STD-883C. The IMS T801 provides high performance arithmetic and floating point operations. The 64 bit floating point unit provides single and double length operation to the ANSI-IEEE 754-1985 standard for floating point arithmetic. It is able to perform floating point operations concurrently with the processor, sustaining a rate of 2.2 Mflops at a processor speed of 20 MHz and 3.3 Mflops at 30 MHz.

1__ Introduction 129 High performance graphics support is provided by microcoded block move instructions which operate at the speed of memory. The two-dimensional block move instructions provide for contiguous block moves as well as block copying of either non-zero bytes of data only or zero bytes only. Block move instructions can be used to provide graphics operations such as text manipulation, windowing, panning, scrolling and screen updating. Cyclic redundancy checking (CRC) instructions are available for use on arbitrary length serial data streams, to provide error detection where data integrity is critical. Another feature of the IMS T801, useful for pattern recognition, is the facility to count bits set in a word. The IMS T801 can directly access a linear address space of 4 Gbytes. The 32 bit wide memory interface uses non-multiplexed data and address lines and provides a data rate of up to 4 bytes every 66 nanoseconds (60 Mbytes/sec) for a 30 MHz device. System Services include processor reset and bootstrap control, together with facilities for error analysis. The standard INMOS communication links allow networks of transputer family products to be constructed by direct point to point connections with no external logic. The IMS T801 links support the standard operating speed of 10 Mbits/sec, but also operate at 20 Mbits/sec. Each link can transfer data bi-directionally at up to 2.35 Mbytes/sec. The transputer is designed to implement the Occam language, detailed in the OCCaM Reference Manual, but also efficiently supports other languages such as C, Pascal and Fortran. Access to the transputer at machine level is seldom required, but if necessary refer to the Transputer Instruction Set - A Compiler Writers’ Guide, where the IMS T800 instruction set is applicable. This data sheet supplies hardware implementation and characterisation details for the IMS T801. It is intended to be read in conjunction with the Transputer Architecture chapter, which details the architecture of the transputer and gives an overview of occam. The IMS T801 instruction set contains a number of instructions to facilitate the implementation of breakpoints. For further information concerning breakpointing, refer to Support for debugging/breakpointing in transputers (technical note 61). Figure 1.2 shows the internal datapaths for the IMS T801.

130 5 __ IMS T801 engineering data ta Bus beet iS) interlace oe ped (} FP opcode instruction Sireamer

4 Kbyte = Po neduer

RAM : 13 : Be - = O eas oe external a memory a : interface oe —_— an: sc me =—= oo ‘Adoress LAA registers [__data_adcress Figure 1.2 IMS T801 internal datapaths

2 Pin designations

Table 2.1 IMS T801 system services Poin nut JO Function VCC, GND Power supply and return CapPlus, CapMinus External capacitor for internal clock power supply Clockin Input clock ProcSpeedSelect0-2 Processor speed selectors Reset System reset ErrorOut Error indicator Analyse Error analysis BootFromRom Boot from external ROM or from link Table 2.2 IMS T801 external memory interface fo Pin invut PFunction ProcClockOut out Processor clock MemA2-31 out Thirty address lines Data0-31 in/out Thirty-two non-multiplexed data lines notMemWrBo-3 out Four byte-addressing write strobes notMemCE out Chip enable MemWait in Memory cycle extender MemReq in Direct memory access request MemGranted out Direct memory access granted Table 2.3 IMS T801 event po Pin vt PO Punction EventReq in Event request EventAck out Event request acknowledge EventWaiting out Event input requested by software Table 2.4 IMS T801 link fo Pin ist Function LinkIn0-3 in Four serial data input channels LinkOuto-3 out Four serial data output channels LinkSpeed in Select speed for Links 0-3 to 10 or 20 Mbits/sec Signa! names are prefixed by not if they are active low, otherwise they are active high. Pinout details for various packages are given on page 186,

3 Processor

The 32 bit processor contains instruction processing logic, instruction and work pointers, and an operand register. It directly accesses the high speed 4 Kbyte on-chip memory, which can store data or programs. Where larger amounts of memory or programs in ROM are required, the processor has access to 4 Gbytes of memory via the External Memory Interface (EMI).

3.1 Registers

The design of the transputer processor exploits the availability of fast on-chip memory by having only a small number of registers; six registers are used in the execution of a sequential process. The small number of registers, together with the simplicity of the instruction set, enables the processor to have relatively simple (and fast) data-paths and control logic. The six registers are: The workspace pointer which points to an area of store where local variables are kept. The instruction pointer which points to the next instruction to be executed. The operand register which is used in the formation of instruction operands. The A, B and C registers which form an evaluation stack. A, 8 and C are sources and destinations for most arithmetic and logical operations. Loading a value into the stack pushes B into C, and A into B, before loading A. Storing a value from A, pops B into A and C into B. Expressions are evaluated on the evaluation stack, and instructions refer to the stack implicitly. For example, the add instruction adds the top two values in the stack and places the result on the top of the stack. The use of a stack removes the need for instructions to respecify the location of their operands. Statistics gathered from a large number of programs show that three registers provide an effective balance between code compactness and implementation complexity. No hardware mechanism is provided to detect that more than three values have been loaded onto the stack. It is easy for the compiler to ensure that this never happens. Any location in memory can be accessed relative to the workpointer register, enabling the workspace to be of any size. Further register details are given in Transputer Instruction Set - A Compiler Writers’ Guide. Registers Locals Program ee a ee rs ee ee Next Inst | | Figure 3.1 Registers

3 Processor 133

3.2 Instructions

The instruction set has been designed for simple and efficient compilation of high-level languages. Alli in- structions have the same format, designed to give a compact representation of the operations occurring most frequently in programs. Each instruction consists of a single byte divided into two 4-bit parts. The four most significant bits of the byte are a function code and the four least significant bits are a data value. [Function [bata _ 7 43 0 Operand Register [ Figure 3.2 Instruction format

3.2.1 Direct functions

The representation provides for sixteen functions, each with a data value ranging from 0 to 15. Ten of these, shown in table 3.1, are used to encode the most important functions. Table 3.1 Direct functions load constant add constant load local store local load local pointer load non-local store non-local jump conditional jump call The most common operations in a program are the loading of small literal values and the loading and storing of one of a small number of variables. The /oad constant instruction enables values between 0 and 15 to be loaded with a single byte instruction. The /oad local and store local instructions access locations in memory relative to the workspace pointer. The first 16 locations can be accessed using a single byte instruction. The load non-local and store non-local instructions behave similarly, except that they access locations in memory relative to the A register. Compact sequences of these instructions allow efficient access to data structures, and provide for simple implementations of the static links or displays used in the implementation of high level programming languages such as OCCam, C, Fortran, Pascal or ADA.

3.2.2 Prefix functions

Two more function codes allow the operand of any instruction to be extended in length; prefix and negative prefix. All instructions are executed by loading the four data bits into the least significant four bits of the operand register, which is then used as the instruction’s operand. Ail instructions except the prefix instructions end by clearing the operand register, ready for the next instruction. The prefix instruction loads its four data bits into the operand register and then shifts the operand register up four places. The negative prefix instruction ts similar, except that it complements the operand register before shifting it up. Consequently operands can be extended to any length up to the length of the operand register by a sequence of prefix instructions. In particular, operands in the range -256 to 255 can be represented using one prefix instruction.

134 5 __ IMS T801 engineering data The use of prefix instructions has certain beneficial consequences. Firstly, they are decoded and executed in the same way as every other instruction, which simplifies and speeds instruction decoding. Secondly, they simplify language compilation by providing a completely uniform way of allowing any instruction to take an operand of any size. Thirdly, they allow operands to be represented in a form independent of the processor wordiength.

3.2.3 Indirect functions

The remaining function code, operate, causes its operand to be interpreted as an operation on the values held in the evaluation stack. This allows up to 16 such operations to be encoded in a single byte instruction. However, the prefix instructions can be used to extend the operand of an operate instruction just like any other. The instruction representation therefore provides for an indefinite number of operations. Encoding of the indirect functions is chosen so that the most frequently occurring operations are represented without the use of a prefix instruction. These include arithmetic, logical and comparison operations such as add, exclusive or and greater than. Less frequently occurring operations have encodings which require a single prefix operation.

3.2.4 Expression evaluation

Evaluation of expressions sometimes requires use of temporary variables in the workspace, but the number of these can be minimised by careful choice of the evaluation order. Table 3.2 Expression evaluation Program Mnemonic x20 loc 0 stl x X tm #24 Pfix 2 lac 4 stl x Xisy+zZ td y el z ‘ add stl x

3.2.5 Efficiency of encoding

Measurements show that about 70% of executed instructions are encoded in a single byte; that is, without the use of prefix instructions. Many of these instructions, such as load constant and add require just one Processor cycle. The instruction representation gives a more compact representation of high level language programs than more conventional instruction sets. Since a program requires less store to represent it, less of the memory bandwidth is taken up with fetching instructions. Furthermore, as memory is word accessed the processor will receive four instructions for every fetch. Short instructions also improve the effectiveness of instruction pre-fetch, which in turn improves processor Performance. There is an extra word of pre-fetch buffer, so the processor rarely has to wait for an instruction fetch before proceeding. Since the buffer is short, there is little time penalty when a jump instruction causes the buffer contents to be discarded.

3___ Processor 135

3.3 Processes and concurrency

A process starts, performs a number of actions, and then either stops without compieting or terminates complete. Typically, a process is a sequence of instructions. A transputer can run several processes in parallel (concurrently). Processes may be assigned either high or low priority, and there may be any number of each (page 136). The processor has a microcoded scheduler which enables any number of concurrent processes to be exe- cuted together, sharing the processor time. This removes the need for a software kernel. At any time, a concurrent process may be Active - Being executed. - Ona list waiting to be executed. Inactive - Ready to input. - Ready to output. - Waiting until a specified time. The scheduler operates in such a way that inactive processes do not consume any processor time. It allocates @ portion of the processor's time to each process in turn. Active processes waiting to be executed are held in two linked lists of process workspaces, one of high priority processes and one of low priority processes (page 136). Each list is implemented using two registers, one of which points to the first process in the list, the other to the last. In the Linked Process List figure 3.3, process Sis executing and P, Q and R are active, awaiting execution. Only the low priority process queue registers are shown; the high priority process ones perform in a similar manner. Registers Locals Program a ¢ — s a Figure 3.3 Linked process list Table 3.3 Priority queue control registers [Function High Priority | Low Priority Pointer to front of active process list Fptro Fptr1 Pointer to back of active process list Bptro Bptrt Each process runs until it has completed its action, but is descheduled whilst waiting for communication from another process or transputer, or for a time delay to complete. in order for several processes to operate in parallel, a low priority process is only permitted to run for a maximum of two time slices before it is forcibly descheduled at the next descheduling point (page 140). The time slice period is 5120 cycles of the external 5 MHz clock, giving ticks approximately 1 ms apart.

136 5 __IMS T801 engineering data A process can only be descheduled on certain instructions, known as descheduling points. (page 140). As a result, an expression evaluation can be guaranteed to execute without the process being timesliced part way through. Whenever a process is unable to proceed, its instruction pointer is saved in the Process workspace and the next process taken from the list. Process scheduling pointers are updated by instructions which cause scheduling operations, and should not be altered directly. Actual process switch times are less than 1 BS, as little state needs to be saved and it is not necessary to save the evaluation stack on rescheduling. The processor provides a number of special operations to support the process model, including start process and end process. When a main process executes a parallel construct, start process instructions are used to create the necessary additional concurrent processes. A start process instruction creates a new process by adding a new workspace to the end of the scheduling list, enabling the new concurrent process to be executed together with the ones already being executed. When a process is made active it is always added to the end of the list, and thus cannot pre-empt processes already on the same list. The correct termination of a parallel construct is assured by use of the end process instruction. This uses a workspace location as a counter of the parallel construct components which have still to terminate. The Counter is initialised to the number of components before the processes are started. Each component ends with an end process instruction which decrements and tests the counter. For all but the last component, the counter is non zero and the component is descheduled. For the last component, the counter is zero and the main process continues.

3.4 Priority

The IMS T801 supports two levels of priority. Priority 1 (low priority) processes are executed whenever there are no active priority 0 (high priority) processes. High priority processes are expected to execute for a short time. If one or more high priority processes are able to proceed, then one is selected and runs until it has to wait for a communication, a timer input, or until it completes processing. If no process at high priority is able to proceed, but one or more processes at low Priority are able to proceed, then one is selected. Low priority processes are periodically timesliced to provide an even distribution of processor time between computationally intensive tasks. If there are n low priority processes, then the maximum latency from the time at which a low priority process becomes active to the time when it starts processing is 2n-2 timeslice periods. It is then able to execute for between one and two timeslice periods, less any time taken by high priority processes. This assumes that No process monopolises the transputer's time; i.e. it has a distribution of descheduling points (page 140). Each timestice period lasts for 5120 cycles of the external 5 MHz input clock (approximately 1 ms at the standard frequency of § MHz). 'f a high priority process is waiting for an external channel to become ready, and if no other high priority process is active, then the interrupt latency (from when the channel becomes ready to when the Process starts executing) is typically 19 processor cycles, a maximum of 78 cycles (assuming use of on-chip RAM). If the floating point unit is not being used at the time then the maximum interrupt latency is only 58 cycles. To ensure this latency, certain instructions are interruptable.

35 Communications

Communication between processes is achieved by means of channels. Process communication is point-to- point, synchronised and unbuffered. As a result, a channel needs no process queue, no message queue and no message buffer.

3 Processor 137

2 eeeeSSFSSSSSSSSSSSSSSSSSSSSSSSSsSSSSSSSSSSSSSSSSSSSSSSSSSSSS A channel between two processes executing on the same transputer is implemented by a single word in memory; a channel between processes executing on different transputers is implemented by point-to-point links. The processor provides a number of operations to support message passing, the most important being input message and output message. The input message and output message instructions use the address of the channel to determine whether the channel is internal or external. Thus the same instruction sequence can be used for both, allowing a process to be written and compiled without knowledge of where its channels are connected. The process which first becomes ready must wait until the second one is also ready. A process performs an input or output by loading the evaluation stack with a pointer to a message, the address of a channel, and a count of the number of bytes to be transferred, and then executing an input message or output message instruction. Data is transferred if the other process is ready. If the channel is not ready or is an external one the process will deschedule.

3.6 Block move

The block move on the transputer moves any number of bytes from any byte boundary in memory, to any other byte boundary, using the smallest possible number of word read, and word or part-word writes. A block move instruction can be interrupted by a high priority process. On interrupt, block move is completed to a word boundary, independent of start position. When restarting atter interrupt, the last word written is written again. This appears as an unnecessary read and write in the simplest case of word aligned block moves, and may cause problems with FIFOs. This problem can be overcome by incrementing the saved destination (BregintSaveLoc) and source pointer (CregintSaveLoc) values by BytesPerWord during the high priority process.

37 Timers

The transputer has two 32 bit timer clocks which ‘tick’ periodically. The timers provide accurate process timing, allowing processes to deschedule themselves until a specific time. One timer is accessible only to high priority processes and is incremented every microsecond, cycling com- pletely in approximately 4295 seconds. The other is accessible only to low priority processes and is incre- mented every 64 microseconds, giving exactly 15625 ticks in one second. It has a full period of approximately 76 hours. Table 3.4 Timer registers Clocko Current value of high priority (level 0) process clock Clock1 Current value of low priority (level 1) process clock TNextRegO Indicates time of earliest event on high priority (level 0) timer queue TNextRegt Indicates time of earliest event on low priority (!evel 1) timer queue The current value of the processor clock can be read by executing a /oad timer instruction. A process can arrange to perform a timer input, in which case it will become ready to execute after a specified time has been reached. The timer input instruction requires a time to be specified. If this time is in the ‘past’ then the instruction has no effect. If the time is in the ‘future’ then the process is descheduled. When the specified time is reached the process is scheduled again.

4 Instruction set summary

The Function Codes table 4.8 gives the basic function code set (page 133). Where the operand is less than 16, a single byte encodes the complete instruction. If the operand is greater than 15, one prefix instruction (pfix) is required for each additional four bits of the operand. If the operand is negative the first prefix instruction will be nfix. Table 4.1 prefix coding Function Memory Mnemonic code code tdc #3 #4 #43 ldc #35 is coded as pfix #3 #2 #23 Ide #5 #4 #45, lac #987 is coded as ptix #9 #2 #29 fix #8 #2 #28 Idec #7 #4 #47 loc “31 (Ide #FFFFFFE1) is coded as nfix #1 #6 #61 Idec #1 #4 #41 operation code 05), the operation can be stored as a single byte comprising the operate function code F and the operand (5 in the example). Where an operation code is greater than 15 (e.g. /add: operation code 16), the prefix function code 2 is used to extend the instruction. Table 4.2 operate coding Function Memory Mnemonic code code add (op. code #5) #F5 is coded as opr add #F #F5 ladd (op. code #16) #21F6 is coded as ptix #1 #2 #21 opr #6 #F #F6 The load device identity (/ddevid) instruction (table 4.20) pushes the device type identity into the A register. Each product is allocated a unique group of numbers for use with the /ddevid instruction. The product identity numbers for the IMS T801 are 20 to 29 inclusive. In the Floating Point Operation Codes tables 4.22 to 4.28, a selector sequence code (page 149) is indicated in the Memory Code column by s. The code given in the Operation Code column is the indirection code, the operand for the /dc instruction. The FPU and processor operate concurrently, so the actual throughput of floating point instructions is better than that implied by simply adding up the instruction times. For full details see Transputer Instruction Set - A Compiler Writers’ Guide.

140 5 __IMS T801 engineering data The Processor Cycles column refers to the number of periods TPCLPCL taken by an instruction executing in internal memory. The number of cycles is given for the basic operation only; where the memory code for an instruction is two bytes, the time for the prefix function (one cycle) should be added. For a 20 MHz transputer one cycle is 50 ns. Some instruction times vary. Where a letter is included in the cycles column it is interpreted from table 4.3. Table 4.3 Instruction set interpretation [ident | Interpretation Bit number of the highest bit set in register A. Bit 0 is the least significant bit. Bit number of the highest bit set in the absolute value of register A. Bit 0 is the least significant bit. Number of places shifted. Number of words in the message. Part words are counted as full words. If the message is not word aligned the number of words is increased to include the part words at either end of the message. Number of words per row. Number of rows. The DE column of the tables indicates the descheduling/error features of an instruction as described in table 4.4. Table 4.4 instruction features [ident [Feature | Seo page] The instruction is a descheduling point 140 The instruction will affect the Error flag 141, 156 The instruction will affect the FP_Error flag 149, 141

41 Descheduling points

The instructions in table 4.5 are the only ones at which a process may be descheduled (page 135). They are also the ones at which the processor will halt if the Analyse pin is asserted (page 155). Table 4.5 Descheduling point instructions input message output message output byte output word timer alt wait timer input stop on error alt wait jump loop end end process stop process

4 Instruction set summary 144

42 Error instructions

The instructions in table 4.6 are the only ones which can affect the Error flag (page 156) directly. Note, however, that the floating point unit error flag FP_Error is set by certain floating point instructions (page 141), and that Error can be set from this flag by focheckerror. Table 4.6 Error setting instructions add add constant subtract multiply fractional multiply divide remainder long add long subtract long divide set error testerr fpcheckerror check word check subscript from 0 check single check count from 1

43 Debugging support

Table 4.21 contains a number of instructions to facilitate the implementation of breakpoints. These instructions. overload the operation of j0. Normally j0 is a no-op which might cause descheduling. SetjObreak enables the breakpointing facilities and causes j0 to act as a breakpointing instruction. When breakpointing is enabled, JO swaps the current iptr and Wptr with an Iptr and Wptr stored above MemStart. The breakpoint instruction does not cause descheduling, and preserves the state of the registers. It is possible to single step the pro- cessor at machine level using these instructions. Refer to Support for debugging/breakpointing in transputers (technical note 61) for more detailed information regarding debugger support.

4.4 Floating point errors

The instructions in table 4.7 are the only ones which can affect the floating point error flag FP_Error (page 149). Error is set from this flag by focheckerror if FP_Error is set. Table 4.7 Floating point error setting instructions fpadd fpsub fpmul fpdiv fpldniaddsn fpldniadddb fpldnimuisn fpldnimuldb fpremfirst fpusagrifirst fpgt fpeq fpuseterror fpuclearerror fptesterror fpuexpincby32 fpuexpdecby32 fpumulby2 fpudivby2 fpur32tor64 fpur64tor32 fpucki32 fpucki64 fprtoi32 fpuabs fpint

142 5 _IMS T801 engineering data Table 4.8 IMS T801 function codes Code Code Cycles

0 Ox j 3 jump

1 1X Idip 1 load local pointer 2 2x pfix 1 prefix 3 3X Idnt 2 load non-local 4 4x Ide 1 load constant 5 5X Idnip 1 load non-local pointer 6 6X ntix 1 negative prefix 7 7X Idt 2 load local 8 8x adc 1 add constant 9 9x call 7 call A AX cj 2 conditional jump (not taken) “ 4 conditional jump (taken) B BX ajw 1 adjust workspace Cc cx eqc 2 equals constant D Dx stl 1 store local E Ex stnl 2 store non-local F FX opr - operate Table 4.9 IMS T801 arithmetic/logical operation codes Pes EE scene S| ee YE Code Code Cycles 46 24F6 and 1 and 4B 24FB or 1 or 33 23F3 xor 1 exclusive or 32 23F2 not 1 bitwise not 41 24F1 shi n+2 shift left 40 24F0 shr n+2 shift right

05 FS add 1 add

72 27F2 fmul 35 fractional multiply (no rounding) 40 fractional multiply (rounding) 2c 22FC div 39 divide 1F 21FF rem 37 remainder

09 FQ gt 2 greater than

04 F4 diff 1 difference

08 F8 prod be4 product for positive register A

m+5 product for negative register A

4 Instruction set summary 143

Table 4.10 IMS T801 long arithmetic operation codes Code Code Cycles Name 16 21F6 ladd 2 long add 38 23F8 Isub 2 long subtract 37 23F7 lsum 3 long sum 4F 24FF \\diff 3 long diff 31 23F1 Imul 33 long multiply 1A 21FA \\div 35 long divide 36 23F6 Ishi n+3 long shift left (n<32) n-28 long shift left(n>32) 35 23F5 | Ishr n43 long shift right (n<32) 1-28 fong shift right (n>32) 19 21F9 norm n+5 normalise (n<32) n-26 normalise (n>32) 3 normalise (n=64) Table 4.11 IMS T801 general operation codes PSP nee [S| me LE Code Code Cycles

00 FO rev 1 reverse

3A 23FA xword 4 extend to word 56 25F6 cword 5 check word 1D 21FD xdble 2 extend to double 4c 24FC csngl 3 check single 42 24F2 mint 1 minimum integer 5A 25FA dup 1 duplicate top of stack 79 27F9 pop 1 Pop processor stack Table 4.12 IMS T801 2D block move operation codes Code Code Cycles 5B 25FB move2dinit 8 initialise data for 2D block move 5C 25FC move2dall (2p+23)sr | 2D block copy 5D 25FD move2dnonzero (2p+23)«r | 2D block copy non-zero bytes 5E 25FE move2dzero (2p+23)«r | 2D block copy zero bytes Table 4.13 IMS T801 CRC and bit operation codes PS [SE [aoe [S| nee LE Code Code Cycles Name 74 27F4 creword 35 calculate crc on word 75 27F5 | erebyte "1 calculate crc on byte 76 27F6 bitent b+2 count bits set in word 77 27F7 bitrewword 36 reverse bits in word 78 27F8 bitrevnbits n+4 reverse bottom n bits in word

144 5__ IMS T801 engineering data Table 4.14 IMS T801 indexing/array operation codes Operation | Memory Processor Code Code Cycles

02 F2 bsub 1 byte subscript

OA FA wsub 2 word subscript 81 28F1 wsubdb 3 form double word subscript 34 23F4 bent 2 byte count SF 23FF went 5 word count

01 FA Ib 5 load byte

4A 24FA move 2w+8 move message Table 4.15 IMS T801 timer handling operation codes Operation | Memory Processor Code Code Cycles 22 22F2 \\dtimer 2 load timer 2B 22FB tin 30 timer input (time future) i>) 4 timer input (time past) D 4E 24FE talt 4 timer alt start 51 25F1 taltwt 15 timer alt wait (time past) D 48 timer alt wait (time future) D 47 24F7 enbt 8 enable timer 2E 22FE | dist 23 disable timer Table 4.16 IMS T801 input/output operation codes. Operation | Memory Processor Code Code Cycles

07 F7 in 2w+19 input message [°)

0B FB out 2w+id output message 19) OF FF outword 23 output word i?) OE FE outbyte 23 output byte D 43 24F3 alt 2 alt start 44 24F4 altwt 5 alt wait (channel ready) D 17 alt wait (channel not ready) D 45 24F5 altend 4 alt end 49 24F9 enbs 3 enable skip 30 23F0 diss 4 disable skip 12 21F2 resetch 3 reset channel 48 24F8 enbe 7 enable channel (ready) 5 enable channel (not ready) 2F 22FF disc 8 disable channel

4 __ Instruction set summary 145 Table 4.17 IMS T801 contro! operation codes PS eee [S| ae Code Code Cycles 20 22F0 ret return 1B 21FB Idpi load pointer to instruction 3c 23FC gajw general adjust workspace

06 Fé gcall general call

21 22F1 ‘| lend loop end (loop) loop end (exit) Table 4.18 IMS T801 scheduling operation codes PES [oe [Ee] me Code Code Cycles oD FD startp 12 start process

03 F3 endp 13 end process

39 23F9 runp 10 run process 15 21F5 stopp 1 stop process 1E 21FE Idpri 1 load current priority Table 4.19 IMS T801 error handling operation codes Pe eon [EE] me | Code Cycles 13 21F3 csub0 check subscript from 0 4D 24FD centt check count from 1 29 22F9 testerr test error false and clear (no error) test error false and clear (error) 10 21FO | seterr set error 55 25F5 | stoperr stop on error (no error) 57 25F7 clrhalterr clear halt-on-error 58 25F8 sethalterr set halt-on-error 59 25F9 testhalterr test halt-on-error Table 4.20 IMS T801 processor initialisation operation codes eS mee [S| me i Code Code Cycles 2A 22FA testpranal 2 test processor analysing 3E 23FE saveh 4 save high priority queue registers 30 23FD savel 4 save low priority queue registers 18 21F8 sthf 1 store high priority front pointer 50 25F0 sthb 1 store high priority back pointer 16 21FC stif 1 store low priority front pointer 17 21F7 stlb 1 store low priority back pointer 54 25F4 sttimer 1 store timer 176 2127FC | Iddevid 1 load device identity 7E 27FE Idmemstartval 1 load value of memstart address

146 5__IMS T801 engineering data Table 4.21 IMS T801 debugger support codes Pee ES omens [ES] ue Code Code Cycles (‘) 00 jump 0 3 jump 0 (break not enabled) an jump 0 (break enabled, high priority) 13 jump 0 (break enabled, low priority) Bi 2BF1 break 9 break (high priority) 4 break (low priority) B2 2BF2 clrjObreak 1 clear jump 0 break enable flag B3 2BF3 setjObreak 1 set jump 0 break enable flag B4 2BF4 testjObreak 2 test jump 0 break enable flag set 7A 27FA timerdisableh 1 disable high priority timer interrupt 7B 27FB timerdisable! 1 disable low priority timer interrupt 7 27FC timerenableh 6 enable high priority timer interrupt 70 27FD | timerenablel 6 enable low priority timer interrupt Table 4.22 IMS T801 floating point load/store operation codes Bia Code Code Cycles 8E 28FE fpldnisn 2 fp load non-local single 8A 28FA fpldnidb 3 fp load non-local double 86 28F6 fpldnisni 4 fp load non-local indexed single 82 28F2 fpldnidbi 6 fp load non-local indexed double oF 29FF fpldzerosn 2 load zero single AO 2AFO fpldzerodb 2 load zero double AA 2AFA fpldnladdsn 8/11 fp load non local & add single F AGB 2AF6 fpldnladddb gn2 fp load non local & add double F AC 2AFC fpldnimulsn 13/20 fp load non loca! & multiply single F AS 2AF8 fpldnimuldb 21/30 fp load non local & multiply double F 88 28F8 fpstnisn 2 fp store non-local single 84 28F4 fpstnidb 3 fp store non-local double 9E 29FE fpstnli32 4 store non-local int32 Processor cycles are shown as Typical/Maximum cycles. Table 4.23 IMS T801 floating point general operation codes Pe SS [omens [ES] wm ‘i Code Code Cycles AB 2AFB fpentry 1 floating point unit entry A4 2AF4 fprev 1 fp reverse AB 2AF3 fpdup 1 fp duplicate

4 __ Instruction set summary 147 Table 4.24 IMS T801 floating point rounding operation codes Operation | Memory Processor Code Code Cycles 22 fpurn set rounding mode to round nearest 06 fpurz set rounding mode to round zero 04 fpurp set rounding mode to round positive 05 fpurm set rounding mode to round minus Table 4.25 iMS T801 floating point error operation codes Operation | Memory Processor Code Code Cycles 83 28F3 fpchkerror check fp error E 9C 29FC fptesterror test fp error false and clear F 23 8 fpuseterror set fp error F 9C 8 fpuclearerror clear fp error F Table 4.26 IMS T801 floating point comparison operation codes Operation | Memory Processor Code Code Cycles 94 29F4 fpgt 4/6 fp greater than F 95 29F5 fpeq 3/5 fp equality F 92 29F2 fpordered 3/4 fp orderability 1 29F1 = | fpnan 23 fp NaN 93 29F3 fpnotfinite 22 fp not finite OE s fpuchki32 3/4 check in range of type int32 F OF 8 fpuchki64 3/4 check in range of type int64 F Processor cycles are shown as Typical/Maximum cycles. Table 4.27 IMS T801 floating point conversion operation codes Operation Processor Code Cycles Name 07 s fpurs2tor64. 3/4 real32 to real64 08 s fpur64tor32 6/9 real64 to real32 9D 29FD fprtoi32 79 real to int32 96 29F6 fpi32tor32 8/10 int32 to real32 98 29F8 fpi32tor64 8/10 int32 to real64 9A 29FA fpb32toré4 8/8 bit32 to real64 oD 8 fpunoround 2/2 real64 to real32, no round Al 2AF1 fpint 5/6 round to floating integer Processor cycles are shown as Typical/Maximum cycles.

148 5__IMS T801 engineering data Table 4.28 IMS T801 floating point arithmetic operation codes Operation Code Code | Single [ Double | H 87 28F7 fpadd 6/9 69a fp add F 89 28F9 fpsub 69 69 fp subtract F 8B 28FB fpmui 118 18/27 | fp multiply F 8c 28FC fpdiv 16/28 31/43 | fp divide F 0B s fpuabs 2/2 22 fp absolute F 8F 28FF fpremfirst 36/46 36/46 | fp remainder first step F 90 29F0 fpremstep 32/36 32/36 | fp remainder iteration 01 s fpusqrttirst 27/29 27/29 | fp square root first step F 02 s fpusqrtstep 42/42 42/42 | fp square root step 03 8 fpusqrtiast 8/9 8/9 | fp square root end OA s fpuexpinc32 6/9 6/9 multiply by 252 F og 8 fpuexpdec32 6/9 6/9 divide by 252 F 12 8 fpumulby2 6/9 6/9 | multiply by 2.0 F W 8 fpudivby2 6/9 6/9 divide by 2.0 F Processor cycles are shown as Typical/Maximum cycles.

5 Floating point unit

The 64 bit FPU provides single and double length arithmetic to floating point standard ANSI-IEEE 754-1985. It is able to perform floating point arithmetic concurrently with the central processor unit (CPU), sustaining 3.3 Mflops on a 30 MHz device. All data communication between memory and the FPU occurs under control of the CPU. The FPU consists of a microcoded computing engine with a three deep floating point evaluation stack for manipulation of floating point numbers. These stack registers are FA, FB and FC, each of which can hold either 32 bit or 64 bit data; an associated flag, set when a floating point value is loaded, indicates which. The stack behaves in a similar manner to the CPU stack (page 132). As with the CPU stack, the FPU stack is not saved when rescheduling (page 135) occurs. The FPU can be used in both low and high priority processes. When a high priority process interrupts a low priority one the FPU state is saved inside the FPU. The CPU will service the interrupt immediately on completing its current operation. The high priority process will not start, however, before the FPU has completed its current operation. Points in an instruction stream where data need to be transferred to or from the FPU are called synchronisation points. At a synchronisation point the first processing unit to become ready will wait until the other is ready. The data transfer will then occur and both processors will proceed concurrently again. In order to make full use of concurrency, floating point data source and destination addresses can be calculated by the CPU whilst the FPU is performing operations on a previous set of data. Device performance is thus optimised by minimising the CPU and FPU idle times. The FPU has been designed to operate on both single length (32 bit) and double length (64 bit) floating point numbers, and returns results which fully conform to the ANSI-IEEE 754-1985 floating point arithmetic standard. Denormalised numbers are fully supported in the hardware. All rounding modes defined by the standard are implemented, with the defauit being round to nearest. The basic addition, subtraction, multiplication and division operations are performed by single instructions. However, certain less frequently used floating point instructions are selected by a value in register A (when allocating registers, this should be taken into account). A /oad constant instruction /dc is used to load register A; the floating point entry instruction fpentry then uses this value to select the floating point operation. This pair of instructions is termed a selector sequence. Names of operations which use fpentry begin with fpu. A typical usage, returning the absolute value of a floating point number, would be dc fpuabs; fpentry; Since the indirection code for fouabs is OB, it would be encoded as Table 5.1 fpentry coding Function Memory Mnemonic code code loc fpuabs #4 #4B fpentry (op. code #AB) #2AFB is coded as pfix #A #2 #2A opr #B #F #FB

150 5__IMS T801 engineering data SS eeeeeeeSSSSSSSSSSSSSSSSSSCO SIMS 801 engineering data The remainder and square root instructions take considerably longer than other instructions to complete. In order to minimise the interrupt latency period of the transputer they are split up to form instruction sequences. As an example, the instruction sequence for a single length square root is fpusqnifirst; fpusqrtstep; fpusqrtstep; — fpusqrtiast; The FPU has its own error flag FP.Error. This reflects the state of evaluation within the FPU and is set in circumstances where invalid operations, division by zero or overflow exceptions to the ANSI-IEEE 754-1985 standard would be flagged (page 141). FP_Erroris also set if an input to a floating point operation is infinite or is not a number (NaN). The FP_Error flag can be set, tested and cleared without affecting the main Error flag, but can also set Error when required (page 141). Depending on how a program is compiled, it is possible for both unchecked and fully checked floating point arithmetic to be performed. Further details on the operation of the FPU can be found in Transputer Instruction Set - A Compiler Writers’ Guide. Table 5.2 Typical floating point operation times for IMS T801 7801-20 1801-30 Operation [Single length [ Double length [ Single length | Double length add 350 ns 350 ns 233 ns 233 ns subtract 350 ns 350 ns 233 ns 233 ns multiply 550 ns 1000 ns 367 ns 667 ns divide 850 ns 1600 ns 567 ns 1067 ns Timing is for operations where both operands are normalised fp numbers.

6 System services

System services include ail the necessary logic to initialise and sustain operation of the device. They also include error handling and analysis facilities.

6.1 Power

Power is supplied to the device via the VCC and GND pins. The supply must be decoupled close to the chip by at least one 100 nF low inductance (e.g. ceramic) capacitor between VCC and GND. Four layer boards are recommended; if two layer boards are used, extra care should be taken in decoupling. Input voltages must not exceed specification with respect to VCC and GND, even during power-up and power- down ramping, otherwise /atchup can occur. CMOS devices can be permanently damaged by excessive periods of latchup.

6.2 CapPlus, CapMinus

The internally derived power supply for internal clocks requires an external low leakage, low inductance 1F capacitor to be connected between CapPlus and CapMinus. A ceramic capacitor is preferred, with an impedance less than 3 Ohms between 100 KHz and 10 MHz. If a polarised capacitor is used the negative terminal should be connected to CapMinus. Total PCB track length should be less than 50 mm. The connections must not touch power supplies or other noise sources. vec CapPlus P.C.B. track Phase-locked f capacitor loops tye (] CapMinus P.C.B. track GND. Figure 6.1 Recommended PLL decoupling

6.3 Clockin

Transputer family components use a standard clock frequency, supplied by the user on the Clockin input. The nominal frequency of this clock for all transputer family components is 5 MHz, regardless of device type, transputer word length or processor cycle time. High frequency internal clocks are derived from Clockin, simplifying system design and avoiding problems of distributing high speed clocks externally. Anumber of transputer devices may be connected to a common clock, or may have individual clocks providing each one meets the specified stability criteria. In a multi-clock system the relative phasing of Clockin clocks is not important, due to the asynchronous nature of the links. Mark/space ratio is unimportant provided the specified limits of Clockin pulse widths are met. Oscillator stability is important. ClockIn must be derived from a crystal oscillator; RC oscillators are not sufficiently stable. ClockIn must not be distributed through a long chain of buffers. Clock edges must be monotonic and remain within the specified voltage and time limits.

152 5 _ IMS T801 engineering data Table 6.1 Input clock SYMBOL PARAMETER [| MIN [ NOM | MAX | UNITS | NOTE TOCLDCH | Clockin pulse width low 40 ns 1 TDCHDCL | Clockin pulse width high 40 ns 1 TDCLDCL | Clockin period ns 1,2,4 TOCerror | Clockin timing error +0.5 ns 13 TDC1DC2 | Difterence in Clockin for 2 linked devices 400 ppm 14 TDCr Clockin rise time 10 ns 15 TOCt Clockin fall time 8 ns 1,5 Notes 1 These parameters are not tested. 2 Measured between corresponding points on consecutive falling edges. 3 Variation of individual falling edges from their nominal times. 4 This value allows the use of 200 ppm crystal oscillators for two devices connected together by a link. 5 Clock transitions must be monotonic within the range VIH to VIL (table 11.3). TOCerror TDCerror TDCerror TDCerror 20v-_— Ne SIN J- - - — v= = = NABAS == (SSE EE TDCLDCH TDCHDCL TDOCLDCL TDCf TDCr Figure 6.2 Clockin timing

6.4 ProcSpeedSelect0-2

Processor speed of the IMS T801 is variable in discrete Steps. The desired speed can be selected, up to the maximum rated for a particular component, by the three speed select lines ProcSpeedSelect0-2. The pins are tied high or low, according to table 6.2, for the various speeds. The frequency of Clockin for the speeds given in table 6.2 is 5 MHz. There are six valid speed select combinations.

6 __ System services 153 Table 6.2 Processor speed selection Proc Proc Proc Processor | Processor Speed Speed Speed Clock Cycle Select2 Select1 SelectO0 | Speed MHz Time ns (°) 0 0 20.0 50.0 0 0 1 225 44.4 0 1 ie) 25.0 40.0 () 1 1 30.0 33.3 1 0 0 35.0 28.6 1 to) 1 Invalid 1 1 0 175 57.1 1 1 1 Invalid Note: Inclusion of a speed selection in this table does not imply immediate availability.

65 Reset

Reset can go high with VCC, but must at no time exceed the maximum specified voltage for VIH. After VCC is valid ClockIn should be running for a minimum period TDCVRL before the end of Reset. The failing edge of Reset initialises the transputer and starts the bootstrap routine. Link outputs are forced low during reset; link inputs and EventReq should be held low. Memory request (DMA) must not occur whilst Reset is high but can occur before bootstrap (page 167). If BootFromRom is high, bootstrapping will take place immediately after Reset goes low, using data from external memory; otherwise the transputer will await an input from any link. The processor will be in the low priority state.

6.6 Bootstrap

The transputer can be bootstrapped either from a link or from external ROM. To facilitate debugging, Boot- FromRom may be dynamically changed but must obey the specified timing restrictions. It is sampled once only by the transputer, before the first instruction is executed after Reset is taken low. If BootFromRom is connected high (e.g. to VCC) the transputer starts to execute code from the top two bytes in externa! memory, at address #7FFFFFFE. This location should contain a backward jump to a program in ROM. Following this access, BootFromRom may be taken low if required. The processor is in the low priority State, and the W register points to MemStart (page 157).

6 System services 155

It BootFromRom is connected low (e.g. to GND) the transputer will wait for the first bootstrap message to arrive on any one of its links. The transputer is ready to receive the first byte on a link within two processor cycles TPCLPCL after Reset goes low. If the first byte received (the control byte) is greater than 1 it is taken as the quantity of bytes to be input. The following bytes, to that quantity, are then placed in internal memory starting at location MemStart. Following reception of the last byte the transputer will start executing code at MemStart as a low priority process. BootFromRom may be taken high after reception of the last byte, if required. The memory space immediately above the loaded code is used as work space. Messages arriving on other links after the control byte has been received and on the bootstrapping link after the last bootstrap byte will be retained until a process inputs from them.

67 Peek and poke

Any location in internal or external memory can be interrogated and altered when the transputer is waiting for a bootstrap from link. If the control byte is 0 then eight more bytes are expected on the same link. The first four byte word is taken as an internal or external memory address at which to poke (write) the second four byte word. If the control byte is 1 the next four bytes are used as the address from which to peek (read) a word of data; the word is sent down the output channel of the same link. Following such a peek or poke, the transputer returns to its previously held state. Any number of accesses may be made in this way until the control byte is greater than 1, when the transputer will commence reading its bootstrap program. Any link can be used, but addresses and data must be transmitted via the same link as the control byte.

6.8 Analyse

if Analyse is taken high when the transputer is running, the transputer will halt at the next descheduling point (page 140). From Analyse being asserted, the processor will halt within three time slice periods plus the time taken for any high priority process to complete. As much of the transputer status is maintained as is necessary to permit analysis of the halted machine, Processor flags Error and HaltOnError are not altered at teset, whether Analyse is asserted or not. Memory refresh continues. Input links will continue with outstanding transfers. Output links will not make another access to memory for data but will transmit only those bytes already in the link buffer. Providing there is no delay in link acknowledgement, the links should be inactive within a few microseconds of the transputer halting. Reset should not be asserted before the transputer has halted and link transfers have ceased. When Reset is taken low whilst Analyse is high, neither the memory configuration sequence nor the block of eight refresh cycles will occur; the previous memory configuration will be used for any external memory accesses. If BootFromRom is high the transputer will bootstrap as soon as Analyse is taken low, otherwise it will await a control byte on any link. If Analyse is taken low without Reset going high the transputer state and operation are undefined. After the end of a valid Analyse sequence the registers have the values given in table 6.4. Table 6.4 Register values after Analyse U MemStart if bootstrapping from a link, or the external memory bootstrap address if bootstrapping from ROM. W MemStart if bootstrapping from ROM, or the address of the first free word after the bootstrap program if bootstrapping from tink. A The value of / when the processor halted. B The value of Wwhen the processor halted, together with the priority of the process when the transputer was halted (i.e. the W descriptor). c The ID of the bootstrapping {ink if bootstrapping from link.

156 5 __IMS T801 engineering data

6.9 ErrorOut

The ErrorOut pin is connected directly to the internal Error flag and follows the state of that flag. If ErrorOut is high it indicates an error in one of the processes caused, for example, by arithmetic overfiow, divide by Zero, array bounds violation or software setting the flag directly (page 141). It can also be set from the floating point unit under certain circumstances (page 141, 149). Once set, the Error flag is only cleared by executing the instruction testerr. The error is not cleared by processor reset, in order that analysis can identify any errant transputer (page 155). A process can be programmed to stop if the Error flag is set; it cannot then transmit erroneous data to other Processes, but processes which do not require that data can still be scheduled. Eventually all processes which rely, directly or indirectly, on data from the process in error will stop through lack of data. By setting the HaltOnError tlag the transputer itself can be programmed to halt if Error becomes set. If Error becomes set after HaltOnErrorhas been set, all processes on that transputer will cease but will not necessarily cause other transputers in a network to halt. Setting HaltOnError after Error will not cause the transputer to halt; this allows the processor reset and analyse facilities to function with the flags in indeterminate states. An alternative method of error handling is to have the errant process or transputer cause alll transputers to halt. This can be done by applying the ErrorOut output signal of the errant transputer to the EventReq pin of a suitably programmed master transputer. Since the process state is preserved when stopped by an error, the master transputer can then use the analyse function to debug the fault. When using such a circuit, note that the Error flag is in an indeterminate state on power up; the circuit and software should be designed with this in mind. Error checks can be removed completely to optimise the performance of a proven program; any unexpected error then occurring will have an arbitrary undefined effect. If a high priority process pre-empts a low Priority one, status of the Error and HaltOnError flags is saved for the duration of the high priority process and restored at the conclusion of it. Status of the Error flag is transmitted to the high priority process but the HaltOnError flag is cleared before the process starts. Either flag can be altered in the process without upsetting the error status of any complex operation being carried out by the pre-empted low priority process. In the event of a transputer halting because of HaltOnError, the links will finish outstanding transfers before shutting down. If Analyse is asserted then all inputs continue but outputs will not make another access to memory for data. Memory refresh will continue to take place. Atter halting due to the Error flag changing from 0 to 1 whilst HaltOnError is set, register / points two bytes past the instruction which set Error. After halting due to the Analyse pin being taken high, register / points one byte past the instruction being executed. In both cases / will be copied to register A. Analyse Slave Slave master [ay baton [TT ranger 1 Transputer Reset ErrorOut[0] ErrorOut[1] Event ' Slave Slave (transputer links not shown) Transputer Transputer 2 3 ErrorOut[2] ErrorOut[3) Figure 6.5 Error handling in a multi-transputer system

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7 Memory

The IMS T801 can access 4 Gbytes of external memory space. The IMS T801 also has 4 Kbytes of fast interna! static memory for high rates of data throughput. Each internal memory access takes one processor cycle ProcClockOut (page 162). Internal and external memory are part of the same linear address space. IMS T801 memory is byte addressed, with words aligned on four-byte boundaries. The least significant byte of a word is the lowest addressed byte. The bits in a byte are numbered 0 to 7, with bit 0 the least significant. The bytes are numbered from 0, with byte 0 the least significant. In general, wherever a value Is treated as a number of component values, the components are numbered in order of increasing numerical significance, with the least significant component numbered 0. Where values are stored in memory, the least significant component value is stored at the lowest (most negative) address. Internal memory starts at the most negative address #80000000 and extends to #80000FFF. User memory begins at #80000070; this location is given the name MemStart. The reserved area of internal memory below MemStart is used to implement link and event channels. Two words of memory are reserved for timer use, TPtrLoc0 for high priority processes and TPtrLoc! for low priority processes. They either indicate the relevant priority timer is not in use or point to the first process on the timer queue at that priority level. Values of certain processor registers for the current low priority process are saved in the reserved /ntSaveLoc locations when a high priority process pre-empts a low priority one. Other locations are reserved for extended features such as block moves and floating point operations. External memory space starts at #80001000 and extends up through #00000000 to #7FFFFFFF. ROM boot- strapping code must be in the most positive address space, starting at #7FFFFFFE. Address space immedi- ately below this is conventionally used for ROM based code.

158 5__ IMS T801 engineering data hi__Machine map _lo Byte address Word offsets occam map [Reset inst [| #7FFFFFFE #0 ! | #80001000 — Start of external memory — #0400 #80000070 MemStart MemStart #1C Extended functions | 80000048 #80000044 #8000040 #8000003C #80000038 #8000034 #8000030 #8000002 we0000028 |, #0000024 [Event #80000020 #08 #8000001C #07 #8000018 #06 #80000014 #05 #8000010 #04 #8000000C #03 #80000008 #02 #8000004 #01 #80000000 (Base of memory) #00 Figure 7.1 IMS T801 memory map Notes 1 These locations are used as auxiliary processor registers and should not be manipulated by the user. Like processor registers, their contents may be useful for implementing debugging tools (Analyse, page 155). For details see Transputer Instruction Set - A Compiler Writers’ Guide.

8 External memory interface

The IMS T801 External Memory Interface (EMI) allows access to a 32 bit address space via separate address and data buses. The external memory cycle is divided into four Tstates with the following functions: T1 Address and control setup time. T2 Data setup time. T3 Data read/write. T4 Data and address hold after access. Each Tstate is half a processor cycle TPCLPCL long. An external memory cycle is always a complete number of cycles TPCLPCL in length. The start of T1 always coincides with a rising edge of ProcClockOut. T2 can be extended indefinitely by adding externally generated wait states of one complete processor cycle each. During an internal memory access cycle the external memory interface address bus MemA2-31 reflects the word address used to access internal RAM, notMemWrBO-3 and notMemCE are inactive and the data bus MemD0-31 is tristated. This is true unless and until a DMA (memory request) activity takes place, when the MemA2-31, MemD0-31, notMemCE and notMemWrBO0-3 signals will be placed in a high impedance state by the transputer. Bus activity is not adequate to trace the internal operation of the transputer in full, but may be used for hardware debugging in conjuction with peek and poke (page 155). ProcClockOut ~—/*4 VY NY Vn YY NN notMemWrB0-3 Y Write Read Read X notMemCE y < MemA2-31 Memoo-s1 | > Figure 8.1 IMS T801 bus activity for 3 internal memory cycles

160 5 __ IMS T801 engineering data

81 Pin functions

8.1.1 MemA2-31

External memory addresses are output on a non-multiplexed 30 bit bus. The address is valid at the start of T1 and remains so until the end of T4.

8.4.2 MemD0-31

The non-multiplexed data bus is 32 bits wide. The data bus is high impedance except when the transputer is writing data. If only one byte is being written, the unused 24 bits of the bus are high impedance at that time. If the data setup time for read or write is too short it can be extended by inserting wait states at the end of T2. 8.1.3 notMemCE The active low signal notMemCE is used to enable external memory on both read and write cycles. Table 8.1 notMemCE to ProcClockOut skew 801-30 801-25 7801-20 SYMBOL | PARAMETER [wins [ Max | win [ MAX | MIN [ MAX | NOTE TPCHEL | notMemCE falling 8 12 10 1 from ProcClockOut rising TPCLEH |} ProcClockOut falling 8 12 10 1 to notMemCE rising Notes. 1 Units are ns. ProcClockOut TPCHEL TPCLEH notMemCE f } Figure 8.2 IMS T801 skew of notMemCE to ProcClockOut

8 External memory interface 161

(6 MHz) CapMinus eno © SS o LinkOIn ErrorOut 100k [] notMemCE GND notMemWrBO | Out _ notMemWrB1 Link 56R notMemWrB2 tee Out ‘As LinkO notMemWrB3 MemD0-7 u IMs _— Link2In T801 MemD8-15 L | tu a Link2Out _ a= 56R MemD16-23 : P Link3in |_-t—} Link3Out MemD24-31 Bakes Reset static Analyse RAM MemWait MemGranted MemReq il Figure 8.3 IMS T801 static RAM application 8.1.4 notMemWrB0-3 Four write enables notMemWrB0-3 are provided, one to write each byte of a word. When writing a word, the four appropriate write enables are asserted; when writing a byte only the appropriate write enable is asserted.

8.1.5 MemWait

Wait states can be selected by taking MemWait high. Externally generated wait states of one complete processor cycle can be added to extend the duration of T2 indefinitely,

8.16 MemReq, MemGranted

Direct memory access (DMA) can be requested at any time by driving the asynchronous MemReg input high. MemGranted follows the timing of the bus being tristated and can be used to signal to the device requesting the DMA that it has control of the bus. Note that MemGranted changes on the falling edge of ProcClockOut and can therefore be sampled to establish control of the bus on the rising edge of ProcClockOut.

162 5__IMS T801 engineering data

8.1.7 ProcClockOut

This clock is derived from the internal processor clock, which is in turn derived from Clockin. Its period is equal to one internal microcode cycle time, and can be derived from the formula TPCLPCL = TDCLDCL / PLLx where TPCLPCL is the ProcClockOut Period, TDCLDCL is the ClockIn Period and PLLx is the phase lock loop factor for the relevant speed part, obtained from the ordering details (Ordering section). Edges of the various external memory strobes are synchronised by, but do not all coincide with, rising or falling edges of ProcClockOut. Table 8.2 ProcClockOut SYMBOL PARAMETER | MIN] NOM [ MAX | UNITS | NOTE | TPCLPCL | ProcClockOut period a1 a+! ns 1 TPCHPCL | ProcClockOut pulse width high b-2.5 b+2.5 ns 2 TPCLPCH | ProcClockOut pulse width low ns 3 TPCstab | ProcClockOut stabili 4 % 4 Notes 1 ais TOCLDCL/PLLx. 2 b is 0.5+TPCLPCL (half the processor clock period). 3 ¢ is TPCLPCL-TPCHPCL. 4 Stability is the variation of cycle periods between two consecutive cycles, measured at corresponding points on the cycles. STeerPcH |, _TecHec. TPCLPCL Figure 8.4 IMS T801 ProcClockOut timing

8__External memory interface 163

8.2 Read cycle

Read cycle data may be set up on the bus at any time after the start of T1, but must be valid when the IMS T801 reads it during T4. Data can be removed any time after the rising edge of notMemCE, but must be off the bus no later than the middle of T1, which allows for bus turn-around time before the data lines are driven at the start of T2 in a processor write cycle. Byte addressing is carried out internally by the IMS T801 for read cycles. Table 8.3 Read cycle 7801-30 801-25 7801-20 SYMBOL | PARAMETER [Min | MAX | MIN | MAX | MIN | MAX | TAVEL Address valid before chip enable low 6 8 10 4,3 TELEH Chip enable low 48 53 58 64 72 78 4,3 TEHEL Delay before chip enable re-assertion | 14 16 20 1,2,3 TEHAX Address hold after chip enable high 6 8 10 1,3 TELDrV | Data valid from chip enable low 0 34 0 40 0 47 3 TAVDrV Data valid from address valid 0 40 0 48 0 57 3 TOrVEH | Data setup before chip enable high 14 18 25 3 TEHDrZ | Data hold after chip enable high 0 14 0 16 0 20 3 TWEHEL | Write enable setup before chip enable | 14 16 20 3,4 low TPCHEL | ProcClockOut high to chip enable low | 6 8 10 1,3 Notes. 1 This parameter is common to read and write cycles and to byte-wide memory accesses. 2 These values assume back-to-back external memory accesses. 3 Units are ns. 4 Timing is for all four write enables notMemWrB0-3. ProcClockOut TPCHEL Memazst Xo) TAVEL peng TELEH TEHEL notMemce —_ Datos [i> TWEHEL notMemWrB0-3 \\ Figure 8.5 IMS T801 external read cycle

164 5__ IMS T801 engineering data

8.3 Write cycle

For write cycles the relevant bytes in memory are addressed by the write enables notMemWrB0-3. If a par- ticular byte is not to be written, then the corresponding data outputs are tristated. notMemWrBO addresses the least significant byte. The write enables are gated with the chip enable signal notMemCE, allowing them to be used without notMemCE for simple designs. Data may be strobed into memory using notMemWrBO-3 without the use of notMemCE, as the write enables go high between consecutive external memory write cycles. Write data is placed on the data bus at the start of T2 and removed at the end of T4. The write cycle is completed with notMemCE going high. Table 8.4 Write cycle 7801-30 | 7801-25 SYMBOL | PARAMETER [an a [a [ mA [Wa [ A] TDWVEH | Data setup before chip enable high 40 50 1 TEHDwZ | Data hold after write 10 8 10 1 TDwZEL | Write data invalid to next chip enable 8 10 1 TWELEL | Write enable setup to chip 0 -2 3 1,2 enable low TEHWEH | Write enable hold after chip enable 1 0 0 1,2 high Notes 1 Units are ns. 2 Timing is for all four write enables notMemWrB0-3. Tstates [T1 | 12 | 73 | 714 | TH | ProcClockOut Sf ‘VSS Xe. notMemCE ‘TOwZEL pl Lee Datao-s Gia. TWELEL i TEHWEH notMemWrB0-3 | lA Figure 8.6 IMS T801 external write cycle

8__External memory interface 165

8.4 Wait

Taking MemWait high with the timing shown in the diagram will extend the duration of T2 by one processor cycle TPCLPCL. One wait state comprises the pair W1 and W2. MemWait is sampled during T2, and should not change state in this region. If MemWait is still high when sampled in W2 then another wait period will be inserted. This can continue indefinitely. Internal memory access is unaffected by the number of wait states selected. The wait state generator can be a simple digital delay line, synchronised to notMemCE. The Single Wait State Generator circuit in figure 8.7 can be extended to provide two or more wait states, as shown in figure 8.8. Table 8.5 Memory wait SYMBOL | win | MAX | Min | MAX | Min [MAX | TPCHWIH | MemWait asserted after 1 ProcClockOut high TAVWtH MemWait asserted after 1 Address vatid TPCHWIL | Wait low after 1 ProcClockOut high Notes 1 Units are ns. Tstates | T1 | 72 [wt | we |3 | t4 | m1 | ProcClockOut Hf WVY\\WNY NW notMemCE TPCHWiL TAVWIH TPCHWHH MemWait notMemWrB0-3 \\ [ Figure 8.7 IMS T801 memory wait timing

8 External memory interface 167

8.5 Direct memory access

Direct memory access (DMA) can be requested at any time by driving the asynchronous MemReq input high. MemReq is sampled during T1 of the processor cycle and the DMA device will then have contro! of the bus at the beginning of the next processor cycle, (after one ProcClockOut for internal accesses and two ProcClockOut cycles for external memory accesses, without wait states). When the processor transfers control of the bus the signals MemA2-31, notMemWrB0-3 and notMemCE are tristated and MemGranted is asserted high. MemGranted follows the timing of the bus being tristated and can be used to signal to the device requesting the DMA that it has contro! of the bus. Note that MemGranted changes on the falling edge of ProcClockOut and can therefore be sampled to establish control of the bus on the rising edge of ProcClockOut. During the DMA cycles, MemReq is sampled during each high phase of ProcClockOut and after it is taken low, control of the bus will be returned to the processor within two ProcClockOut cycles. The processor is still able to access its internal memory while the DMA transter proceeds, however when an external memory request is made the processor is forced to wait until the end of the DMA request. The DMA device has no access to the transputer's internal memory. While control of the bus is being transferred from the processor to the DMA device, an extra clock phase, (one quarter of a ProcClockOut cycle) is allowed before the DMA transfer begins to ensure that the not- MemCE and notMemWrB0-3 signals have been driven high before being tristated. This normally removes the requirement for external pull-up resistors. DMA allows a bootstrap program to be loaded into external memory for execution after reset. If MemReq is asserted high during reset, MemGranted will be asserted high allowing access to the external memory before the bootstrap sequence begins. MemReq must be asserted for at least one period of TOCLDCL of Clockin before Reset is asserted. The DMA control circuitry should ensure that correct operation will result if Reset should interrupt a normal DMA cycle. MemReq LLL MemGranted KLE Reset Bootstrap activity [8] B Bootstrap sequence Figure 8.9 IMS T801 DMA sequence at reset

168 5__ IMS T801 engineering data Table 8.6 Memory request 7801-30 7801-25 7801-20 sypo._| PARAMETER [an [Ma [aT wax [wi | MAX | NOTE TMRHMGH | Memory request response time 58 70 a 85 TMRLMGL | Memory request end response 60 75 80 90 time TAZMGH Address bus tristate before 0 0 0 MemGranted TOZMGH Data bus tristate before 0 0 0 MemGranted Notes 1 Maximum response time a depends on whether an external memory cycle is in progress. Maximum time is (2 processor cycles) + (number of wait state cycles) for word access. 2 Units are ns. Tstate | T1 | T2| 73] T4171 | T2| Th] T4| 11] T2] 73/74 | 71 | a . | | MemA2-31 coe > KO Data0-31 SEED rT | id 1 MemReq | ! rare — MemGranted | Write TriState DMA Write Figure 8.10 IMS T801 memory request timing

—SSSSSSSSSSSSSSSSSS—s

9 Events

EventReq and EventAck provide an asynchronous handshake interface between an external event and an internal process. When an external event takes EventReq high the external event channel (additional to the external link channels) is made ready to communicate with a process. When both the event channel and the process are ready the processor takes EventAck high and the process, if waiting, is scheduled. EventAck is removed after EventReq goes low. EventWaiting is asserted high by the transputer when a process executes an input on the event channel; typically with the occam EVENT ? ANY instruction. It remains high whilst the transputer is waiting for or servicing EventReq and is returned low when EventAck goes high. The EventWaiting pin changes near the falling edge of ProcClockOut and can therefore be sampled by the rising edge of ProcClockOut. The EventWaiting pin can only be asserted by executing an in instruction on the event channel. The EventWaiting pin is not asserted high when an enable channel (enbc) instruction is executed on the Event channel (during an ALT construct in occam, for example). The EventWaiting pin can be asserted by executing the occam input on the event channel (such as Event ? ANY), provided that this does not occur as a guard in an alternative process. The EventWaiting pin can not be used to signify that an alternative Process (ALT) is waiting on an input from the event channel. EventWaiting allows a process to control external logic; for example, to clock a number of inputs into a memory mapped data latch so that the event request type can be determined. Only one process may use the event channel at any given time. if no process requires an event to occur EventAck will never be taken high. Although EventReq triggers the channel on a transition from low to high, it must not be removed before EventAck is high. EventReq should be low during Reset; if not it will be ignored until it has gone low and returned high. EventAck is taken low when Reset occurs. It the process is a high priority one and no other high priority process is running, the latency is as described on page 136. Setting a high priority task to wait for an event input allows the user to interrupt a transputer Program running at low priority. The time taken from asserting EventReq to the execution of the microcode interrupt handler in the CPU is four cycles. The following functions take place during the four cycles: Cycle 1 Sample EventReq at pad on the rising edge of ProcClockOut and synchronise. Cycle 2 Edge detect the synchronised EventReq and form the interrupt request. Cycle 3 Sample interrupt vector for microcode ROM in the CPU. Cycle 4 Execute the interrupt routine for Event rather than the next instruction.

170 5 IMS 7801 engineering data Table 9.1 Event SYMBOL PARAMETER | Min | Nom | MAX [UNITS | NOTE TVHKH Event request response 0 TKHVL Event request hold 0 TVLKL Delay before removal of event acknowledge 0 ard TKLVH Delay before re-assertion of event request 0 TKHEWL | Event acknowledge to end of event waiting 0 TKLEWH | End of event acknowledge to event waiting 0 Notes 1 ais 3 processor cycles TPCLPCL. EventReq TVHKH TKHVL EventAck TKHEWL TKLEWH EventWaiting 4 4 Process waiting for Event Event waiting for Process Figure 9.1 IMS T801 event timing

10 Links

Four identical INMOS bi-directional serial links provide synchronized communication between processors and with the outside world. Each link comprises an input channel and output channel. A link between two transputers is implemented by connecting a link interface on one transputer to a link interface on the other transputer. Every byte of data sent on a link is acknowledged on the input of the same link, thus each signal line carries both data and control information. The quiescent state of a link output is low. Each data byte is transmitted as a high start bit followed by a one bit followed by eight data bits followed by a low stop bit. The least significant bit of data is transmitted first. After transmitting a data byte the sender waits for the acknowledge, which consists of a high start bit followed by a zero bit. The acknowledge signifies both that a process was able to receive the acknowledged data byte and that the receiving link is able to receive another byte. The sending link reschedules the sending process only after the acknowledge for the fina! byte of the message has been received. The IMS T801 links allow an acknowledge packet to be sent before the data packet has been fully received. This overlapped acknowledge technique is fully compatible with all other INMOS transputer links. The IMS 7801 links support the standard INMOS communication speed of 10 Mbits/sec. In addition they can be used at 20 Mbits/sec for IMS T801-20 and IMS 7801-25. Links are not synchronised with Clockin or ProcClockOut and are insensitive to their phases. Thus links from independently clocked systems may communicate, providing only that the clocks are nominally identical and within specification. Links are TTL compatible and intended to be used in electrically quiet environments, between devices on a single printed circuit board or between two boards via a backplane. Direct connection may be made between devices separated by a distance of less than 300 millimetres. For longer distances a matched 100 Ohm transmission line should be used with series matching resistors RM. When this is done the line delay should be less than 0.4 bit time to ensure that the reflection returns before the next data bit is sent. Buffers may be used for very long transmissions. If so, their overall propagation delay should be stable within the skew tolerance of the link, although the absolute value of the delay is immaterial. Link speeds can be set by LinkSpeed. LinkSpeed allows Links 0, 1, 2 or 3 to be set to 10 or 20 Mbits/sec. Table 10.1 shows uni-directional and bi-directional data rates in Kbytes/sec for each link speed. Data rates are quoted for a transputer using internal memory, and will be affected by a factor depending on the number of external memory accesses and the length of the external memory cycle. Table 10.1 Speed Settings for Transputer Links Link Special_| Mbits/sec [Uni [Bi 0 910 1 1740 H"H[0]1]2[3[4[5[e[7]t SAL, | Data | | Ack | Figure 10.1 IMS T801 link data and acknowledge packets

172 5__IMS T801 engineering data Table 10.2 Link SYMBOL PARAMETER [ MIN | NOM | MAX | UNITS | NOTE TJOr LinkOut rise time 20 ns TJOF LinkOut fall time 10 ns TJOr Linkin rise time 20 ns TJDt Linkin fall time 20 ns TJQUD Buffered edge delay ns TJBskew | Variation in TJQUD 20 Mbits/s 3 ns

10 Mbits/s 10 ns

CLIZ Linkin capacitance @ f=1MHz 7 pF CLL LinkOut load capacitance 50 pF RM Series resistor for 1009 transmission line ohms Notes 1 These parameters are sampled, but are not 100% tested. 2 This is the variation in the total delay through buffers, transmission lines, differential receivers etc., caused by such things as short term variation in supply voltages and differences in delays for rising and falling edges. LinkOut TJOr TOF ° Toor = Retor Figure 10.2 IMS T801 link timing Latest TJQUD Earliest TIQUD Linkin 1.5V----—- ---- TJBskew Figure 10.3 IMS T801 buffered link timing

10 Links 173

Transputer family device A LinkOut, Linkin Linkin LinkOut Transputer family device B Figure 10.4 IMS T801 Links directly connected Transputer family device A Zo=1000hms LinkOut [an Linkin Linkin 0 (—}— LinkOut Zo=1000hms RM Transputer family device B Figure 10.5 IMS T801 Links connected by transmission line Transputer family device A LinkOut [> Linkin Linkin <q LinkOut Transputer family device B Figure 10.6 IMS T801 Links connected by buffers

ah Electrical specifications W41 DC electrical characteristics Table 11.1 Absolute maximum ratings SYMBOL PARAMETER [MIN | MAX’ [UNITS | NOTE | VCC DC supply voltage 7.0 Vv 1,2,3 VI, VO Voltage on input and output pins VCC+0.5 Vv 1,2,3 W Input current +25 mA 4 OSCT Output short circuit time (one pin) 1 s 2 TS Storage temperature 150 °C 2 TA Ambient temperature under bias 125 °C 2 PDmax Maximum allowable dissipation 2 Ww Notes 1 All voltages are with respect to GND. 2 This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operating sections of this specification is not implied. Stresses greater than those listed may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 3 This device contains circuitry to protect the inputs against damage caused by high static voltages or electrical fields. However, it is advised that normal precautions be taken to avoid application of any voltage higher than the absolute maximum rated voltages to this high impedance circuit. Unused inputs should be tied to an appropriate logic level such as VCC or GND. 4 The input current applies to any input or output pin and applies when the voltage on the pin is between GND and VCC. Table 11.2 Operating conditions SYMBOL. PARAMETER [ MIN | MAX | UNITS | NOTE vec DC supply voltage 4.75 §.25 Vv Vi, VO Input or output voltage 0 vec Vv cL Load capacitance on any pin 60 pF TA Operating temperature range 0 70 °C Notes 1 All voltages are with respect to GND. 2 Excursions beyond the supplies are permitted but not recommended; see DC characteristics. 3 Air flow rate 400 linear ft/min transverse air flow.

11__ Electrical specitications 175 Table 11.3 DC characteristics SYMBOL PARAMETER [Win [WAX [UNITS | NOTE ] VIH High level input voltage 2.0 VCC+0.5 Vv 4,2 VIL Low level input voltage, 0.5 08 Vv 1.2 u Input current @ GND<VI<VCC +10 pA 42 VOH Output high voltage @ IOH=2mA VCC-1 v 1,2 VOL Output low voltage @ lOL=4mA 0.4 v 1,2 10S Output short circuit current @ GND<VO<VCC. 36 65 mA 1,2,3,6 65 100 mA 1,2,4,6 10Z Tristate output current @ GND<VO<VCC +10 pA 12 PD Power dissipation 12 Ww 25 CIN Input capacitance @ f=1MHz 7 pF 6 coz Output capacitance @ f=1MHz 10 pF 6 Notes 1 All voltages are with respect to GND. 2 Parameters for IMS T801-S measured at 4.75V<VCC<5.25V and 0°C<TA<70°C. Input clock frequency = 5 MHz. 3 Current sourced from non-link outputs excluding ProcClockOut. 4 Current sourced from link outputs and ProcClockOut. 5 Power dissipation varies with output loading and program execution. Powar dissipation for processor operating at 20 MHz. 6 This parameter is sampled and not 100% tested.

11.2 Equivalent circuits

ri] [toad for: | Rt | R2__ [Equivalent load: Link outputs 1K96 47K | 1 Schottky TTL input Output Other outputs | 970R | 24K |2 Schottky TTL inputs 50pF == {| Diodes are 1N916 GND Figure 11.1 Load circuit for AC measurements

176 5__IMS T801 engineering data Vdd-1 Inputs VIH ov Vdd-1 Inputs VIL ov tPHL Vdd Outputs 1.5V ov {pLH Vdd Outputs ASV ov Figure 11.2 AC measurements timing waveforms vcc Test point 510R Output under test 50pF I t GND Figure 11.3 Tristate load circuit for AC measurements

11.3 AC timing characteristics

Table 11.4 Input, output edges SYMBOL PARAMETER [MIN [| MAX | UNITS | NOTE TDr input rising edges 20 TDF Input falting edges 20 TQr Output rising edges 25 TOf Output falling edges 15 Notes 1 Non-link pins; see section on links. 2 All inputs except Clockin; see section on Clockin. 3 These parameters are not tested. 4 These parameters are sampled, but are not 100% tested.

11__ Electrical specifications 177 Tot Tr Tat Tar Figure 11.4 IMS T801 input and output edge timing 30 30 Rise time Rise time il 20 i 20 i Time Time i ns Fall time ns Fall time 10 10 Skew 40 60 80 100 40 60 80 100 Load Capacitance pF Load Capacitance pF Link and ProcClockOut EMI! Figure 11.5 Typical rise/fall times Notes

1 Skew is measured between notMemCE with a standard load (2 Schottky TTL inputs and 30 pF) and notMemCE

with a load of 2 Schottky TTL inputs and varying capacitance.

11.4 Power rating

Internal power dissipation Pry7 of transputer and peripheral chips depends on VCC, as shown in figure 11.6. Pryr is substantially independent of temperature. Total power dissipation Pp of the chip is Pp = Print + Pro where Pro is the power dissipation in the input and output pins; this is application dependent. Internal working temperature T, of the chip is Ty = Ta +0J4* Pp where Ty, is the external ambient temperature in °C and ¢J, is the junction-to-ambient thermal resistance in °CW. 6J4 for each package is given in the Packaging Specifications section.

178 § IMS T801 engineering data _— 7801-30 (projected) a

800 Lc — 7801-25

• a Power PINT 600-} ~ mw 500 44 46 48 50 52 54 56 VCC Volts Figure 11.6 IMS T801 internal power dissipation vs VCC 650 Power 600 + PD mW 550 500 15 20 25 30 Processor frequency MHz Figure 11.7 IMS T801 typical power dissipation with processor speed

12 Pertormance

The performance of the transputer is measured in terms of the number of bytes required for the program, and the number of (internal) processor cycles required to execute the program. The figures here relate to occam programs. For the same function, other languages should achieve approximately the same performance as occam. With transputers incorporating an FPU, this type of performance calculation is straight forward when consider- ing only integer data types. However, when floating point calculations using the REAL32 and REAL64 data types are present in the program, complications arise due to the concurrency inherent in the transputer's de- sign whereby integer calculations can be overlapped with floating point calculations. A more comprehensive guide to the impact of this concurrency on transputer performance can be found in the Transputer instruction Set - A Compiler Writers’ Guide.

12.1 Performance overview

These figures are averages obtained from detailed simulation, and should be used only as an initial guide; they assume operands are of type INT. The abbreviations in table 12.1 are used to represent the quantities indicated. In the replicator section of the table, figures in braces {} are not necessary if the number of replications is a compile time constant. To estimate performance, add together the time for the variable references and the time for the operation. Table 12.1 Key to performance table np | number of component processes ne | number of processes earlier in queue r 1 if INT parameter or array parameter, 0 if not ts | number of table entries (table size) w | width of constant in nibbles p number of places to shift Eg | expression used in a guard Et | timer expression used in a guard Tb | most significant bit set of multiplier ((-1) if the multiplier is 0) Tbp | most significant bit set in a positive multiplier when counting from zero ((-1) if the multiplier is 0) Tbe | most significant bit set in the two's complement of a negative multiplier nsp | Number of scalar parameters in a procedure nap | Number of array parameters in a procedure

180 5__IMS T801 engineering data Table 12.2 Performance PT Size tyres) Names variables in expression V1+r 2.142(r) assigned to or input to V14r 1.14(r) in PROC or FUNCTION call, corresponding to an INT parameter Vier 1,1+(r) channels _ WW 24 Array Variables (for single dimension arrays) constant subscript ) 0 variable subscript 5.3 7.3 expression subscript 5.3 7.3 Declarations CHAN OF protoco/ 3.4 3.4 [size]CHAN OF protocol 9.4 2.2 +420.2ssize PROC body+2 0 Primitives assignment 0 0 input 4 26.5 output 1 26 STOP 2 25 SKIP 0 0 Arithmetic operators + - 1 1 iol 2 39 / 2 40 REM 2 38 >> << 2 3+p Modulo Arithmetic operators PLUS 2 2 MINUS 1 1 TIMES (fast multiply, positive operand) 1 4+Tbp TIMES (fast multiply, negative operand) 1 5+Tbe Boolean operators OR 4 8 AND NOT 1 2 Comparison operators = constant 0 1 = variable 2 3 <> constant 1 3 <> variable 3 5 > < 1 2 >= <= 2 4 Bit operators NN Vo« ~ 2 2 Expressions constant in expression w w check if error 4 6

12 Performance 181

Table 12.3 Performance TSize bytes) Time (eyeles) | Timers timer input 2 3 timer AFTER if past time 2 4 with empty timer queue 2 31 non-empty timer queue 2 38+ne+9 ALT (timer) with empty timer queue 6 52 non-empty timer queue 6 59+nes9 timer alt guard 8+2Eg+2Et 344+2Eg+2Et Constructs SEQ 0 0 IF 1.3 1.4 if guard 3 43 ALT (non timer) 6 26 alt channel guard 10.2+2Eg 20+2Eg skip alt guard 84+2Eg 10+2Eg WHILE 4 12 Procedure or function call +Naps2.3 +ape2.3 Replicators

12.2 Fast multiply, TIMES

The IMS T801 has a fast integer multiplication instruction product. For a positive multiplier its execution time is 44Tbp cycles, and for a negative multiplier 5+Tbe cycles (table 12.1). The time taken for a multiplication by zero is 3 cycles. Implementations of high level languages on the transputer may take advantage of this instruction. For example, the occam modulo arithmetic operator TIMES is implemented by the instruction and the right-hand operand is treated as the multiplier. The fast multiplication instruction is also used in high level language implementations for the multiplication implicit in multidimensional array access.

182 5__ IMS T801 engineering data

12.3 Arithmetic

A set of functions are provided within the development system to support the efficient implementation of multiple length integer arithmetic. In the IMS T8041, floating point arithmetic is taken care of by the FPU. In table 12.4 n gives the number of places shifted and all arguments and results are assumed to be local. Full details of these functions are provided in the OCcam reference manual, supplied as part of the development system and available as a separate publication. When calculating the execution time of the predefined maths functions, no time needs to be added for calling overhead. These functions are compiled directly into special purpose instructions which are designed to support the efficient implementation of multiple length integer arithmetic and floating point arithmetic. Table 12.4 Arithmetic performance amas [age [ona Cycles parameter access + LONGADD 2 7 LONGSUM 3 8 LONGSUB 2 7 LONGDIFF 3 8 LONGPROD 34 8 LONGDIV 36 8 SHIFTRIGHT (n<32) 44n 8 (n>=32) n-27 SHIFTLEFT (n<32) 44n 8 (n>=32) n-27 NORMALISE (n<32) n+6 7 (n>=32) n-25 (n=64) 4 ASHIFTRIGHT SHIFTRIGHT+2 5 ASHIFTLEFT SHIFTLEFT+4 5 ROTATERIGAT SHIFTRIGAT 7 ROTATELEFT SHIFTLEFT 7 FRACMUL LONGPROD+4 5 t Assuming local variables.

12__ Performance 183

12.4 Floating point operations

All references to REAL32 or REAL64 operands within programs compiled for the IMS T801 normally produce the following performance figures. Table 12.5 Floating point performance [~~~ __| Size (bytes) | REAL32 Time (cycles) | REAL64 Time (cycles) Names variables in expression 3.1 3 5 assigned to or input to 31 3 5 in PROC or FUNCTION call, corresponding to a REAL parameter ter Vier 14+r Arithmetic operators + = 2 7 7 * 2 1 20 7 2 17 32 REM aa) 19 34 Comparison operators = 2 4 4 <> 3 6 6 > < 2 5 5 >= <s 3 7 7 Conversions REAL32 to - 2 3 REAL64 to - 2 6 To INT32 from - 5 9 9 To INT64 from - 18 32 32 INT32 to - 3 7 7 INT64 to - 14 24 22

12.4.1 Floating point functions

These functions are provided by the development system. They are compiled directly into special purpose instructions designed to support the efficient implementation of some of the common mathematical functions of other languages. The functions provide ABS and SQRT for both REAL32 and REAL64 operand types. Table 12.6 IMS T801 floating point arithmetic performance + cycles for parameter access + Cycles | REAL32 [REAL __ | ABS 2 8 SQRT 118 8 DABS 2 12 DSQRT 244 12 + Assuming local variables.

184 5 IMS T801 engineering data SS, ____5_IMS 801 engineering data

12.4.2 Special purpose functions and procedures

The functions and procedures given in tables 12.8 and 12.9 are Provided by the development system to give access to the special instructions available on the IMS T801. Table 12.7 shows the key to the table. Table 12.7 Key to special performance table most significant bit set in the word counting from zero number of words per row (consecutive memory locations) number of rows in the two dimensional move number of bits to reverse Table 12.8 Special purpose functions performance + cycles for Function Parameter access + BITCOUNT 2+Tb 2 CRCBYTE ab 8 CRCWORD 35 8 BITREVNBIT S+nr 4 BITREVWORD 36 2 + Assuming local variables. Table 12.9 Special purpose procedures performance + cycles for Procedure Cycles parameter access MOVE2D 8+(2n+23)sr 8 DRAW2D 8+(2n+23)sr 8 CLIP2D 8+(2n+23)sr 8 t Assuming local variables.

12.5 Effect of external memory

Extra processor cycles may be needed when program and/or data are held in external memory, depending both on the operation being performed, and on the speed of the external memory. After a processor cycle which initiates a write to memory, the processor continues execution at full speed until at least the next memory access. Whilst a reasonable estimate may be made of the effect of external memory, the actual performance will depend upon the exact nature of the given sequence of operations. External memory is characterized by the number of extra processor cycles per external memory cycle, denoted as e. The value of e for the IMS T801 is greater than or equal to 1. If a program is stored in external memory, and e has the value 2 or 3, then no extra cycles need be estimated for linear code sequences. For larger values of @, the number of extra cycles required for linear code sequences may be estimated at (e-3)/4. A transfer of control may be estimated as requiring e+3 cycles. These estimates may be refined for various constructs. In table 12.10 n denotes the number of components in a construct. In the case of IF, the n'th conditional is the first to evaluate to TRUE, and the costs include the costs of the conditionals tested. The number of bytes in an array assignment or communication is denoted by b.

12 _ Performance 185 Table 12.10 External memory performance IMS T801 Program off chip Data off chip Boolean expressions e-2 0 IF 3en-8 en Replicated IF (66-4)n+7 (5e-2)n+8 Replicated SEQ (3e-3)n+2 (4e-2)n PAR (3e-1)n+8 Sen+4 Replicated PAR (10e-8)n+8 16en-12 ALT (2e-4)n+6e (2e-2)n+10e-8 Array assignment and ) max (2e, e(b/2)) communication in one transputer The following simulation results illustrate the effect of storing program and/or data in external memory. The results are normalized to 1 for both program and data on chip. The first program (Sieve of Erastosthenes) is an extreme case as it is dominated by small, data access intensive loops; it contains no concurrency, communication, or even multiplication or division. The second program is the pipeline algorithm for Newton Raphson square root computation. Table 12.11 IMS T801 external memory performance Program off chip 13] 15 ] 1.7 | 1.9 1 Data off chip 15) 18] 214 | 23 1 Program and data off chip 18] 22 | 2.7 | 32 1 13] 16) 18 | 2.0 1

12.6 Interrupt latency

{f the process is a high priority one and no other high priority process is running, the latency is as described in table 12.12. The timings given are in full processor cycles TPCLPCL; the number of Tm states is also given where relevant. Maximum latency assumes all memory accesses are internal ones. Table 12.12 Interrupt latency [typical Maximum TPCLPCL TPCLPCL IMS T801 with FPU in use 19 38 78 156 IMS 7801 with FPU not in use 19 38 58 116

13.1 100 pin grid array package Index . 1 2 3 4 5 6 7 8 9 10 O > Oo o, © © O e, 0 o o © © o o, © oO o not Link Link G Mem © > o O o, o, oO > oO Proc Link Link Proc not Boot J | Mem Out! From WrB1 Rom 0 o o, oO o, Oo o> © o K Link Link Link vec Cap Proc Proc In3 Out2 Outd Plus Speedo | Speed2 Figure 13.1 IMS T&01 100 pin grid array package pinout - top view

M index # Er 170987654321 + ©9OOOOOOOOIA F ©OGOOOOOOOO|B O©@OOOOOOOOO'C ®@®©O9OOO0000/0 ABI kK ®@OOOOOOOOOIE @O©O9OOOOOOO|F @OOOOOOOOOIG ©@9OOOOOOO08]H tL} ee00000000)|J ©9O9OOOOOOO|K i a B2 Cc | L | = Eo is i Figure 13.2 100 pin grid array package dimensions Table 13.1 100 pin grid array package dimensions Millimetres [_inches _| [Nom [Tor [| NOM | TOL__| A 26.924 40.254 1.060 +0.010 Bi 17.019 0.127 0.670 +0.005 B2 18.796 £0.127 0.740 +0.005 c 2.456 £0.278 0.097 +0.011 D 4,572 40.127 0.180 +0.005 E 3.302 £0,127 0.130 +0.005 F 0.457 +£0.051 0.018 0.002 | Pin diameter G 1.143 40.127 0.045 0.005 | Flange diameter K 22.860 £0.127 0.900 0.005 L 2.540 40.127 0.100 0.005 M 0.508 0.020 Chamfer Table 13.2 100 pin grid array package junction to ambient thermal resistance [SymsoL[_—S=S—SPARAMETER |S MIN’ | NOM | MAX [UNITS | NOTE | At 400 linear fymin transverse air flow [as cw [|

——SSSSSSSSSSSSSSSSSSMSSSSe This section indicates the designation of speed and package selections for the various devices. Speed of Clockin is 5 MHz for all parts. Transputer processor cycle time is nominal; it can be calculated more exactly using the phase lock loop factor PLLx, as detailed in the external memory section. For availability contact local INMOS sales office or authorised distributor. Table 14.1 IMS T801 ordering details INMOS Processor | Processor designation clock speed | cycle time | PLLx g IMS T801-G20S 20.0 MHz 50 ns 4.0 | Ceramic Pin Grid IMS T801-G25S 25.0 MHz 40ns 5.0 | Ceramic Pin Grid IMS T801-G30S 30.0 MHz 33 ns 6.0 | Ceramic Pin Grid IMS T801-G20M 20.0 MHz 50 ns 4.0 | Ceramic Pin Grid