IMST225-J25S

IMST225 STMICROELECTRONICS | Alldatasheet

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{v7 SGS-THOMSON YZ, wichoELEcrnonics IMS T225 See 16-bit transputer Sn

FEATURES

®@ 16 bit architecture ™ 33 ns internal cycle time @ 30 MIPS peak instruction rate ® Debugging support @ 4 Kbytes on-chip static RAM ® 60 Mbytes/sec sustained data rate to internal memory ®@ 64 Kbytes directly addressable external memory System 16 bit ™@ 30 Mbytes/sec sustained data rate to external memory Services [ 78 | Processor © 630 ns response to interrupts ® Four INMOS serial links 5/10/20 Mbits/sec . ® Bi-directional data rate of 2.4 Mbytes/sec per link Link ® Internal timers of 1ms and 64ns services ® Boot from ROM or communication links Link ® Single 5 MHz clock input (76) tit @ Single +5V +5% power supply 35 (3) . Link ™ Packaging 68 pin PGA / 68 pin PLCC / 100 pin CQFP RAM 16 ™@ Extended temperature version available Ce ae APPLICATIONS interface © Real time processing Vena (ae) ti ® Microprocessor applications Interface ‘8 merece ® High speed multi processor systems ® Industrial control ® Robotics ® System simulation ® Digital signal processing ® Telecommunications ® Fault tolerant systems ® Medical instrumentation February 1997 Bm 7929237 0090734 41T i 42 1454 04

1 Introduction

The IMS T225 transputer is a 16 bit CMOS microcomputer with 4 Kbytes on-chip RAM for high speed pro- cessing, an externalmemory interface and four standard INMOS communication links. The instruction set achieves efficient implementation of high level languages such as ANSI C and provides direct support for concurrency when using either a single transputer or a network. Procedure calls, process switching and typical interrupt latency are sub-microsecond. For convenience of description, the IMS T225 operation is split into the basic blocks shown in figure 1.1. VDD GND CapPlus 1 . CapMinus System 16 bit Reset Services | 16 _| Processor Analyse Error BootFromROM Clockin z LinkSpecial ProcSpeedSelect0-2 Link LinkOSpecial | Services |. Link123Special Link Linkino 16_} interface |» LinkOuto

4 Kbytes

DisableiIntRAM on nip (36 | ae{ tink Linkint RAM h Interface LinkOutt Link Linkin2 ProcClockOut 16 |] interface |» LinkOut2 notMemCE notMemWrB0-1 Link ~ Linking External 16_] interface |» LinkOut3 Memory Interface [6] EventReq MemWait MemBAcc MemReq <5 > memoo-15 MemGranted [16 memao-as Figure 1.1 IMS T225 block diagram The IMS T225 is functionally equivalent to the IMS T222 but has the addition of three speed select pins (ProcSpeedSelect0-2) and improved links. The IMS T225 is pin compatible with the IMS T222 andis a direct replacement in many applications. The IMS T225 can directly access a linear address space of 64 Kbytes. System Services include processor reset and bootstrap control, together with facilities for error analysis. The INMOS communication links allow networks of transputers to be constructed by direct point to point connections with no external logic. The links support the standard operating speed of 10 Mbits/sec, but syns —— Be 7929237 0090736 2ei2

also operate at 5 or 20 Mbits/sec. The links have been improved over those of the IMS 222 and fully support overlapped acknowledge; each IMS 7225 link can transfer data bi-directionally at up to 2.4 Mbytes/sec. The transputer is designed to efficiently implement high level languages such as ANSI C and occam. Access to the transputer at machine level is seldom required, but if necessary refer to the Transputer in- struction Set — A Compiler Writer's Guide. A summary of the transputer instruction set can be found in section 11. The IMS T225 instruction set contains a number of instructions to facilitate the implementation of break- points. For further information concerning breakpointing, refer to Support for debugging/breakpointing in transputers (technical note 61). 4 156 y sis ___ ysee-mompgony mm 7929237 0090737 1¢c5

2 Pin designations

Signal names are prefixed by not if they are active low, otherwise they are active high. Pinout details for various packages are given in section 9. [Pie iv Fanetin VCC, GND Power supply and return CapPlus, CapMinus External capacitor for internal clock power supply Clockin Input clock ProcSpeedSelect0-2 Processor speed selectors Reset System reset Error Error indicator Analyse Error analysis BootFromROM Boot from external ROM or from link DisableintRAM Disable internal RAM Table 2.1 IMS T225 system services a ProcClockOut out Processor clock MemA0-15 out Sixteen address lines MemD0-15 in/out Sixteen data lines notMemWrBo-1 out Two byte-addressing write strobes notMemCE out Chip enable MemBAcc in Byte access mode selector MemWait in Memory cycle extender MemReq in Direct memory access request MemGranted out Direct memory access granted Table 2.2 IMS T225 external memory interface EventReq Event request EventAck Event request acknowledge Table2.3 IMS T225 event a Linkin0-3 Four serial data input channels LinkOut0-3 Four serial data output channels LinkSpecial Select non-standard speed as 5 or 20 Mbits/sec LinkOSpecial Select special speed for Link 0 Link123Special Select special speed for Links 1, 2,3 Table 2.4 IMS T225 link assess vss me 7929237? 0090738 ObS a

3 System services

System services include all the necessary logic to initialize and sustain operation of the device. They also include error handling and analysis facilities.

3.1 Power

Power is supplied tothe device via the VDD and GND pins. Several of eachare provided to minimize induc- tance within the package. All supply pins must be connected. The supply must be decoupled close to the Chip by at least one 100 nF low inductance (e.g. ceramic) capacitor between VDD and GND. Four layer boards are recommended; if two layer boards are used, extra care should be taken in decoupling. Input voltages must not exceed specification with respect toVDD and GND, even during power-up and Power-down ramping, otherwise /afchup can occur. CMOS devices can be permanently damaged by ex- cessive periods of latchup. 3.2. CapPlus, CapMinus The internally derived power supply for internal clocks requires an external low leakage, low inductance ‘1nF capacitor to be connected between CapPlus and CapMinus. A ceramic capacitor is preferred, with an impedance less than 3 Ohms between 100 KHz and 20 MHz. If a polarized capacitor is used the nega- tive terminal should be connected to CapMinus. Total PCB track length should be less than 50 mm. The connections must not touch power supplies or other noise sources. vDD [| CapPlus —_P.C.B track Phase—locked Decoupling | loops capacitor 1 nF (| CapMinus P.C.B track | GND Figure 3.1 Recommended PLL decoupling 3.3. Clockin Transputerfamily components use a standard clock frequency, supplied by the user on theClockin input. The nominal frequency of this clock for all transputer family components is 5 MHz, regardless of device type, transputer word length or processor cycle time. High frequency internal clocks are derived from Clockin, simplifying system design and avoiding problems of distributing high speed clocks externally. A number of transputer devices may be connected to a common clock, or may have individual clocks pro- viding each one meets the specified stability criteria. In a multi-clock system the relative phasing ofClock- In clocks is not important, due to the asynchronous nature of the links. Mark/space ratio is unimportant provided the specified limits of ClockIn pulse widths are met. Oscillator stability is important. ClockIn must be derived from a crystal oscillator; RC oscillators are not sufficiently stable. Clockin must not be distributed through a long chain of buffers. Clock edges must be monotonic and remain within the specified voltage and time limits. s/)__gyrsge-mwompoyy mm 7929237 0090739 TTL

To SsSSSSSssSssesssssSSSSSSSSSSSSSSSs Parameter [ Min [Nom | Max | Notes TDCLDCH | Clockin pulse width low 40 TDCHDCL | Clockin pulse width high 40 TDCLDCL | Clockin period 200 1,3 TDCerror Clockin timing error 0.5 2 TDCiDC2 | Difference in Clockin for 2 linked devices 400 3 TDCr Clockin rise time 10 4 TDCf Clockin fall time 8 4 Notes 1 Measured between corresponding points on consecutive falling edges. 2. Variation of individual falling edges from their nominal times. 3. This value allows the use of 200ppm crystal oscillators for two devices connected together by a link. 4 Clock transitions must be monotonic within the range VIH to VIL (table 8.3). Table 3.1 Clockin timing TDCerror TDCerror | TDCerror TDCerror 2oy === NQNE===o7 NNSC===2: 08v —~—-—\\YS—--- 7 POSE T= TDCLDCH TDOCHDCH TDCLDCL |<— TDC TDCr. Figure 3.2 Clockin timing mm 7929237 oOo0740 713 a

3.4 ProcSpeedSelect0-2

Processor speed of the IMS T225 is variable in discrete steps. The desired speed can be selected, up to the maximum rated for a particular component, by the three speed select linesProcSpeedSelect0-2. The pins are tied high or low, according to the table below, for the various speeds. The pins are arranged so that the IMS T225 can be plugged directly into a board designed for a IMS T222. Only six of the possible speed select combinations are currently used; the other two are not valid speed selectors. The frequency of Clockin for the speeds given in the table is 5 MHz. ProcSpeed- | ProcSpeed- | ProcSpeed- Processor Processor Notes Select2 Select Select Clock Cycle Speed MHz Time ns 0 0 0 20.0 50.0 0 i) 1 22.5 44.4 Not supported 0 1 i} 25.0 40.0 0 1 1 30.0 33.3 Not supported 1 0 0 35.0 28.6 Not supported 1 ty) 1 Invalid 1 1 0 17.5 57.1 Not supported 1 1 1 Invalid Table 3.2 Processor speed selection

3.5 Bootstrap

The transputer can be bootstrapped either from a link or from external ROM. To facilitate debugging, Boot- FromROM may be dynamically changed but must obey the specified timing restrictions. Itis sampled once only by the transputer, before the first instruction is executed after Reset is taken low. If BootFromROM is connected high (e.g. to VDD) the transputer starts to execute code from the top two bytes in external memory, at address #7FFE. This location should contain a backward jump to a program in ROM. Following this access, BootFromROM may be taken lowif required. The processor is in the low priority state, and the W register points to MemStart (page 11). !f BootFromROM is connected low (e.g. to GND) the transputer will wait for the first bootstrap message to arrive on anyone ofits links. The transputeris ready to receive the first byte ona link within two processor cycles TPCLPCL after Reset goes low. If the first byte received (the control byte) is greater than 1 it is taken as the quantity of bytes to be input. The following bytes, to that quantity, are then placedin internal memory starting at location MemStart. Fol- lowing reception of the last byte the transputer will start executing code at MemStartas a low priority pro- cess. BootFromROM may be taken high after reception of the last byte, if required. The memory space immediately above the loaded code is used as work space. A byte arriving on other links after the control byte has been received and on the bootstrapping link after the last bootstrap byte, will be retained and no acknowledge will be sent until a process inputs from them. ss)_y-seesmommgoyy Me 7929237 0090741 EST

3.6 Peek and poke

Any location in internal or external memory can be interrogated and altered when the transputer is waiting for a bootstrap from link. If the control byte is 0 then four more bytes are expected on the same link. The first two byte word is taken as an internal or external memory address at which to poke (write) the second two byte word. If the control byte is 1 the next two bytes are used as the address from which to peek (read) a word of data; the word is sent down the output channel of the same link. Following such a peek or poke, the transputer returns to its previously held state. Any number of accesses may be made in this way until the control byte is greater than 1, when the transputer will commence read- ing its bootstrap program. Any link can be used, but addresses and data must be transmitted via the same link as the control byte. 3.7. Reset Reset can go high with VDD, but must at no time exceed the maximum specified voltage for VIH, After VDDis valid Clockin should be running fora minimum period TOCVRL before the end of Reset. The falling edge of Reset initializes the transputer and starts the bootstrap routine. Link outputs are forced low during reset; link inputs and EventReq should be held low. Memory request (DMA) must not occur whilst Reset is high but can occur before bootstrap (page 23). If BootFromROM is high bootstrapping will take place immediately after Reset goes low, using data from external memory; otherwise the transputer will await an input from any link. The processor will be in the low priority state.

3.8 Analyse

{f Analyse is taken high when the transputer is running, the transputer will halt at the next descheduling point (page 46). From Analyse being asserted, the processor will halt within three time slice periods plus the time taken for any high priority process to complete. As much of the transputer status is maintained as is necessary to permit analysis of the halted machine. Processor flags Error and HaltOnError are not altered at reset, whether Analyse is asserted or not. Input links will continue with outstanding transfers. Output links will not make another access to memory for data but will transmit only those bytes already in the link buffer. Providing there is no delay in link ac- knowledgement, the links should be inactive within a few microseconds of the transputer halting. Reset should not be asserted before the transputer has halted and link transfers have ceased. IfBoot- FromROM is high the transputer will bootstrap as soon as Analyse is taken low, otherwise it will await acontrol byte on any link. If Analyse is taken low without Reset going high the transputer state and opera- tion are undefined. After the end of a valid Analyse sequence the registers have the values given in table 3.3.

1 MemStart if bootstrapping from a link, or the external memory bootstrap address if bootstrapping

from ROM. W_ | MemStart if bootstrapping from ROM, or the address of the first free word after the bootstrap program if bootstrapping from link. A The value of | when the processor halted. B The value of W when the processor halted, together with the priority of the process when the transputer was halted (i.e. the W descriptor). c The ID of the bootstrapping link if bootstrapping from link. Table 3.3. Register values after Analyse Me 7929¢e37? OOIO74e Sob

3.9 Error

The Error pin is connected directly to the internal Errorlag and follows the state of that flag. If Error is high it indicates an error in one of the processes caused, for example, by arithmetic overflow, divide by Zero, array bounds violation or software setting the flag directly (page 46). Once set, the Errortlag is only cleared by executing the instruction festerr. The erroris not cleared by processor reset, in order that analy- sis can identify any errant transputer (page 8). Aprocesscan be programmed to stopif the Errortlag is set; it cannot then transmit erroneous data to other Processes, but processes which do not require that data can still be scheduled. Eventually all processes which rely, directly or indirectly, on data from the Process in error will stop through lack of data. By setting the Ha/tOnErrortlag the transputer itselfcan be Programmed to halt if Errorbecomes set. If Error becomes set after Ha/tOnErrorhas been set, all processes on that transputer will cease but will not neces- sarily cause other transputers in a network to halt. Setting Ha/tOnErroratter Errorwill not cause the trans- puter to halt; this allows the processor reset and analyse facilities to function with the flags in indeterminate states. An alternative method of error handling is to have the errant Process or transputer cause all transputers to halt. This can be done by applying the Error output signal of the errant transputer to the EventReq pin of a suitably programmed master transputer. Since the Process state is preserved when stopped by an error, the master transputer can then use the analyse function to debug the fault. When using sucha circuit, note that the Error flag is in an indeterminate state on power up; the circuit and software should be de- signed with this in mind. Error checks can be removed completely to optimize the performance of a proven Program; any unex- Pected error then occurring will have an arbitrary undefined effect. Ifa high priority process pre-empts a low Priority one, status of the Errorand HaltOnErrorflags is saved for the duration of the high priority process and restored at the conclusion of it. Status of the Errorflag is transmitted to the high priority process but the HaltOnErrortlag is cleared before the process starts. Either flag can be altered in the process without upsetting the error status of any complex operation being carried out by the pre-empted low priority process. Inthe event of a transputer halting because of Ha/tOnError, the links will finish outstanding transfers before shutting down. If Analyse is asserted then all inputs continue but outputs will not make another access to memory for data. After halting due to the Evrorflag changing from 0 to 1 whilst Ha/tOnErroris set, register | points two bytes Past the instruction which set Error. After halting due to the Analyse pin being taken high, register! points one byte past the instruction being executed. in both cases|I will be copied to register A. Master Analyse Slave Slave itch T It | 7 it Reset Error[0) Error[1] Event Slave Slave (transputer links not shown) Transputer ! Transp uter Error[2] a Error(3] Figure 3.5 Error handling in a multi-transputer system 47, Shoes ise mm 7929237 OO90744 369 me

4 Memory

The IMS T225 has 4 Kbytes of fast internal static memory for high rates of data throughput. Each internal memory access takes one processor cycle ProcClockOut. The transputer can also access an additional 60 Kbytes of external memory space. Internal and external memory are part of the same linear address space. Internal RAM can be disabled by holding DisableIntRAM high. All internal addresses are then mapped to external RAM. This pin should not be altered after Reset has been taken low. IMS T225 memory is byte addressed, with words aligned on two-byte boundaries. The least significant byte of a word is the lowest addressed byte. The bits in a byte are numbered 0 to 7, with bit 0 the least significant. The bytes are numbered from 0, with byte 0 the least significant. In general, wherever a value is treated as a number of component values, the components are numbered in order of increasing numerical significance, with the least significant compo- nent numbered 0. Where values are stored in memory, the least significant component value is stored at the lowest (most negative) address. Internal memory starts at the most negative address #8000 and extends to #8FFF. User memory begins at #8024; this location is given the name MemStart. An instruction /dmemstartvalis provided to obtain the value of MemStart. The context of a process in the transputer model involves a workspace descriptor (WPtr) and an instruc- tion pointer (IPtr). WPtr is a word address pointer to a workspace in memory. IPtr points to the next instruc- tion tobe executed for the process which is the currently executing process. The context switch performed by the breakpoint instruction swaps the WPtr and IPtr of the currently executing process with the WPtr and IPtr held above MemStart. Twocontexts are held above MemStart, one for high priority and one for low priority; this allows processes at both levels to have breakpoints. Note that on bootstrapping from a link, these contexts are overwritten by the loaded code. If this is not acceptable, the values should be peeked from memory before bootstrapping from a link. The reserved area of internal memory below MemStart is used to implement link and event channels. Twowords of memory are reserved for timer use, 7PtrLocO for high priority processes and 7PtrLoc? for low priority processes. They either indicate the relevant priority timer is not in use or point to the first pro- cess on the timer queue at that priority level. Values of certain processor registers for the current low priority process are saved in the reserved /ntSave- Loc locations when a high priority process pre-empts a low priority one. External memory space starts at #9000 and extends up through #0000 to #7FFF. ROM bootstrapping code must be in the most positive address space, starting at #7FFE. Address space immediately below this is conventionally used for ROM based code. ais 7, TNs mm 7929237 0090745 2TS me

hi Machine map lo Byte address Word offsets occam map #9000 — Start of external memory —#0800 [ko par ron rs Notes

1 These locations are used as auxiliary processor registers and should not be manipulated by the

user. Like processor registers, their contents may be useful for implementing debugging tools (Analyse, page 8). For details see the 7ransputer Instruction Set — A Compiler Writers’ Guide. Figure 4.1 IMS T225 memory map ages ss mm 7929237 OOFO74b 13]

5 External memory interface

The IMS 7225 External Memory Interface (EMI) can access a 64 Kbyte physical address space, and pro- vides a sustained bandwidth of 30 Mbytes/sec. It accesses a 16 bit wide address space via separate ad- dress and data buses. The data bus can be configured for either 16 bit or 8 bit memory access, all lowing the use of a single bank of byte-wide memory. Both word-wide and byte-wide access may be mixedin a single memory system (see section 5.5). The timing parameters given in this chapter are based on tests on a limited number of samples and may change when full characterization is completed. The external memory cycle is divided into four Tstates with the following functions: T1_ Address and control setup time. T2 Data setup time. T3 Data read/write. T4 Data and address hold after access. Each Tstate is half a processor cycle TPCLPCL long (see section 5.2). An external memory cycle is al- ways a complete number of cycles TPCLPCL in length and the start of T1 always coincides with a rising edge of ProcClockOut. T2 can be extended indefinitely by adding externally generated wait states of one complete processor cycle each. During an internal memory access cycle the external memory interface address bus MemA0-15 reflects the word address used to access internal RAM, notMemWrB0-1 and notMemCE are inactive and the data bus MemD0-15's tristated. This is true unless and until a DMA (memory request) activity takes place, when the lines will be placed in a high impedance state by the transputer. Bus activity is not adequate to trace the internal operation of the transputer in full, but may be used for hardware debugging in conjunction with peek and poke (page 8). Procclockout = ff Vf LS notMemWrB0-1 __Y Write ~~ Read Read XY _ MemA0-15 ___X_ Address X Address X Address X_ MemD015 ©} Figure 5.1 IMS 7225 bus activity for 3 internal memory cycles aise 47, FENN mm 7929237 0090747 O73 mf

Figure 5.2 below shows an example of an IMS T225 being used in a static RAM application. Geppius oo al L ses rs Clockin pmnus Z : (5MHz) GND Linkin Error 100K | notMemCE notMemWrBO LinkoOut ——> 56R IMS LinktIn + MemD8-11 i. 5 Link2in 6 lem Li is Link3In “- eK 4 inka IStatic Link3out {48 Lin MemD0-3 16K 4] |RAM Static Reset RAM Analyse Memmor | MemGranted Figure 5.2 IMS T225 static RAM application

5.1 Pin functions

5.11 MemA0-15

External memory addresses are output on a non-multiplexed 16 bit address bus (MemA0-15). The ad- dress is valid at the start of T1 and remains so until the end of T4. Byte addressing is carried out internally by the IMS T2265 for read cycles. For write cycles the relevant bytes in memory are addressed by the write enables notMemWrB0-1.

5.1.2 MemD0-15

The non-multiplexed data bus (MemD0-15) is 16 bits wide. Read cycle data may be set up on the bus. at any time after the start of T1, but must be valid when the IMS 7225 reads it during T4, Data can be re- moved any time after the rising edge of notMemCE, but must be off the bus no later than the middle of T1, which allows for bus turn-around time before the data lines are drivenat the start of T2 ina Processor write cycle. Write data is placed on the bus at the start of T2 and removed at the end of T4. The writing of data into memory is normally synchronized to notMemCE going high. The data bus is high impedance except when the transputer is writing data. If onlyone byte is being written, the unused 8 bits of the bus are high impedance at that time. ee 15/56 Ee 7929237 0090748 TOY

5.1.3 notMemWrB0-1 Twowrite enables are provided, one to write each byte of the word. When writing a word, both write enables are asserted; when writing a byte only the appropriate write enable is asserted. notMemWrB0 addresses the least significant byte. ‘The write enables are synchronized with the chip enable signalinotMemCE, allowing themto beused with- out notMemCE for simple designs. Data may be strobed into memory using notMemWrB0-1 without the use of notMemCE, as the write en- ables go high between consecutive external memory write cycles. The write enables are placed in a high impedance state during DMA, and are inactive during internal memory access. 5.1.4 notMemCE The active low signal notMemCE is used to enable external memory on both read and write cycles. 5.1.5 | MemBAcc The IMS T225 performs word access at even memory locations. Access to byte-wide memory can be achieved by taking MemBAcc high. Where all external memory operations are to byte-wide memory, MemBAcc may be wired permanently high. The state of this signal is latched during T2. |f MemBAcc is low then a full word will be accessed in one external memory cycle, otherwise the high and low bytes of the word will be separately accessed during two consecutive cycles. The first (least significant) byte is accessed at the word address (MemA0 is low). The second (most significant) byte is accessed at the word address +1 (MemA0 is high).

5.1.6 MemWait

If the data setup time for read or write is too short it can be extended by inserting wait states at the end of T2 (see section 5.6). Waitstates can be selected by takingMem Wait high. MemWait is sampled during T2, and should not change state in this region. Internal memory access is unaffected by the number of wait states selected.

5.1.7 MemReq, MemGranted

Direct memory access (DMA) can be requested at any time by taking the asynchronous MemRegq input high. MemGranted can be used to signal to the device requesting the DMA that it has control of the bus. For external memory cycles, the IMS T225 samples MemReq during the first high phase of ProcClockOut afternotMemCE goes low. In the absence of an external memory cycle, MemReq is sampled during every rising edge of ProcClockOut. MemA0-15, MemD0-15, notMemWrB0-1 and notMemCE are tristated be- fore MemGranted is asserted.

5.1.8 ProcClockOut

This clock is derived from the internal processor clock, which is in turn derived from Clockin (see sec- tion 5.2). ‘sist ST Ss mm 7929237 0090749 940

5.2 Processor clock

This clock is derived from the internal processor clock, which is in turn derived fromClockin, Its period is equal to one internal microcode cycle time, and can be derived from the formula TPCLPCL = TDCLDCL / PLLx where TPCLPCL is the ProcClockOut Period, TDCLDCL is the Clockin Period and PLLx is the phase lock loop factor for the relevant speed part, obtained from the ordering details (refer to section 10). Edges of the various external memory strobes are synchronized by, but do not all coincide with, rising or falling edges of ProcClockOut. 7225-25 Parameter [in [ma TPCLPCL ProcClockOut period 38 42 ns TPCHPCL | ProcClockOut pulse width high 14 26 ns TPCLPCH | ProcClockOut pulse width low a ns 23 TPCstab ProcClockOut stability 8 % 1 Notes

1 Stability is the variation of cycle periods between two consecutive cycles, measured at corre-

‘sponding points on the cycles. 2 ais TPCLPCL-TPCHPCL. 3. This is a nominal value. Table 5.1 ProcClockOut TPCLPCH TPCHPCL TPCLPCL Figure 5.3 IMS T225 ProcClockOut timing _ Si ——_ zis mm 7929237 0090750 bbe

5.3 Read cycles

External memory addresses are output on the non-multiplexed 16 bit address bus (MemA0-15). The ad- dress is valid at the start of T1 and remains so until the end of T4, with the timing shown in figure 5.4. Byte addressing is carried out internally by the IMS T225 for read cycles, The non-multiplexed data bus (MemD0-15) is 16 bits wide. Read cycle data may be set up on the data bus at any time after the start of T1, but must be valid when the IMS 7225 reads it during T4. Data can be removed any time after the rising edge of notMemCE, but must be off the bus no later than the middle of T1, which allows for bus turn-around time before the data lines are driven atthe start ofT2 in a processor write cycle. 7225-25 Parameter [in [Max | TAVEL Address valid before chip enable low 6 ns 1 TELEH | Chip enable low 54 66 ns 1 TEHEL | Delay before chip enable re-assertion 15 ns 1,2 TEHAX | Address hold after chip enable high 1 ns 1 TELDrV | Data valid from chip enable low 0 40 ns TAVDrV | Data valid from address valid 0 53 ns TDrVEH | Data setup before chip enable high 17 ns TEHDrZ | Data hold after chip enable high 0 ns TWEHEL | Write enable setup before chip enable low 16 ns 3 TPCHEL | ProcClockOut high to chip enable low 4 17 ns 1 TEHPCH | Chip enable high to ProcClockOut high 5 ns Notes 1 This parameter is common to read and write cycles and to byte-wide memory accesses. 2 These values assume back-to-back external memory accesses. 3 Timing is for both write strobes notMemWrB0-1. Table 5.2 Read Tstate | if | 12 | 13 | 14 | 1 ProcClockOut TPCHEL }-TEHPCH MemA0-15 TAVEL f TEHAX | TELEH TEHEL notMemCE | TAVDrV TDrVEH TELDrV f-TEHD?Z MemD0-15 | > TWEHEL | notMemWrBo-1 _/ \\ | Figure 5.4 IMS T225 external read cycle M@™ 7929237 0090751 STo

5.4 Write cycles

For write cycles the relevant bytes in memory are addressed by the write strobes notMemWrB0-1. Write data is placed on the data bus (MemDO-15) at the start of T2 and removed at the end of T4. It is normally written into memory in synchronism with notMemCE going high. Twowrite strobes are provided, one to write each byte of the word. When writing a word, both write strobes are asserted; when writing a byte only the appropriate write enable is asserted.notMemWrB0 addresses the least significant byte. The IMS T225 will, by default, perform word access at even memory locations, this is termed word access mode. Access to byte-wide memory can be achieved by taking the MemBAcc signal high, this is termed byte access mode (see section 5.5.2). In word access mode a full word will be accessed in one external memory cycle, in byte access mode the high and low bytes of the word willbe separately accessed during two consecutive cycles. Both word-wide and byte-wide access may be mixed in a single memory system. Figure 5.6 showsa write access of the least significant byte of the word when in word access mode (Mem- BAcc low). MemA0 is low to signify access of the least significant byte of the word at the word address. Data may be strobed into memory using notMemWrB0-1 without the use of notMemCE, as the write strobes go high between consecutive external memory write cycles. The write strobes are placed in a high impedance state during DMA, and are inactive during internal memory access. 7225-25 Parameter [in Te | TDWVEH | Data setup before chip enable high 40 TEHDwZ | Data hold after write 3 20 TDWZEL | Write data invalid to next chip enable 1 TWELEL | Write enable setup before chip enable low -3 3 1 TEHWEH | Write enable hold after chip enable high -3 3 1 Notes 1 Timing is for both write strobes notMemWrB0-1. Table 5.3 Write Tstate m1 | v2 | 13 | tT | 11 | ProcClockOut MemA0-15 notMemCE \\ i S

7 TDwZEL

MemDo-15, TWELEL [TeHweH notMemWrBo-1 Figure 5.5 IMS T225 external write cycle 5.099 ——__se We 7929237 0090752 435

Tstate | M1 | 2 | 13 | m4 | 1 | 12 ProcClockOut —/ NS MemA1-15 Xe Psy AGOSS eas X MemAO \\ / notMemCE \\ / \\ | MemD0-7 (Least significant byte) | MemD8=15 |) | notMemWrBO \\ / \\ notMemWrB1 7 \\ Figure 5.6 IMS T225 least significant byte write in word access mode

5.5 MemBAcc

The IMS T225 will, by default, perform word access at even memory locations. Access to byte-wide memory can be achieved by taking MemBAcc high with the timing shown. Where all external memory operations are to byte-wide memory, MemBAcc may be wired permanently high. The state of this signal is latched during T2. Where external memory operations may be to both byte and word wide memory, MemBAcc should be obtained by address decoding. If you use a memory system in which word wide memory may be used in byte access mode it is recommended that notMemWrB1 is OR gated with MemAQ, to prevent any spurious data being written to the RAM. If MemBAcc is low then a full word will be accessed in one external memory cycle, otherwise the high and low bytes of the word will be separately accessed during two consecutive cycles. The first (least significant) byte is accessed at the word address (MemA0 is low). The second (most significant) byte is accessed at the word address +1 (MemA0 is high). 5.5.1. Word Read/Write in Byte Access Mode With MemBAcc high, the first cycle is identical with a normal word access cycle. However, it will be imme- diately followed by another memory cycle, which will use MemD0-7 to read or write the second (most sig- nificant) byte of data. During this second cycle, fora write, notMemWrBO0-1 both go lowas in the first cycle and MemA0 goes high. For a read, notMemWrB0-1 remain high and MemA0 goes high. MemD8-15 are high impedance for both read and write in the second cycle. Figure 5.7 shows a word write to byte-wide memory. us _gysggeqpoqwmoyy mw 7929237 0090753 37] a

Tstate |. T1 | 12 | 13 | tT | m1 | t2 | 13 | 14 | 1 ProcClockOut SJ \\_/ \\/ \\/ VS! MemAO \\ / \\ Memp0-7 Wostsignieart bye) —{ MemD8-15 Most significant byte —_— notMemCE TEHWEH =| TWELEL TWELEL _ notMemWrBO =| TWELEL notMemWrB1 MemBAcc TELBAH TELBAL Figure 5.7 IMS T225 word write to byte-wide memory

5.5.2 Byte Write in Byte Access Mode

Writing a Most Significant Byte In the first cycle notMemWrB1 will go low and notMemWrB0 will remain high. MemA0 remains low. In the second cycle MemA0 goes high and notMemWrBO0-1 go low. The data is written on MemDO0-7 in the second cycle. Figure 5.8 shows a write access of the most significant byte of the word when in byte access mode (Mem- BAcc high). During the first access a normal word access is performed with notMemWrB1 active low to select the most significant byte. During the second cycle, MemD0-7 writes the most significant byte ac- cessed at word address + 1 (MemA0 is high). Writing a Least Significant Byte In the first cycle notMemWrB1 remains high and notMemWrB0 goes low. MemA0 remains low. In the second cycle MemAO and notMemWrB0 go high, notMemWrB1 remains high. Data is written on MemD0-7 in the first cycle. TELBAH | MemBAcc high from chip enable 10 TELBAL |MemBAcc low from chip enable 27 Table 5.4 Byte-wide memory access ssp se me 7929237 0090754 208

Tstate [tm | 12 | 13 | 1a TA T2 | 13 ™ | 1 ProcClockOut Memat-18 | MemAO \\ / \\ | MemDo-7 | notMemCE | TEHWEH: TWELEL TWELEL | notMemWrBO TWELEL notMemWrB1 | MemBAcc | TELBAH TELBAL | Figure 5.8 IMS T225 most significant byte write to byte-wide memory 2S __7ses-mowpoy mm 792923? 0090755 144 mm

5.6 Wait

Wait states can be selected by taking MemWait high. MemWait is sampled during T2, and should not change state in this region. Await state is one processor cycle TPCLPCL long and comprises the pairW1 and W2, each half a proces- sor cycle long (see figure 5.9). If MemWait is still high when sampled in W2 then another wait period will be inserted. This can continue indefinitely. Internal memory access is unaffected by the number of wait states selected. The setup and hold timing requirements for MemWait are the same as for a normal word read/write cycle. Each wait state inserted extends the length of MemA0-15, MemD0-7, notMemCE, and notMemWrBo by one ProcClockOut cycle (TPCLPCL). If wait states are required to extend a byte access cycle, then the time in the cycle at which MemBAcc needs to be asserted is delayed (relative to the falling edge ofnotMemCE) by one TPCLPCL for each wait State inserted (see figure 7.9). MemWait also needs to be re-asserted for the second byte accessed (MemA is high), to extend this cycle. The timing requirements of the second assertion of wait are identical to the first except that the timing is relative to the equivalent rising edge of ProcClockOut in the second byte access. Note that the number of wait states inserted in the even and odd byte accesses can be different. 7225-25 Parameter [ain [ma TPCHWIH | MemWait asserted after ProcClockOut high TPCHWIL | MemWait low after ProcClockOut high Table 5.5 Memory wait Tstate | T1 | T2 | Wi| W2} 73 | T4 | T1 | T2 | w1| we| 73 | T4 ProcClockOut MemA1-15 MemAO \\ notMemCE notMemWrBO TPCHWIL* MemWait ~ TPCHWtH MemBAcc TELBAH+TPCLPCL * J TELBAL+TPCLPCL MemD0-15 = Least significant byte. ) {Most Significant byte. Figure 5.9 IMS T225 word write to byte wide memory with a single wait state mm 7929237 0090756 O80

The wait state generator can be a simple digital delay line, synchronized tonotMemCE. The Single Wait State Generator circuit in figure 5.10 can be extended to provide two or more wait states, as shown in figure 5.11. VOD 1112 74F74 as Ldap notMemCE D Q MemWait | ProcClockOut cP | j Figure 5.10 Single wait state generator [aan _ H 1 VDD t 1/6 74F04 ds l ds | qk | aR | D Q D Q MemWait | GND cp cp | 12 74F74 | ProcClockOut | ae Figure 5.11 Extendable wait state generator

5.7 Direct memory access

Direct memory access (DMA) can be requested at any time by taking the asynchronous MemReq input high. For external memory cycles, the IMS T225 samples MemRegq during the first high phase of ProcClockOut after notMemCE goes low. In the absence of an external memory cycle, MemReg is sampled during every rising edge of ProcClockOut. MemA0-15, MemD0-15, notMemWrB0-1 and notMemCE are tristated before MemGranted is asserted. Removal of MemReq is sampled at each rising edge of ProcClockOut and MemGranted removed with the timing shown in figure 5.14. Further external bus activity, either external cycles or reflection of internal cycles, will commence during the next low phase of ProcClockOut. notMemCE, notMemWrB0-1, MemA0-15 and MemD0-15 are in a high impedance state during DMA. External circuitry must ensure that notMemCE and notMemWrB0-1 do not become active whilst control is being transferred; it is recommended that a 10K resistoris connected from VDD to each pin. DMA cannot interrupt an external memory cycle. DMA does not interfere with internal memory cycles in any way, al- though a program running in internal memory would have to wait for the end of DMA before accessing external memory. DMA cannot access internal memory. 24/56 $G$") WM 7929237 009075? TL?

DMA allows a bootstrap program to be loaded into external RAM ready for execution after reset. IfMem- Req is held high throughout reset, MemGranted will be asserted before the bootstrap sequence begins. MemReq mustbe high at least one period TDCLDCL of Clockin before Reset. The circuit should be de- signed to ensure correct operation if Reset could interrupt a normal DMA cycle, MemReq MemGranted Reset Bootstrap [8] activity B Bootstrap sequence Figure 5.12 IMS T225 DMA sequence at reset MemReq TTT \\ [/ \\ Internal memory cycles eeemal |tsHra|Tal74] [T1| T2a]wawd Tal T4] terface activi LEM eycle_| interface activity EMI cycle EMI cycle with wait HH} MemGranted / \\ / \\ notMemwrBo-s VX notMemcE = \\ {$Y \\ fOr Memaoas 1X) E> Figure 5.13 IMS 1225 operation of MemReq and MemGranted with external and internal memory cycles Mi 752525? 0090756 953 me

Parameter [in [ma TMRHMGH | Memory request response time 60 a TMRLMGL | Memory request end response time 65 125 TAZMGH _ | Address bus tristate before MemGranted 0 TAVMGL | Address bus active after MemGranted end 0 TDZMGH | Data bus tristate before MemGranted 0 TEZMGH | Chip enable tristate before MemGranted 0 TEVMGL Chip enable active after MemGranted end 6 TWEZMGH | Write enable tristate before MemGranted 0 TWEVMGL | Write enable active after MemGranted end 6 Notes

1 Maximum response time a depends on whether an external memory cycle is in progress and

whether byte access is active. Maximum time is (2 processor cycles) + (number of wait state cycles) for word access; in byte access mode this time is doubled.

2 When using DMA, notMemCE and notMemWrB0-1 should be pulled up with a resistor (typically

10K). Capacitance should be limited to a maximum of 50pF. Table 5.6 Memory request timing Tstate T1 +} T2 | 73 | 14 11 ProcClockOut | MemReq | IRHMGH | ™ ct TMRLMGL MemGranted TAZMGH TAVMGL | MemA0-15 TDZMGH + MemD0-15 TEZMGH I~ | TEVMGL notMemCE TWEZMGH | > TWEVMGL } notMemWrB0-1 | Figure 5.14 IMS T225 memory request timing ms 792923? 0090759 597

6 Events

EventReq and EventAck provide an asynchronous handshake interface between an external event and an internal process. When an external event takes EventReg high the external event channel (additional to the external link channels) is made ready to communicate with a process. When both the event channel and the process are ready the processor takes EventAck high and the process, if waiting, is scheduled. EventAck is removed after EventReq goes low. Only one process may use the event channel at any given time. If no process requires an event to occur EventAck will never be taken high. Although EventReg triggers the channel on a transition from low to high, it must not be removed before EventAck is high. EventReq should be low during Reset; if not it will be ignored until it has gone low and returned high. EventAck is taken low when Reset occurs. If the process is a high priority one and no other high priority process is running, typical latency is 19 full processor cycles TCPLCPL, and maximum latency (assuming all memory accesses are internal) is 53 full processor cycles. Setting a high priority task to wait for an event input allows the user to interrupt a transputer program running at low priority. The time taken from asserting EventReq to the execution of the microcode interrupt handler in the CPU is four cycles. The following functions take place during the four cycles: Cycle 1 Sample EventReq at pad on the rising edge of ProcClockOut and synchronize. Cycle 2 Edge detect the synchronized EventReq and form the interrupt request. Cycle 3 Sample interrupt vector for microcode ROM in the CPU. Cycle 4 Execute the interrupt routine for Event rather than the next instruction. 7225-25 Parameter | Min | Max | TVHKH | EventReq response [) TKHVL | EventReq hold 0 TVLKL Delay before removal of EventAck oO 127 TKLVH Delay before re-assertion of EventReq 0 Table 6.1 Event EventReq TVHKI >| TVLKL TKHVL. TKLV EventAck Figure 6.1 IMS T225 event timing mm 7929237 0090760 501 a

7 Links

Four identical INMOS bi-directional serial links provide synchronised communication between processors and with the outside world. Each link comprises an input channel and output channel. A link between two transputers is implemented by connecting a link interface on one transputer to a link interface on the other transputer. Every byte of data sent on a link is acknowledgedon the input of the same link, thus each signal line carries both data and control information. The quiescent state of a link output is low. Each data byte is transmitted as a high start bit followed by a ‘one bit followed by eight data bits followed by a low stop bit. The least significant bit of data is transmitted first. After transmitting a data byte the sender waits for the acknowledge, which consists of a high start bit followed by a zero bit. The acknowledge signifies both that a Process was able to receive the acknowl- edged data byte and that the receiving link is able to receive another byte. The sending link reschedules the sending process only after the acknowledge for the final byte of the message has been received. The IMS T2285 links support the standard INMOS communication speed of 10 Mbits/sec. In addition they can be used at 5 or 20 Mbits/sec for 25 MHz devices, and 20 Mbits/sec for faster devices. Links are not synchronised with Clockin or ProcClockOut and are insensitive to their phases. Thus links from indepen- dently clocked systems may communicate, providing only that the clocks are nominally identical and within specification. Links are TTL compatible and intended to be used in electrically quiet environments, between devices on a single printed circuit board or between two boards via a backplane. Direct connection may be made be- tween devices separated by a distance of less than 300 millimetres. For longer distances a matched 100 ohm transmission line should be used with series matching resistorsRM. When this is done the line delay should be less than 0.4 bit time to ensure that the reflection returns before the next data bit is sent. Buffers may be used for very long transmissions. If so, their overall propagation delay should be stable within the skew tolerance of the link, although the absolute value of the delay is immaterial. Link speeds can be set by LinkSpecial, LinkOSpecial and Link1 |23Special. The link 0 speed canbe set independently. Table 7.1 shows uni-directional and bi-directional data rates in Kbytes/sec for each link speed; LinknSpecial is to be read as LinkOSpecial when selecting link 0 speed and as Link123Special for the others. Data rates are quoted for a transputer using internal memory, and will be affected by afactor depending on the number of external memory accesses and the length of the external memory cycle. Link Linkn Kbytes/sec Special | Special | Mbits/sec [ uni 7 BF | 0 10 910 1250 1 5 450 670 oO 10 910 1250 1 20 1740 2350 Table 7.1 Speed settings for transputer links eise__yrsge-oqmgoy Mm 792923? 0090761 44a

wTH[oT sje] s[a[ sie] 7|e Paley | Data | | Ack | Figure 7.1 IMS 7225 link data and acknowledge packets [Symbot [Parameter | Min | Nom | Max | Unite | Notes | TJQr LinkOut rise time 20 ns TJQF LinkOut fall time 10 ns TJDr Linkin rise time 20 ns TJD Linkin fall time 20 ns TJQUD Buffered edge delay ns TJBskew | Variationin TJQUD 20 Mbits/s 3 ns

10 Mbits/s 10 ns

5 Mbits/s 30 ns

CLIZ Linkin capacitance @ f=1MHz 7 pF CLL LinkOut load capacitance 50 pF RM Series resistor for 100W transmission line ohms Notes 1. This is the variation in the total delay through buffers, transmission lines, differential receivers etc., caused by such things as short term variation in supply voltages and differences in delays for rising and falling edges. Table 7.2 Link LinkOut TJQr TJQt Linkin 10% en ae TJDr. TJDE Figure 7.2 IMS T225 link timing mM 7929237? OCOd07be 384

8 Electrical specifications

8.1. Absolute maximum ratings [Svasat | PanANETER in [Wak [ONT [WOTES] VDD DC supply voltage 0 7.0 Vv 1,2,3 vi, VO Voltage on input and output pins 0.5 VDD+0.5 v 1,2,3 ii} Input current +25 mA 4 OscT Output short circuit time (one pin) 1 Ss 2 TS Storage temperature 65 150 °C 2 PDmax Maximum allowable dissipation 2 Ww Notes 1 All voltages are with respect to GND. 2. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operating sections of this specification is not implied. Stresses greater than those listed may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

3 This device contains circuitry to protect the inputs against damage caused by high static voltages

or electrical fields. However, it is advised that normal precautions be taken to avoid application of any voltage higher than the absolute maximum rated voltages to this high impedance circuit. Unused inputs should be tied to an appropriate logic level such as VDD or GND.

4 The input current applies to any input or output pin and applies when the voltage on the pin is

between GND and VDD. Table 8.1 Absolute maximum ratings

8.2 Operating conditions

[Srweo | PARAWETER [WIN [WAX [UNTS [NOTES] VDD DC supply voltage 4.75 5.25 Vv 1 VI, VO Input or output voltage 0 VDD Vv 1,2 cL Load capacitance on any pin 60 pF 3 TA Operating temperature range to) 70 °C 4 Notes 1 All voltages are with respect to GND. 2 Excursions beyond the supplies are permitted but not recommended; see DC characteristics. 3 Excluding LinkOut load capacitance. 4 Air flow rate 400 linear ft/min transverse air flow. Table 8.2 Operating conditions mm 7929237 OO907b4 157

8.3 DC electrical characteristics

[svmsoc[—___PARAWETER [WIN [WAX [UNITS [NOTES VIH High level input voltage 2.0 VDD+0.5 Vv 1,2 VIL Low level input voltage -0.5 0.8 Vv 1,2 " Input current @ GND<VI<VDD +10 pA 1,2 VOH Output high voltage @ IOH=2mA VDD-1 Vv 1,2 VOL Output low voltage @ IOL=4mA 0.4 Vv 1,2 1oz Tristate output current @ GND<V0<VDD +10 pA 1,2 PD Power dissipation 700 mW 23 CIN Input capacitance @ f=1MHz 7 pF Coz Output capacitance @ f=1MHz 10 pF Notes 1 All voltages are with respect to GND. 2 Parameters for IMS T225-S measured at 4.75V<VDD<5.25V and 0°C<TA<70°C. Input clock frequency = 5 MHz. 3 Power dissipation varies with output loading and program execution. Table 8.3 DC characteristics mi 7929237 0050765 093

8.4 Equivalent circuits

| Jo. 1.5V D.U.T. 1Mohm SOpF | lou GND Note: This circuit represents the device sinking IOL and sourcing |OH with a 50pF capacitive load. Figure 8.1 Load circuit for AC measurements inputs VDD-1 Ti ov VDD-1 Inputs VIL ov tpHL VDD Outputs 15V ov tpLH VDD Outputs KASV ov Figure 8.2 AC measurements timing waveforms Mm 7929237 00907bb TeT a

$e 22S

8.5 AC timing characteristics

SYMBOL PARAMETER [| MIN” | MAX” J UNITS ] NOTES TDr Input rising edges 20 2 TDf Input falling edges 20 1,2 TQr Output rising edges 25 1 TOf Output falling edges 15 1 Notes 1 Non-link pins; see section on links. 2 All inputs except Clockin; see section on Clockin. Table 8.4 Input and output edges TDt TDr | Tar Tar | Figure 8.3 IMS T225 input and output edge timing j 30 30 Rise time Rise time Time*° Time ns ir Fall time 10 a Fall time ns 10 | 40 60 80 100 40 60 80 100 Load capacitance pF Load capacitance pF Link EMI Figure 8.4 Typical rise/fall times ase ___ysse-myowgpoy @ 7929237 0090767 Ibb

8.6 Power rating

Internal power dissipation Piz of transputer and peripheral chips depends onVDD, as shown in figure 8.5. Pinr is substantially independent of temperature. 600 T. 25 500 225- Power PINT mw 400 300 44°46 48 50 52 54 56 VDD Volts Figure 8.5 IMS T225 internal power dissipation vs VDD Total power dissipation Pp of the chip is Pp =Pint +Pio where Pig is the power dissipation in the input and output pins; this is application dependent. Internal working temperature T, of the chip is Ty =Ta #84ax Po where Ta is the external ambient temperature in °C and 6 ya is the junction-to-ambient thermal resistance in°CM. Further information about device thermal characteristics can be found in section 9.4. mm 7929237 00907b8 472

9 Package details

94 68 pin grid array package 1 2 3 4 5 6 z 8 9 10 cop | tinko | Proc Link | Link | Link | Link ] Link ] Pisoble! | Pius | special Soc ind | Outr | out2 | ine | ind | ent,

5 OOO OF ©

roe. Link | Linkt23] Link | Link | Link roe, Oo Om ROM Woit © 7, © roc Mi ° mncex of © © , Jy 68 pin grid array ous . oc “ i i © o ‘ oG D4 az | Ao © © 07 Al O-© O- J Mem Mem Mem Al3 AT AS OOOO DI3 | O15 Figure 9.1 IMS T225 68 pin grid array package pinout 36/56 568 Si me 7929237 0090769 739 a

PAT OTS TONE TOGO 3 425 TST 4. 6F ee ee | i a a 2 Agr oes 1 o.097 Toro {aise T “244 2790] ep ook acie oozo toate | Gaar | Oco Ie toso Tt .0eg | L070 | 26.6701 26,924 27178 |

1 Sl a

eT —— Td ioopsc] =F sans Et Oso [1.060 {5070 | 25.6701 26.934 | 27178 | Oe | A SA A Az A k-—— D —| Al 4 a ws 4 a 4 = ede wo 987654 321 t SSCODODOOOB|A ©OOOOOOOOO!A ee @@!op ee @OlF ® ©e/c G@OOOOOOOOO!) sa Zn nai lpdu © 200000000)x ky7 SGS-THOMSON i SIF iMicRoetecrnonics PACKAGE OUTLINE:

68 CERAMIC PIN GRID ARRAY

[Eades as ux asf RP 99-0600 Figure 9.2 IMS T225 68 pin grid array package dimensions (7 OMS suis me 7929237 0090770 450 mm

9.2 68 pin PLCC J-bend package Bw » Bess CONG _ s esc 8308 20% Sa2nd 20449950, CS0S9S505e Ga OL Se B0PZELVLVLS§ S8ssssfesssssescs 0003550 s 3555505550 65 7 ProcSpeedSelect2 (10 Oo 60 ]D DisablelntRAM BootFromROMq pEventAck Reset Q D ProcSpeedSelectO Error p Analyse ProcSpeedelect 15 pMemBAcc lemDOq 55 |D MemWai' Menor IMS 7225 bMemiveg lemD2q 1 H OU MemGranted Momb3q 68 pin plastic DN MemD4q 1 1 pnotMem: MemD5 | 20 chip carrier 9 pnotMemvirBo GND ; DnotMemWrB1 MemD6 top view OMemAO MemD7g DMemAt MemD8q DMemA2 MemD9q| 25 45 |DMemA3 MemD10q 30 35 40 DMemA4 S600622S22t5 SESSESE ESS5SS555 2353255 222 57=F 72 Figure 9.3 IMS T225 68 pin PLCC J-bend package pinout Bm 7929237 OO90771 397

[ow [2 ouENSONS wo [ATER MENGES [om] vesenrneon Toa] rr | Lez Toss | ogo 10930 | 22.6061 23114 | 23622 | a TY | Cai 10.042 T= 0.056 T1067 [3.4224 A M + Fe de O wp 7 q b q b a dt, af r d b 83 - poo gee q b q b ot thes ali - | »D 38 40 iF D c As = DiItiou 1 oxi es depocenent tom | VA iVGROELECTRONICS notional centre line = £0.007". PACKAGE OUTLINE

68 PLASTIC LEADED CHIP_CARRIER

[EWakefeld awe dal 99-6510 lk YX. Maraplele gangs | __jAq4] _ 99-6510 Bi} Figure 9.4 IMS T225 68 pin PLCC J-bend package dimensions gy ss:ngy is B® 7929237 0090772 223

9.3 100 pin cavity-up ceramic quad flat pack (CQFP) package g 8 3 i Boro nima-0o B 2 BEtOEETETE S8308 ofe 9 LSSSSESISTIIOE ESLS BS AAA NC oj 95 90 85 80 Sr Proc’! dSelect2 Memb'5 == 75) |= NC MemD11 cr F==> NC MemD12 =o E=> CopMinus mD14 cao ES Clockin Memb ih IMS 7225 70||F=>5 LinkSpecial lem. a | + Ht -— Lin ecial MemAl4 co 100 pin ceramic —a Link 2$Specia 1b) = uad flatpack ES voy rout a | ris == = | ray =e lemA10 ar . E=5 CinkOu MemA9 ——I|99 ( Cavity Up ) F= Linkin MemA8 60| |= LinkOut2 MemA7 Cr F—3 LinkIn2 MemA6 Cx F=> LinkOut3 MemA5 =| = Linking NC Cr 25 -— GND NC oc 55//--=— EventReq NC cc = NC N¢ oo -== NG N¢ oo =e NC Coro—1 39 35 40 45 50 += NC UOOUCCUOUUOOOUOOd ooo SEEsEESE Oo Eeseluss= GSOLOES SD gsSetesec

22272555 GLSEEHSS

220 €>22 Bas ee" 3 a 8 2 GS a Figure 9.5 IMS T225 100 pin cavity-up ceramic quad flat pack package pinout “CUS ____ ky segemwowpsony mm 7929237 0090773 1LbT a

ou CONTECH DIMENSIONS. run} ALTERNATIVE DMENSONS, Nox] ___FEYSIONS Se a a Te faz == ors = a ra ozo = Toast pope = oo] rc rots [= 10.230 19.095 T= 19-099] ro asesol = ——Tad'iso og T= 1 ossi | 4-p Tot 119.800 | 70.000-120-2001 0.780 7a7 10.785 oMIN CC A eZ } re ipeso| = igisol ogas | — [-o715 | Pei ise4ol 14.000 [14 isol-o545 1 oss1 [0587] r & a eT 4 Se | a A A a 4 i a a i o AE | ra] [E] ¢ (Seating Plane Coplanarity) FARRAR AAA = sg = a | \\== = | = |= = a3 a =s ° / = TY a UUOUGOUUUGUONOdOOUU E A Notes; e———— 1. Moximum lead csplacement trom iE7 SGS-THOMSON natal conte the = 202m SYM iMicROELscrRONICS PACKAGE OUTLINE: CAVITY UP.

100 CERAMIC QUAD FLATPACK

[PeRratyts ss woes [RP 99-6008 Figure 9.6 IMS T225 100 pin cavity-up ceramic quad flat pack package dimensions ms 7929237 0090774 OTb a

9.4 Thermal specification

The IMS 7225 is tested to a maximum silicon temperature of 100°C. For operation within the given specifi- cations, the case temperature should not exceed 8PC. For temperatures above 85°C the operation of the device cannot be guaranteed and reliability may be impaired. For further information on reliability refer to the SGS-THOMSON Microelectronics Quality and Reliability Program. Be 7929237 0090775 132 a

This section indicates the designation of speed and Package selections for the various devices. Speed of Clockin is 5 MHz for all parts. Transputer Processor cycle time is nominal; it can be calculated more exactly using the phase lock loop factor PLLx, as detailed in the external memory interface section 5. For availability contact your local SGS-THOMSON sales office or authorized distributor. SGS-THOMSON | Processor Processor | PLLx | Package designation clock speed | cycle time IMS T225-G25S 25.0 MHz [4ons | 5.0 | 68 pin ceramic pin grid array IMS T225-J25S 25.0MHz [ 40ns [5.0 [68 pin PLCC J-bend IMS T225-F25S 25.0 MHz [40ns [5.0 | 100 pin ceramic quad flat pack Table 10.1 IMS T2285 ordering details An extended temperature version is available, see the /MS T225E Datasheet tor details. 57, esey —___wss mm 7929237 0090776 979 a

11.‘ Transputer instruction set summary

11.1 Introduction

The Function Codes table 11.9 (page 48) gives the basic function code set. Where the operand value is less than 16, a single byte encodes the complete instruction. If the operand value is greaterthan 15, one prefix instruction (pfix) is required for each additional four bits of the operand. If the operand is negative the first prefix instruction will be nfix. Examples of prefix coding are given in table 11.1. Mnemonic Function code Memory code ide #3 #4 #43 loc #35, is coded as pfix #3 #2 #23 Ide #5 #4 #45 lac #987 is coded as plix #9 #2 #29 plix #8 #2 #28 loc #7 #4 #47 toc -31 ( /dc #FFFFFFE1) ( /de #FFE1) t is coded as ntix cal #6 #61 loc #1 #4 #41 t IMS 7222, IMS T225 Table 11.1 prefixcoding Tables 11.10 to 11.30 (pages 48-55) give details of the operation codes. Where an operation code is less than 16 (e.g. adc operation code 05), the operation can be stored as a single byte comprising the operate function code F and the operand (5 in the example). Where an operation code is greater than 15 (e.g. /adat operation code 16), the prefix tunction code 2 is used to extend the instruction. Mnemonic Function code Memory code add (op. code #5) #F5, is coded as opr add #F #F5 ladd (op. code #16) #21F6 is coded as plix #1 #2 #21 opr #6 #F #F6 Table 11.2 operate coding 44/56 5GS St me 7929237 0090777 405 a

11 Transputer instruction set summary

11.1.1 Product identity numbers

The load device identity (/ddevio) instruction (table 11.10) pushes the device type identity into the A regis- ter. Each productis allocated a unique group of numbers for use with the /ddevidinstruction. Product identi- ty numbers are given in table 11.3. [Product | Identity numbers IMS T425 0 to 9 inclusive IMS T805 10 to 19 inclusive IMS T225 40 to 49 inclusive IMS T400 50 to 59 inclusive Table 11.3 Product identity numbers

11.1.2 Floating point unit

In the floating point unit (FPU) basic addition, subtraction, multiplication and division operations are per- formed by single instructions. However, certain less frequently used floating point instructions are selected by a value in register A (when allocating registers, this should be taken into account). A /oad constantin- struction /dc is used to load register A; the floating point entryinstruction fpentry then uses this value to select the floating point operation. This pair of instructions is termed a se/ector sequence. In the Floating Point Operation Codes tables 11.23 to 11.29, a selector sequence code is indicated in the Memory Code column by s. The code given in the Operation Code columnis the indirection code, the oper- and for the /dc instruction. The FPU and processor operate concurrently, so the actual throughput of floating point instructions is bet- ter than that implied by simply adding up the instruction times. For full details see Transputer Instruction Set—A Compiler Writer's Guide.

11.1.3 Notation

The Processor Cycles column refers to the number of periods TPCLPCL (refer to ProcClockOut) taken by an instruction executing in internal memory. The number of cycles is given for the basic operation only; where the memory code for an instruction is two bytes, the time for the prefix function (one cycle) should be added. Some instruction times vary. Where aletter is included in the cycles column itis interpreted from table 11.4. [ Ident | Interpretation b Bit number of the highest bit set in register A. Bit 0 is the least significant bit. mt | Bit number of the highest bit set in the absolute value of register A. Bit 0 is the least signifi- cant bit. n Number of places shifted. w Number of words in the message. Part words are counted as full words. If the message is not word aligned the number of words is increased to include the part words at either end of the message. Pt | Number of words per row. rt |Number of rows. t does not apply to IMS T225, Table 11.4 Instruction set interpretation 7. ——__sise me 7929237 0050778 741) a

The DEF column of the tables indicates the descheduling/error features of an instruction as described in table . [ene [reste Seo seat D The instruction is a descheduling point 11.2 E The instruction will affect the Error flag 11.3 Ft |The instruction will affect the FP_Error flag 11.6 t applies to IMS T805 only Table 11.5 Instruction features

11.2 Descheduling points

The instructions in table 11.6 are the only ones at which a process may be descheduled. They are also the ones at which the processor will halt if the Analyse pin is asserted (refer to Analyse section). input message output message output byte output word timer alt wait timer input stop on error alt wait jump Joop end end process start process Table 11.6 Descheduling point instructions

11.3 Error instructions

The instructions in table 11.7 are the only ones which can affect the Evrortlag directly. Note, however, that the floating point unit error flag FP_Erroris set by certain floating point instructions (section 11.6), and that Errorcan be set from this flag by fpcheckerror. add add constant subtract multiply fractional multiply + divide remainder Jong add Jong subtract long divide set error testerr fpcheckerror$ check word check subscript from 0 check single check count from 1 t+ does not apply to IMS T225 + applies to IMS T805 only Table 11.7 Error setting instructions

11.4 Debugging support

Table 11.20 (page 52) contains a number of instructions to facilitate the implementation of breakpoints. These instructions overload the operation of /0. Normally /Ois a no-op which might cause descheduling. SetjObreak enables the breakpointing facilities and causes /Oto act as a breakpointing instruction. When breakpointing is enabled, /Oswaps the current Iptr and Wptr with an Iptr and Wptr stored above MemS- tart. The breakinstruction does not cause descheduling, and preserves the state of the registers. Itis pos- sible to single step the processor at machine level using these instructions. Refer to Support for debug- ging/breakpointing in transputers (technical note 61) for more detailed information regarding debugger support.

11.5 Block move

The block move instructions (Table 11.21) move any number of bytes from any byte boundary in memory, to any other byte boundary, using the smallest possible number of word read, and word or part-word writes. ‘The @m 75929237 00590775 646

A block move instruction can be interrupted by a high priority process. On interrupt, block move is com- pleted to a word boundary, independent of start position. When restarting after interrupt, the last word writ- ten is written again. This appears as an unnecessary read and write in the simplest case of word aligned block moves, and may cause problems with FIFOs. This problem can be overcome by incrementing the saved destination (BregIntSaveLoc) and source pointer (CregintSaveLoc) values by BytesPerWord during the high priority process.

11.6 Floating point errors (IMS T805 only)

The FPU has its own error flag FP_Error. This reflects the state of evaluation within the FPU and is set in circumstances where invalid operations, division by zero or overflow exceptions to the ANSI-IEEE 754-1985 standard would be flagged. FP_Erroris also set if an input to a floating point operation is infinite oris nota number (NaN). The FP_Evrorflag can be set, tested and cleared without affecting the main Error flag, but can also set Errorwhen required. Depending on howa program is compiled, itis possible for both unchecked and fully checked floating point arithmetic to be performed. The instructions in table 11.8 are the only ones which can affect the floating point error flag FP_Error. Erroris set from this flag by fpcheckerrorif FP_Erroris set. fpadd fpsub pmul fpdiv Ipidniaddsn fpldniadddb fpldnimulsn fpldnlmuldb fpremfirst fpusqrttirst fpgt fpeq fpuseterror fpuctearerror fptesterror fpuexpincby32 fpuexpdecby32 fpumulby2 fpudivby2 fpur32tor64 fpur64tor32 tpucki32 tpucki64 fprtoi32 fpuabs tpint Table 11.8 Floating point error setting instructions

11.7 General instructions

The following tables list the complete instruction set which is common to all variants of the transputer. Ex- ceptions are noted at the bottom of each table by t or ¢. yy sgsmieseggg vss mm 7929237 0090760 3TT

———_T AN CSS: T2258 esse” | "exo [res [Gee [Pe Code Code Cycles

0 Ox j 3 jump

1 1X IdIp 1 load local pointer 2 2x Pfix 1 prefix 3 3X Idnl 2 load non-local 4 4x Ide 1 load constant 5 5X Idnip 1 load nonlocal pointer 6 6X nfix 1 negative prefix 7 7X Idi 2 load local 8 8X ade 1 add constant 9 9X call 7 call A AX Gj 2 conditional jump (not taken) 4 conditional jump (taken) B BX ajw 1 adjust workspace Cc cx eqc 2 equals constant D Dx stl 1 store local E Ex stnl 2 store non-local F FX opr - operate Table 11.9 Function codes Precio” | esse” | rons | Peace” | DP Code Code Cycles 2A 22FA testpranal 2 test processor analyzing 3E 23FE saveh 4 save high priority queue registers 3D 23FD savel 4 save low priority queue registers 18 21F8 | sthf 1 store high priority front pointer 50 25FO sthb 1 store high priority back pointer 1c 21FC stif 1 ‘store low priority front pointer 17 21F7 stb 1 store low priority back pointer 54 25F4 sttimer 1 store timer 17¢ 2127FC | Iddevid 1 load device identity 7E 27FE Idmemstartval 1 load value of memstart address Table 11.10 Processor initialisation operation codes 8 _ gy-gempqmmoy mm 7929237 0050781 234

Operation | Memory [eee devices | devices 46 24F6 and 1 1 and 4B 24FB jor 1 1 or 33 23F3 | xor 1 1 exclusive or 32 23F2 = | not 1 1 bitwise not 4 24F1 | shi n+2 n+2__| shift left 40 24FO | shr n+2 n+2 | shift right

05 FS add 1 1 add

53 25F3 | mul 23 38 multiply 72 t+ 27F2~ | fmul 35, fractional multiply (no rounding) 40 fractional multiply (rounding) 2c 22FC_ div 24 39 divide 1F 21FF rem 21 37 remainder

09 FO gt 2 2 greater than

04 F4 Giff 1 1 difference

52 25F2 |sum 1 1 sum

08 Fs prod b+4 b+4 | product for positive register A

08 F8 prod m+5, m+5 | product for negative register A

Table 11.11 Arithmetic/logical operation codes Operation | Memory == eee devices | devices 16 21F6 = jladd 2 2 long add 38 23F8 = |Isub 2 2 long subtract 37 23F7 |Ilsum 3 3 long sum 4F 24FF | idiff 3 3 long diff 31 23F1 | Imul 17 33 | long multiply 1A 21FA |Idiv 19 35 long divide 36 23F6 | Ishi ned n+3 | long shift left (n<32) —t (n<16) n-12 n-28 | long shift left(n>32) t (n=16) 35 23F5 = |Ishr n+3 n+3 | long shift right (n<32) —_ t (n<16) n-12 n-28 |long shift right (n>32) — t (n>16) 19 21F9 |norm n+5 n+5 | normalise (n<32) t (n<16) n-10 n-26 | normalise (n>32) t (n216) 3 3 normalise (n=64) t (n=32) Table 11.12 Long arithmetic operation codes mm 7929237 0050762 172

[Precio | Mens’ | Memens | Pee” | Meme Code Code Cycles

00 FO rev 1 reverse

3A 23FA = | xword 4 extend to word 56 25F6 = | cword 5 check word 1D 21FD xdble 2 extend to double 4c 24FC esngl 3 check single 42 24F2 mint 1 minimum integer 5A 25FA dup 1 duplicate top of stack 79 27F9 pop 1 pop processor stack Table 11.13 General operation codes Operation | Memory icoiictie 5 devices | devices

02 F2 bsub 1 1 byte subscript

OA FA wsub 2 2 word subscript Bit 28F1 wsubdb 3 3 form double word subscript 34 23F4 = | bent 2 2 byte count 3F 23FF | went 4 5 word count

01 FA Ib 5 5 load byte

3B 23FB {sb 4 4 store byte 4A 24FA | move 2w+8 2w+8 | move message Table 11.14 Indexing/array operation codes [rccae™ | Mens” | revere | Peace” | em Code Code Cycles 22 22F2 Idtimer 2 load timer 2B 22FB tin 30 timer input (time future) D 4 timer input (time past) D 4E 24FE talt 4 timer alt start 51 25F1 taltwt 15 timer alt wait (time past) D 48 timer alt wait (time future) D 47 24F7 enbt 8 enable timer 2E 22FE dist 23 disable timer Table 11.15 Timer handling operation codes ms 7929237 0090783 005 me

Operation | Memory Processor Code Code Cycles

07 F7 in 2w+19 input message D

0B FB out 2w+19 output message D OF FF outword 23 output word D OE FE outbyte 23 output byte D 43 24F3 alt 2 alt start 44 24F4 altwt 5 alt wait (channel ready) D 17 alt wait (channel not ready) D 45 24F5 altend 4 alt end 49 24F9 enbs 3 enable skip 30 23F0 diss 4 disable skip 12 21F2 resetch 3 reset channel 48 24F8 enbe 7 enable channel (ready) 5 enable channel (not ready) 2F 22FF disc 8 disable channel Table 11.16 Input/output operation codes Operation | Memory Processor Code Code Cycles 20 22F0 ret return 1B 21FB \\dpi load pointer to instruction 3c 23FC | gajw general adjust workspace

06 F6 gcall general call

21 22F1 lend loop end (loop) loop end (exit) Table 11.17 Control operation codes Operation | Memory Processor Code Code Cycles oD FD startp 12 start process

03 F3 endp 13 end process

39 23F9 runp 10 run process 15 21F5 stopp ab] stop process 1E 21FE Idpri 1 load current priority Table 11.18 Scheduling operation codes a Si 51/56 mm 75929237 00590784 THS Me

[rset | Yeni” | Memone | Peer |e Code Code Cycles 13 21F3 csub0 2 check subscript from 0 4D 24FD = |centt 3 check count from 1 29 22F9 testerr 2 test error false and clear (no error) 3 test error false and clear (error) 10 21FO seterr 1 set error 55 25F5 stoperr 2 stop on error (no error) 57 25F7 elrhalterr 1 clear halt-on-error 58 25F8 sethalterr 1 set halt-on-error 59 25F9 testhalterr 2 test halt—on-error Table 11.19 Error handling operation codes Pesce | Nendo” | Womens | Peyeee” |e Code Code Cycles 0 00 jump 0 3 jump 0 (break not enabled) "1 jump 0 (break enabled, high priority) 13 jump 0 (break enabled, low priority) B1 2BF1 break 9 break (high priority) W break (low priority) B2 2BF2 clrjObreak 1 clear jump 0 break enable flag B3 2BF3 setjObreak 1 set jump 0 break enable flag B4 2BF4 testjObreak 2 test jump 0 break enable flag set 7A 27FA | timerdisableh 1 disable high priority timer interrupt 7B 27FB | timerdisablel 1 disable low priority timer interrupt 7c 27FC | timerenableh 6 enable high priority timer interrupt 7D 27FD _|timerenablel 6 enable low priority timer interrupt Table 11.20 Debugger support codes Pesce” | Mersey | Mremore | Pees” | mI Code Code Cycles 5B t 25FB move2dinit 8 initialise data for 2D block move sCt 25FC move2dall (2p+23) xr | 2D block copy 5Dt 25FD move2dnonzero | (2p+23) xr | 2D block copy non-zero bytes SEt 25FE (2p+23) xr | 2D block copy zero bytes Table 11.21 2D block move operation codes mm 7929237 0090785 941

Operation | Memory Processor Code Code Cycles 74 27F4 — | creword 35 calculate crc on word 75 27F5 crebyte 1 calculate crc on byte 76 27F6 bitent b+2 count bits set in word 77 27F7 bitrevword 36 reverse bits in word 78 27F8 bitrevnbits n+4 reverse bottom n bits in word Table 11.22 CRC and bit operation codes

11.8 Floating point instructions

11.9 Floating point instructions for IMS T805 only

Operation | Memory Processor Code Code Cycles 8E 28FE fpldnisn 2 fp load non-local single 8A 28FA fpldnidb 3 fp load non-local double 86 28F6 fpidnisni 4 fp load non-local indexed single 82 28F2 fpldnidbi 6 fp load non-local indexed double OF 29FF fpldzerosn 2 load zero single AO 2AFO fpldzerodb 2 load zero double AA 2AFA fpldniaddsn 8/11 fp load non local & add single F AG 2AF6 fpldniadddb 92 fp load non local & add double F AC 2AFC fpldnimulsn 13/20 fp load non local & multiply single F AB 2AF8 fpldnimuldb 21/30 fp load non local & multiply double F 88 28F8 fpstnisn 2 fp store non-local single 84 28F4 fpstnidb 3 fp store non-local double 9E 29FE fpstnli32 4 store non-local int32 Processor cycles are shown as Typical/Maximum cycles. Table 11.23 Floating point load/store operation codes Operation | Memory Processor Code Code Cycles AB 2AFB | fpentry floating point unit entry A4 2AF4 fprev fp reverse AS 2AF3 | fpdup fp duplicate Table 11.24 Floating point general operation codes Mi 7929237? OO9074b 616

Peso” | Messe | Mvmone | Payee | me | Code Code Cycles 22 s fpurn set rounding mode to round nearest 06 s fpurz set rounding mode to round zero 04 s fpurp set rounding mode to round positive 05 s fpurm set rounding mode to round minus. Table 11.25 Floating point rounding operation codes Pesce” | Mea | Mvmone | Payee” | me PFI Code Code Cycles 83 28F3 fpchkerror check fp error E 9c 29FC fptesterror test fp error false and clear F 23 s fpuseterror set fp error F 9c s fpuclearerror clear fp error F Table 11.26 Floating point error operation codes cain’ | Mremons | Foye” | me DP Code Code Cycles 94 29F4 fpgt 4/6 fp greater than F 95 29F5 | fpeq 3/5 fp equality F 92 29F2 fpordered 3/4 fp orderability 91 29F1 fpnan 23 fp NaN 93 29F3 fpnotfinite 2/2 fp not finite OE s fpuchki32 3/4 check in range of type int32 F OF s fpuchki64 3/4 check in range of type int64 F Table 11.27 Floating point comparison operation codes [rsase™ | Nenisy | Mremors | Pee" | PF Code Code Cycles 07 s fpur32tor64 3/4 real32 to real64 F 08 s fpur64tor32 6/9 real64 to real32 F 9D 29FD =| fprtoi32 7/9 real to int32 F 96 29F6 fpi32tor32 8/10 int32 to real32 98 29F8 fpis2tor64 8/10 int32 to real64 9A 29FA = | fpb32tor64 8/8 bit32 to real64 oD s fpunoround 2/2 real64 to real32, no round Al 2AF1 fpint 5/6 round to floating integer F Table 11.28 Floating point conversion operation codes mm 7929237 0090787 754 me

Operation | Memory Processor Cycles Code Code Single 87 28F7 fpadd 6/9 6/9 fp add F 89 28F9 fpsub 6/9 6/9 fp subtract F 8B 28FB fpmul 11/18 18/27 fp multiply F 8c 28FC fpdiv 16/28 31/43 ‘| fp divide F OB s fpuabs 2/2 2/2 fp absolute F 8F 28FF fpremfirst 36/46 36/46 fp remainder first step F 90 29F0 fpremstep 32/36 32/36 | fp remainder iteration 01 s fpusqrifirst 27/29 27/29 fp square root first step F 02 s fpusqristep 42/42 42/42 fp square root step 03 s fpusqrtlast 8/9 8/9 fp square root end 0A s fpuexpinc32 6/9 6/9 multiply by 292 F 09 s fpuexpdec32 6/9 6/9 divide by 232 F 12 s fpumulby2 6/9 6/9 multiply by 2.0 F a s fpudivby2 6/9 6/9 divide by 2.0 F Table 11.29 Floating point arithmetic operation codes

11.10 Floating point instructions for IMS T400 and IMS T425 only

Operation | Memory Processor Code Code Cycles 73 27F3 cflerr 3 check floating point error 9c 29FC fptesterr 1 load value true (FPU not present) 63 26F3 unpacksn 15 unpack single length fp number 6D 26FD | roundsn 12/15 round single length fp number 6C 26FC postnormsn 5/30 post—normalise correction of single length fp number 71 27F1 \\dinf 1 load single length infinity Table 11.30 Floating point support operation codes “ M™@ 7929237 0090788 bI0