IMP8980DC

IMP8980D A1PROS | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 14

Technical content

Features

♦ ST-BUS compatible ♦ 8-line x 32-channel inputs ♦ 8-line x 32-channel outputs ♦ 256 ports non-blocking switch ♦ Single power supply (+5V) ♦ 30mW power consumption ♦ Microprocessor-control interface ♦ Pin-compatible with Mitel MT8980 Functional Description The ST-BUS architecture can be used both in software-controlled digital voice and data switching. The ST-Bus serial streams operate continuously at 2048kbit/s and are arranged in 125µs wide frames which contain 32 8-bit channels. The IMP8980D can switch data from channels on ST-BUS inputs to channels on ST-BUS outputs and simultaneously allows its controlling microprocessor to read channels on ST-BUS inputs or write to channels on ST-BUS outputs (Message Mode). To the microprocessor, the IMP8980D looks like a memory periph- eral. The microprocessor can write to the IMP8980D to establish switched connec- tions between input ST-BUS channels and output ST-BUS channels or to transmit messages on output ST-BUS channels. By reading from the IMP8980D, the micro- processor can receive messages from ST-BUS input channels or check which Serial to Parallel Converter Frame Counter Control Register Control Interface Output MUX Connection Memory Parallel to Serial Converter ODE STi0 STi1 STi2 STi3 STi4 STi5 STi6 STi7 STo0 STo1 STo2 STo3 STo4 STo5 STo6 STo7 DS CS R/W A5/ DTA D7/ CSTo C4i F0i VDD VSS Data Memory ISO 9001 Registered

© IMP, Inc. IMP8980D DS-5-002 handles the microprocessor control signals CS, DTA, R/W and DS. There are two parts to any address in the Data Memory or Connection 2-7 Memory. The higher order bits come from the Control Register, which may be written to or read from via the Control Interface. The lower order bits come from the address lines directly. The Control Register also allows the chip to broadcast messages on all ST-BUS outputs (i.e., to put every channel into Message Mode), or to split the memory so that reads are from the Data Memory and writes are to the Connection Memory Low. The Connection Memory High determines whether individual output channels are in Message Mode, and allows individual output channels to go into a high- impedance state, which enables arrays of IMP8980D s to be constructed. It also controls the CSTo pin. All ST-BUS timing is derived from the C4i and F0i signals. Software Control The address lines on the Control Interface give access to the Control Register directly or, depending on the contents of the Control Register, to the High or Low sections of the Connection Memory or to the Data Memory.If address line A5 is low, then the Control Register is addressed regardless of the other address lines (see Figure 3). If A5 is high, then the address lines A4-A0 select the memory location corresponding to channel 0-31 for the memory and stream selected in the Control Register. The data in the Control Register consists of mode control bits, memory select bits, and stream address bits (see Figure 4). The memory select bits allow the Connection Memory High or Low or the Data Memory to be chosen, and the stream address bits define one of the ST-BUS input or output streams. Bit 7 of the Control Register allows split memory operation - reads are from the Data Memory and writes are to the Connection Memory Low. The other mode control bit, bit 6, puts every output channel on every output switched connections have already been established. By integrating both switching and interprocessor communications, the IMP8980D allows systems to use distrib- uted processing and to switch voice or data in an ST-BUS architecture. Hardware Description Serial data at 2048 kbit/s is received at the eight ST-BUS inputs (STi0 to STi7), and serial data is transmitted at the eight ST-BUS outputs (STo0 to STo7). Each serial input accepts 32 channels of digital data, each channel containing an 8-bit word which may represent a PCM-encoded analog/voice sample as provided by a codec. This serial input word is converted into parallel data and stored in the 256 X 8 Data Memory. Locations in the Data Memory are associated with particular channels on particular ST-BUS input streams. These locations can be read by the microprocessor which controls the chip. Locations in the Connection Memory, which is split into high and low parts, are associated with particular ST-BUS output streams. When a channel is due to be transmitted on an ST-BUS output, the data for the channel can either be switched from an ST-BUS input or it can originate from the microprocessor. If the data is switched from an input, then the contents of the Connection Memory Low location associated with the output channel is used to address the Data Memory. This Data Memory address corresponds to the channel on the input ST-BUS stream on which the data for switching arrived. If the data for the output channel originates from the microprocessor (Message Mode), then the contents of the Connection Memory Low location associated with the output channel are output directly, and this data is output repetitively on the channel once every frame until the microprocessor intervenes. The Connection Memory data is received, via the Control Interface, at D7 to D0. The Control Interface also receives address information at A5 to A0 and

stream into active Message Mode; i.e., the contents of the Connection Memory Low are output on the ST-BUS output streams once every frame unless the ODE pin is low. In this mode the chip behaves as if bits 2 and 0 of every Connection Memory High location were 1, regardless of the actual values. If bit 6 of the Control Register is 0, then bits 2 and 0 of each Connection Memory Figure 3- Address Memory Map A5 A4 A3 A2 A1 A0 HEX ADDRESS LOCATION

0 X X X X X 00-1F Control Register*

1 0 0 0 0 0 20 Channel 0† 1 0 0 0 0 1 21 Channel 1† GG GG GG G G GG GG GG G G GG GG GG G G 1 1 1 1 1 1 3F Channel 31† * Writing to the Control Register is the only fast transaction. † Memory and stream are specified by the contents of the Control Register. High location function normally (see Figure 5). If bit 2 is 1, the associated ST- BUS output channel is in Message Mode; i.e., the byte in the corresponding Connec- tion Memory Low location is transmitted on the stream at that channel. Otherwise, one of the bytes received on the serial inputs is transmitted and the contents of the Connection Memory Low define the ST-BUS input stream and channel where the byte is to be found (see Figure 6). Figure 4 - Control Register Bits 76 54 32 10 Mode Control Bits (Unused) Memory Select Bits Stream Address Bits BIT NAME DESCRIPTION

7 Split When 1, all subsequent reads are from the Data Memory

Memory and writes are to the Connection Memory Low, except when the Control Register is accessed again. When 0, the Memory Select bits specify the memory for subsequent operations. In either case, the Stream Address Bits select the subsection of the memory which is made available.

6 Message When 1, the contents of the Connection Memory Low are output

Mode on the Serial Output streams except when the ODE pin is low. When 0, the Connection Memory bits for each channel determine what is output. 5 (unused) 4-3 Memory 0-0 - Not to be used Select Bits 0-1 - Data Memory (read only from the microprocessor port) 1-0 - Connection Memory Low 1-1 - Connection Memory High 2-0 Stream The number expressed in binary notation on these bits refers to Address the input or output ST -BUS stream which corresponds to the Bits subsection of memory made accessible for subsequent operations.

© IMP, Inc. IMP8980D DS-5-004 Figure5 - Connection Memory High Bits 76 54 32 10 No Corresponding Memory - These bits give 0s if read. Per Channel Control Bits BIT NAME DESCRIPTION

2 Message When 1, the contents of the corresponding location in Connection

Channel Memory Low are output on the location ’s channel and stream. When 0, the contents of the corresponding location in Connection Memory Low act as an address for the Data Memory and so determine the source of the connection to the location’s channel and stream. 1 CSTo This bit is output on the CSTo pin one channel early. The CSTo bit for stream 0 is output first.

0 Output If the ODE pin is high and bit 6 of the Control Register is 0, then

Enable this bit enables the output driver for the location ’s channel and stream. This allows individual channels on individual streams to be made high-impedance, allowing switching matrices to be constructed. A "1" enables the driver and a "0" disables it. If the ODE pin is low, then all serial outputs are high-impedance. If it is high and bit 6 in the Control Register is 1, then all outputs are active. If the ODE pin is high and bit 6 in the Control Register is 0, then the bit 0 in the Connection Memory High location enables the output drivers for the corresponding individual ST-BUS output stream and channel. Bit 0=1 enables the driver and bit 0=0 disables it (see Figure 5). Bit 1 of each Connection Memory High location (see Figure 5) is output on the CSTo pin once every frame. To allow for delay in any external control circuitry the bit is output one channel before the corresponding channel on the ST-BUS streams, and the bit for stream 0 is output first in the channel; e.g., bit 1’s for channel 9 of streams 0-7 are output synchronously with ST-BUS channel 8 bits 7-0.

Applications

Figures 7 and 8 show how IMP8980Ds and MT8964s form a simple digital switching system. Figure 7 shows the interface between the IMP8980D’s and the filter/codecs. Figure 8 shows the position of these components in an example architec- ture. The Mitel MT8964 filter/codec in Figure 7 receives and transmits digitized voice signals on the ST-BUS input DR, and ST-BUS output DX, respectively . These signals are routed to the ST-BUS inputs and outputs on the top IMP8980D, which is used as a digital speech switch. The MT8964 is controlled by the ST-BUS input DC originating from the bottom IMP8980D , which generates the appropriate signals from an output channel in Message Mode. This architecture optimizes the messaging capability of the line circuit by building signalling logic, e.g., for on-off hook detection, which commu- nicates on an ST-BUS output. This signalling ST-BUS output is monitored by a microprocessor (not shown) through an ST-BUS input on the bottom IMP8980D. Figure 8 shows how a simple digital switching system may be designed using the ST-BUS architecture. This is a private telephone network with 256 extensions which uses a single IMP8980D as a speech

Figure 10 Application Circuit MEK6802D3 System IMP 8980 CSTo ODE STo0 STo1 STo2 STo3 STo4 STo5 STo6 SRo7 VSS CS DTA STi0 STi1 STi2 STi3 STi4 STi5 STi6 STi7 VDD F0i C4i ADS R/W D7-D0 A15-A0 R/W MR VMA E A15 A14 A13 VMA MD HCT 138 MD HCT 138 MD HCT 138 MD HCT 138 A12 A11 A10 VMA MD HCT 240 DTA CS C4i F0i MR 510Ω 100pF 4MHz 2MΩ 909Ω 1/4W SN HCT 393 SN HCT 393 C4i

© IMP, Inc. IMP8980D DS-5-008 ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. * Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. Absolute Maximum Ratings* Parameter Symbol Min Max Units 1 V DD - VSS -0.3 7 V 2 Voltage on Digital Inputs V I VSS-0.3 V DD+0.3 V 3 Voltage on Digital Outputs V O VSS-0.3 V DD+0.3 V

4 Current at Digital Outputs I O 40 mA

5 Storage Temperature T S -65 +150 °C

6 Package Power Dissipation P D 2 W

Recommended Operating Conditions - Voltages are with respect to ground (VSS ) unless otherwise stated. Characteristics Sym Min Typ ‡ Max Units Test Conditions

1 Operating Temperature T OP -40 +85 °C

2 Positive Supply V DD 4.75 5.25 V

3 Input Voltage V I 0 VDD V

‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. Characteristics Sym Min Typ ‡ Max Units Test Conditions

1 Supply Current I DD 6 10 mA Outputs unloaded

2 Input High Voltage V I H 2.0 V 3 Input Low Voltage V I L 0.8 V

4 Input Leakage I I L 5 µA VI between V SS and VDD

5 Input Pin Capacitance C I 8 p F

6 Output High Voltage V OH 2.4 V I OH = 10 mA 7 Output High Current I OH 10 15 mA Sourcing. V OH=2.4V 8 Output Low Voltage V OL 0.4 V I OL = 5 mA 9 Output Low Current I OL 5 10 mA Sinking. V OL = 0.4V 10 High Imp. Leakage I OZ 5 µA V O between VSS and VDD

11 Output Pin Capacitance CO 8 pF

when testing output levels or high impedance states. S2 is switched to VDD or VSS when testing output levels or high impedance states. Figure 11 Output Load Test

†† Timing is over recommended temperature & power supply voltages. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. * Contents of Connection Memory are not lost if the clock stops, however, ST -BUS outputs go into the high impedance state. NB: Frame Pulse is repeated every 512 cycles of C4i. Characteristics Sym Min Typ ‡ Max Units Test Conditions

1 Clock Period* t CLK 220 244 300 ns

2 Clock Width High t CH 95 122 150 ns

3 Clock Width Low t CL 110 122 150 ns

4 Clock Transition Time t CTT 20 ns

5 Frame Pulse Setup TIme tCCT 20 ns

6 Frame Pulse Hold Time tFPH 0.020 670 µs

7 Frame Pulse Width t FPW 244 ns

2.0V 0.8V 2.0V 0.8V Figure 12 Frame Allignment Figure 13 Clock Timing

© IMP, Inc. IMP8980D DS-5-0010 † Timing is over recommended temperature & power supply voltages. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. * High Impedance is measured by pulling to the appropriate rail with RL , with timing corrected to cancel time taken to discharge CL . Characteristics Sym Min Typ ‡ Max Units Test Conditions Inputs

1 STo0/7 Delay-Active to High Z tSAZ 20 50 80 ns R L=1 KΩ*, CL=150 pF

2 STo0/7 Delay-High Z to Active t SZA 25 60 125 ns C L=150 pF

3 STo0/7 Delay-Active to Active t SAA 30 65 125 ns C L=150 pF

4 STo0/7 Hold Time t SOH 25 45 ns C L=150 pF

5 Output Driver Enable Delay t OED 45 125 ns R L=1 KΩ*, CL=150 pF

6 External Control Hold Time t XCH 0 50 ns C L=150 pF

7 External Control Delay t XCD 75 110 ns C L=150 pF

8 Serial Input Setup Time t SIS -40 -20 ns

9 Serial Input Hold Time t SIH 90 ns

2.0V 0.8V 2.4V 0.4V 2.4V 0.4V 2.4V 0.4V 2.4V 0.4V C4i STo0 to STo7 CSTo STo0 to STo7 STo0 to STo7 Bit Cell Boundary tSOH tSAZ tSZA tSOH tSAA tXCH tXCD tOED tOED ODE STo0 to ST o7 2.0V 0.8V 2.4V 0.4V Bit Cell Boundaries C4i STo0 to STo7 2.0V 0.8V 2.0V 0.8V tSIS tSIH Figure 14 Serial Outputs and External Control Figure 15 Output Driver Enable Figure 16 Serial Inputs

† Timing is over recommended temperature & power supply voltages. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. * High Impedance is measured by pulling to the appropriate rail with R L, with timing corrected to cancel time taken to discharge C L. ➀ Processor accesses are dependent on the C4i clock, and so some timings are expressed as multiples of the C4i clock period. Characteristics Sym Min Typ ‡ Max Units Test Conditions

1 Chip Select Setup Time t CSS 20 0 ns

2 Read/Write Setup Time t RWS 25 5 ns

3 Address Setup Time t ADS 25 5 ns

4 Acknowledgement Fast tAKD 40 100 ns C L=150 pF

Delay Slow tAKD 2.7 7.2 cycles C4i cycles ➀

5 Fast Write Data Setup Time tFWS 20 ns

6 Slow Write Data Delay t SWD 2.0 1.7 cycles C4i cycles ➀ 7 Read Data Setup Time tRDS 0.5 cycles C4i cycles ➀, CL= 150 pF

8 Data Hold Time Read tDHT 20 ns R L=1 KΩ * , CL=150 pF

9 Read Data To High Imp. t RDZ 50 90 ns R L=1 KΩ * , CL=150 pF

10 Chip Select Hold Time t CSH 0 ns

11 Read/Write Hold Time t RWH 0 ns

12 Address Hold Time t ADH 0 ns

13 Acknow. Hold Time t AKH 10 60 80 ns R L=1 KΩ * , CL=150 pF 2.0V 0.8V 2.0V 0.8V 2.0V 0.8V 2.0V 0.8V 2.4V 0.4V 0.8V (Read) 0.8V (Write) 2.4V (Read) 2.0V (Write) DS CS to DTA to R/W tCSS tRWS tADS tAKD tRDS tSWD tFWS tRDZ tAKH tADH tCSH tRWH tDHT Figure 17 Processor Bus

© IMP, Inc. IMP8980D DS-5-0012 Pin # Name Description 40 44 DIP PLCC 1 2 DTA Data Acknowledgement (Open Drain Output). This is the data acknowledgement on the microprocessor interface. This pin is pulled low to signal that the chip has processed the data. A 909 Ω, 1/4W, resistor is recommended to be used as a pullup. 2 3 STi0 ST-BUS Input 0 to 2 (Inputs). These are the inputs for -4 -5 -STi2 the 2048 kbit/s ST-BUS input streams. 5 7 STi3 ST-BUS Input 3 to 7 (Inputs). -9 -11 -STi7 These are the inputs for the 2048 kbit/s ST-BUS input streams. 10 12 VDD Power Input. Positive Supply. 11 13 F0i Framing 0-Type (Input). This is the input for the frame synchronization pulse for the 2048 kbit/s ST-BUS streams. A low on this input causes the internal counter to reset on the next negative transition of C4i 12 14 C4i 4.096 MHz Clock (Input). ST-BUS bit cell boundaries lie on the alternate falling edges of this clock. 13 15 A0 Address 0 to 2 (Inputs). These are the inputs for the -15 -17 -A2 address lines on the microprocessor interface. 16 19 A3 Address 3 to 5 (Inputs). These are the inputs for the -18 -21 -A5 address lines on the microprocessor interface. 19 22 DS Data Strobe (Input). This is the input for the active high data strobe on the microprocessor interface. 20 23 R/W Read or Write (Input). This is the input for the read/write signal on the microprocessor interface - high for read, low for write. 21 24 CS Chip Select (Input). This is the input for the active low chip select on the microprocessor interface 22 25 D7 Data 7 to 5 (Three-state I/O Pins). These are the -24 -27 -D5 bidirectional data pins on the microprocessor interface. 25 29 D4 Data 4 to 0 (Three-state I/O Pins). These are the -29 -33 -D0 bidirectional data pins on the microprocessor interface. 30 34 V SS Power Input. Negative Supply (Ground). 31 35 STo7 ST-BUS Output 7 to 3 (Three-state Outputs). These -35 -39 -ST03 are the pins for the eight 2048 kbit/s ST-BUS output streams. 36 41 STo2 ST-BUS Output 2 to 0 (Three-state Outputs). These -38 -43 - STo0 are the pins for the eight 2048 kbit/s ST-BUS output streams. 39 44 ODE Output Drive Enable (Input). If this input is held high, the STo0-STo7 output drivers function normally. If this input is low, the STo0-STo7 output drivers go into their high impedance state. NB: Even when ODE is high, channels on the STo0-STo7 outputs can go high impedance under software control. 40 1 CSTo Control ST-BUS Output (Complementary Output). Each frame of 256 bits on this ST-BUS output contains the values of bit 1 in the 256 locations of the Connection Memory High. 6, NC No Connection. 18, 28, Pin Description

Ordering Information

Ordering Part Number Package Type IMP8980DC 40 Pin Ceramic DIP IMP8980DE 40 Pin Plastic DIP IMP8980DP 44 Pin PLCC IMP8980DP/T Tape and Reel, 44 Pin PLCC Figure 2 Pin Connections

40 Pin CERDIP/Plastic DIP

44 Pin PLCC

© IMP, Inc. IMP8980D DS-5-0014 IMP , Inc. Corporate Headquarters 2830 N. First Street San Jose, CA 95134 Tel: 408.432.9100 Main Tel: 800.434.3722 Fax: 408.434.0335 e-mail: info@impinc.com http://www.impweb.com Information furnished by IMP, Inc. is believed to be accurate and reliable. No responsibility is assumed by IMP for use of this product nor for any infringements of patents or trademarks or other rights of third parties resulting from its use. IMP reserves the right to make changes in specifications at any time without notice. IMP does not authorize or warrant any IMP products for use in life support devices and/ or systems without the expressed written approval of an officer of IMP, Inc. The IMP logo is a registered trademark of IMP, Inc. All other company and product names are trademarks of their respective owners. © 2000 IMP, Inc. Printed in USA Part No.: Document Number: IMP8980D DS 05/00 ISO 9001 Registered