VL6524 STMICROELECTRONICS | Alldatasheet
Document overview
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- PDF pages: 70
Technical content
Datasheet sections
- 1 Overview
- 1.1 Description
- 2 Electrical interface
- 3 System architecture
- 3.1 Operation
- 3.1.1 Video pipe
- 3.2 Microprocessor functions
- 4 Operational modes
- 5 Clock control
- 5.1 Input clock
- 5.2 System clock division
- 5.3 Pixel clock (PCLK)
- 5.4 PCLK gating
- 6 Output frame size control
- 6.1 Frame format
- 6.1.1 Cropping module
- 6.1.2 Subsampling module
- 6.2 Frame rate control
- 6.2.1 Horizontal mirror and vertical flip
- 6.3 ViewLive Operation
- 6.4 Context switching
- 7 Output data formats
- 7.1 YUV 4:2:2 data format
- 7.2 RGB and Bayer data formats
- 7.2.1 Manipulation of RGB data
Datasheet sections
- 12 Optical specifications
- 12.1 Average sensitivity
- 12.2 Spectral response
- 13 Electrical characteristics
- 13.1 Absolute maximum ratings
- 13.2 Operating conditions
- 13.3 DC electrical characteristics
- 13.4 AC electrical characteristics
- 13.4.1 External clock
- 13.4.2 Chip enable
- 13.4.3 I²C slave interface
- 13.4.4 Parallel data interface timing
- 13.5 ESD handling characteristics
- 14 Package outline
- 14.1 SmOP
- 14.2 LGA
Features
■ 640H x 480V active pixels ■ 3.6 µm pixel size, 1/6 inch optical format ■ RGB Bayer color filter array ■ Integrated 10-bit ADC ■ Integrated digital image processing functions, including defect correction, lens shading correction, demosaicing, sharpening, gamma correction and color space conversion ■ Embedded camera controller for automatic exposure control, automatic white balance control, black level compensation, 50/60 Hz flicker cancellation and flashgun support ■ Up to 30 fps progressive scan, flexible subsampling and cropping modes ■ ITU-R BT.656-4 YUV (YCbCr) 4:2:2 with embedded syncs, RGB 565, RGB 444 or Bayer 10-bit output formats ■ Viewlive feature allows different sizes, formats and reconstruction settings to be applied to alternate frames ■ 8-bit parallel video interface, horizontal and vertical syncs, 24 MHz clock ■ Two-wire serial control interface (I2C) ■ On-chip PLL, 6.5 to 26 MHz clock input ■ Analog power supply, from 2.4V to 3.0V ■ Separate I/O power supply, 1.8V or 2.8V levels ■ 3.3V tolerant I/O for power supply > 2.7V ■ Integrated power management with power switch, automatic power-on reset and power- safe pins ■ Low power consumption, ultra low standby current ■ Dual-element plastic lens, F# 2.8, ~59° DFOV (VS6524)
Description
The VL6524/VS6524 is a general purpose VGA resolution CMOS color digital camera featuring low size and low power consumption. This complete camera module is ready to connect to camera enabled baseband processors, back-end IC devices or PDA engines.
Applications
■ Mobile phone ■ Videophone ■ Video surveillance ■ Medical ■ Machine Vision ■ Toys ■ PDA ■ Biometry ■ Bar Code Reader ■ Lighting Control SmOP LGA
1 Overview
1.1 Description
The VL6524/VS6524 is a VGA resolution CMOS imaging device designed for low power systems. Video data is output from the VS6524 over an 8-bit parallel bus in RGB, YCbCr or bayer formats and is controlled via an I²C interface. The VL6524/VS6524 requires an analogue power supply of between 2.4 V to 3.0 V and a digital supply of either 1.8 V or 2.8 V (dependant on interface levels required). An input clock is required in the range 6.5 MHz to 26 MHz. The device contains an embedded video processor and delivers fully color processed images at up to 30 frames per second. The video processor integrates a wide range of image enhancement functions, designed to ensure high image quality, these include:
- Automatic exposure control
- Automatic white balance
- Lens shading compensation
- Defect correction algorithms
- Demosaic (Bayer to RGB conversion)
- Matrix compensation
- Sharpening
- Gamma correction
- Flicker cancellation
2 Electrical interface
pins on the device is shown in Figure 36. Table 1. VL6524/VS6524 signal description
1 GND PWR Analogue ground
2 D02 OUT Data output D2
3 D03 OUT Data output D3
4 HSYNC OUT Horizontal synchronization output
5 VSYNC OUT Vertical synchronization output
6 D07 OUT Data output D7
7 D06 OUT Data output D6
8 D05 OUT Data output D5
9 D04 OUT Data output D4
11 GND PWR Digital ground
12 FSO OUT Flash output
13 CE IN Chip enable signal active HIGH
14 SCL IN I²C clock input
15 SDA I/O I²C data line
17 D01 OUT Data output D1
18 D00 OUT Data output D0
19 PCLK OUT Pixel qualification clock
3 System architecture
- VGA-sized pixel array
- Video timing generator
- Video pipe
- Statistics gathering unit
- Clock generator
- Microprocessor A simplified block diagram is shown in Figure 1.
Figure 1. VL6524/VS6524 simplified block diagram
3.1 Operation
along with qualification signals.
VL6524/VS6524 System architecture The whole system is controlled by an embedded microprocessor that is running firmware stored in an internal ROM. The external host communicates with this microprocessor over an I²C interface. The microprocessor does not handle the video data itself but is able to control all the functions within the video pipe. Real-time information about the video data is gathered by a statistics engine and is available to the microprocessor. The processor uses this information to perform real-time image control tasks such as automatic exposure control.
3.1.1 Video pipe
The main functions contained within the VL6524/VS6524 video processing pipe are as follows. Gain and offset: This function is used to apply gain and offset to data coming from the sensor array. The required gain and offset values result from the automatic exposure and white balance functions from the microprocessor. Anti-vignette: This function is used to compensate for the radial roll-off in intensity caused by the lens. By default the anti-vignette setting matches the lens used in this module and does not need to be adjusted. Crop: This function allows the user to select an arbitrary Window Of Interest (WOI) from the VGA-sized pixel array. It is fully accessible to the user. Defect correction: This function runs a defect correction filter over the data in order to remove defects from the final output. This function has been optimized to attain the minimum level of defects from the system and does not need to be adjusted. Demosaic: This module performs an interpolation on the Bayer data from the sensor array to produce an RGB image. It also applies an anti-alias filter. Subsampler: This module allows the image to be sub-sampled in the X and Y directions by 2, 3, 4, 5 or 6. Matrix: This function performs a color-space conversion from the sensor RGB data to standard RGB color space. Sharpening: This module increases the high frequency content of the image in order to compensate for the low-pass filtering effects of the previous modules. Gamma: This module applies a programmable gain curve to the output data. It is user adjustable. YUV conversion: This module performs color space conversion from RGB to YUV. It is used to control the contrast and color saturation of the output image as well as the fade to black feature. Dither: This module is used to reduce the contouring effect seen in RGB images with truncated data. Output formatter: This module controls the embedded codes which are inserted into the data stream to allow the host system to synchronize with the output data. It also controls the optional HSYNC and VSYNC output signals.
System architecture VL6524/VS6524
3.2 Microprocessor functions
The microprocessor inside the VL6524/VS6524 performs the following tasks: Host communication: handles the I²C communication with the host processor. Video pipe configuration: configures the video pipe modules to produce the output required by the host. Automatic exposure control: In normal operation the VL6524/VS6524 determines the appropriate exposure settings for a particular scene and outputs correctly exposed images. Flicker cancellation: The 50/60Hz flicker frequency present in the lighting (due to fluorescent lighting) can be cancelled by the system. Automatic white balance: The microprocessor adjusts the gains applied to the individual color channels in order to achieve a correctly color balanced image. Dark calibration: The microprocessor uses information from special dark lines within the pixel array to apply an offset to the video data and ensure a consistent ‘black’ level. Active noise management: The microprocessor is able to modify certain video pipe functions according to the current exposure settings determined by the automatic exposure controller. The main purpose of this is to improve the noise level in the system under low lighting conditions. Functions which ‘strength’ is reduced under low lighting conditions (e.g. sharpening) are controlled by ‘dampers’. Functions which ‘strength’ is increased under low lighting conditions are controlled by ‘promoters’. The fade to black operation is also controlled by the microprocessor
4 Operational modes
by I²C transactions from the host system or automatically after time-outs. Figure 2. State machine at power -up and user mode transitions low or the supplies are removed.
- The internal digital supply of the VL6524/VS6524 is shut down by an internal switch mechanism. This method allows a very low power-down current value.
- The device input / outputs are fail-safe, and consequently can be considered high impedance. Supplies OFF Standby Power-down CE pin LOW CE pin PAUSE mode Supplies turned-off Supplies turned ON & CE pin LOW Supplies turned OFF STOP mode Flashgun mode Run mode Note: 1 It is possible to enter any of the user modes direct from Standby via an I2C command HIGH State Machine at power-up I2C controlled user mode transitions
- The digital supplies must be on and stable.
- The internal digital supply of the VL6524/VS6524 is enabled by an internal switch mechanism.
- All internal registers are reset to default values by an internal power on reset cell.
Figure 3. Power up sequence UNINITIALISED, this mode is not a user mode. in this state automatically sets a transition through the PAUSE state to the run mode. is halted. This mode is used to set up the required output format before outputting any data. has no effect until the next RUN to PAUSE transition (Table 13). RUN mode:This is the fully operational mode.
VL6524/VS6524 Operational modes ViewLive: this feature allows different sizes, formats and reconstruction settings to be applied to alternate frames of data, while in run mode. FLASHGUN mode: In flashgun mode, the array is configured for use with an external flashgun. A flash is triggered and a single frame of data is output and the device automatically switches to Pause Mode. Mode transitions Transitions between operating modes are normally controlled by the host by writing to the Mode control register. Some transitions can occur automatically after a time out. If there is no activity in the PAUSE state then an automatic transition to the STOP state occurs. This functionality is controlled by the Power management control register. Writing 0xFF disables the automatic transition to STOP mode.
5 Clock control
5.1 Input clock
an input frequency of 6.5 MHz, the numerator can be set to 13 and the denominator to 2. The default input frequency is 12 MHz.
5.2 System clock division
and a maximum frame rate of 15fps VGA.
5.3 Pixel clock (PCLK)
additional interframe lines are added into the output data stream. Figure 4. Frame output format against framerate
VL6524/VS6524 Clock control Similarly when using sub-sampled output modes the PCLK frequency is not reduced but instead pairs of PCLKs are 'dropped', see Section 6.1.2: Subsampling module for details. The PCLK edge used to qualify the output data is fully programmable. It is also possible to program the state of the PCLK line (high or low) for the times when it is inactive.
5.4 PCLK gating
By default the PCLK output from the VL6524/VS6524 is not continuous. The PCLK qualifies all video data (and embedded codes if selected) on each video line and each interframe line but does not qualify the interline blanking data. In non-subsampled modes the PCLK is continuous during the video data output. The operation of the PCLK can be controlled using the bPClkSetup register (Table 29).
6 Output frame size control
6.1 Frame format
line consists of embedded line codes (if selected), active pixel data and interline blank data. not captured by the host system. The default 30fps VGA output frame is shown in Figure 5. Figure 5. VGA 30fps output frame only 1280 clocks (or 1288 if embedded codes are enabled). Output formatter control bank.
6.1.1 Cropping module
Figure 6 shows the example with pipe setup bank0.
1460 PCLKs
1280 PCLKs
Figure 6. Crop controls ( Table 16: Pipe setup bank0 control) frame with lines of blanking data thus the overall frame length is not reduced. unchanged as the number of interline clocks increases by the same amount. Figure 7. Crop 30fps output frame
6.1.2 Subsampling module
lists the available image sizes. Figure 8. PCLK waveform in subsampled modes number of lines in a frame must be an integer multiple of the subsample ratio.
6.2 Frame rate control
Table 2. Subsampled image sizes
4 QQVGA 160 by 120
5 SQCIF 128 by 96
6.2.1 Horizontal mirror and vertical flip
Pipe setup bank0 control register bank.
6.3 ViewLive Operation
alternate frames of the output data. View live control for register description). Pipe setup bank0 control and Pipe setup bank1 control. Pipe setup bank0 control setup is used when ViewLive is disabled. Pipe setup bank1 control on each alternate frame. Figure 9. ViewLive frame output format
Output frame size control VL6524/VS6524
6.4 Context switching
It is possible to control which pipe setup bank is used and to switch between banks without the need to pause streaming, the change will occur at the next frame boundry after the change to the register has been made. For example this function allows the VL6524/VS6524 to stream an output targetting a display (e.g. RGB 444) and switch to capture an image (e.g. YUV 4:2:2) with no need to pause streaming or enter any other operating mode. The register bNonViewLive_ ActivePipeSetupBank allows selection of the pipe setup bank (see Table 15: Pipe setup bank selection).
7 Output data formats
- YUV4:2:2
- RGB565
- RGB444 (encapsulated as 565)
- RGB444 (zero padded)
- Bayer 10-bit In all output formats there are 2 output bytes per pixel. The required data format is selected using the bdataFormat0 register described in Table 16. The various options available for each format are controlled using the bRgbSetup and bYuvSetup registers (Table 29).
7.1 YUV 4:2:2 data format
Figure 10. Standard Y Cb Cr data order Figure 11. Y Cb Cr data swapping options
7.2 RGB and Bayer data formats
- RGB565
- RGB444 (encapsulated as RGB565)
- RGB444 (zero padded)
- Bayer 10-bit Note: Pixels in Bayer 10-bit data output are defect corrected, correctly exposed and white balanced. Any or all of these functions can be disabled. In each of these modes 2 bytes of data are required for each output pixel. The encapsulation of the data is shown in Figure 12.
Figure 12. RGB and Bayer data formats
VL6524/VS6524 Output data formats
7.2.1 Manipulation of RGB data
It is possible to modify the encapsulation of the RGB data in a number of ways:
- swap the location of the RED and BLUE data
- reverse the bit order of the individual color channel data
- reverse the order of the data bytes themselves
7.2.2 Dithering
An optional dithering function can be enabled for each RGB output mode to reduce the appearance of contours produced by RGB data truncation. This is enabled through the DitherControl register (Table 28: Dither control).
Data synchronization methods VL6524/VS6524
8 Data synchronization methods
External capture systems can synchronize with the data output from VL6524/VS6524 in one of two ways: 1. Synchronization codes are embedded in the output data 2. Via the use of two additional synchronization signals: VSYNC and HSYNC Both methods of synchronization can be programmed to meet the needs of the host system.
8.1 Embedded codes
The embedded code sequence can be inserted into the output data stream to enable the external host system to synchronize with the output frames. The code consists of a 4-byte sequence starting with 0xFF , 0x00, 0x00. The final byte in the sequence depends on the mode selected. Two types of embedded codes are supported by the VL6524/VS6524: Mode 1 (ITU656) and Mode 2. The bSyncCodeSetup register is used to select whether codes are inserted or not and to select the type of code to insert (Table 29: Output formatter control). When embedded codes are selected each line of data output contains 8 additional clocks: 4 before the active video data and 4 after it.
8.1.1 Prevention of fals e synchronization codes
The VL6524/VS6524 is able to prevent the output of 0xFF and/or 0x00 data from being misinterpreted by a host system as the start of synchronization data. This function is controlled the bCodeCheckEnable register (Table 29: Output formatter control).
8.1.2 Mode 1(ITU656 compatible)
The structure of an image frame with ITU656 codes is shown in Figure 13.
Figure 13. ITU656 frame structure with even codes Output formatter control register bank. Table 3. ITU656 embedded synchronization code definition (even frames)
8.1.3 Mode 2
The structure of a mode 2 image frame is shown Figure 14. Figure 14. Mode 2 frame structure (VGA example) For mode 2, the synchronization codes are as listed in Table 5. Table 4. ITU656 embedded synchronization code definition (odd frames) Table 5. Mode 2 - embedded synchronization code definition
8.2 VSYNC and HSYNC
active video portion of the output frame regardless of its size.
8.2.1 Horizontal synchr onization signal (HSYNC)
- enable/disable
- select polarity
- all lines or active lines only
- manual or automatic In automatic mode the HSYNC signal envelops all the active video data on every line in the output frame regardless of the programmed image size. Line codes (if selected) fall outside the HSYNC envelope as shown in Figure 15.
Figure 15. HSYNC timing example is programmed in the bHsyncFallingH and bHsyncFallingL registers (Table 29).
8.2.2 Vertical synchronization (VSYNC)
- enable/disable
- select polarity
- manual or automatic In automatic mode the VSYNC signal envelops all the active video lines in the output frame regardless of the programmed image size as shown in Figure 16.
Figure 16. VSYNC timing example described in Table 29: Output formatter control.
VL6524/VS6524 Getting started
9 Getting started
9.1 Initial power up
Before any communication is possible with the VL6524/VS6524 the following steps must take place: 1. Apply VDD (1.8V or 2.8V) 2. Apply AVDD (2.8V) 3. Apply an external CLOCK (6.5 MHz to 26 MHz) 4. Assert CE line HIGH These steps can all take place simultaneously. After these steps are complete a delay of 200 µs is required before any I²C communication can take place, see Figure 3: Power up sequence.
9.2 Minimum startup command sequence
- Enable the microprocessor - before any commands can be sent to the VL6524/VS6524, the internal microprocessor must be enabled by writing the value 0x06 to the MicroEnable register 0xC003 (Table 7: Low-level control registers). 2. Enable the digital I/O - after power up the digital I/O of the VL6524/VS6524 is in a high- impedance state (‘tri-state’). The I/O are enabled by writing the value 0x01 to the Enable I/O register 0xC034 (Table 7: Low-level control registers). 3. The user can then program the system clock frequency and setup the required output format before placing the VL6524/VS6524 in RUN mode by writing 0x02 to the bUserCommand register 0x0180 (Table 9: Mode control). The above three commands represent the absolute minimum required to get video data output. The default configuration results in an output of VGA, 30 fps, YUV data format with ITU embedded codes requiring a external clock frequency of 12MHz. In practice the user is likely to require to write some additional setup information prior to receive the required data output.
10 Host communication - I²C control interface
extended interface is known as the V2W interface. STOP and START conditions can only be generated by a V2W master. the transmitter if the data byte has been successfully received or not. of the data flow between the master and the slave. master is writing to or reading from the slave. Figure 17. Write message sends a repeated START (Sr). Figure 18. Read message
2 Index Bytes
after reading a final byte of data. Figure 19. Detailed overview of message format
- Master generates a START condition to signal the start of new message.
- Master outputs, MS bit first, a 7-bit device address of the slave the master is trying to
equipment to change their contents. Others (such as the chip id) are read only. includes “real” registers, SRAM, ROM and/or micro controller values. Figure 24. Internal register index space
different locations within the sensor. The range of instructions available are detailed below. Single location, single byte data read or write. Write no data byte. Only sets the index for a subsequent read message. Multiple location, multiple data read or write for fast information transfers. For the master writing to the slave the R/W bit is set to zero. message is terminated with a stop condition from the master. Figure 25. Random location, single write
data returned is that accessed by the previous read or write message. and NOT the index value. This was the case in older V2W implementations. line cannot rise, which is part of the stop condition. Figure 26. Current location, single read
Figure 29. Multiple location read
Figure 30. Multiple location read starting from a random location
11 Register map
The VL6524/VS6524 I²C write address is 0x20. represent them and are therefore stored in more than 1 location. Note: For all 16 bit parameters the MSB register must be written before the LSB register. The data stored in each location can be interpreted in different ways as shown below. Float 900 is used in ST co-processors to represent floating point numbers in 2 bytes of data.
- represent the number as a binary floating point number. Normalize the mantissa and calculate the exponent to give a binary scientific representation of 1.xxxxxxxxx * 2^y.
- The x symbols should represent 9 binary digits of the mantissa, round or pad with zeros to achieve 9 digits in total. Remove the leading 1 from the mantissa as it is redundant.
- To calculate the y value Bias the exponent by adding to 31 decimal then converting to binary.
- The data can then be placed in the structure above.
Table 6. Data type
VL6524/VS6524 Register map Example Convert -0.41 to Float 900 Convert the fraction into binary by successive multiplication by 2 and removal of integer component 0.41 * 2 = 0.82 0 0.82 * 2 = 1.64 1 0.64 * 2 = 1.28 1 0.28 * 2 = 0.56 0 0.56 * 2 = 1.12 1 0.12 * 2 = 0.24 0 0.24 * 2 = 0.48 0 0.48 * 2 = 0.96 0 0.96 * 2 = 1.92 1 0.92 * 2 = 1.84 1 0.84 * 2 = 1.68 1 0.68 * 2 = 1.36 1 0.36 * 2 = 0.72 0 This gives us -0.0110100011110. We then normalize by moving the decimal point to give - 1.10100011110 * 2^-2. The mantissa is rounded and the leading zero removed to give 101001000. We add the exponent to the bias of 31 that gives us 29 or 11101. A leading zero is added to give 6 bits 011101. The sign bit is set at 1 as the number is negative. This gives us 1011 1011 0100 1000 as our Float 900 representation or BB48 in hex. To convert the encoded representation back to a decimal floating point, we can use the following formula. Real is = (-1)^sign * ((512+mantissae)>> 9) * 2^(exp-31) Thus to convert BB48 back to decimal, the following procedure is followed: Note that >>9 right shift is equal to division by 2^9. Sign = 1 Exponent = 11101 (29 decimal) Mantissa = 101001000 (328 decimal) This gives us: real = -1 * 1.640625 * 0.25 real = -0.41015625 When compared to the original -0.41, we see that some rounding errors have been introduced.
enable register is set to 0x06. Table 7. Low-level control registers Table 8. Device parameters Table 9. Mode control
Table 10. Mode status Table 11. RunModeControl Table 12. Clock manager input control Table 13. Power management control
Table 14. Frame rate control Table 15. Pipe setup bank selection Table 16. Pipe setup bank0 control corresponding to no sub-sampling.
Table 17. Pipe setup bank1 control corresponding to no sub-sampling.
Table 18. View live control Table 19. White balance control
Table 20. Exposure control calculated by the algorithm. The exposure parameters are set manually. Weight is Centered or Backlit or Flat. EV. This is a signed register.
Table 21. Exposure status Table 22. Exposure algorithm control Control exposure leaky integrator. Set to 0 for reactive systems. Set to 4 for more stable systems. Table 23. Flashgun control
- The mode control register has priority over this function
MSB 0x1783 R/W M I 0x02 This is used to set the duration of the flash.
Table 24. Flicker frequency control Modes for anti-flicker compilation. Table 25. Defect correction control Table 26. Sharpening control changes in the image (i.e. Noise). Table 27. Fade to black damper control Set to disable fade to black operation.
1.0 effectively disables fade to black.
Table 28. Dither control Table 29. Output formatter control
12 Optical specifications
12.1 Average sensitivity
The average sensitivity is a measure of the image sensor response to a given light stimulus. the experiment is repeated with no illumination to give a value Xdark. Table 30. Optical specifications (1)
- All measurements made at 23°C ± 2°C
Horizontal field of view 46 49 51 deg. Vertical field of view 35 37 39 deg.
- Value determined through calculation
- By design the device has an acceptable quality between hyperfocal distance /2 and infinity.
Table 31. VS6524 average sensitivity
12.2 Spectral response
The spectral response for the VS6524 sensor is shown in Figure 31. Figure 31. VS6524 spectral response Quantum efficiency - Sensitivity = 0.71V/lux.sec.
13.1 Absolute maximum ratings
periods may affect device reliability.
13.2 Operating conditions
Table 32. Absolute maximum ratings Table 33. Supply specifications
- Module can contain routing resistance up to 5 Ω.
13.3 DC electrical characteristics
Note: Over operating conditions unless otherwise specified. Table 34. DC electrical characteristics
0.2 VDD
0.4 VDD
Table 35. Typical current consumption
13.4 AC electrical characteristics
13.4.1 External clock
clock input is fail-safe in power down mode.
13.4.2 Chip enable
CE is a CMOS digital input. The module is powered down when a logic 0 is applied to CE. Chapter 4 for power down and for power-up sequence.
13.4.3 I²C slave interface
Table 36. External clock Table 37. Serial interface voltage levels (1)
- Maximum V IH = VDDmax + 0.5 V
- C b = capacitance of one bus line in pF
Figure 32. Voltage level specification Table 38. Timing specification (1)
- All values are referred to a V IHmin = 0.9 VDD and VILmax = 0.1 VDD
- C b = capacitance of one bus line in pF
13.4.4 Parallel data interface timing
signals (HSYNC, VSYNC, PCLK and FSO). bit-serial output configurations. The port is disabled (high impedance) upon reset. Figure 35. Parallel data output video timing
13.5 ESD handling characteristics
Table 39. Parallel data interface timings Table 40. ESD handling characteristics
14.1 SmOP
Figure 36. VS6524Q06J outline drawing Note:# Image direction register use default settings.
1 GND
Figure 37. VS6524Q06J socket assembly outline drawing for information only Note:# Image direction register use default settings.
14.2 LGA
conditions are also marked on the inner box label. ECOP ACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Table 41. LGA package mechanical data
Table 41. LGA package mechanical data (continued)
Figure 38. VL6524QOMH outline drawing
Table 42. VL6524 pin assignment
1 AVDD 10 GND 19 DIO7 28 GND
2 GND 11 NC 20 DIO6 29 PCLK
3 SDA 12 NC 21 DIO5 30 VDD
4 SCL 13 NC 22 DIO4 31 NC
6 VDD 15 AVDD 24 DIO3 33 NC
7 CLK 16 HSYNC 25 DIO2 34 NC
8 GND 17 VSYNC 26 DIO1 35 NC
Table 43. Order codes Table 44. Document revision history 21-Mar-2006 1 Initial release. 06-Nov-2006 3 Addition of VL6524 reference and package outline drawing.