IM564-X6D

IM564-X6D INFINEON | Alldatasheet

Document overview

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Technical content

Features

 Fully isolated Dual In-Line molded module  Very low thermal resistance due to DCB substrate  Lead-free terminal plating; RoHS compliant Inverter  TRENCHSTOP™ IGBTs for Inverter  Rugged SOI gate driver technology with stability against transient and negative voltage  Allowable negative VS potential up to -11 V for signal transmission at VBS = 15 V  Integrated bootstrap functionality  Over current shutdown  Built-in NTC thermistor for temperature monitor  Under-voltage lockout at all channels  Low-side common emitter  Sleep function  Fast track shutdown  Cross-conduction prevention  All of 6 switches turn off during protection PFC  CoolMOS™ Power MOSFET for PFC  Rapid switching emitter controlled diode Potential applications  Air-conditioners, Fans, Pumps, Low power motor drives

Datasheet 2 of 26 Verison 2.3 2021-12-21 CIPOS™ Mini IM564 IM564-X6D/IM564-X6DS Product validation Product validation Qualified for industrial applications according to the relevant tests of JEDEC47/20/22. Table 1 Product Information Base Part Number Package Type Standard Pack Remarks Form MOQ IM564-X6D DIP 36x21D 14 pcs / Tube 280 pcs IM564-X6DS DIP 36x21D 14 pcs / Tube 280 pcs Extended stand-off

Datasheet 3 of 26 Verison 2.3 2021-12-21 CIPOS™ Mini IM564 IM564-X6D/IM564-X6DS Table of Contents Table of Contents

Datasheet 4 of 26 Verison 2.3 2021-12-21 CIPOS™ Mini IM564 IM564-X6D/IM564-X6DS Internal Electrical Schematic

1 Internal Electrical Schematic

N (17) W (18) U (20) P (21) X (22) NX (23) (2) VB(U) (15) ITRIP (14) VFO (10) LIN(U) (11) LIN(V) (12) LIN(W) (16) VSS (13) VDD (4) VB(V) (6) VB(W) (7) HIN(U) (8) HIN(V) (9) HIN(W) (1) VS(U) (3) VS(V) (5) VS(W) V (19) GX (24) Thermistor VSS VDD LIN3 LIN2 LIN1 VFO ITRIP LO3 LO2 LO1 HO1 HO2 HO3 VB1 VS1VB2 VS2 VB3 VS3 HIN3 HIN2 HIN1 RBS1 RBS2 RBS3 Figure 1 Internal electrical schematic

Datasheet 5 of 26 Verison 2.3 2021-12-21 CIPOS™ Mini IM564 IM564-X6D/IM564-X6DS Pin Description

2 Pin Description

2.1 Pin Assignment

(1) VS(U) (2) VB(U) (3) VS(V) (4) VB(V) (5) VS(W) (6) VB(W) (7) HIN(U) (8) HIN(V) (9) HIN(W) (10) LIN(U) (11) LIN(V) (12) LIN(W) (13) VDD (14) VFO (15) ITRIP (16) VSS (23) NX (22) X (21) P (20) U (19) V (18) W (17) N (24) GX Figure 2 Pin configuration Table 2 Pin assignment Pin Number Pin name Pin Description

1 VS(U) U-phase high-side floating IC supply offset voltage

2 VB(U) U-phase high-side floating IC supply voltage

3 VS(V) V-phase high-side floating IC supply offset voltage

4 VB(V) V-phase high-side floating IC supply voltage

5 VS(W) W-phase high-side floating IC supply offset voltage

6 VB(W) W-phase high-side floating IC supply voltage

7 HIN(U) U-phase high-side gate driver input

8 HIN(V) V-phase high-side gate driver input

9 HIN(W) W-phase high-side gate driver input

10 LIN(U) U-phase low-side gate driver input

11 LIN(V) V-phase low-side gate driver input

12 LIN(W) W-phase low-side gate driver input

13 VDD Low-side control supply

14 VFO Fault output / Temperature monitor

15 ITRIP Over-current shutdown input

16 VSS Low-side control negative supply

17 N Low-side emitter

Datasheet 6 of 26 Verison 2.3 2021-12-21 CIPOS™ Mini IM564 IM564-X6D/IM564-X6DS Pin Description Pin Number Pin name Pin Description

18 W Motor W-phase output

19 V Motor V-phase output

20 U Motor U-phase output

21 P Positive output voltage / Positive bus input voltage

22 X PFC MOSFET drain

23 NX PFC MOSFET source

24 GX PFC MOSFET gate

2.2 Pin Description

HIN(U, V, W) and LIN(U, V, W) (Low-side and high- side control pins, Pin 7 - 12) These pins are positive logic and they are responsible for the control of the integrated IGBT s. The Schmitt -trigger input threshold s of them are such to guarantee LSTTL and CMOS compatibility down to 3.3 V controller outputs. A p ull-down resistor of about 5 kΩ is internally provided to pre - bias input during supply start -up, and a zener clamp is provided to protect the pin. Negative pulses down to an absolute minimum of -5.5 V are allowed that offers an outstanding robustness. Input Schmitt-trigger and noise filter provide noise rejection to short input pulses. The noise filter suppresses control pulses shoter than the filter time tFIL,IN. The Figure 4 describes how the filter works. An input pulse-width shorter than 1 µs is not recommended. IM564 INPUT NOISE FILTER  k5 Schmitt-Trigger SWITCH LEVEL VIH; VILVSS HINx LINx VDD Figure 3 Input pin structure HIN LIN HO LOlow high tFIL,IN tFIL,INa) b) HIN LIN HO LO Figure 4 Input filter timing diagram The integrated gate drive r additionally provides a shoot-through prevention capability that avoids the simultaneous on -states of the same leg (i.e. HO1 and LO1, HO2 and LO2, HO3 and LO3). When both inputs of the same leg are activated, only formerly activated one is remained activated so that the leg is kept steadily in a safe state. A minimum deadtime insertion of typically 360 ns is also provided by driver, in order to reduce cross - conduction of the IGBTs. VFO (Fault-output and NTC, Pin 14) The V FO pin indicates a module failure in case of under voltage at pin V DD or in case of triggered over current detection at ITRIP. A n external pull-up resistor is required. VFO VSS VDD RON,FLT From ITRIP - Latch From UV detection IM564 Thermistor Figure 5 Internal circuit at pin VFO The sleep function is activated after each trigger of ITRIP or under -voltage lockout. A new edge input signal is mandatory to activate gate drives after falut-clear time as shown in Figure 11. ITRIP (Over current detection function, Pin 15) The IM564 product family provides an over current detection function by connecting the ITRIP input with the IGBT current feedback. The ITRIP comparator threshold (typ. 0.525 V) is referenced to VSS. A n input noise filter (tITRIPMIN = typ. 300 ns) prevents the driver to detect false over -current events. Over current detection generates a shutdown of outputs of the gate driver. Fast track shutdown

Datasheet 7 of 26 Verison 2.3 2021-12-21 CIPOS™ Mini IM564 IM564-X6D/IM564-X6DS Pin Description function allows low -side outputs to be turned off faster than high-side outputs about 200 ns. The fault-clear time is set to minimum 100 µs. VDD, V SS (Low-side c ontrol supply and reference, Pin 13, 16) VDD is the control supply and it provides power both to input logic and to output stage. Input logic is referenced to VSS ground. The under -voltage circuit enables the device to operate at power on when a supply voltage of at least a typical voltage of VDDUV+ = 12.4 V is present. The gate driver shuts down all the outputs, when the VDD supply voltage is below VDDUV- = 11.5 V. This prevents the IGBTs from critically low gate voltage levels during on-state and therefore from excessive power dissipation. VB(U, V, W) and V S(U, V, W) (High -side supplies, Pin 1 - 6) VB to V S is the high -side supply voltage. The high - side circuit can float with respect to V SS following the high-side IGBT emitter voltage. Due to the low power consumption, the floating driver stage is supplied by integrated bootstrap circuit. The under-voltage detection operates with a rising supply threshold of typical V BSUV+ = 1 1.5 V and a falling threshold of VBSUV- = 10.7 V. VS(U, V, W) provide a high robustness against negative voltage in respect of VSS of -50 V transiently. This ensures very stable designs even under harsh conditions. N (Low-side emitter, Pin 17) The low-side common emitter is available for current measurement . It is recommended to keep the connection to pin V SS as short a s possible to avoid unnecessary inductive voltage drops. W, V, U (High-side emitter and low-side collector, Pin 18 - 20) These pins are connected to motor U, V, W input pins P (Positive bus input voltage, Pin 21) The high -side IGBT s and PFC diode cathode are connected to the bus voltage. It is noted that the bus voltage does not exceed 450 V. X, NX, GX (Single boost PFC, Pins 22-24) These pins are drain, source, and gate of MOSFET for single boost PFC stage.

Datasheet 8 of 26 Verison 2.3 2021-12-21 CIPOS™ Mini IM564 IM564-X6D/IM564-X6DS Absolute Maximum Ratings

3 Absolute Maximum Ratings

(VDD = 15 V, VGE = 15 V and TJ = 25° C, if not stated otherwise)

3.1 Module Section

Description Symbol Condition Value Unit Storage temperature range TSTG -40 ~ 125 °C Operating case temperature TC Refer to Figure 7 -40 ~ 125 °C Operating junction temperature TJ -40 ~ 150 °C Isolation test voltage VISO 1 min, RMS, f = 60 Hz 2000 V

3.2 Inverter Section

Description Symbol Condition Value Unit Max. blocking voltage VCES IC = 250 µA 600 V DC link supply voltage of P-N VPN Applied between P-N 450 V DC link supply voltage (surge) of P-N VPN(surge) Applied between P-N 500 V Continuous collector current IC TC = 25° C, TJ < 150° C ±20 A TC = 80° C, TJ < 150° C ±15 Maximum peak collector current IC(peak) TC = 25° C, TJ < 150° C less than 1 ms ±40 A Power dissipation per IGBT Ptot 63.1 W Short circuit withstand time1 tSC VDC ≤ 400V, TJ = 150° C 5 µs

3.3 Control Section

Description Symbol Condition Value Unit High-side offset voltage VS 600 V Repetitive peak reverse voltage of bootstrap diode VRRM 600 V Module supply voltage VDD -1 ~ 20 V High-side floating supply voltage (VB reference to VS) VBS -1 ~ 20 V Input voltage(LIN, HIN, ITRIP) VIN -5.5 ~ VDD+0.5 V 1 Allowed number of short circuits: < 1000; time between short circuits: > 1 s.

Datasheet 9 of 26 Verison 2.3 2021-12-21 CIPOS™ Mini IM564 IM564-X6D/IM564-X6DS Absolute Maximum Ratings

3.4 PFC Section

Description Symbol Condition Value Unit Max. blocking voltage VDSS VGS = 0 V, ID = 1 mA 600 V Gate-source voltage VGS DC ±20 V AC (f > 1 Hz) ±30 Continuous drain current ID TC = 25°C, TJ ≤ 150°C ±20 A TC = 80°C, TJ ≤ 150°C ±15 Maximum peak drain current ID(peak) TJ ≤ 150°C, TC = 25°C ±40 A Power dissipation Ptot 88.6 W Diode forward current IF TC = 25°C, TJ ≤ 150°C 20 A TC = 80°C, TJ ≤ 150°C 15 Diode pulsed current IF(peak) TC = 25°C, TJ ≤ 150°C 40 A Diode non repetitive surge forward current IFSM TC = 25°C, tp = 10 ms, sine half-wave 120 A

Datasheet 10 of 26 Verison 2.3 2021-12-21 CIPOS™ Mini IM564 IM564-X6D/IM564-X6DS Thermal Characteristics

4 Thermal Characteristics

Description Symbol Condition Value Unit Min. Typ. Max. Single IGBT thermal resistance, junction-case(Inverter) RthJC (See Figure 7 for TC measurement point)

1.98 K/W

Single Diode thermal resistance, junction-case(Inverter) RthJC,D 3.24 K/W Single MOSFET thermal resistance, junction-case(PFC) RthJC (See Figure 7 for TC measurement point)

1.41 K/W

Single Diode thermal resistance, junction-case(PFC) RthJC,D 2.34 K/W

Datasheet 11 of 26 Verison 2.3 2021-12-21 CIPOS™ Mini IM564 IM564-X6D/IM564-X6DS Recommended Operation Conditions

5 Recommended Operation Conditions

All voltages are absolute voltages referenced to VSS -potential unless otherwise specified. Description Symbol Value Unit Min. Typ. Max. DC link supply voltage of P-N VPN 0 - 450 V Low-side supply voltage VDD 13 15 17.5 V High-side floating supply voltage (VB vs. VS) VBS 13 - 17.5 V Logic input voltages LIN, HIN, ITRIP VIN VITRIP 0 - 5 V Inverter PWM carrier frequency fPWM - - 20 kHz PFC switching frequency fPWM(PFC) 150 kHz External deadtime between HIN and LIN DT 1.5 - - µs Voltage between VSS – N and NX (including surge) VCOMP -5 - 5 V Minimum input pulse width PWIN(ON) PWIN(OFF) 1 - - µs Control supply variation ΔVBS, ΔVDD

1 V/µs

PFC MOSFET gate-source voltage VGE 10 15 18 V PFC MOSFET external gate parameters RG - 5.1 - Ω CGS - 4.7 - nF RGS - 10 - kΩ

Datasheet 12 of 26 Verison 2.3 2021-12-21 CIPOS™ Mini IM564 IM564-X6D/IM564-X6DS Static Parameters

6 Static Parameters

(VDD = 15 V, VGE = 15 V and TJ = 25° C, if not stated otherwise)

6.1 Inverter Section

Description Symbol Condition Value Unit Min. Typ. Max. Collector-emitter voltage VCE(Sat) IC = 20 A, TJ = 25° C IC = 20 A, TJ = 150° C 1.75 2.0 2.05 - V Collector-emitter leakage current ICES VCE = 600 V - - 1 mA Diode forward voltage VF IF = 20 A, TJ = 25° C IF = 20 A, TJ = 150° C 2.2 2.15 2.8 - V

6.2 Control Section

Description Symbol Condition Value Unit Min. Typ. Max. Logic "1" input voltage (LIN, HIN) VIH 1.7 2.0 2.3 V Logic "0" input voltage (LIN, HIN) VIL 0.7 0.9 1.1 V ITRIP positive going threshold VIT,TH+ 475 525 570 mV ITRIP input hysteresis VIT,HYS 45 70 - mV VDD and VBS supply under voltage positive going threshold VDD and VBS supply under voltage negative going threshold VDD and VBS supply under voltage lockout hysteresis VDDUVH VBSUVH 0.5 0.9 - V Quiescent VBx supply current (VBx only) IQBS HIN = 0 V - - 300 µA Quiescent VDD supply current (VDD only) IQDD LIN = 0 V, HINX = 5 V - - 1.1 mA Input bias current for LIN, HIN IIN+ VIN = 5 V - 1.1 1.7 mA Input bias current for ITRIP IITRIP+ VITRIP = 5 V - 68 185 µA Input bias current for VFO IFO VFO = 5 V, VITRIP = 0 V - 60 - µA VFO output voltage VFO IFO = 10 mA, VITRIP = 1 V - 0.35 - V Bootstrap diode forward voltage VF_BSD IF = 0.3 mA - 1.0 - V Bootstrap diode resistance RBSD VF1 = 4 V, VF2 = 5 V - 37 - Ω

Datasheet 13 of 26 Verison 2.3 2021-12-21 CIPOS™ Mini IM564 IM564-X6D/IM564-X6DS Static Parameters

6.3 PFC Section

Description Symbol Condition Value Unit Min. Typ. Max. PFC MOSFET drain-source on- state resistance RDS(on) ID = 20 A, VGS= 15 V, TJ = 25° C ID = 20 A, VGS= 15 V, TJ = 150° C 0.086 0.156 0.115 - Ω PFC MOSFET drain-source leakage current IDSS VDS = 600 V, VGS= 0 V - - 1 mA PFC diode forward voltage VF IF = 20 A, TJ = 25° C IF = 20 A, TJ = 150° C 1.4 1.3 - V

Datasheet 14 of 26 Verison 2.3 2021-12-21 CIPOS™ Mini IM564 IM564-X6D/IM564-X6DS Dynamic Parameters

7 Dynamic Parameters

(VDD = 15 V, VGE = 15 V and TJ = 25° C, if not stated otherwise)

7.1 Inverter Section

Description Symbol Condition Value Unit Min. Typ. Max. Turn-on propagation delay time ton VLIN, HIN = 5 V, IC = 20 A, VDC = 300 V - 740 - ns Turn-on rise time tr - 60 - ns Turn-on switching time tc(on) - 200 - ns Reverse recovery time trr - 215 - ns Turn-off propagation delay time toff VLIN, HIN = 0 V, IC = 20 A, VDC = 300 V - 860 - ns Turn-off fall time tf - 20 - ns Turn-off switching time tc(off) - 65 - ns Short circuit propagation delay time tSCP From VIT,TH+ to 10% ISC - 1600 - ns IGBT turn-on energy (includes reverse recovery of diode) Eon VDC = 300 V, VDD = 15 V, IC = 20 A TJ = 25° C TJ = 150° C 710 780 µJ IGBT turn-off energy Eoff VDC = 300 V, VDD = 15 V, IC = 20 A TJ = 25° C TJ = 150° C 250 350 µJ Diode recovery energy Erec VDC = 300 V, VDD = 15 V, IC = 20 A TJ = 25° C TJ = 150° C 115 µJ

7.2 Control Section

Description Symbol Condition Value Unit Min. Typ. Max. Input filter time ITRIP tITRIP VITRIP = 1 V - 530 - ns Input filter time at LIN, HIN for turn on and off tFIL,IN VLIN, HIN = 0 V or 5 V - 290 - ns Fault clear time after ITRIP-fault tFLTCLR 100 280 - µs ITRIP to Fault propagation delay tFLT VLIN, HIN = 0 or VLIN, HIN = 5 V, VITRIP = 1 V - 680 1000 ns Internal deadtime DTIC - 360 - ns Matching propagation delay time (On and Off) all channels MT External dead time > 500 ns - 20 - ns

Datasheet 15 of 26 Verison 2.3 2021-12-21 CIPOS™ Mini IM564 IM564-X6D/IM564-X6DS Dynamic Parameters

7.3 PFC Section

Description Symbol Condition Value Unit min typ max Input capacitance Ciss VGS = 0 V, VDC = 400 V, f = 250 kHz - 1952 - pF Output capacitance Coss - 33 - Effective output capacitance, energy related1 Co(er) VGS = 0 V, VDC = 0..400 V - 62 - Gate charge total QG VDC = 400 V, ID = 10.5 A, VGS = 0 to 10 V - 45 - nC Turn-on delay time td(on) VDC = 400 V, ID = 20 A, RG = 5.1 Ω, CGS = 4.7 nF, RGS = 10 kΩ, TJ = 25° C - 30 - ns Turn-on rise time tr - 25 - ns Turn-off delay time td(off) - 110 - ns Turn-off fall time tf - 20 - ns Reverse recovery time trr - 45 - ns Turn-on energy Eon VDC = 400 V, ID = 20 A, RG = 5.1 Ω, CGS = 4.7 nF, RGS = 10 kΩ TJ = 25° C TJ = 150° C 310 390 µJ Turn-off energy Eoff VDC = 400 V, ID = 20 A, RG = 5.1 Ω, CGS = 4.7 nF, RGS = 10 kΩ TJ = 25° C TJ = 150° C 110 130 µJ Diode recovery energy Erec VDC = 400 V, ID = 20 A, RG = 5.1 Ω, CGS = 4.7 nF, RGS = 10 kΩ TJ = 25° C TJ = 150° C 140 µJ 1 Co(er) is a fixed capacitance that gives the same stored energy as Coss while VDS is rising from 0 to 400 V.

Datasheet 16 of 26 Verison 2.3 2021-12-21 CIPOS™ Mini IM564 IM564-X6D/IM564-X6DS Thermistor

8 Thermistor

Description Condition Symbol Value Unit Min. Typ. Max. Resistance TNTC = 25° C RNTC - 85 - k B-constant of NTC (Negative Temperature Coefficient) B(25/100) - 4092 - K -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 500 1000 1500 2000 2500 3000 3500 Thermistor temperature [℃] Thermistor resistance [kΩ ] Figure 6 Thermistor resistance – temperature curve and table (For more information, please refer to the application note ‘AN2016-10 CIPOS Mini Technical description’) 50 55 60 65 70 75 80 85 90 95 100 105 110 115 120 125 130 Thermistor temperature [℃] Thermistor resistance [kΩ ] Min. Typ. Max.

Datasheet 17 of 26 Verison 2.3 2021-12-21 CIPOS™ Mini IM564 IM564-X6D/IM564-X6DS Mechanical Characteristics and Ratings

9 Mechanical Characteristics and Ratings

Description Condition Value Unit Min. Typ. Max. Comparative Tracking Index (CTI) 600 - - V Mounting torque M3 screw and washer 0.49 - 0.78 Nm Backside Curvature Refer to Figure 8 -50 - 100 µm Weight - 6.83 - g

Datasheet 18 of 26 Verison 2.3 2021-12-21 CIPOS™ Mini IM564 IM564-X6D/IM564-X6DS Qualification Information

10 Qualification Information

UL Certification File number: E314539 RoHS Compliant Yes (Lead-free terminal plating) ESD HBM(Human Body Model) Class 2 CDM(Charged Device Model) Class

Datasheet 19 of 26 Verison 2.3 2021-12-21 CIPOS™ Mini IM564 IM564-X6D/IM564-X6DS Diagrams and Tables

11 Diagrams and Tables

11.1 TC Measurement Point

Figure 7 TC measurement point1

11.2 Backside Curvature Measurment Point

Figure 8 Backside curvature measurement position 1Any measurement except for the specified point in Figure 7 is not relevant for the temperature verification and brings wrong or different information.

Datasheet 20 of 26 Verison 2.3 2021-12-21 CIPOS™ Mini IM564 IM564-X6D/IM564-X6DS Diagrams and Tables

11.3 Switching Time Definition

0.9V 2.0V 90% 10%10% 10% 90% toff tf ton tr tc(off) tc(on) 10% trr 10% irm irm Figure 9 Switching times definition of inverter part vGS iD vDS 90% 10% td(off) tf tr td(on) trr 10% 90% 10% 10% 90% Figure 10 Switching times definition of PFC part

11.4 Sleep function timing diagram

Figure 11 Sleep function timing diagram

Datasheet 21 of 26 Verison 2.3 2021-12-21 CIPOS™ Mini IM564 IM564-X6D/IM564-X6DS Application Guide

12.1 Typical Application Schematic

<Signal for protection> VDD line 5 or 3.3V line Current sensing N (17) W (18) U (20) P (21) X (22) NX (23) (2) VB(U) (15) ITRIP (14) VFO (10) LIN(U) (11) LIN(V) (12) LIN(W) (16) VSS (13) VDD (4) VB(V) (6) VB(W) (7) HIN(U) (8) HIN(V) (9) HIN(W) (1) VS(U) (3) VS(V) (5) VS(W) V (19) GX (24) VSS VDD LIN3 LIN2 LIN1 VFO ITRIP LO3 LO2 LO1 HO1 HO2 HO3 VB1 VS1 VB2 VS2 VB3 VS3 HIN3 HIN2 HIN1 RBS1 RBS2 RBS3 PFC gate driver IC AC 3-ph AC Motor Input surge voltage sensing <Signal for protection> Micro Controller #6 #7 VDD line RG CGSRGS Figure 12 Typical application circuit  #1 Input circuit − RC filter can be used to reduce input signal noise. (100 Ω, 1 nF) − The capacitors should be located close to the IPM (to VSS terminal especially).  #2 Itrip circuit − To prevent a mis operation of protection function, RC filter is recommended. − The capacitor should be located close to Itrip and VSS terminals.  #3 VFO circuit − VFO pin is open drain configuration. This terminal should be pulled up to the bias voltage of the 5 V/3.3 V through a proper resistor. − It is recommended that RC filter is placed close to the controller.  #4 VB-VS circuit − Capacitors for high-side floating supply voltage should be placed close to VB and VS terminals.  #5 Snubber capacitor − The wiring among the IPM, snubber capacitor and shunt resistors should be short as possible.  #6 Shunt resistor

Datasheet 22 of 26 Verison 2.3 2021-12-21 CIPOS™ Mini IM564 IM564-X6D/IM564-X6DS Application Guide − SMD type shunt resistors are strongly recommended to minimize its internal stray inductance.  #7 Ground pattern − Pattern overlap of power ground and signal ground should be minimized. The patterns should be connected at one end of shunt resistor only for the same potential.  #8 Input surge voltage protection circuit − This protection circuit can be added to protect PFC MOSFET from excessive surge voltage.  #9 Inrush current protection circuit − Proper inrush current protection circuit has to be considered. − Additional components such as thermistor, relay, or bypass diode may be required depending on the system design and the operating conditions including grid fluctuation.

12.2 Performance Chart

Figure 13 Maximum operating current SOA of inverter part1 1This maximum operating current SOA is just one of example based on typical characteristics for this product. It can be changed by each user’s actual operating conditions. 0 25 50 75 100 125 150 Maximum output current, IO [ARMS] Case temperature, TC [oC] fSW = 5 kHz VDC = 400 V, VDD = VBS = 15 V, SVPWM fSW = 15 kHz

Datasheet 23 of 26 Verison 2.3 2021-12-21 CIPOS™ Mini IM564 IM564-X6D/IM564-X6DS Package Outline Figure 14 IM564-X6D

Datasheet 24 of 26 Verison 2.3 2021-12-21 CIPOS™ Mini IM564 IM564-X6D/IM564-X6DS Package Outline Figure 15 IM564-X6DS

Datasheet 25 of 26 Verison 2.3 2021-12-21 CIPOS™ Mini IM564 IM564-X6D/IM564-X6DS

Revision history

Date of release Description of changes Version 2.0 2019-08-09 Initial Release Version 2.1 2019-11-05 Added remark in Table 1 Corrected error in Figure 9 Version 2.2 2020-04-24 Corrected error in Figure 13 Updated Figure 14 and Figure 15 Version 2.3 2021-12-21 Updated Figure 12

81726 München, Germany

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