IM4702

IM4702 INTERSIL | Alldatasheet

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CB nl = IM4702/4712 ® : Baud Rate Generator 3 T-15-33-09 § GENERAL DESCRIPTION FEATURES be] The IM4702/12 Baud Rate Generators provide neces- © Provides 14 Most Commonly Used BAUD Rates rd sary clock signals for digital data transmission systems, © On-Chip Oscillator Requires Only One External Part =" such as UARTs, using a 2.4576MHz crystal oscillator as an (M4712) Input. They control up to 8 output channels and can be cas- caded for output expansion. egomrols uP ro eon Tranemuseion Channels Output rate is controlled by four digital input lines, and TTL Compa utpute ink 1.6m. with the specified crystal, is selectable from zero” through © Uses Standard 2.4576MHz Crystal 9600 Baud. In addition, 19200 Baud is possible via hardwir- ® Low Power Consumption: 5.6mW Guaranteed ing. Maximum Standby Multi-channel operation is facilitated by making the clock © Pin and Function Compatible With 4702B and HD- frequency and the +8 prescaler outputs available external- 4702 ly. This allows up to eight simultaneous Baud rates to be © Inputs Feature Active Pull-Ups generated. The M4712 is identical to the IM4702 with the exception PIN DESCRIPTION that the 1M4712 integrates the oscillator feedback resistor [signal | Pin | Description and two load capacitors on-chip. [Go—G | 1.24 | Presosler Outputs ORDERING INFORMATION | ECP | 4 | &xternal Glock Enable Input Order Temperature Package [cP | 5 | ExternalClock input Number Range 8 [Ox | 6 | CrystalOutput jepncenpp | 9 [Lk | 7 | onetatinput ————d IM4702IPE_| —40°Cto +85°C | _16-pin PLASTIC Sa Negative Supply ~arcto 485°C | 16-pin CERD [| co | |_ Glock Output IM4712WJE 40°C to pin IP [z~ 110 | Baud Rate 0 16-pin PLASTIC [ So-Se [14-11] Baud Rate Select inputs [im [15 | Multipiexed input Positive Supply [sagen | r _s [ commenwerioa Teas | i = a : : TH : | Clos BI #2 vo0 ter BD H Te D Hit Ct > || sft es L) ee ed: Babs c ' ocis ee, ike Matt 2 || ir yeaa Cor td: spe ' | UPL, ce | ee PU Uo ooro-2 eee UE eae Figure 2:in EE 7, Configuration ' 'V VIV HT (Outline drawings wot dad sel i es JE, PE) | ' CO eth “immer cron} {liniaccacaeedocdsaesece 0973-1 Figure 1: Functional Diagram INTERSIL’S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE. THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTASILITY AND FITNESS FOR A PARTICULAR USE. NOTE: AI typical valves have boon charactertred but are not tested. 11-18

• IM4702/4712 SBIINTTETESIM, iS T-75-33-04 nu : p NOTE: Stresses above those listed under “Absolute Maximum Ratings” g ABSOLUTE MAXIMUM RATINGS tna) cause porndnan! damage to te davce, These are sess retings only Supply Voltage (Vpp—Vgs) «+++ s+seesereseereees FB.0V and functional operation of the device at these or any other conditions

ELECTRICAL CHARACTERISTICS

DC CHARACTERISTICS vVpp= +5V+10% Vgg=OV, Ta= —40°C to + 85°C Limits Input Voltage High ee cs Input Voltage Low PT 50% Ves Input Current Other Inputs | Vin=Vpp ee ee High 1.4742 All other pins grounded | st +t0 | Mie Input Current 1, 4702 Pin under test at ground ee Low 4742 All other Inputs at Vpp. | tt pA Other Inputs | =15 | 100 _| Output Voltage High lou< — 1A; Inputs at Vgs or Vop | Voo-05 | si v Output Voltage Low loL< + 1pA; Inputs at Vss or Vop Ee Output Current Inputs at-Vgs or Vpp | -o1 | | Ouiputs _| Vor +26 | -10 [| Output Current | O, __| jot [| Low Allother Vo=0.4; Inputs at Vg or Vj mA ° if < i | | Eop=Vppi CP=Vss Istpy Quiescent Supply Current All other Inputs = Veg or Vpp, All outputs open

IM4702/4712 ESINTERSIL. ¥ 7-75-33-09 3 AC CHARACTERISTICS vpp= + 8V Vss=0V, Ta= 26°C 8 [min | Max _| 8 a Propagation delay, ly to CO [| ars | || as0_| put4712) [|e [tn | Cy(excepto,)=sopF [| 260 _| Propagation delay(1}, CP to CO a Cio) = 79F Y [220 _| . + =#— Propagation delay CO ° on Auszoone -— 4 [tm | propagation delay), CO to Input ; | es | | to Transttontimes <20ns [| _75_| [tm | Output Transition Time, (1) Input low=1.0V [| _ 160 | [tm ~__|_ (excepto) Inputhigh=Veo-tov [| 75 _—| [sem Fs st yo | i | io | | Clock pulse width(3) tyCP(H) | | | witixa7ozy [| [1 | | |, Pulse Width thd l3(4712) | 10 | | tld (47 12) [io [| NOTES: 1. Propagation delays and output transition times will vary with output load capacitance. 2. For multichannel! operation, propagation delay (CO to Qa) plus set-up time (Select to CO) Is guaranteed to be less than 367ns for the 1M4702/12. 3, The first high level clock pulse after Exp goes low must be at least 200ns wide to ensure reseling of all counters. 4. For dosign reference only, not 100% tested.

© IM4702/4712 SSINTERSIL < T-75 -33-07 a ; tlt) ota CPx o* a staked 60% co 4 te | : Ws Sl XC C5 X e . wet Ye z 101 | 10% tin Cen 0373-3 Figure 3: Switching Waveforms FUNCTIONAL DESCRIPTION Table 1: Clock Modes and Initialization Digital data transmission systems employ a wide range of standardized bit rates, ranging from 50 baud (for electrome- a Operation chanical devices) to 9600 baud (for high speed modems). Au H L Clocked from I, Modem electronic systems commonly use niversat Asyn- x L LPL | Clocked from CP chronous Receiver and Transmitter circuits (UARTs) to con- vert paralie! data inputs into a serial bit stream (transmitter) x t ft pontnyous Reset and to reconvert the serial bit stream into parallel outputs set During (receiver). In order to resynchronize the incoming serial CP=HIGH Time data, the reciever requires a clock rate which Is a multiple of the incoming bit rate. Popular MOSLSI UART circuits use a H = HIGH Level clock that Is 16 times the transmitted bit rate. The IM4702/ L = LOW Level 12 can generate 14 standard clock rates from one common x = Don't Care high frequency input. Ez = 1st HIGH Level Clock Pulse After E; The IM4702/12 contains the following five function sub- «= GosLow Se Aner SCP syatarns. . , FLTLFLE = Clock Pulses Oscillator — For conventional operation generating 16 out- . 0373-8 put clock pulses per bit period, the input clock frequency Counter Network -— The prescaler output Qo is a square must be 2.4576MHz (i.e. 9600 baud x 16 x 16, since the wave of 1% the Input frequency, and is used to drive the scan counter and the first flip-flop of the counter chain act frequency counter network generating 13 standardized fre- as an internal + 16 prescaler). A lower input frequency will quencies. Note that the frequencies are labeled in the block result in a proportionally lower output frequency. diagram and described in terms of the transmission bit rate, The IM4702/12 can be driven from two alternate clock In @ conventional system using a 2.4576MHz clock input, sources: (1) When the Eop (External Clock Enable) input is the actua! output frequencies are 16 times higher. LOW, the CP input is the clock source. (2) When the Ecp The output from the first frequency divider flip-flop is thus input is HIGH, a crystal connected between |, and O,, or a labeled 9600, since it is used to transmit or receive 9600 signal applied to the |, input, is the clock source. baud (bits per second). The actual frequency at this node is Preacaler (Scan Counter) — The clock frequency is made 16 x 9.6kHz=153.6kHz. Seven more cascaded binaries available on the CO (Clock Output) pin and is applied to the generate the appropriate frequencies for bit rates 4800, + 6 prescaler with buffered outputs Qo, Qy, and Qo. 2400, 1200, 600, 300, 150, and 75.

IM4702/4712 AINMERSIL % T-75 -33-09 8 The other five bit rates are generated by Individual coun- Table 2: Truth Table for Rate Select Inputs g ters: s Output Rate (Z) a bit rate 1200 is divided by 6 to generate bit rate 200, Note 1 a bit rate 200 is divided by 4 to generate bit rate 50, L L L L Multiplexed Input (Ixy) N bit rate 2400 is divided by 18 to generate bit rate 134.5 L L L H Multiplexed Input (Iyy) with a frequency error of —0.87%, L L H L 50 Baud bit rate 2400 is also divided by 22 to generate bit rate L L H H 75 Baud 110 with a frequency error of ~0.83%, and L H L L 494.5 Baud BH rate 9600 is divided by 16/3 to generate bit rate L fH L H '200 Baud The 16/3 division is accomplished by alternating the divide t H H L 600 Baud ratio between 5 (twice) and 6 (once). The result is an exact L H H H 2400 Baud average output frequency with some frequency modulation. H L L L 9600 Baud Taking advantage of the + 16 feature of the UART, the H L L H 4800 Baud: resulting distortion fs less than 0.78% regardless of the H L H L 1800 Baud number of elements in a character, and therefore well within H L H H 4200 Baud the timing accuracy specified for high speed communica- tions equipment. Alll signals except 1800, have a 50% duty H H L L 2400 Baud cycle. H H L H 300 Baud Output Multiplexer — The outputs of the counter network H H H L 150 Baud are fed to a 16-input muitiplexer, which Is controlled by the H H H H 110 Baud Rate Select inputs (Sp—S3). The multiplexer output is then tesynchronized with the incoming clock in order to cancel ha eter all cumulative delays and to present an output signal at the eval buffered output. (Z) that is synchronous with the prescaler ‘Note 1; Actual output frequency Is 16 times the indicated output rate, as- outputs (Q9—Qz). Table 2 lists the correspondance be- suming @ clock frequency of 2.4576MHz, tween select code and output bit rate. Two of the 16 codes 5 do not select an internally generated frequency, but select Table 3: Crystal Specifications an input into which the user can feed either a different, non- ical Crystal Spec standardized frequency, or a static level (HIGH or LOW) to Tye “y pe generate “zero baud". Frequency 2.4576MHz “AT” Cut The bit rates most commonly used in modern data termi- Series Resistance (Max) 2500 nals (140, 150, 300, 1200, 2400 baud) require that no more Unwanted Modes —6dB (Min) than one input be grounded, easily achieved with a single Type of Operation Parallel pole, 5-position switch. 2400 baud Is selected by two differ- ent codes, so that the whole spectrum of modern digital Load Capacitance S2pF£0.5pF communication rates has a common HIGH on the Sg input. initlalization (Reset) — The initialization circuit generates a APPLICATIONS common master reset signal for all flip-flops in the IM4702/ Single Channel Bit Rate Generator 12. This signal is derived from a digital differentiator that Figure 4 shows the simplest application of the IM4702/ senses the first HIGH level on the CP input after the Ecp 12. This circuit generates one of five possible bit rates as input goes LOW. Upon initialization, all counters are reset determined by the setting of a single pole, 5-position switch. and all outputs will be in the LOW state. When Egp Is HIGH, The Bit Rate Output (Z) drives one standard TTL load or selecting the Crystal input, CP must be LOW; a HIGH level four low power Schottky loads over the full temperature on CP would apply a continuous reset. range. The possible output frequencies correspond to 100, All inputs to the 4702/12 except |, have on-chip pull-up 150, 300, 1200, and 2400 or 3600 Baud. For many low cost. circuits; the |, input of the 4712 has a high value resistor terminals, these five bit rates are adequate, tled to Oy. This mode of operation is commonly chosen for applica- tions using industry standard 1402/6402 UARTs.

IM4702/4712 EHINTERSIL § T+75 -33-87 048 Nn to 3

9 SPST SWITCH =

29 oo = bd 29 49 O+8v cpl 0 i 30 S684 > dice pos Ee : tk Pe 5 | meari2 “ pe % . » 24876 wits LGQ.00_O1_Oz_Z Yeen (0 — CRYSTAL fy cess OOH 1 oureur 2s TRO is Ww 2 RRL aay 40 0373-7 Figure 7: M4712 Baud Rate Generator With IM6402 CMOS UART