IM29LV001T ETC1 | Alldatasheet

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This advanced data sheet contains product specifications which are subject to change without notice. Rev. 0.27 Integrated Memory Technologies, Inc. 2285 Martin Ave., STE A, Santa Clara, CA 95050. Tel. (408) 986 -1088 Fax (408) 727 -8696 IMT IM29LV001T and IM29LV001B 1 M Bit (128K x 8) 3.3V-Only Flash Memory Features:

  • · 0.40 µm, triple-poly double-metal CMOS process
  • · Single power supply operation 3.3V ± 10% for both read and write
  • · High endurance > 10,000 program/erase cycles
  • · Fast read access time 70 and 90 ns
  • · Single page erasability for optimal data alterability Page size: 512 bytes
  • Hardwired data protection Inhibits program and erase operations of the top ( IM29LV001T) or bottom (IM29LV001B) 32 pages of the array for false write and virus prevention.
  • · Flexible boot block configurability
  • · Fast program and erase operations: Byte program : < 35 µsec typical Page erase : < 7 msec typical Chip erase : < 2 sec typical
  • · Self-timed program/erase operations with end-of-cycle detection Data# Polling and Toggle Bit
  • · Inadvertent write protection Glitch filtering for WE# and CE# Low Vcc (< 2.2 V ) write inhibit Hardwired data protection
  • · Low Icc for power conservation Read: 6 ma typical Write: 10 ma typical Stand-by: 10 µA typical
  • · Compatible with JEDEC byte wide pin- out and single-supply flash command standards
  • · Package types: 32-pin PLCC, TSOP and PDIP Others available upon request General Descriptions The IM29LV001T/B is a 1 Mega -bit, 5V-only page erasable flash mem ory organized as 128K X 8 bits.It is manufactured with IMT’s proprietary double metal, 0.40 µm CMOS flash technology. High performance cell design and advanced process technology attain better reliability, manufacturability, circuit performance and future scaleability than other alternative approaches. Fast, self-timed program/erase operations are made possible with an innovative cell and array architecture which is free from the over-erase problem of the traditional stacked-gate structures. Single page ( 512 bytes) data alterability ensures optimum flexibility and efficiency in program codes, parameters and data storage. It also allows backward compatibility to other large -erase-block based flash products for direct replacement. The IM29LV001T/B is design ed with interface features for direct in -system programming and erase operations. Vendor re-programmable, hardwired data protection is provided for absolute prevention in inadvertent data alteration and virus infection. The IM29LV001 conforms to the JEDEC byte wide memory pin-out and single supply flash command standards. Designed, manufactured and tested for extended endurance applications, the IM29LV001 is specified for more than 10 4 cycling endurance and greater than 10 years of data retention.

This advanced data sheet contains product specifications which are subject to change without notice. Rev. 0.27 Integrated Memory Technologies, Inc. 2285 Martin Ave., STE A, Santa Clara, CA 95050. Tel. (408) 986 -1088 Fax (408) 727 -8696 IMT Block Diagram Pin-out Assignments A12 A15 A16 N/C Vcc WE N/C DQ0 A14 A13 A11 OE A10 CE DQ7 DQ1 DQ2 Vss DQ3 DQ4 DQ5 DQ6 N/C A16 A15 A12 DQ0 DQ1 DQ2 16Vss Vcc WE N/C A14 A13 A11 OE A10 CE DQ7 DQ6 DQ5 DQ4 DQ3 32-pin PDIP 32-pin PLCC A16 A15 A12 A4 A3 DQ0 DQ1 DQ2 Vss Vcc N/C A14 A13 A11 A10 CE DQ7 DQ6 DQ5 DQ4 DQ3 OE WE N/C A16 A15 A12 A4A3 DQ0 DQ1 DQ2 Vss Vcc NC A14 A13 A11 A10 DQ7 DQ6 DQ5 DQ4 DQ3 OE CE WE N/C Standard 32-pin TSOP Reverse 32-pin TSOP Control Signal Inputs and Logic WE CE Address Input and Pre-decorder A16 I/O Buffer and Data Latch DQ0 DQ7 Y-Gating Flash Cell Array Y-Dec X-Dec Command Logic and State Machine High Voltage Generators and Logic OE

This advanced data sheet contains product specifications which are subject to change without notice. Rev. 0.27 Integrated Memory Technologies, Inc. 2285 Martin Ave., STE A, Santa Clara, CA 95050. Tel. (408) 986 -1088 Fax (408) 727 -8696 IMT Flexible Boot Block Architecture The page erase function of IM29LV001T/B erases only the bytes located inside the 512- byte boundary (as defined by A9 - A16) of the selected page. It does not affect any other memory location o utside of the page boundary. Any page of the array can be used as an independent data storage unit which is not affected by the erase and programming operations of the rest of the array. A boot block of any size can be constructed by selecting a contiguous , or non-contiguous if so desired, group of pages from the top or bottom address. This provides the most convenient boot block configuration than those utilizing the fixed - size boot block approach. Hard Wired Data Protection A hard wired data protection op tion is provided for the first 32 pages either from the top address ( IM29LV001T) or from the bottom address ( IM29LV001B). This option can be utilized to protect the BIOS boot codes which usually reside in the top or bottom 16K -byte address range. Device Operation Read The read operation of the IM29LV001T/B is activated by setting CE# and OE# to low (VIL) and WE# to high (VIH). Data is obtained from the output pins. CE# controls the device selection function. When CE# is high, the device is deselected and only standby power is consumed. When CE# is low, the device is selected. OE# controls the output buffer. It is used to gate data from the output pins. The data bus is in high i mpedance state when either CE# or OE# is high. See Fig. 1 for the read cycle timing diagram. Write The write ope ration is used to issue commands and data for the program and erase functions of the device. It is initiated by forcing CE# low, OE# high and WE# low. The addresses are latched by the falling edge of either CE# or WE#, whichever occurs last. The data is latched by the rising edge of either CE# or WE#, whichever occurs first. See Fig. 2 for the timing diagram of writing a command with WE# as the controlling signal, and Fig. 3 for that with CE# as the controlling signal. Erase: Page and Chip Erase The IM29LV001T/B provides two erase functions: page erase and chip erase. The page erase function erases a single page (512 bytes in size) at a time. It is activated by writing the page erase command to the part. The page erase command is consisted of 6 write cycles as shown in Table 2. The first 5 cycles contain the command codes, while the 6th cycle asserts the page address (A9 to A16) by forcing the correct address signals to the address pins. See Fig. 9 for the flow chart and Fig. 5 for the page erase timing diagram. The chip erase function erases the complete 1 mega-bit array simultaneously. It is activated by a 6 -byte command cycle shown in Table 2. See Fig. 6 for the timing diagram and Fig. 10 for the flow chart. The page and chip erase operations, once initiated, will trigger an internal timer to start the erase operation until completion, which takes typically 6 ms for the page and 2 sec for the chip erase. During this period, the data and address buses of the part are in high impedance states. The system buses OPERATION CE# OE# WE# A0 A1 A9 I/O Read VIL VIL VIH Ain Note 1 Ain Note 1 Ain Note 1 DOUT Standby VIH X X X X X HIGHZ Output Disable VIL VIH VIH X X X HIGHZ Write VIL VIH VIL Ain Note 1 Ain Note 1 Ain Note 1 DIN Enable Hardwired Dat a Protect VIL VH Note 1 VIL X X VH Note 1 X Disable Hardwired Data Protect VH VH Note 1 VIL X X VH Note 1 X Verify Hardwired Data Protect VIL VIL VIH VIL VIH VH Note 1 CODE Product Identification Manufacturer ID Byte 1 VIL VIL VIH VIL VIL VH Note 1 7FH Byte 2 VIL VIL VIH VIH VIH VH Note 1 1FH Device ID VIL VIL VIH VIH VIL VH Note 1 A5H/A6HNote 2 Note 1: VH=12 V, Ain = address input, X = don’t care. Note 2: A5H for IM29LV001T and A6H for IM29LV001B Table 1 Operation Modes

This advanced data sheet contains product specifications which are subject to change without notice. Rev. 0.27 Integrated Memory Technologies, Inc. 2285 Martin Ave., STE A, Santa Clara, CA 95050. Tel. (408) 986 -1088 Fax (408) 727 -8696 IMT are free for other operations. Program Byte program operation is initiated by issuing a program command which is consisted of 4 write cycles as shown in Table 2. The first 3 cycles contain the command codes and the 4 th cycle asserts the byte address and data. See Fig. 11 for the flow chart and Fig. 4 for the timing diagram. The program operation, once initiated, will continue internally until completion, typically within 20 µs. During the byte programming period, the data and address buses of the part are in high impedance state. The system buses are free for other operations. For example, during the byte programming period, the host is free to perform other tasks, such as to fetch data from other locations in the system for the next byte - program operation. Program/Erase Status Detection: Data# Polling and Toggle Bit The IM29LV001T/B provides two status bits for detecting the completion of a program or erase period. They are the Data# Polling (DQ7) and Toggle (DQ 6) bits. During the program or erase operation, the only valid read operations of the part are to read Data# Polling and Toggle Bits. Both bits are enabled and can be detected after the program or erase cycle is initiated by the first rising edge of WE# or CE# signal. See Fig. 7 and 8 for the timing diagrams and Fig. 9, 10 and 11 for the flow charts representation of the usage of Data# Polling and Toggle Bit in page erase, chip erase and byte program operations. Data# Polling (DQ7) When the IM29LV001T/B is in the program or erase period, any attempt to read DQ7 will receive the complement of the intended data of the program or erase operation. Once the program or erase cycle is completed, DQ 7 will show true data. The device is then ready for the next operation. See Fig. 7 for Data# Polling timing diagram. Toggle Bit (DQ6) During the program or erase cycle, any consecutive attempts to read DQ 6 will produce alternating 0’s and 1’s. It will start with “0” and then toggle between “0” and “1”. When the program or erase cycle is completed, the toggling action will stop. The device is then ready for the next operation. See Fig. 8 for Toggle Bit timing diagram. Data Protection The IM29LV001T/B provides both hardware and software features to protect nonvolatile data from inadvertent writes. Optional Hardwired data protection for selected sectors : The program and erase operations of the first ( IM29LV001T) or last (IM29LV001B) 32 pages can be disabled permanently to prevent false write and/or virus infection. As shown in Table 1, the hardwired protection mode can be enabled by applying V H, or 12 Volt, to A9 and OE#, and VIL to CE# and WE#. The mode can be disabled by applying the same voltages to the above pins except CE#, where V H is applied. To verify the status of the hardwired data protection mode, A9 is set to VH ( or 12 Volt), CE#, OE# and A0 to VIL, and WE# and A1 to VIH. If D0 = “1” then the hardwired data protection mode is enabled. Or vice versa, if D0 = “0”. The status of the hardwired data Command First Cycle Second Cycle Third Cycle Fourth Cycle Fifth Cycle Sixth Cycle Add Data Add Data Add Data Add Data Add Data Add Data Read xxxxH F0H Reset/ Read 5555H AAH 2AAAH 55H 5555H F0H Byte Add Byte Data Program 5555H AAH 2AAAH 55H 5555H A0H Byte Add Byte Data Page Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H Page Add 30H Chip Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H Product Identification Manufacturer ID Byte 1 5555H AAH 2AAAH 55H 5555H 90H xx00H 7FH Byte 2 5555H AAH 2AAAH 55H 5555H 90H xx11H 1FH Device ID 5555H AAH 2AAAH 55H 5555H 90H xx01H A5H/A6HNote Note: A5H for IM29LV001T and A6H for IM29LV001B Table 2 Command Definitions

This advanced data sheet contains product specifications which are subject to change without notice. Rev. 0.27 Integrated Memory Technologies, Inc. 2285 Martin Ave., STE A, Santa Clara, CA 95050. Tel. (408) 986 -1088 Fax (408) 727 -8696 IMT protection mode can also be verified by software means. See Table 3 for the command code to access the status bit of the top and bottom sector. The hardwired data protection mode can not be disabled by software means, however. Noise/Glitch Protection : A WE# or CE# noise glitch of less than 5 ns will not initiate a program or erase cycle. VCC Power Up/Down Detection: The program or erase oper ation is inhibited when V CC is less than 3.5V. Write Inhibit Mode : The program or erase operation is inhibited if any one of the following conditions is enforced: OE# low, CE# high, or WE# high. This pr events inadvertent data alterations during power-up or power-down period. Product Identification The product identification mode identifies the device as the IM29LV001T/B and the manufacturer as IMT. This mode may be accessed by hardware or sof tware operations. They are typically used by a Flash Memory programmer to identify the IMT IM29LV001T/B device and apply the correct algorithm to program the data. See Table 1 for har dware operation or Table 2 for software operation codes. The manufacturer ID for IMT is consisted of two bytes. The first byte is 7F which is located at A0=0 and A1=0. The second byte is 1F, located at A0=1 and A1=1. The device ID is A1, located at A1=0 and A0=1. See Table 4 for manufacturer and device ID designations. Termination of Product Identification Mode To return to the standard read mode, the Software Product Identification mode must be terminated. It is accomplished by issuing the Reset/Read operation, which returns the device to the read operation. See Table 2 for the Reset/Read command codes. Byte 1 Byte 2 Address Data Address Data ID Type A16-2 A1 A0 A16-2 A1 A0 Manufacturer ID X 0 0 7FH X 1 1 1FH Device ID X 0 1 A5H/A6HNote Not Applicable Note: A5H for IM29LV001T and A6H for IM29LV001B Table 4 Product Identification Table Command First Cycle Second Cycle Third Cycle Fourth Cycle Add Add Data Add Data Add Data A16 - A2 A1 A0 Data/Status Read Hardwired Protection Status Bit 5555H AAH 2AAAH 55H 5555H 90H Don’t Care 1 0 Protected: D0 = 1, D7 -1=Don’t Care Unprotected: D0 = 0, D7 -1=Don’t Care Table 3 Hardwired Protection Status Bit Read Command

This advanced data sheet contains product specifications which are subject to change without notice. Rev. 0.27 Integrated Memory Technologies, Inc. 2285 Martin Ave., STE A, Santa Clara, CA 95050. Tel. (408) 986 -1088 Fax (408) 727 -8696 IMT Absolute Maximum Ratings Storage temperature…… -65°C to +150 °C Ambient temperature with power Voltage with respect to ground All the other pins… -0.5 V to Vcc + 0.5 V Operating Ranges Ambient Temperature : Commercial ( C ) Devices…0 °C to 70 °C Industrial ( I ) Devices…… -40 °C to +85 °C Extended ( E ) Devices… -55 °C to 125 °C Vcc Supply Voltages : 3.0 V to 3.6 V DC Parameters: Limits Symbol Parameter Min Max Units Test Conditions ICC Power Supply Current CE#=OE#=VIL,WE#=VIH , all I/Os open, Read 10 mA Address input = V IL/VIH, at f=1/TRC, Min., VCC=VCC, Max Write 15 mA CE#=WE#=VIL, OE#=VIH, VCC = VCC, Max. ISB1 Standby Power Supply Current TTL input mA CE# = VIH, VCC = VCC, Max. ISB2 CMOS input 15 µA CE# = VCC -0.3V, VCC = VCC, Max. ILI Input Leakage Current 1 µA VIN =GND to VCC, VCC = VCC, Max. ILO Output Leakage Current 10 µA VOUT =GND to VCC , VCC = VCC, Max. VIL Input Low Voltage 0.8 V VCC = VCC, Max. VIH Input High Voltage 2.0 V VCC = VCC, Max. VOL Output Low Voltage 0.4 V IOL = 2.1 mA, V CC = VCC, Min. VOH Output High Voltage 2.4 V IOH = -400µA, VCC = VCC, Min. VH High voltage input for Product ID and Hardwired Data Protection modes 11.5 12.5 V CE# = OE# =V IL, WE# = V IH IH High voltage input for Product ID and Hardwired Data Protection modes 50 µA CE# = OE# = VIL, WE# = V IH, A9 = VH, Max. AC Parameters: a) Read Characteristics: Parameter Description IM29LV001- IM29LV001- IM29LV001- IM29LV001- 120 Min Max Min Max Min Max Min Max Unit tRC Read cycle time 55 70 90 120 ns tAA Address to outp ut delay 55 70 90 120 ns tCE CE# to output delay 55 70 90 120 ns tOE OE# to output delay 25 35 45 60 ns tCLZ CE# low to output active 0 0 0 0 ns tOLZ OE# low to output active 0 0 0 0 ns tCHZ CE# high to output at high -Z 20 30 40 50 ns tOHZ OE# high to output at high -Z 20 30 40 50 ns tOH Output hold from address change 0 0 0 0 ns

This advanced data sheet contains product specifications which are subject to change without notice. Rev. 0.27 Integrated Memory Technologies, Inc. 2285 Martin Ave., STE A, Santa Clara, CA 95050. Tel. (408) 986 -1088 Fax (408) 727 -8696 IMT b) Write Characteristics: Parameter Description IM29LV001-55 IM29LV001-70 IM29LV001-90 IM29LV001-120 Min Max Min Max Min Max Min Max Unit tWC Write command cycle time 55 70 90 120 ns tAS Address setup time 0 0 0 0 ns tAH Address hold time 35 45 55 60 ns tDS Data setup time 20 30 40 45 ns tDH Data hold time 0 0 0 0 ns tOES OE# setup time 0 0 0 0 ns tOEH OE# hold time 0 0 0 0 ns tCS CE# setup time 0 0 0 0 ns tCH CE# hold time 0 0 0 0 ns tCP CE# write pulse width 25 35 45 50 ns tCPH CE# write pulse width high 20 30 30 35 ns tWS WE# setup time 0 0 0 0 ns tWH WE# hold time 0 0 0 0 ns tWP WE# write pulse width 25 35 45 50 ns tWPH WE# write pulse width high 20 30 30 35 ns tWHWH1 Byte programming time 30 30 30 30 µs tWHWH2 Page erase time 9 9 9 9 ms tWHWH3 Chip erase time 3 3 3 3 s tCEP CE# access time for Data# Polling and Toggle bit read 55 70 90 120 ns tOEP OE# access time for Data# Polling and Toggle bit read 25 35 45 60 ns Test Conditions Timing measurement reference level Output loading 55ns and 70 ns parts…………………….. 1 TTL load + 30 pF 90 ns and 120 ns parts…………………… 1 TTL load + 100 pF

This advanced data sheet contains product specifications which are subject to change without notice. Rev. 0.27 Integrated Memory Technologies, Inc. 2285 Martin Ave., STE A, Santa Clara, CA 95050. Tel. (408) 986 -1088 Fax (408) 727 -8696 IMT t RCt tCE tOE CLZt tAA tOHZ DATA VALIDDATA VALIDHIGH Z DQ VIH t tOH t CHZ HIGH Z tAS tAH tOES t tWPH tDS tDH tWP OEH Fig. 1 Read Cycle Timing Diagram Fig. 2 WE Controlled Command Write Timing Diagram CS tCH ADDRESS WE OE CE DQ ADDRESS WE OE CE DATA VALID OLZ

This advanced data sheet contains product specifications which are subject to change without notice. Rev. 0.27 Integrated Memory Technologies, Inc. 2285 Martin Ave., STE A, Santa Clara, CA 95050. Tel. (408) 986 -1088 Fax (408) 727 -8696 IMT DATA VALIDHIGH Z tAS t OES t t DS tDH t CP CPH OEH Fig. 3 CE Controlled Command Write Timing Diagram ADDRESS CE OE DQ WE t WPH t WP Fig. 4 Byte Programming Mode Timing Diagram DQ ADDRESS WE OE CE THREE-BYTE COMMAND CODE FOR BYTE PROGRAMMING MODE t t t 2AAA 55555555 Add DataAA 55 A0 AH tWS tWH tWC WHWH1 Internal Programming Start DATA BYTE

This advanced data sheet contains product specifications which are subject to change without notice. Rev. 0.27 Integrated Memory Technologies, Inc. 2285 Martin Ave., STE A, Santa Clara, CA 95050. Tel. (408) 986 -1088 Fax (408) 727 -8696 IMT

80 AA 55

SIX-BYTE COMMAND CODE FOR PAGE ERASE OPERATION Fig. 5 Page Erase Timing Diagram 5555 55AA 30 Page Address ADDRESS CE OE DQ WE tWPH WP t Internal Erase Start SIX-BYTE COMMAND CODE FOR CHIP ERASE OPERATION Fig. 6 Chip Erase Timing Diagram ADDRESS CE OE DQ WE t WHWH2 t WHWH3WC t t 5555 2AAA 5555 5555 2AAA 5555 AA 55 80 AA 55 10

This advanced data sheet contains product specifications which are subject to change without notice. Rev. 0.27 Integrated Memory Technologies, Inc. 2285 Martin Ave., STE A, Santa Clara, CA 95050. Tel. (408) 986 -1088 Fax (408) 727 -8696 IMT t CEP ADDRESS WE OE DQ7 X X X CE X t OEP Fig. 7 Data Polling Timing Diagram t tOEH OES t X Fig. 8 Toggle Bit Timing Diagram t WHWH1,2,or 3 tOEH OES t WHWH1,2,or 3 ADDRESS WE OE CE t CEP t OEP DQ6

This advanced data sheet contains product specifications which are subject to change without notice. Rev. 0.27 Integrated Memory Technologies, Inc. 2285 Martin Ave., STE A, Santa Clara, CA 95050. Tel. (408) 986 -1088 Fax (408) 727 -8696 IMT Time Out For t WHWH2? Page Erase Completion Yes No Start Data# Polling: DQ7=Data? 5555H/AAH 2AAAH/55H 5555H/80H Page Address/30H Page Erase Completion Yes No Toggle Bit: DQ6 stops toggling? Page Erase Completion Yes No 5555H/AAH 2AAAH/55H Fig. 9 Page Erase Flow Chart

This advanced data sheet contains product specifications which are subject to change without notice. Rev. 0.27 Integrated Memory Technologies, Inc. 2285 Martin Ave., STE A, Santa Clara, CA 95050. Tel. (408) 986 -1088 Fax (408) 727 -8696 IMT Time Out For t WHWH3? Chip Erase Completion Yes Start Data# Polling: DQ7=Data? 5555H/AAH 2AAAH/55H 5555H/80H 5555H/10H Chip Erase Completion Yes No Toggle Bit: DQ6 stops toggling? Chip erase Completion Yes No 5555H/AAH 2AAAH/55H No Fig. 10 Chip Erase Flow Chart

This advanced data sheet contains product specifications which are subject to change without notice. Rev. 0.27 Integrated Memory Technologies, Inc. 2285 Martin Ave., STE A, Santa Clara, CA 95050. Tel. (408) 986 -1088 Fax (408) 727 -8696 IMT Time Out For t WHWH1? Byte Program Completion Yes Start Data# Polling: DQ7=Data? 5555H/AAH 2AAAH/55H 5555H/A0H Program Byte Address/Data Byte Program Completion Yes No Toggle Bit: DQ6 stops toggling? Byte Program Completion Yes NoNo Fig. 11 Byte Program Flow Chart