ILI9806E

ILI9806E ETC | Alldatasheet

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a-Si TFT LCD Single-Chip Driver 480(RGB)x864 Resolution, 16.7M-color Without internal GRAM Data Sheet Version: V097 Document No: ILI9806E_IDT_V097_20140324 ILI TECHNOLOGY CORP. 8F, No. 38, Taiyuan St, Jhubei City, Taiwan 302, R.O.C. Tel.886-3-5600099; Fax.886-3-5600585 http://www.ilitek.com

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 2 of 328 Table of Contents SECTION PAGE

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 3 of 328

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 4 of 328

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 5 of 328

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 6 of 328

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 7 of 328

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 8 of 328

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 9 of 328

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 14 of 328 Tables

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 15 of 328

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 16 of 328 Introduction The ILI9806E is a 16.7M single-chip SOC driver for a-Si TFT liquid crystal display panels with a resolution up to 480(RGB)x864. The ILI9806E is comprised of a 1441-channel source driver, an gate-IC-less level shifter, and a power supply circuit. The ILI9806E supports 3-line serial peripheral interf ace to input commands. The ILI9806E supports a RGB (16-/18-/24-bit) data bus for video image display. For hi gh-speed serial interface, the MIPI DSI interface mode, the ILI9806E supports two data lanes and one clock l ane for high-speed and low power transmission in both directions with low EMI noise. The ILI9806E operates a wide range of an analog power supplies. The ILI9806E supports sleep mode and deep standby power management functions, m a k i n g t h e I L I 9 8 0 6 E a n i d e a l L C D d r i v e r f o r m e d i u m o r s m a l l s i z e d portable products such as digital cellular phones, sm art phones, MP3 players, personal media players and similar devices with color graphics display where conser ving battery power is desired. Additionally, it has an internal DC/DC converter that generates the LCD driving voltage and the voltage follower circuit for LCD driver.

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 17 of 328 1. Features Š Display resolution options: ¾ 480(RGB) (H) X 864 (V) ¾ 480(RGB) (H) X 854 (V) ¾ 480(RGB) (H) X 800 (V) ¾ 480(RGB) (H) X 720 (V) ¾ 480(RGB) (H) X 640 (V) Š Display color modes ¾ Full color mode: 16.7M colors (24-bit data, R: 8-bit, G: 8-bit, B: 8-bit) ¾ Reduced color modes: 262K colors (18-bit data, R: 6-bit, G: 6-bit, B: 6-bit) 65K colors (16-bit data, R: 5-bit, G: 6-bit, B: 5-bit) Š Display module ¾ Supports 1441 source channel outputs ¾ Supports gate control signals to gate driver in the panel ¾ Supports 2-dot / column inversion ¾ Gamma correction (1 preset Gamma curve) ¾ On module VCOM control (DDVDL+0.3V to 0V common electrode output voltage range) Š Interface types ¾ MIPI-DSI (Display Serial Interface) interface Supports one data lane / maximum speed 850Mbps or Supports two data lanes / maximum speed 500Mbps Supports DSI version 1.02.00 Supports D-PHY version 1.00.00 Supports DCS version 1.02.00 ¾ MIPI-DPI (Display Pixel Interface) interface 16 bit/pixel (R: 5-bit, G: 6-bit, B: 5-bit) 18 bit/pixel (R: 6-bit, G: 6-bit, B: 6-bit) 24 bit/pixel (R: 8-bit, G: 8-bit, B: 8-bit) ¾ 3 line-9bit SPI (Serial Peripheral Interface) interface Š Power saving mode: ¾ Deep-standby mode ¾ Sleep mode

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 18 of 328 Š Other on-chip functions / Miscellaneous ¾ Supports inversion mode ¾ Software programmable color depth mode ¾ Supports DC VCOM driving ¾ DC VCOM voltage generator and adjustment ¾ OTP (One-Time Programming) memory store initialization register settings ¾ Provide 3 times OTP to store DC VCOM value setting, ID setting ¾ Supports CABC (Content Adaptive Brightness Control) function ¾ Separate RGB Gamma correction ¾ Supports 3-Gamma DGC (Digital Gamma Correction) function ¾ Color enhancement function ¾ Supports control the ILI4002 and ILI4003 IC ¾ VGHO/VGLO voltage generator for gate control signal in panel ¾ Supports gate control signals to gate driver in panel (GIP) Š Input power ¾ I/O supply voltage range for IOVCC to DGND = 1.65V ~ 3.6V ¾ Analog supply voltage range for VCI/VCIR/VCIP to AGND/DGND/CGND/VSSR1/VSSR2/VSSR3 = 2.5V ~ 3.6V ¾ OTP programming voltage, VPP = 5.0V Š Source/VCOM/Gate power supply voltage ¾ DDVDH-AGND=4.75 to 6.5V (Step-up 1 output voltage range) ¾ DDVDL-AGND = -6.5 to -4.75V (Step-up 2 output voltage range) ¾ VCL-AGND = -1 X VCIP (Step-up 3 output voltage range) ¾ DC VCOM = -4.0V to 0V, a step 12.5mV (Common electrode voltage range) ¾ VREG1OUT= 3.0V to 6.1875V (DDVDH-0.3V) (Positive gamma high voltage range) ¾ VREG2OUT= -3.0V to -6.1875V (DDVDL+0.3V) (Negative gamma high voltage range) ¾ VGH-AGND = 8.0V to 18.0V (Positive gate driver output voltage range) ¾ VGL-AGND = -8.0V to -18.0V (Negative gate driver output voltage range) ¾ VGL_REG-AGND = -7.0 to -15.5V (Negative gate driver output voltage range) ¾ VGH_REG-AGND = 8.5V to 16.0V (Positive gate driver output voltage range)

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 19 of 328 2. Device Overview 2.1. Block Diagram E-Fuse 3Wire SPI DPI( RGB ) 16-bit 18-bit 24-bit CSX SCL SDI / SDA VS HS PCLK RESX IOVCC Regulator VCIR VSSR[2] RC-OSC . Timing Controller Charge - Pump Power Circuit C11P/C11N DDVDH Source Driver S[ 1441:0] Level Shifters For GIP GOUT[32:1] LVGL VCORE CGND DE Brightness Control MIPI I /F HS_D0P/N HS_D1P/N HS_CP/N DGND Grayscale Reference Voltage SDO C12P/C12N VCORE_MIPI EXTP EXTN VGHO VCIP DGND V12_MIPI Index Register (IR) Control Register (CR ) Graphics Operation Read Latch Write Latch Address Counter (AC ) DA Converter Level Shift Data Latch VREG2OUT C13P/C13N C14P/C14N DDVDL C22P/C22N C23P/C23N C24P/C24N C21P/C21N VCL C32P/C32N C31P/C31N VGH C41P/C41N VGL C51P/C51N VGH_REG VGL_REG REG REG VGL VREG1OUT CABC LEDPWM LEDON VPP VCOM VREF RegVREF15 NBWSEL VCI VSSR[3] DSWAP PSWAP ERR LANSEL VSSR[1] AGND VGH VGLO TE_R / TE_L ]IM[3:0 ]DB[23:0 VGSW[3:0] GPO[3:0] TESTDIN [7:0] TESTDOUT [3:0] TESTD_EN ( . Pin Ref

Description

GOUT_VGHO GOUT_VGLO Power Circuit Figure 1 Block Diagram

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 20 of 328 2.2. Block Function Description 2.2.1. System Interface The interface operating mode (DPI or DSI) is selected by hardware pins IM [3:0], see Table 1 below. Table 1 System Operating Mode Note 1 IM3 IM2 IM1 IM0 Interface IO Pin in Use 0 0 1 1 DPI with SPI (3-line 9-bit) DB[23:0] ,VS, HS, DE, PCLK, SDI,SDO,SCL(rising edge),CSX 1 0 0 1 1 0 1 0 1 0 1 1 DB[23:0] , VS, HS, DE, PCLK, SDI,SDO,SCL(falling edge),CSX 0 1 0 1 MIPI DSI Interface HS_D0P,HS_D0N, HS_D1P, HS_D1N, HS_CP, HS_CN 0 1 1 1 MIPI DSI Interface+SPI (When set IM[3:0]=0111, the SPI I/F only supports the CABC function (command 51h~56h, 5Eh, 5Fh), and the others command are prohibited.) HS_D0P,HS_D0N, HS_D1P, HS_D1N, HS_CP, HS_CN,SDI,SDO,SCL(rising edge) ,CSX 1 1 1 1 MIPI DSI Interface+SPI (When set IM[3:0]=1111, the SPI I/F only supports the CABC function (command 51h~56h, 5Eh, 5Fh), and the others command are prohibited.) HS_D0P,HS_D0N, HS_D1P, HS_D1N, HS_CP, HS_CN, SDI,SDO,SCL(falling edge) ,CSX 2.2.2. Parallel RGB Interface The DPI (RGB) interface is used as the external interf ace for displaying moving pictures. When the DPI (RGB) interface is selected, display operations are synchroni zed with the externally supplied signals, VS, HS, and PCLK. In DPI (RGB) interface mode, data (DB[23:0]) are written in synchronization with these signals according to the polarity of the DE signal (Data Enable); this is done in order to prevent flicker on the display while updating display data. 2.2.3. Grayscale Volt age Generating Circuit The grayscale voltage generating circuit generates the LCD drive voltage which corresponds to 256 grayscale level set in the Gamma correction register. The ILI9806E can display up to 16.7M colors at the maximum. 2.2.4. Timing Generating The timing generator is used to generate timing signals for operating internal circuits. 2.2.5. Oscillator The ILI9806E incorporates an RC oscillator circuit. Command settings are used to change the frame frequency. Note 1 Set Number of Set number of colors using set pixel format: 3Ah.

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 21 of 328 2.2.6. Source Driver Circuit The LCD display driver circuit consists of a 480-output source driver (S0~S1441). The display pattern data is latched when 480RGB pixels of data are input. The voltage is output from the source driver according to the latched data. 2.2.7. Panel Control Circuit The panel control circuit outputs GOUT [32:1] signals at either VGH, VGL, VGH_REG, VGL_REG, LVGL level. 2.2.8. Power Supply Circuit The LCD drive power supply circuit generates the voltage levels for driving a panel. Voltage levels are adjusted according to register setting. 2.2.9. MIPI DSI Controller Circuit The MIPI DSI controller circuit consists of the D-PHY controller, Protocol Control Unit (PCU), Packet Processing Unit (PPU), ECC generating circui t, internal data/command buffer and analog transceiver. The D-PHY controls communication with the analog block and the ECC generati ng circuit generates the ECC to check the outgoing data stream for accuracy of the receiving data packet. The PCU cont rols outgoing and incoming data streams and the PPU controls transmitting packet distribution and merging. The internal data and command buffer is used for temporary storage of incoming command and display data. 2.2.10. CABC (Content Adap tive Brightness Control) The CABC (Content Adaptive Brightness Control) dynamic backlight control function is used to reduce the power consumption of the luminance source.

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 22 of 328 2.3. Pin Descriptions Table 2 Bus Interface Pins Bus Interface Pins Pin Name I/O Descriptions IM[3:0] I -Select the interface mode IM3 IM2 IM1 IM0 Interface 0 0 1 1 DPI with SPI 3-line (SCL rising edge) 1 0 0 1 1 0 1 0 1 0 1 1 DPI with SPI 3-line (SCL falling edge) 0 1 0 1 MIPI DSI 0 1 1 1 MIPI DSI+SPI (SCL rising edge) 1 1 1 1 MIPI DSI+SPI (SCL falling edge) RESX I - The external reset input. Initializes the chip with a low input. Be sure to execute a power-on reset after supplying power. CSX I -A chip select signal. Low: the chip is selected and accessible High: the chip is not selected and not accessible Fix to IOVCC or DGND level when not in use. SCL I - The SPI Interface (SCL): Serves as a write signal and writes data at the rising edge. - Serial interface (SCL): Serial clock input. Fix to IOVCC or DGND level when not in use. DB[23:0] I/O - A 24-bit parallel bi-directional data bus for DPI (RGB) I/F Fix to IOVCC , DGND level or Open when not in use SDI (SDA) I/O Serial data input pin used for the SPI Interface. SDI : Serial data input pin SDA : Serial data input/output bidirectional pin Fix to IOVCC or DGND level when not in use SDO O Serial data output pin used for the SPI Interface. Leave the pin to open when not in use. TE_L / TE_R O -Tearing effect output TE_L= TE_R Leave the pin to open when not in use. PCLK I - Dot clock signal for DPI (RGB) interface operation. Fix to DGND level when not in use. VS I - Frame synchronizing signal for DPI (RGB) interface operation. Fix to DGND level when not in use. HS I - Line synchronizing signal for DPI (RGB) interface operation. Fix to DGND level when not in use.

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 23 of 328 DE I - Data enable signal for DPI (RGB) interface operation. Low : access enabled. H i g h : a c c e s s i n h i b i t e d . Fix to DGND level when not in use. HS_CP HS_CN I MIPI DSI differential clock pair (DSI-CLK+/-). If MIPI are not used, they should be connected to DGND. HS_D0P HS_D0N HS_D1P HS_D1N I/O MIPI DSI differential data pair (DSI-Dn+/-). If MIPI are not used, they should be connected to DGND ERR O - CRC and ECC error output pin for MIPI interface, activated by S/W command. This pin is output low when it is not activated. When this pin is activated, it output high if CRC/ECC error found. Leave the pin to open when not in use. LANSEL I - Input pin to select 1 data lane or 2 data lanes in MIPI interface. L o w : 1 d a t a l a n e . H i g h : 2 d a t a l a n e s . - The pin have internal pull low resister. Fix to DGND level when not in use. DSWAP PSWAP I - Differential clock polarity swap For MIPI DSI interface DSWAP PSWAP Pins CLK_P CLK_N D0_P D0_N D1_P D1_N

0 CLK_P CLK_N D0_P D0_N D1_P D1_N

1 CLK_N CLK_P D0_N D0_P D1_N D1_P

0 CLK_P CLK_N D1_P D1_N D0_P D0_N

1 CLK_N CLK_P D1_N D1_P D0_N D0_P

Fix to DGND level when not in use. NBWSEL I - Input pin to select the gamma voltage level sequence of V0~V255. L o w : V 0 > V 1 > … > V 2 5 4 > V 2 5 5 , n o r m a l l y w h i t e . H i g h : V 2 5 5 > V 2 5 4 > … > V 1 > V 0 , n o r m a l l y b l a c k . Fix to DGND level when not in use. VGSW[3:0] I - Input pin to select the different application. - The pins have internal pull-low resister. Leave the pin to open when not in use. GPO[3:0] O - General purpose output pins. Leave the pin to open when not in use. LEDON O - Used for turning On/Off external LED backlight control. Leave the pin to open when not in use. LEDPWM O - The PWM frequency output for LED driver control. Leave the pin to open when not in use.

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 24 of 328 Table 3 Driver Output Pins Driver Output Pins Pin Name I/O Descriptions S[0:1441] O - Source output voltage signals applied to a LCD panel. GOUT[1:32] O - Gate control signals and the swing voltage level is VGHO to VGLO. GOUT_VGHO O - High voltage level for GIP control signals and gate circuit of panel. GOUT_VGLO O - Low voltage level for GIP control signals and gate circuit of panel. V G H O O - H i g h v o l t a g e l e v e l f o r G I P c o n t r o l s i g n a l s a n d g a t e c i r c u i t o f p a n e l . VGLO O - Low voltage level for GIP control signals and gate circuit of panel. LVGL O - Low voltage level for gate circuit of panel. V C O M O - Regulator output for common voltage of panel. DMY_VSS O - Dummy Source. Leave the pin to open when not in use.

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 25 of 328 Table 4 Charge Pump Relative Pins Charge Pump Relative Pins Pin Name I/O Descriptions DDVDH O - Output voltage from step-up circuit 1, generated from VCI. - Connect to a stabilizing capacitor between DDVDH and AGND. DDVDL O - Output voltage from step-up circuit 2, generated from VCI. - Connect to a stabilizing capacitor between DDVDL and AGND. VCL O - Output voltage from step-up circuit 3, generated from VCI. - Connect to a stabilizing capacitor between VCL and AGND. VGH O - Output voltage from step-up circuit 4, generated from VCI. - Connect to a stabilizing capacitor between VGH and AGND. VGL O - Output voltage from step-up circuit 5, generated from VCI. - Connect to a stabilizing capacitor between VGL and AGND. C11P, C11N C12P, C12N C13P, C13N C14P, C14N - - Connect the charge-pumping capacitor for generating DDVDH level. - Capacitor connection pins for the step-up circuit 1. C21P, C21N C22P, C22N C23P, C23N C24P, C24N - - Connect the charge-pumping capacitor for generating DDVDLlevel. - Capacitor connection pins for the step-up circuit 2. C31P, C31N C32P, C32N - - Connect the charge-pumping capacitor for generating VCL level. - Capacitor connection pins for the step-up circuit 3. C41P, C41N - - Connect the charge-pumping capacitor for generating VGH level. - Capacitor connection pins for the step-up circuit 4. C51P, C51N - - Connect the charge-pumping capacitor for generating VGL level. - Capacitor connection pins for the step-up circuit 5. Table 5 ILI4002 and ILI4003 Control Pins ILI4002 and ILI4003 Control Pins Pin Name I/O Descriptions E X T P (CTRL_A) O -CTRL_A : Control signal for a external charge pump IC (ex: ILI4002 or ILI4003) - The level voltage is between VCI and GND. EXTN (CTRL_B) O -CTRL_B : Control signal for a external charge pump IC (ex: ILI4002 or ILI4003) - The level voltage is between VCI and GND.

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 26 of 328 Table 6 Power Pins Power Pins Pin Name I/O Descriptions VCI P - Power supply for analog system. - VCI, VCIR and VCIP should be the same input voltage level of 2.5 ~ 3.6V. VCIR P - Power supply for regulator low voltage reference circuit. - VCI, VCIR and VCIP should be the same input voltage level of 2.5 ~ 3.6V. VCIP P - Power supply for DC/DC converter. - VCI, VCIR and VCIP should be the same input voltage level of 2.5 ~ 3.6V. IOVCC P - Power supply for I/O block. Excluded MIPI interface. VCORE O - internal logic voltage output - Connect a capacitor for stabilization. VGH_REG O - Output voltage generated from VGH. - Connect a capacitor for stabilization. Leave the pin to open when not in use. VGL_REG O - Output voltage generated from VGL. LDO output used for panel voltage. - Connect a capacitor for stabilization. Leave the pin to open when not in use. VREF15 O - Regulator output voltage for power voltage. - Connect a capacitor for stabilization. VREG1OUT O - Output voltage generated from DDVDH. LDO output for positive gamma voltage generator. VREG2OUT O - Output voltage generated from DDVDL. LDO output for negative gamma voltage generator. VCORE_MIPI O - Regulator output for internal MIPI DSI analog system (1.5V typical) - Connect a capacitor for stabilization. V12_MIPI O - Regulator output for internal MIPI DSI low power system (1.2V typical) - Connect a capacitor for stabilization. AGND P - System ground for analog circuit. CGND P - System ground for DC/DC convertor. DGND P - System ground for internal digital system. VSSR[1] VSSR[2] VSSR[3] P - System ground for regulator low voltage reference circuit. VPP I - OTP programming power.

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 27 of 328 Table 7 Test Pins Test Pins Pin Name I/O Descriptions PADA[1:4] PADB[1:4] I/O - These test pins for chip attachment detection. - PADA[1:4] are output pins and PADB[1:4] are input pins - For normal operation: Connect PADA1 and PADB1 together by ITO trace. Connect PADA2 and PADB2 together by ITO trace. Connect PADA3 and PADB3 together by ITO trace. Connect PADA4 and PADB4 together by ITO trace. CONTACT1A CONTACT2A CONTACT1B CONTACT2B I/O - Test pin, for test bonding quality, IC internal connect CONTACT1A , CONTACT1B, CONTACT2A with CONTACT2B TESTD_EN I/O - Test pin, It is not accessible to user. must be open. - This pin have internal pull low resister. TESTDIN[7:0] - - Test pin, It is not accessible to user. must be open. - This pin have internal pull low resister. TESTDOUT[3:0] - - Test pin, It is not accessible to user. must be open. DMY - - These pins are dummy (Non-function inside).

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 28 of 328 2.4. Pin assignment

1 DMY _ VS S

2 DMY _ VS S

3 DMY _ VS S

4 PADA1

5 PADB1

6 VCO M

7 VCO M

8 VCO M

9 VCO M

10 VCO M

11 CON TACT1A

12 CON TACT1B

13 VPP

14 VPP

15 VPP

16 VPP

17 VPP

18 VG L

19 VG L

20 VG L O

21 VG L O

22 VG L _REG

23 VG L _REG

24 VG H _REG

25 VG H _REG

26 VCL

27 VCL

28 VCL

29 VCL

30 VREF15

31 VREF15

32 VREF15

33 VREF15

34 AG N D

35 AG N D

36 AG N D

37 AG N D

38 VCI

39 VCI

40 VCI

41 VCI

42 VCIR

43 VCIR

44 VCIR

45 VCIR

46 VSSR[1]

47 VSSR[1]

48 VSSR[1]

49 VSSR[1]

50 TESTD IN[ 0]

51 TESTD IN[ 1]

52 TESTD IN[ 2]

53 TESTD IN[ 3]

54 DMY

55 TESTD IN[ 4]

56 TESTD IN[ 5]

57 DMY

58 DMY

59 DMY

60 VREG 2OU T

61 VREG 2OU T

62 VREG 1OU T

63 DG N D

64 DG N D

65 DG N D

66 VCO RE

67 VCO RE

68 VCO RE

69 VCI

70 VCI

71 VCI

72 VCL

73 VCL

74 VCL

75 VCL

76 VCL

77 VCL

78 AG N D

79 AG N D

80 AG N D

81 IO VCC

82 LA NSEL

83 DSW AP

84 PSW A P

85 DG N D

86 TESTD IN[ 6]

87 NB WSE L

88 VG SW [3]

89 VG SW [2]

90 VG SW [1]

91 VG SW [0]

92 IO VCC

93 TESTD IN[ 7]

94 TESTD OUT[ 0]

95 IM[3]

96 IM[2]

97 IM[1]

98 IM[0]

99 GP O[ 3 ]

100 GPO[ 2 ]

101 GPO[ 1 ]

102 GPO[ 0 ]

103 TESTDOU T[1]

104 TE_L

105 TESTDOU T[2]

106 SD O

107 SD I

108 TESTDOU T[3]

109 SCL

110 TESTD_EN

111 CSX

112 RES X

113 DG N D

114 DG N D

115 DG N D

116 IOVCC

117 IOVCC

118 IOVCC

119 DB[23 ]

120 DB[22 ]

121 DB[21 ]

122 DB[20 ]

123 DB[19 ]

124 DB[18 ]

125 DB[17 ]

126 DB[16 ]

127 DB[15 ]

128 DB[14 ]

129 DB[13 ]

130 DB[12 ]

131 DB[11 ]

132 DB[10 ]

133 DB[9]

134 DB[8]

135 DB[7]

136 DB[6]

137 DB[5]

138 DB[4]

139 DB[3]

140 DB[2]

141 DB[1]

142 DB[0]

144 PCL K

147 LED PW M

148 LED ON

149 DMY

150 ERR

151 IOVCC

152 IOVCC

153 IOVCC

154 DG N D

155 DG N D

156 DG N D

157 DDVDH

158 DDVDH

159 DDVDH

160 DDVDH

161 AG N D

162 AG N D

163 AG N D

164 AG N D

165 DDVDL

166 DDVDL

167 DDVDL

168 DDVDL

169 DDVDL

170 VCI

171 VCI

172 VCI

173 VCI

174 DG N D

175 DG N D

176 DG N D

177 DG N D

178 VCO RE

179 VCO RE

180 VCO RE

181 VCO RE

182 DG N D

183 DG N D

184 DG N D

185 DG N D

186 DG N D

187 HS_ D 1 P

188 HS_ D 1 P

189 HS_ D 1 P

190 HS_ D 1 P

191 HS_ D 1 N

192 HS_ D 1 N

193 HS_ D 1 N

194 HS_ D 1 N

195 DG N D

196 DG N D

197 HS_ CP

198 HS_ CP

199 HS_ CP

200 HS_ CP

201 HS_ CN

202 HS_ CN

203 HS_ CN

204 HS_ CN

205 DG N D

206 DG N D

207 HS_ D 0 P

208 HS_ D 0 P

209 HS_ D 0 P

210 HS_ D 0 P

211 HS_ D 0 N

1181 S[ 714]1182 S[715 ] 1183 S[ 716]1184 S[717] 1185 S[ 718]1186 S[719] 1187 S[ 720]1188 DMY _ VS S 1189 DMY _VSS1190 DMY 1191 DMY1192 DMY 1193 DMY1194 DMY 1195 DMY1196 DMY 1197 DMY1198 DMY 1199 DMY1200 DMY 1201 DMY1202 DMY 1203 DMY1204 DMY 1205 DMY1206 DMY 1207 DMY1208 DMY 1209 DMY1210 DMY 1211 DMY1212 DMY 1213 DMY1214 DMY 1215 DMY1216 DMY 1217 DMY1218 DMY 1219 DMY1220 DMY 1221 DMY1222 DMY 1223 DMY1224 DMY 1225 DMY1226 DMY 1227 DMY1228 DMY 1229 DMY1230 DMY 1231 DMY1232 DMY 1233 DMY1234 DMY 1235 DMY _VSS1236 DMY _ VS S 1237 S[ 721]1238 S[722] 1239 S[ 723]1240 S[724] 1241 S[ 725]1242 S[726] 1243 S[ 727]1244 S[728] 1245 S[ 729]1246 S[730] 1247 S[ 731]1248 S[732] 1249 S[ 733]1250 S[734] 1251 S[ 735]1252 S[736] 1253 S[ 737]1254 S[738] 1255 S[ 739]1256 S[740] 1257 S[ 741]1258 S[742] 1259 S[ 743]1260 S[744] 1261 S[ 745]1262 S[746] 1263 S[ 747]1264 S[748] 1265 S[ 749]1266 S[750] 1267 S[ 751]1268 S[752] 1269 S[ 753]1270 S[754] 1271 S[ 755]1272 S[756] 1273 S[ 757]1274 S[758] 1275 S[ 759]1276 S[760] 1277 S[ 761]1278 S[762] 1279 S[ 763]1280 S[764] 1281 S[ 765]1282 S[766] 1283 S[ 767]1284 S[768] 1285 S[ 769]1286 S[770] 1287 S[ 771]1288 S[772] 1289 S[ 773]1290 S[774] 1291 S[ 775]1292 S[776] 1293 S[ 777]1294 S[778] 1295 S[ 779]1296 S[780] 1297 S[ 781]1298 S[782] 1299 S[ 783]1300 S[784] 1301 S[ 785]1302 S[786] 1303 S[ 787]1304 S[788] 1305 S[ 789]1306 S[790] 1307 S[ 791]1308 S[792] 1309 S[ 793]1310 S[794] 1311 S[ 795]1312 S[796] 1313 S[ 797]1314 S[798] 1315 S[ 799]1316 S[800] 1317 S[ 801]1318 S[802] 1319 S[ 803]1320 S[804] 1321 S[ 805]1322 S[806] 1323 S[ 807]1324 S[808] 1325 S[ 809]1326 S[810] 1327 S[ 811]1328 S[812] 1329 S[ 813]1330 S[814] 1331 S[ 815]1332 S[816] 1333 S[ 817]1334 S[818] 1335 S[ 819]1336 S[820] 1337 S[ 821]1338 S[822] 1339 S[ 823]1340 S[824] 1341 S[ 825]1342 S[826] 1343 S[ 827]1344 S[828] 1345 S[ 829]1346 S[830] 1347 S[ 831]1348 S[832] 1349 S[ 833]1350 S[834] 1351 S[ 835]1352 S[836] 1353 S[ 837]1354 S[838] 1355 S[ 839]1356 S[840] 1357 S[ 841]1358 S[842] 1359 S[ 843]1360 S[844] 1361 S[ 845]1362 S[846] 1363 S[ 847]1364 S[848] 1365 S[ 849]1366 S[850] 1367 S[ 851]1368 S[852] 1369 S[ 853]1370 S[854] 1371 S[ 855]1372 S[856] 1373 S[ 857]1374 S[858] 1375 S[ 859]1376 S[860] 1377 S[ 861]1378 S[862] 1379 S[ 863]1380 S[864] 1381 S[ 865]1382 S[866] 1383 S[ 867]1384 S[868] 1385 S[ 869]1386 S[870] 1387 S[ 871]1388 S[872] 1389 S[ 873]1390 S[874] 1391 S[ 875]1392 S[876] 1393 S[ 877]1394 S[878] 1395 S[ 879]1396 S[880] 1397 S[ 881]1398 S[882] 1399 S[ 883]1400 S[884] 1401 S[ 885]1402 S[886] 1403 S[ 887]1404 S[888] 1405 S[ 889]1406 S[890] 1407 S[ 891]1408 S[892] 1409 S[ 893]1410 S[894] 1411 S[ 895]1412 S[896] 1413 S[ 897]1414 S[898] 1415 S[ 899]1416 S[900] 1417 S[ 901]1418 S[902] 1419 S[ 903]1420 S[904] 1421 S[ 905]1422 S[906] 1423 S[ 907]1424 S[908] 1425 S[ 909]1426 S[910] 1427 S[ 911]1428 S[912] 1429 S[ 913]1430 S[914] 1431 S[ 915]1432 S[916] 1433 S[ 917]1434 S[918] 1435 S[ 919]1436 S[920] 1437 S[ 921]1438 S[922] 1439 S[ 923]1440 S[924] 1441 S[ 925]1442 S[926] 1443 S[ 927]1444 S[928] 1445 S[ 929]1446 S[930] 1447 S[ 931]1448 S[932] 1449 S[ 933]1450 S[934] 1451 S[ 935]1452 S[936] 1453 S[ 937]1454 S[938] 1455 S[ 939]1456 S[940] 1457 S[ 941]1458 S[942] 1459 S[ 943]1460 S[944] 1461 S[ 945]1462 S[946] 1463 S[ 947]1464 S[948] 1465 S[ 949]1466 S[950] 1467 S[ 951]1468 S[952] 1469 S[ 953]1470 S[954] 1471 S[ 955]1472 S[956] 1473 S[ 957]1474 S[958] 1475 S[ 959]1476 S[960] 1477 S[ 961]1478 S[962] 1479 S[ 963]1480 S[964] 1481 S[ 965]1482 S[966] 1483 S[ 967]1484 S[968] 1485 S[ 969]1486 S[970] 1487 S[ 971]1488 S[972] 1489 S[ 973]1490 S[974] 1491 S[ 975]1492 S[976] 1493 S[ 977]1494 S[978] 1495 S[ 979]1496 S[980] 1497 S[ 981]1498 S[982] 1499 S[ 983]1500 S[984] 1501 S[ 985]1502 S[986] 1503 S[ 987]1504 S[988] 1505 S[ 989]1506 S[990] 1507 S[ 991]1508 S[992] 1509 S[ 993]1510 S[994] 1511 S[ 995]1512 S[996] 1513 S[ 997]1514 S[998] 1515 S[ 999]1516 S[1000] 1517 S[ 1001]1518 S[1002] 1519 S[ 1003]1520 S[1004] 1521 S[ 1005]1522 S[1006] 1523 S[ 1007]1524 S[1008] 1525 S[ 1009]1526 S[1010] 1527 S[ 1011]1528 S[1012] 1529 S[ 1013]1530 S[1014] 1531 S[ 1015]1532 S[1016] 1533 S[ 1017]1534 S[1018] 1535 S[ 1019]1536 S[1020] 1537 S[ 1021]1538 S[1022] 1539 S[ 1023]1540 S[1024] 1541 S[ 1025]1542 S[1026] 1543 S[ 1027]1544 S[1028] 1545 S[ 1029]1546 S[1030] 1547 S[ 1031]1548 S[1032] 1549 S[ 1033]1550 S[1034] 1551 S[ 1035]1552 S[1036] 1553 S[ 1037]1554 S[1038] 1555 S[ 1039]1556 S[1040] 1557 S[ 1041]1558 S[1042] 1559 S[ 1043]1560 S[1044] 1561 S[ 1045]1562 S[1046] 1563 S[ 1047]1564 S[1048] 1565 S[ 1049]1566 S[1050] 1567 S[ 1051]1568 S[1052] 1569 S[ 1053]1570 S[1054] 1571 S[ 1055]1572 S[1056] 1573 S[ 1057]1574 S[1058] 1575 S[ 1059]1576 S[1060] 1577 S[ 1061]1578 S[1062] 1579 S[ 1063]1580 S[1064] 1581 S[ 1065]1582 S[1066] 1583 S[ 1067]1584 S[1068] 1585 S[ 1069]1586 S[1070] 1587 S[ 1071]1588 S[1072] 1589 S[ 1073]1590 S[1074] 1591 S[ 1075]1592 S[1076] 1593 S[ 1077]1594 S[1078] 1595 S[ 1079]1596 S[1080] 1597 S[ 1081]1598 S[1082] 1599 S[ 1083]1600 S[1084] 1601 S[ 1085]1602 S[1086] 1603 S[ 1087]1604 S[1088] 1605 S[ 1089]1606 S[1090] 1607 S[ 1091]1608 S[1092] 1609 S[ 1093]1610 S[1094] 1611 S[ 1095]1612 S[1096] 1613 S[ 1097]1614 S[1098] 1615 S[ 1099]1616 S[1100] 1617 S[ 1101]1618 S[1102] 1619 S[ 1103]1620 S[1104] 1621 S[ 1105]1622 S[1106] 1623 S[ 1107]1624 S[1108] 1625 S[ 1109]1626 S[1110] 1627 S[ 1111]1628 S[1112] 1629 S[ 1113]1630 S[1114] 1631 S[ 1115]1632 S[1116] 1633 S[ 1117]1634 S[1118] 1635 S[ 1119]1636 S[1120] 1637 S[ 1121]1638 S[1122] 1639 S[ 1123]1640 S[1124] 1641 S[ 1125]1642 S[1126] 1643 S[ 1127]1644 S[1128] 1645 S[ 1129]1646 S[1130] 1647 S[ 1131]1648 S[1132] 1649 S[ 1133]1650 S[1134] 1651 S[ 1135]1652 S[1136] 1653 S[ 1137]1654 S[1138] 1655 S[ 1139]1656 S[1140] 1657 S[ 1141]1658 S[1142] 1659 S[ 1143]1660 S[1144] 1661 S[ 1145]1662 S[1146] 1663 S[ 1147]1664 S[1148] 1665 S[ 1149]1666 S[1150] 1667 S[ 1151]1668 S[1152] 1669 S[ 1153]1670 S[1154] 1671 S[ 1155]1672 S[1156] 1673 S[ 1157]1674 S[1158] 1675 S[ 1159]1676 S[1160] 1677 S[ 1161]1678 S[1162] 1679 S[ 1163]1680 S[1164] 1681 S[ 1165]1682 S[1166] 1683 S[ 1167]1684 S[1168] 1685 S[ 1169]1686 S[1170] 1687 S[ 1171]1688 S[1172] 1689 S[ 1173]1690 S[1174] 1691 S[ 1175]1692 S[1176] 1693 S[ 1177]1694 S[1178] 1695 S[ 1179]1696 S[1180] 1697 S[ 1181]1698 S[1182] 1699 S[ 1183]1700 S[1184] 1701 S[ 1185]1702 S[1186] 1703 S[ 1187]1704 S[1188] 1705 S[ 1189]1706 S[1190] 1707 S[ 1191]1708 S[1192] 1709 S[ 1193]1710 S[1194] 1711 S[ 1195]1712 S[1196] 1713 S[ 1197]1714 S[1198] 1715 S[ 1199]1716 S[1200] 1717 S[ 1201]1718 S[1202] 1719 S[ 1203]1720 S[1204] 1721 S[ 1205]1722 S[1206] 1723 S[ 1207]1724 S[1208] 1725 S[ 1209]1726 S[1210] 1727 S[ 1211]1728 S[1212] 1729 S[ 1213]1730 S[1214] 1731 S[ 1215]1732 S[1216] 1733 S[ 1217]1734 S[1218] 1735 S[ 1219]1736 S[1220] 1737 S[ 1221]1738 S[1222] 1739 S[ 1223]1740 S[1224] 1741 S[ 1225]1742 S[1226] 1743 S[ 1227]1744 S[1228] 1745 S[ 1229]1746 S[1230] 1747 S[ 1231]1748 S[1232] 1749 S[ 1233]1750 S[1234] 1751 S[ 1235]1752 S[1236] 1753 S[ 1237]1754 S[1238] 1755 S[ 1239]1756 S[1240] 1757 S[ 1241]1758 S[1242] 1759 S[ 1243]1760 S[1244] 1761 S[ 1245]1762 S[1246] 1763 S[ 1247]1764 S[1248] 1765 S[ 1249]1766 S[1250] 1767 S[ 1251]1768 S[1252] 1769 S[ 1253]1770 S[1254] 1771 S[ 1255]1772 S[1256] 1773 S[ 1257]1774 S[1258] 1775 S[ 1259]1776 S[1260] 1777 S[ 1261]1778 S[1262] 1779 S[ 1263]1780 S[1264] 1781 S[ 1265]1782 S[1266] 1783 S[ 1267]1784 S[1268] 1785 S[ 1269]1786 S[1270] 1787 S[ 1271]1788 S[1272] 1789 S[ 1273]1790 S[1274] 1791 S[ 1275]1792 S[1276] 1793 S[ 1277]1794 S[1278] 1795 S[ 1279]1796 S[1280] 1797 S[ 1281]1798 S[1282] 1799 S[ 1283]1800 S[1284] 1801 S[ 1285]1802 S[1286] 1803 S[ 1287]1804 S[1288] 1805 S[ 1289]1806 S[1290] 1807 S[ 1291]1808 S[1292] 1809 S[ 1293]1810 S[1294] 1811 S[ 1295]1812 S[1296] 1813 S[ 1297]1814 S[1298] 1815 S[ 1299]1816 S[1300] 1817 S[ 1301]1818 S[1302] 1819 S[ 1303]1820 S[1304] 1821 S[ 1305]1822 S[1306] 1823 S[ 1307]1824 S[1308] 1825 S[ 1309]1826 S[1310] 1827 S[ 1311]1828 S[1312] 1829 S[ 1313]1830 S[1314] 1831 S[ 1315]1832 S[1316] 1833 S[ 1317]1834 S[1318] 1835 S[ 1319]1836 S[1320] 1837 S[ 1321]1838 S[1322] 1839 S[ 1323]1840 S[1324] 1841 S[ 1325]1842 S[1326] 1843 S[ 1327]1844 S[1328] 1845 S[ 1329]1846 S[1330] 1847 S[ 1331]1848 S[1332] 1849 S[ 1333]1850 S[1334] 1851 S[ 1335]1852 S[1336] 1853 S[ 1337]1854 S[1338] 1855 S[ 1339]1856 S[1340] 1857 S[ 1341]1858 S[1342] 1859 S[ 1343]1860 S[1344] 1861 S[ 1345]1862 S[1346] 1863 S[ 1347]1864 S[1348] 1865 S[ 1349]1866 S[1350] 1867 S[ 1351]1868 S[1352] 1869 S[ 1353]1870 S[1354] 1871 S[ 1355]1872 S[1356] 1873 S[ 1357]1874 S[1358] 1875 S[ 1359]1876 S[1360] 1877 S[ 1361]1878 S[1362] 1879 S[ 1363]1880 S[1364] 1881 S[ 1365]1882 S[1366] 1883 S[ 1367]1884 S[1368] 1885 S[ 1369]1886 S[1370] 1887 S[ 1371]1888 S[1372] 1889 S[ 1373]1890 S[1374] 1891 S[ 1375]1892 S[1376] 1893 S[ 1377]1894 S[1378] 1895 S[ 1379]1896 S[1380] 1897 S[ 1381]1898 S[1382] 1899 S[ 1383]1900 S[1384] 1901 S[ 1385]1902 S[1386] 1903 S[ 1387]1904 S[1388] 1905 S[ 1389]1906 S[1390] 1907 S[ 1391]1908 S[1392] 1909 S[ 1393]1910 S[1394] 1911 S[ 1395]1912 S[1396] 1913 S[ 1397]1914 S[1398] 1915 S[ 1399]1916 S[1400] 1917 S[ 1401]1918 S[1402] 1919 S[ 1403]1920 S[1404] 1921 S[ 1405]1922 S[1406] 1923 S[ 1407]1924 S[1408] 1925 S[ 1409]1926 S[1410] 1927 S[ 1411]1928 S[1412] 1929 S[ 1413]1930 S[1414] 1931 S[ 1415]1932 S[1416] 1933 S[ 1417]1934 S[1418] 1935 S[ 1419]1936 S[1420] 1937 S[ 1421]1938 S[1422] 1939 S[ 1423]1940 S[1424] 1941 S[ 1425]1942 S[1426] 1943 S[ 1427]1944 S[1428] 1945 S[ 1429]1946 S[1430] 1947 S[ 1431]1948 S[1432] 1949 S[ 1433]1950 S[1434] 1951 S[ 1435]1952 S[1436] 1953 S[ 1437]1954 S[1438] 1955 S[ 1439]1956 S[1440] 1957 S[ 1441]1958 DMY _ VS S 1959 DMY _VSS 1960 GOUT _ V GLO 1961 GOUT_ V GLO1962 GOUT _ V GLO 1963 GOUT_ V GLO1964 GOUT _ V GLO 1965 GOUT_ V GLO1966 DMY _ VG H 1967 DMY _VG H1968 GOUT _ V GHO 1969 GOUT_ V GHO1970 GOUT _ V GHO 1971 GOUT_ V GHO1972 GOUT _ V GHO 1973 GOUT_ V GHO1974 DMY _ VS S 1975 DMY _VSS1976 DMY 1977 DMY1978 DMY 1979 DMY1980 DMY 1981 DMY1982 DMY 1983 DMY1984 DMY 1985 DMY1986 DMY 1987 DMY1988 DMY 1989 DMY1990 DMY 1991 DMY1992 DMY 1993 DMY1994 DMY 1995 DMY1996 DMY 1997 DMY1998 DMY 1999 DMY2000 DMY 2001 DMY2002 DMY 2003 DMY2004 DMY 2005 DMY2006 DMY 2007 DMY2008 DMY 2009 DMY2010 DMY 2011 DMY2012 DMY 2013 DMY2014 DMY 2015 DMY2016 DMY _ VS S 2017 DMY _VSS2018 GOUT [ 1 7 ] 2019 GOUT[ 1 7 ]2020 GOUT [ 1 8 ] 2021 GOUT[ 1 8 ]2022 GOUT [ 1 9 ] 2023 GOUT[ 1 9 ]2024 GOUT [ 2 0 ] 2025 GOUT[ 2 0 ]2026 GOUT [ 2 1 ] 2027 GOUT[ 2 1 ]2028 GOUT [ 2 2 ] 2029 GOUT[ 2 2 ]2030 GOUT [ 2 3 ] 2031 GOUT[ 2 3 ]2032 GOUT [ 2 4 ] 2033 GOUT[ 2 4 ]2034 GOUT [ 2 5 ] 2035 GOUT[ 2 5 ]2036 GOUT [ 2 6 ] 2037 GOUT[ 2 6 ]2038 GOUT [ 2 7 ] 2039 GOUT[ 2 7 ]2040 GOUT [ 2 8 ] 2041 GOUT[ 2 8 ]2042 GOUT [ 2 9 ] 2043 GOUT[ 2 9 ]2044 GOUT [ 3 0 ] 2045 GOUT[ 3 0 ]2046 GOUT _ V GLO 2047 GOUT_ V GLO2048 GOUT _ V GLO 2049 VG H _REG2050 VG H _RE G 2051 VG H _REG2052 LVGL 2053 LV GL2054 LVGL 2055 GOUT[ 3 1 ]2056 GOUT [ 3 1 ] 2057 GOUT[ 3 2 ]2058 GOUT [ 3 2 ] 2059 GOUT_ V GLO2060 GOUT _ V GLO 2061 GOUT_ V GLO2062 GOUT _ V GHO 2063 GOUT_ V GHO2064 GOUT _ V GHO 2065 PA D A42066 PADB4 2067 DMY _VSS2068 DMY _ VS S

2069 DMY _VSS

-320 -220 -120 -20 180 280 380 -12000 -11000 -10000 -9000 -8000 -7000 -6000 -5000 -4000 -3000 -2000 -10000

187 HS _ D 1 P

188 HS _ D 1 P

189 HS _ D 1 P

190 HS _ D 1 P

191 HS _ D 1 N

192 HS _ D 1 N

193 HS _ D 1 N

194 HS _ D 1 N

197 HS _ C P

198 HS _ C P

199 HS _ C P

200 HS _ C P

201 HS _ C N

202 HS _ C N

203 HS _ C N

204 HS _ C N

207 HS _ D 0 P

208 HS _ D 0 P

209 HS _ D 0 P

210 HS _ D 0 P

211 HS _ D 0 N

212 HS _ D 0 N

213 HS _ D 0 N

214 HS _ D 0 N

215 DG N D

216 DG N D

217 V1 2_ MIPI

218 V1 2_ MIPI

219 V1 2_ MIPI

220 VCO RE_ MIPI

221 VCO RE_ MIPI

222 VCO RE_ MIPI

223 VCI

224 VCI

225 VCI

226 VCI

227 VCI

228 VCI

229 VCI

230 VCI

231 DMY

232 TE_R

233 VS SR[2]

234 VS SR[2]

235 VS SR[2]

236 VS SR[2]

237 DMY

238 DMY

239 VG H _RE G

240 VG H _RE G

241 EXTP

242 EXTP

243 DMY

244 DMY

245 EXTN

246 EXTN

247 DMY

248 DMY

249 VCIP

250 VCIP

251 VCIP

252 VCIP

253 VCIP

254 VCIP

255 CG N D

256 CG N D

257 CG N D

258 CG N D

259 CG N D

260 CG N D

261 C11P

262 C11P

263 C11P

264 C11N

265 C11N

266 C11N

267 C12P

268 C12P

269 C12P

270 C12N

271 C12N

272 C12N

273 C13P

274 C13P

275 C13P

276 C13N

277 C13N

278 C13N

279 C14P

280 C14P

281 C14P

282 C14N

283 C14N

284 C14N

285 DDVDH

286 DDVDH

287 DDVDH

288 DDVDH

289 CG N D

290 CG N D

291 CG N D

292 CG N D

293 CG N D

294 DDVDL

295 DDVDL

296 DDVDL

297 DDVDL

298 DDVDL

299 DDVDL

300 C21P

301 C21P

302 C21P

303 C21N

304 C21N

305 C21N

306 C22P

307 C22P

308 C22P

309 C22N

310 C22N

311 C22N

312 C23P

313 C23P

314 C23P

315 C23N

316 C23N

317 C23N

318 C24P

319 C24P

320 C24P

321 C24N

322 C24N

323 C24N

324 VCIP

325 VCIP

326 VCIP

327 VCIP

328 VCIP

329 VCL

330 VCL

331 VCL

332 VCL

333 VCL

334 VCL

335 VCL

336 VS SR[3]

337 VS SR[3]

338 VS SR[3]

339 CG N D

340 CG N D

341 CG N D

342 CG N D

343 C31P

344 C31P

345 C31P

346 C31N

347 C31N

348 C31N

349 C32P

350 C32P

351 C32P

352 C32N

353 C32N

354 C32N

355 VCO RE

356 VCO RE

357 VCO RE

358 AG N D

359 AG N D

360 AG N D

361 C41P

362 C41P

363 C41N

364 C41N

365 VG H

366 VG H

367 VG H O

368 VG H O

369 VG H _RE G

370 VG H _RE G

371 C51P

372 C51P

373 C51N

374 C51N

375 VG L _ RE G

376 VG L _ RE G

377 VG L O

378 VG L O

379 VG L

380 VG L

381 VG L

382 VG L

383 DMY

384 DMY

385 DMY

386 DMY

387 CO N TACT2A

388 CO N TACT2B

389 VCO M

390 VCO M

391 VCO M

392 VCO M

393 VCO M

394 PADA2

395 PADB2

396 DMY _ VS S

397 DMY _ VS S

398 DMY _ VS S

399 DMY _VS S

400 DMY _ VS S 401 DMY _VS S402 PADA3 403 PA D B3404 GOUT_V GHO 405 GOUT _ V GHO406 GOUT_V GHO 407 GOUT _ V GLO408 GOUT_V GLO 409 GOUT _ V GLO410 GOUT[ 1] 411 GOUT [ 1 ]412 GOUT[ 2] 413 GOUT [ 2 ]414 LVGL 415 LV GL416 LVGL 417 VG H _REG418 VG H _ RE G 419 VG H _REG420 GOUT_V GLO 421 GOUT _ V GLO422 GOUT_V GLO 423 GOUT [ 3 ]424 GOUT[ 3] 425 GOUT [ 4 ]426 GOUT[ 4] 427 GOUT [ 5 ]428 GOUT[ 5] 429 GOUT [ 6 ]430 GOUT[ 6] 431 GOUT [ 7 ]432 GOUT[ 7] 433 GOUT [ 8 ]434 GOUT[ 8] 435 GOUT [ 9 ]436 GOUT[ 9] 437 GOUT [ 1 0 ]438 GOUT[ 10 ] 439 GOUT [ 1 1 ]440 GOUT[ 11 ] 441 GOUT [ 1 2 ]442 GOUT[ 12 ] 443 GOUT [ 1 3 ]444 GOUT[ 13 ] 445 GOUT [ 1 4 ]446 GOUT[ 14 ] 447 GOUT [ 1 5 ]448 GOUT[ 15 ] 449 GOUT [ 1 6 ]450 GOUT[ 16 ] 451 GOUT _ V GHO452 GOUT_V GHO 453 GOUT _ V GHO454 GOUT_V GHO 455 GOUT _ V GHO456 GOUT_V GHO 457 DMY _VG H458 DMY _ VG H 459 GOUT _ V GLO460 GOUT_V GLO 461 GOUT _ V GLO462 GOUT_V GLO 463 GOUT _ V GLO464 GOUT_V GLO 465 DMY _VS S466 DMY _ VS S 467 S[ 0]468 S[1] 469 S[ 2]470 S[3] 471 S[ 4]472 S[5] 473 S[ 6]474 S[7] 475 S[ 8]476 S[9] 477 S[ 10]478 S[11] 479 S[ 12]480 S[13] 481 S[ 14]482 S[15] 483 S[ 16]484 S[17] 485 S[ 18]486 S[19] 487 S[ 20]488 S[21] 489 S[ 22]490 S[23] 491 S[ 24]492 S[25] 493 S[ 26]494 S[27] 495 S[ 28]496 S[29] 497 S[ 30]498 S[31] 499 S[ 32]500 S[33] 501 S[ 34]502 S[35] 503 S[ 36]504 S[37] 505 S[ 38]506 S[39] 507 S[ 40]508 S[41] 509 S[ 42]510 S[43] 511 S[ 44]512 S[45] 513 S[ 46]514 S[47] 515 S[ 48]516 S[49] 517 S[ 50]518 S[51] 519 S[ 52]520 S[53] 521 S[ 54]522 S[55] 523 S[ 56]524 S[57] 525 S[ 58]526 S[59] 527 S[ 60]528 S[61] 529 S[ 62]530 S[63] 531 S[ 64]532 S[65] 533 S[ 66]534 S[67] 535 S[ 68]536 S[69] 537 S[ 70]538 S[71] 539 S[ 72]540 S[73] 541 S[ 74]542 S[75] 543 S[ 76]544 S[77] 545 S[ 78]546 S[79] 547 S[ 80]548 S[81] 549 S[ 82]550 S[83] 551 S[ 84]552 S[85] 553 S[ 86]554 S[87] 555 S[ 88]556 S[89] 557 S[ 90]558 S[91] 559 S[ 92]560 S[93] 561 S[ 94]562 S[95] 563 S[ 96]564 S[97] 565 S[ 98]566 S[99] 567 S[ 100]568 S[101] 569 S[ 102]570 S[103] 571 S[ 104]572 S[105] 573 S[ 106]574 S[107] 575 S[ 108]576 S[109] 577 S[ 110]578 S[111] 579 S[ 112]580 S[113] 581 S[ 114]582 S[115] 583 S[ 116]584 S[117] 585 S[ 118]586 S[119] 587 S[ 120]588 S[121] 589 S[ 122]590 S[123] 591 S[ 124]592 S[125] 593 S[ 126]594 S[127] 595 S[ 128]596 S[129] 597 S[ 130]598 S[131] 599 S[ 132]600 S[133] 601 S[ 134]602 S[135] 603 S[ 136]604 S[137] 605 S[ 138]606 S[139] 607 S[ 140]608 S[141] 609 S[ 142]610 S[143] 611 S[ 144]612 S[145] 613 S[ 146]614 S[147] 615 S[ 148]616 S[149] 617 S[ 150]618 S[151] 619 S[ 152]620 S[153] 621 S[ 154]622 S[155] 623 S[ 156]624 S[157] 625 S[ 158]626 S[159] 627 S[ 160]628 S[161] 629 S[ 162]630 S[163] 631 S[ 164]632 S[165] 633 S[ 166]634 S[167] 635 S[ 168]636 S[169] 637 S[ 170]638 S[171] 639 S[ 172]640 S[173] 641 S[ 174]642 S[175] 643 S[ 176]644 S[177] 645 S[ 178]646 S[179] 647 S[ 180]648 S[181] 649 S[ 182]650 S[183] 651 S[ 184]652 S[185] 653 S[ 186]654 S[187] 655 S[ 188]656 S[189] 657 S[ 190]658 S[191] 659 S[ 192]660 S[193] 661 S[ 194]662 S[195] 663 S[ 196]664 S[197] 665 S[ 198]666 S[199] 667 S[ 200]668 S[201] 669 S[ 202]670 S[203] 671 S[ 204]672 S[205] 673 S[ 206]674 S[207] 675 S[ 208]676 S[209] 677 S[ 210]678 S[211] 679 S[ 212]680 S[213] 681 S[ 214]682 S[215] 683 S[ 216]684 S[217] 685 S[ 218]686 S[219] 687 S[ 220]688 S[221] 689 S[ 222]690 S[223] 691 S[ 224]692 S[225] 693 S[ 226]694 S[227] 695 S[ 228]696 S[229] 697 S[ 230]698 S[231] 699 S[ 232]700 S[233] 701 S[ 234]702 S[235] 703 S[ 236]704 S[237] 705 S[ 238]706 S[239] 707 S[ 240]708 S[241] 709 S[ 242]710 S[243] 711 S[ 244]712 S[245] 713 S[ 246]714 S[247] 715 S[ 248]716 S[249] 717 S[ 250]718 S[251] 719 S[ 252]720 S[253] 721 S[ 254]722 S[255] 723 S[ 256]724 S[257] 725 S[ 258]726 S[259] 727 S[ 260]728 S[261] 729 S[ 262]730 S[263] 731 S[ 264]732 S[265] 733 S[ 266]734 S[267] 735 S[ 268]736 S[269] 737 S[ 270]738 S[271] 739 S[ 272]740 S[273] 741 S[ 274]742 S[275] 743 S[ 276]744 S[277] 745 S[ 278]746 S[279] 747 S[ 280]748 S[281] 749 S[ 282]750 S[283] 751 S[ 284]752 S[285] 753 S[ 286]754 S[287] 755 S[ 288]756 S[289] 757 S[ 290]758 S[291] 759 S[ 292]760 S[293] 761 S[ 294]762 S[295] 763 S[ 296]764 S[297] 765 S[ 298]766 S[299] 767 S[ 300]768 S[301] 769 S[ 302]770 S[303] 771 S[ 304]772 S[305] 773 S[ 306]774 S[307] 775 S[ 308]776 S[309] 777 S[ 310]778 S[311] 779 S[ 312]780 S[313] 781 S[ 314]782 S[315] 783 S[ 316]784 S[317] 785 S[ 318]786 S[319] 787 S[ 320]788 S[321] 789 S[ 322]790 S[323] 791 S[ 324]792 S[325] 793 S[ 326]794 S[327] 795 S[ 328]796 S[329] 797 S[ 330]798 S[331] 799 S[ 332]800 S[333] 801 S[ 334]802 S[335] 803 S[ 336]804 S[337] 805 S[ 338]806 S[339] 807 S[ 340]808 S[341] 809 S[ 342]810 S[343] 811 S[ 344]812 S[345] 813 S[ 346]814 S[347] 815 S[ 348]816 S[349] 817 S[ 350]818 S[351] 819 S[ 352]820 S[353] 821 S[ 354]822 S[355] 823 S[ 356]824 S[357] 825 S[ 358]826 S[359] 827 S[ 360]828 S[361] 829 S[ 362]830 S[363] 831 S[ 364]832 S[365] 833 S[ 366]834 S[367] 835 S[ 368]836 S[369] 837 S[ 370]838 S[371] 839 S[ 372]840 S[373] 841 S[ 374]842 S[375] 843 S[ 376]844 S[377] 845 S[ 378]846 S[379] 847 S[ 380]848 S[381] 849 S[ 382]850 S[383] 851 S[ 384]852 S[385] 853 S[ 386]854 S[387] 855 S[ 388]856 S[389] 857 S[ 390]858 S[391] 859 S[ 392]860 S[393] 861 S[ 394]862 S[395] 863 S[ 396]864 S[397] 865 S[ 398]866 S[399] 867 S[ 400]868 S[401] 869 S[ 402]870 S[403] 871 S[ 404]872 S[405] 873 S[ 406]874 S[407] 875 S[ 408]876 S[409] 877 S[ 410]878 S[411] 879 S[ 412]880 S[413] 881 S[ 414]882 S[415] 883 S[ 416]884 S[417] 885 S[ 418]886 S[419] 887 S[ 420]888 S[421] 889 S[ 422]890 S[423] 891 S[ 424]892 S[425] 893 S[ 426]894 S[427] 895 S[ 428]896 S[429] 897 S[ 430]898 S[431] 899 S[ 432]900 S[433] 901 S[ 434]902 S[435] 903 S[ 436]904 S[437] 905 S[ 438]906 S[439] 907 S[ 440]908 S[441] 909 S[ 442]910 S[443] 911 S[ 444]912 S[445] 913 S[ 446]914 S[447] 915 S[ 448]916 S[449] 917 S[ 450]918 S[451] 919 S[ 452]920 S[453] 921 S[ 454]922 S[455] 923 S[ 456]924 S[457] 925 S[ 458]926 S[459] 927 S[ 460]928 S[461] 929 S[ 462]930 S[463] 931 S[ 464]932 S[465] 933 S[ 466]934 S[467] 935 S[ 468]936 S[469] 937 S[ 470]938 S[471] 939 S[ 472]940 S[473] 941 S[ 474]942 S[475] 943 S[ 476]944 S[477] 945 S[ 478]946 S[479] 947 S[ 480]948 S[481] 949 S[ 482]950 S[483] 951 S[ 484]952 S[485] 953 S[ 486]954 S[487] 955 S[ 488]956 S[489] 957 S[ 490]958 S[491] 959 S[ 492]960 S[493] 961 S[ 494]962 S[495] 963 S[ 496]964 S[497] 965 S[ 498]966 S[499] 967 S[ 500]968 S[501] 969 S[ 502]970 S[503] 971 S[ 504]972 S[505] 973 S[ 506]974 S[507] 975 S[ 508]976 S[509] 977 S[ 510]978 S[511] 979 S[ 512]980 S[513] 981 S[ 514]982 S[515] 983 S[ 516]984 S[517] 985 S[ 518]986 S[519] 987 S[ 520]988 S[521] 989 S[ 522]990 S[523] 991 S[ 524]992 S[525] 993 S[ 526]994 S[527] 995 S[ 528]996 S[529] 997 S[ 530]998 S[531] 999 S[ 532]1000 S[ 533] 1001 S[534]1002 S[ 535] 1003 S[536]1004 S[ 537] 1005 S[538]1006 S[ 539] 1007 S[540]1008 S[ 541] 1009 S[542]1010 S[ 543] 1011 S[544]1012 S[ 545] 1013 S[546]1014 S[ 547] 1015 S[548]1016 S[ 549] 1017 S[550]1018 S[ 551] 1019 S[552]1020 S[ 553] 1021 S[554]1022 S[ 555] 1023 S[556]1024 S[ 557] 1025 S[558]1026 S[ 559] 1027 S[560]1028 S[ 561] 1029 S[562]1030 S[ 563] 1031 S[564]1032 S[ 565] 1033 S[566]1034 S[ 567] 1035 S[568]1036 S[ 569] 1037 S[570]1038 S[ 571] 1039 S[572]1040 S[ 573] 1041 S[574]1042 S[ 575] 1043 S[576]1044 S[ 577] 1045 S[578]1046 S[ 579] 1047 S[580]1048 S[ 581] 1049 S[582]1050 S[ 583] 1051 S[584]1052 S[ 585] 1053 S[586]1054 S[ 587] 1055 S[588]1056 S[ 589] 1057 S[590]1058 S[ 591] 1059 S[592]1060 S[ 593] 1061 S[594]1062 S[ 595] 1063 S[596]1064 S[ 597] 1065 S[598]1066 S[ 599] 1067 S[600]1068 S[ 601] 1069 S[602]1070 S[ 603] 1071 S[604]1072 S[ 605] 1073 S[606]1074 S[ 607] 1075 S[608]1076 S[ 609] 1077 S[610]1078 S[ 611] 1079 S[612]1080 S[ 613] 1081 S[614]1082 S[ 615] 1083 S[616]1084 S[ 617] 1085 S[618]1086 S[ 619] 1087 S[620]1088 S[ 621] 1089 S[622]1090 S[ 623] 1091 S[624]1092 S[ 625] 1093 S[626]1094 S[ 627] 1095 S[628]1096 S[ 629] 1097 S[630]1098 S[ 631] 1099 S[632]1100 S[ 633] 1101 S[634]1102 S[ 635] 1103 S[636]1104 S[ 637] 1105 S[638]1106 S[ 639] 1107 S[640]1108 S[ 641] 1109 S[642]1110 S[ 643] 1111 S[644]1112 S[ 645] 1113 S[646]1114 S[ 647] 1115 S[648]1116 S[ 649] 1117 S[650]1118 S[ 651] 1119 S[652]1120 S[ 653] 1121 S[654]1122 S[ 655] 1123 S[656]1124 S[ 657] 1125 S[658]1126 S[ 659] 1127 S[660]1128 S[ 661] 1129 S[662]1130 S[ 663] 1131 S[664]1132 S[ 665] 1133 S[666]1134 S[ 667] 1135 S[668]1136 S[ 669] 1137 S[670]1138 S[ 671] 1139 S[672]1140 S[ 673] 1141 S[674]1142 S[ 675] 1143 S[676]1144 S[ 677] 1145 S[678]1146 S[ 679] 1147 S[680]1148 S[ 681] 1149 S[682]1150 S[ 683] 1151 S[684]1152 S[ 685] 1153 S[686]1154 S[ 687] 1155 S[688]1156 S[ 689] 1157 S[690]1158 S[ 691] 1159 S[692]1160 S[ 693] 1161 S[694]1162 S[ 695] 1163 S[696]1164 S[ 697] 1165 S[698]1166 S[ 699] 1167 S[700]1168 S[ 701] 1169 S[702]1170 S[ 703] 1171 S[704]1172 S[ 705] 1173 S[706]1174 S[ 707] 1175 S[708]1176 S[ 709] 1177 S[710]1178 S[ 711] 1179 S[712]1180 S[ 713] 1181 S[714]1182 S[ 715] 1183 S[716]1184 S[ 717] 1185 S[718]1186 S[ 719] 1187 S[720]1188 DMY _VSS 1189 DMY _VS S1190 DMY 1191 DMY1192 DMY 1193 DMY1194 DMY 1195 DMY1196 DMY 1197 DMY1198 DMY 1199 DMY1200 DMY 1201 DMY1202 DMY 1203 DMY1204 DMY 1205 DMY1206 DMY 1207 DMY1208 DMY 1209 DMY1210 DMY 1211 DMY1212 DMY 1213 DMY1214 DMY 1215 DMY1216 DMY 1217 DMY1218 DMY 1219 DMY1220 DMY 1221 DMY1222 DMY 1223 DMY1224 DMY 1225 DMY1226 DMY 1227 DMY1228 DMY 1229 DMY1230 DMY 1231 DMY1232 DMY 1233 DMY1234 DMY 1235 DMY _VS S1236 DMY _VSS 1237 S[721]1238 S[ 722] 1239 S[723]1240 S[ 724] 1241 S[725]1242 S[ 726] 1243 S[727]1244 S[ 728] 1245 S[729]1246 S[ 730] 1247 S[731]1248 S[ 732] 1249 S[733]1250 S[ 734] 1251 S[735]1252 S[ 736] 1253 S[737]1254 S[ 738] 1255 S[739]1256 S[ 740] 1257 S[741]1258 S[ 742] 1259 S[743]1260 S[ 744] 1261 S[745]1262 S[ 746] 1263 S[747]1264 S[ 748] 1265 S[749]1266 S[ 750] 1267 S[751]1268 S[ 752] 1269 S[753]1270 S[ 754] 1271 S[755]1272 S[ 756] 1273 S[757]1274 S[ 758] 1275 S[759]1276 S[ 760] 1277 S[761]1278 S[ 762] 1279 S[763]1280 S[ 764] 1281 S[765]1282 S[ 766] 1283 S[767]1284 S[ 768] 1285 S[769]1286 S[ 770] 1287 S[771]1288 S[ 772] 1289 S[773]1290 S[ 774] 1291 S[775]1292 S[ 776] 1293 S[777]1294 S[ 778] 1295 S[779]1296 S[ 780] 1297 S[781]1298 S[ 782] 1299 S[783]1300 S[ 784] 1301 S[785]1302 S[ 786] 1303 S[787]1304 S[ 788] 1305 S[789]1306 S[ 790] [] -320 -220 -120 -20 180 280 380 000 0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10000 11000 12000

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 29 of 328 2.5. Bump Arrangement Output PAD Input PAD 9040 Alignment mark ALMARK_L_T (- 11870, 305) 3030303030 Unit : um ALMARK_R_T (1 1 8 7 0, 3 0 5 ) 3030303030 Unit : um

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 30 of 328 2.6. Pad Coordination No. Pad Name X Y No. Pad Name X Y No. Pad Name X Y No. Pad Name X Y

1 DMY_VSS -11910 -315 61 VREG2OUT -8310 -315 121 DB[21] -4710 -315 181 VCORE -1110 -315

2 DMY_VSS -11850 -315 62 VREG1OUT -8250 -315 122 DB[20] -4650 -315 182 DGND -1050 -315

3 DMY_VSS -11790 -315 63 DGND -8190 -315 123 DB[19] -4590 -315 183 DGND -990 -315

4 PADA1 -11730 -315 64 DGND -8130 -315 124 DB[18] -4530 -315 184 DGND -930 -315

5 PADB1 -11670 -315 65 DGND -8070 -315 125 DB[17] -4470 -315 185 DGND -870 -315

6 VCOM -11610 -315 66 VCORE -8010 -315 126 DB[16] -4410 -315 186 DGND -810 -315

7 VCOM -11550 -315 67 VCORE -7950 -315 127 DB[15] -4350 -315 187 HS_D1P -750 -315

8 VCOM -11490 -315 68 VCORE -7890 -315 128 DB[14] -4290 -315 188 HS_D1P -690 -315

9 VCOM -11430 -315 69 VCI -7830 -315 129 DB[13] -4230 -315 189 HS_D1P -630 -315

10 VCOM -11370 -315 70 VCI -7770 -315 130 DB[12] -4170 -315 190 HS_D1P -570 -315

11 CONTACT1A -11310 -315 71 VCI -7710 -315 131 DB[11] -4110 -315 191 HS_D1N -510 -315

12 CONTACT1B -11250 -315 72 VCL -7650 -315 132 DB[10] -4050 -315 192 HS_D1N -450 -315

13 VPP -11190 -315 73 VCL -7590 -315 133 DB[9] -3990 -315 193 HS_D1N -390 -315

14 VPP -11130 -315 74 VCL -7530 -315 134 DB[8] -3930 -315 194 HS_D1N -330 -315

15 VPP -11070 -315 75 VCL -7470 -315 135 DB[7] -3870 -315 195 DGND -270 -315

16 VPP -11010 -315 76 VCL -7410 -315 136 DB[6] -3810 -315 196 DGND -210 -315

17 VPP -10950 -315 77 VCL -7350 -315 137 DB[5] -3750 -315 197 HS_CP -150 -315

18 VGL -10890 -315 78 AGND -7290 -315 138 DB[4] -3690 -315 198 HS_CP -90 -315

19 VGL -10830 -315 79 AGND -7230 -315 139 DB[3] -3630 -315 199 HS_CP -30 -315

20 VGLO -10770 -315 80 AGND -7170 -315 140 DB[2] -3570 -315 200 HS_CP 30 -315

21 VGLO -10710 -315 81 IOVCC -7110 -315 141 DB[1] -3510 -315 201 HS_CN 90 -315

22 VGL_REG -10650 -315 82 LANSEL -7050 -315 142 DB[0] -3450 -315 202 HS_CN 150 -315

23 VGL_REG -10590 -315 83 DSWAP -6990 -315 143 DE -3390 -315 203 HS_CN 210 -315

24 VGH_REG -10530 -315 84 PSWAP -6930 -315 144 PCLK -3330 -315 204 HS_CN 270 -315

25 VGH_REG -10470 -315 85 DGND -6870 -315 145 HS -3270 -315 205 DGND 330 -315

26 VCL -10410 -315 86 TESTDIN[6] -6810 -315 146 VS -3210 -315 206 DGND 390 -315

27 VCL -10350 -315 87 NBWSEL -6750 -315 147 LEDPWM -3150 -315 207 HS_D0P 450 -315

28 VCL -10290 -315 88 VGSW[3] -6690 -315 148 LEDON -3090 -315 208 HS_D0P 510 -315

29 VCL -10230 -315 89 VGSW[2] -6630 -315 149 DMY -3030 -315 209 HS_D0P 570 -315

30 VREF15 -10170 -315 90 VGSW[1] -6570 -315 150 ERR -2970 -315 210 HS_D0P 630 -315

31 VREF15 -10110 -315 91 VGSW[0] -6510 -315 151 IOVCC -2910 -315 211 HS_D0N 690 -315

32 VREF15 -10050 -315 92 IOVCC -6450 - 315 152 IOVCC -2850 -315 212 HS_D0N 750 -315

33 VREF15 -9990 -315 93 TESTDIN[7] -6390 -315 153 IOVCC -2790 -315 213 HS_D0N 810 -315

34 AGND -9930 -315 94 TESTDOUT[0] -6330 -315 154 DGND -2730 -315 214 HS_D0N 870 -315

35 AGND -9870 -315 95 IM[3] -6270 -315 155 DGND -2670 -315 215 DGND 930 -315

36 AGND -9810 -315 96 IM[2] -6210 -315 156 DGND -2610 -315 216 DGND 990 -315

37 AGND -9750 -315 97 IM[1] -6150 -315 157 DDVDH -2550 -315 217 V12_MIPI 1050 -315

38 VCI -9690 -315 98 IM[0] -6090 -315 158 DDVDH -2490 -315 218 V12_MIPI 1110 -315

39 VCI -9630 -315 99 GPO[3] -6030 -315 159 DDVDH -2430 -315 219 V12_MIPI 1170 -315

40 VCI -9570 -315 100 GPO[2] -5970 -315 160 DDVDH -2370 -315 220 VCORE_MIPI 1230 -315

41 VCI -9510 -315 101 GPO[1] -5910 -315 161 AGND -2310 -315 221 VCORE_MIPI 1290 -315

42 VCIR -9450 -315 102 GPO[0] -5850 -315 162 AGND -2250 -315 222 VCORE_MIPI 1350 -315

43 VCIR -9390 -315 103 TESTDOUT[1] -5790 -315 163 AGND -2190 -315 223 VCI 1410 -315

44 VCIR -9330 -315 104 TE_L -5730 -315 164 AGND -2130 -315 224 VCI 1470 -315

45 VCIR -9270 -315 105 TESTDOUT[2] -5670 -315 165 DDVDL -2070 -315 225 VCI 1530 -315

46 VSSR[1] -9210 -315 106 SDO -5610 -315 166 DDVDL -2010 -315 226 VCI 1590 -315

47 VSSR[1] -9150 -315 107 SDI -5550 -315 167 DDVDL -1950 -315 227 VCI 1650 -315

48 VSSR[1] -9090 -315 108 TESTDOUT[3] -5490 -315 168 DDVDL -1890 -315 228 VCI 1710 -315

49 VSSR[1] -9030 -315 109 SCL -5430 -315 169 DDVDL -1830 -315 229 VCI 1770 -315

50 TESTDIN[0] -8970 -315 110 TESTD_EN - 5 3 7 0 - 3 1 5 1 7 0 V C I - 1 7 7 0 - 3 1 5 2 3 0 V C I 1 8 3 0- 3 1 5

51 TESTDIN[1] -8910 -315 111 CSX -5310 -315 171 VCI -1710 -315 231 DMY 1890 -315

52 TESTDIN[2] -8850 -315 112 RESX -5250 -315 172 VCI -1650 -315 232 TE_R 1950 -315

53 TESTDIN[3] -8790 -315 113 DGND -5190 -315 173 VCI -1590 -315 233 VSSR[2] 2010 -315

54 DMY -8730 -315 114 DGND -5130 -315 174 DGND -1530 -315 234 VSSR[2] 2070 -315

55 TESTDIN[4] -8670 -315 115 DGND - 5070 -315 175 DGND -1470 -315 235 VSSR[2] 2130 -315

56 TESTDIN[5] -8610 -315 116 IOVCC -5010 -315 176 DGND -1410 -315 236 VSSR[2] 2190 -315

57 DMY -8550 -315 117 IOVCC -4950 -315 177 DGND -1350 -315 237 DMY 2250 -315

58 DMY -8490 -315 118 IOVCC -4890 -315 178 VCORE -1290 -315 238 DMY 2310 -315

59 DMY -8430 -315 119 DB[23] -4830 -315 179 VCORE -1230 -315 239 VGH_REG 2370 -315

60 VREG2OUT -8370 -315 120 DB[22] -4770 -315 180 VCORE -1170 -315 240 VGH_REG 2430 -315

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 31 of 328 No. Pad Name X Y No. Pad Name X Y No. Pad Name X Y No. Pad Name X Y 241 EXTP 2490 -315 301 C21P 6090 -315 361 C41P 9690 -315 421 GOUT_VGLO 11438 312.5 242 EXTP 2550 -315 302 C21P 6150 -315 362 C41P 9750 -315 422 GOUT_VGLO 11424 187.5 243 DMY 2610 -315 303 C21N 6210 -315 363 C41N 9810 -315 423 GOUT[3] 11410 312.5 244 DMY 2670 -315 304 C21N 6270 -315 364 C41N 9870 -315 424 GOUT[3] 11396 187.5 245 EXTN 2730 -315 305 C21N 6330 -315 365 VGH 9930 -315 425 GOUT[4] 11382 312.5 246 EXTN 2790 -315 306 C22P 6390 -315 366 VGH 9990 -315 426 GOUT[4] 11368 187.5 247 DMY 2850 -315 307 C22P 6450 -315 367 VGHO 10050 -315 427 GOUT[5] 11354 312.5 248 DMY 2910 -315 308 C22P 6510 -315 368 VGHO 10110 -315 428 GOUT[5] 11340 187.5 249 VCIP 2970 -315 309 C22N 6570 -315 369 VGH_REG 10170 -315 429 GOUT[6] 11326 312.5 250 VCIP 3030 -315 310 C22N 6630 -315 370 VGH_REG 10230 -315 430 GOUT[6] 11312 187.5 251 VCIP 3090 -315 311 C22N 6690 -315 371 C51P 10290 -315 431 GOUT[7] 11298 312.5 252 VCIP 3150 -315 312 C23P 6750 -315 372 C51P 10350 -315 432 GOUT[7] 11284 187.5 253 VCIP 3210 -315 313 C23P 6810 -315 373 C51N 10410 -315 433 GOUT[8] 11270 312.5 254 VCIP 3270 -315 314 C23P 6870 -315 374 C51N 10470 -315 434 GOUT[8] 11256 187.5 255 CGND 3330 -315 315 C23N 6930 -315 375 VGL_REG 10530 -315 435 GOUT[9] 11242 312.5 256 CGND 3390 -315 316 C23N 6990 -315 376 VGL_REG 10590 -315 436 GOUT[9] 11228 187.5 257 CGND 3450 -315 317 C23N 7050 -315 377 VGLO 10650 -315 437 GOUT[10] 11214 312.5 258 CGND 3510 -315 318 C24P 7110 -315 378 VGLO 10710 -315 438 GOUT[10] 11200 187.5 259 CGND 3570 -315 319 C24P 7170 -315 379 VGL 10770 -315 439 GOUT[11] 11186 312.5 260 CGND 3630 -315 320 C24P 7230 -315 380 VGL 10830 -315 440 GOUT[11] 11172 187.5 261 C11P 3690 -315 321 C24N 7290 -315 381 VGL 10890 -315 441 GOUT[12] 11158 312.5 262 C11P 3750 -315 322 C24N 7350 -315 382 VGL 10950 -315 442 GOUT[12] 11144 187.5 263 C11P 3810 -315 323 C24N 7410 -315 383 DMY 11010 -315 443 GOUT[13] 11130 312.5 264 C11N 3870 -315 324 VCIP 7470 -315 384 DMY 11070 -315 444 GOUT[13] 11116 187.5 265 C11N 3930 -315 325 VCIP 7530 -315 385 DMY 11130 -315 445 GOUT[14] 11102 312.5 266 C11N 3990 -315 326 VCIP 7590 -315 386 DMY 11190 -315 446 GOUT[14] 11088 187.5 267 C12P 4050 -315 327 VCIP 7650 -315 387 CONTACT2A 11250 -315 447 GOUT[15] 11074 312.5 268 C12P 4110 -315 328 VCIP 7710 -315 388 CONTACT2B 11310 -315 448 GOUT[15] 11060 187.5 269 C12P 4170 -315 329 VCL 7770 -315 389 VCOM 11370 -315 449 GOUT[16] 11046 312.5 270 C12N 4230 -315 330 VCL 7830 -315 390 VCOM 11430 -315 450 GOUT[16] 11032 187.5 271 C12N 4290 -315 331 VCL 7890 -315 391 VCOM 11490 -315 451 GOUT_VGHO 11018 312.5 272 C12N 4350 -315 332 VCL 7950 -315 392 VCOM 11550 -315 452 GOUT_VGHO 11004 187.5 273 C13P 4410 -315 333 VCL 8010 -315 393 VCOM 11610 -315 453 GOUT_VGHO 10990 312.5 274 C13P 4470 -315 334 VCL 8070 -315 394 PADA2 11670 -315 454 GOUT_VGHO 10976 187.5 275 C13P 4530 -315 335 VCL 8130 -315 395 PADB2 11730 -315 455 GOUT_VGHO 10962 312.5 276 C13N 4590 -315 336 VSSR[3] 8190 -315 396 DMY_VSS 11790 -315 456 GOUT_VGHO 10948 187.5 277 C13N 4650 -315 337 VSSR[3] 8250 -315 397 DMY_VSS 11850 -315 457 DMY_VGH 10934 312.5 278 C13N 4710 -315 338 VSSR[3] 8310 -315 398 DMY_VSS 11910 -315 458 DMY_VGH 10920 187.5 279 C14P 4770 -315 339 CGND 8370 -315 399 DMY_VSS 11760 312.5 459 GOUT_VGLO 10906 312.5 280 C14P 4830 -315 340 CGND 8430 -315 400 DMY_VSS 11732 187.5 460 GOUT_VGLO 10892 187.5 281 C14P 4890 -315 341 CGND 8490 -315 401 DMY_VSS 11718 312.5 461 GOUT_VGLO 10878 312.5 282 C14N 4950 -315 342 CGND 8550 -315 402 PADA3 11704 187.5 462 GOUT_VGLO 10864 187.5 283 C14N 5010 -315 343 C31P 8610 -315 403 PADB3 11690 312.5 463 GOUT_VGLO 10850 312.5 284 C14N 5070 -315 344 C31P 8670 -315 404 GOUT_VGHO 11676 187.5 464 GOUT_VGLO 10836 187.5 285 DDVDH 5130 -315 345 C31P 8730 -315 405 GOUT_VGHO 11662 312.5 465 DMY_VSS 10766 312.5 286 DDVDH 5190 -315 346 C31N 8790 -315 406 GOUT_VGHO 11648 187.5 466 DMY_VSS 10752 187.5 287 DDVDH 5250 -315 347 C31N 8850 -315 407 GOUT_VGLO 11634 312.5 467 S[0] 10738 312.5 288 DDVDH 5310 -315 348 C31N 8910 -315 408 GOUT_VGLO 11620 187.5 468 S[1] 10724 187.5 289 CGND 5370 -315 349 C32P 8970 -315 409 GOUT_VGLO 11606 312.5 469 S[2] 10710 312.5 290 CGND 5430 -315 350 C32P 9030 -315 410 GOUT[1] 11592 187.5 470 S[3] 10696 187.5 291 CGND 5490 -315 351 C32P 9090 -315 411 GOUT[1] 11578 312.5 471 S[4] 10682 312.5 292 CGND 5550 -315 352 C32N 9150 -315 412 GOUT[2] 11564 187.5 472 S[5] 10668 187.5 293 CGND 5610 -315 353 C32N 9210 -315 413 GOUT[2] 11550 312.5 473 S[6] 10654 312.5 294 DDVDL 5670 -315 354 C32N 9270 -315 414 LVGL 11536 187.5 474 S[7] 10640 187.5 295 DDVDL 5730 -315 355 VCORE 9330 -315 415 LVGL 11522 312.5 475 S[8] 10626 312.5 296 DDVDL 5790 -315 356 VCORE 9390 -315 416 LVGL 11508 187.5 476 S[9] 10612 187.5 297 DDVDL 5850 -315 357 VCORE 9450 -315 417 VGH_REG 11494 312.5 477 S[10] 10598 312.5 298 DDVDL 5910 -315 358 AGND 9510 -315 418 VGH_REG 11480 187.5 478 S[11] 10584 187.5 299 DDVDL 5970 -315 359 AGND 9570 -315 419 VGH_REG 11466 312.5 479 S[12] 10570 312.5 300 C21P 6030 -315 360 AGND 9630 -315 420 GOUT_VGLO 11452 187.5 480 S[13] 10556 187.5

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 32 of 328 No. Pad Name X Y No. Pad Name X Y No. Pad Name X Y No. Pad Name X Y 481 S[14] 10542 312.5 541 S[74] 9702 312.5 601 S[134] 8862 312.5 661 S[194] 8022 312.5 482 S[15] 10528 187.5 542 S[75] 9688 187.5 602 S[135] 8848 187.5 662 S[195] 8008 187.5 483 S[16] 10514 312.5 543 S[76] 9674 312.5 603 S[136] 8834 312.5 663 S[196] 7994 312.5 484 S[17] 10500 187.5 544 S[77] 9660 187.5 604 S[137] 8820 187.5 664 S[197] 7980 187.5 485 S[18] 10486 312.5 545 S[78] 9646 312.5 605 S[138] 8806 312.5 665 S[198] 7966 312.5 486 S[19] 10472 187.5 546 S[79] 9632 187.5 606 S[139] 8792 187.5 666 S[199] 7952 187.5 487 S[20] 10458 312.5 547 S[80] 9618 312.5 607 S[140] 8778 312.5 667 S[200] 7938 312.5 488 S[21] 10444 187.5 548 S[81] 9604 187.5 608 S[141] 8764 187.5 668 S[201] 7924 187.5 489 S[22] 10430 312.5 549 S[82] 9590 312.5 609 S[142] 8750 312.5 669 S[202] 7910 312.5 490 S[23] 10416 187.5 550 S[83] 9576 187.5 610 S[143] 8736 187.5 670 S[203] 7896 187.5 491 S[24] 10402 312.5 551 S[84] 9562 312.5 611 S[144] 8722 312.5 671 S[204] 7882 312.5 492 S[25] 10388 187.5 552 S[85] 9548 187.5 612 S[145] 8708 187.5 672 S[205] 7868 187.5 493 S[26] 10374 312.5 553 S[86] 9534 312.5 613 S[146] 8694 312.5 673 S[206] 7854 312.5 494 S[27] 10360 187.5 554 S[87] 9520 187.5 614 S[147] 8680 187.5 674 S[207] 7840 187.5 495 S[28] 10346 312.5 555 S[88] 9506 312.5 615 S[148] 8666 312.5 675 S[208] 7826 312.5 496 S[29] 10332 187.5 556 S[89] 9492 187.5 616 S[149] 8652 187.5 676 S[209] 7812 187.5 497 S[30] 10318 312.5 557 S[90] 9478 312.5 617 S[150] 8638 312.5 677 S[210] 7798 312.5 498 S[31] 10304 187.5 558 S[91] 9464 187.5 618 S[151] 8624 187.5 678 S[211] 7784 187.5 499 S[32] 10290 312.5 559 S[92] 9450 312.5 619 S[152] 8610 312.5 679 S[212] 7770 312.5 500 S[33] 10276 187.5 560 S[93] 9436 187.5 620 S[153] 8596 187.5 680 S[213] 7756 187.5 501 S[34] 10262 312.5 561 S[94] 9422 312.5 621 S[154] 8582 312.5 681 S[214] 7742 312.5 502 S[35] 10248 187.5 562 S[95] 9408 187.5 622 S[155] 8568 187.5 682 S[215] 7728 187.5 503 S[36] 10234 312.5 563 S[96] 9394 312.5 623 S[156] 8554 312.5 683 S[216] 7714 312.5 504 S[37] 10220 187.5 564 S[97] 9380 187.5 624 S[157] 8540 187.5 684 S[217] 7700 187.5 505 S[38] 10206 312.5 565 S[98] 9366 312.5 625 S[158] 8526 312.5 685 S[218] 7686 312.5 506 S[39] 10192 187.5 566 S[99] 9352 187.5 626 S[159] 8512 187.5 686 S[219] 7672 187.5 507 S[40] 10178 312.5 567 S[100] 9338 312.5 627 S[160] 8498 312.5 687 S[220] 7658 312.5 508 S[41] 10164 187.5 568 S[101] 9324 187.5 628 S[161] 8484 187.5 688 S[221] 7644 187.5 509 S[42] 10150 312.5 569 S[102] 9310 312.5 629 S[162] 8470 312.5 689 S[222] 7630 312.5 510 S[43] 10136 187.5 570 S[103] 9296 187.5 630 S[163] 8456 187.5 690 S[223] 7616 187.5 511 S[44] 10122 312.5 571 S[104] 9282 312.5 631 S[164] 8442 312.5 691 S[224] 7602 312.5 512 S[45] 10108 187.5 572 S[105] 9268 187.5 632 S[165] 8428 187.5 692 S[225] 7588 187.5 513 S[46] 10094 312.5 573 S[106] 9254 312.5 633 S[166] 8414 312.5 693 S[226] 7574 312.5 514 S[47] 10080 187.5 574 S[107] 9240 187.5 634 S[167] 8400 187.5 694 S[227] 7560 187.5 515 S[48] 10066 312.5 575 S[108] 9226 312.5 635 S[168] 8386 312.5 695 S[228] 7546 312.5 516 S[49] 10052 187.5 576 S[109] 9212 187.5 636 S[169] 8372 187.5 696 S[229] 7532 187.5 517 S[50] 10038 312.5 577 S[110] 9198 312.5 637 S[170] 8358 312.5 697 S[230] 7518 312.5 518 S[51] 10024 187.5 578 S[111] 9184 187.5 638 S[171] 8344 187.5 698 S[231] 7504 187.5 519 S[52] 10010 312.5 579 S[112] 9170 312.5 639 S[172] 8330 312.5 699 S[232] 7490 312.5 520 S[53] 9996 187.5 580 S[113] 9156 187.5 640 S[173] 8316 187.5 700 S[233] 7476 187.5 521 S[54] 9982 312.5 581 S[114] 9142 312.5 641 S[174] 8302 312.5 701 S[234] 7462 312.5 522 S[55] 9968 187.5 582 S[115] 9128 187.5 642 S[175] 8288 187.5 702 S[235] 7448 187.5 523 S[56] 9954 312.5 583 S[116] 9114 312.5 643 S[176] 8274 312.5 703 S[236] 7434 312.5 524 S[57] 9940 187.5 584 S[117] 9100 187.5 644 S[177] 8260 187.5 704 S[237] 7420 187.5 525 S[58] 9926 312.5 585 S[118] 9086 312.5 645 S[178] 8246 312.5 705 S[238] 7406 312.5 526 S[59] 9912 187.5 586 S[119] 9072 187.5 646 S[179] 8232 187.5 706 S[239] 7392 187.5 527 S[60] 9898 312.5 587 S[120] 9058 312.5 647 S[180] 8218 312.5 707 S[240] 7378 312.5 528 S[61] 9884 187.5 588 S[121] 9044 187.5 648 S[181] 8204 187.5 708 S[241] 7364 187.5 529 S[62] 9870 312.5 589 S[122] 9030 312.5 649 S[182] 8190 312.5 709 S[242] 7350 312.5 530 S[63] 9856 187.5 590 S[123] 9016 187.5 650 S[183] 8176 187.5 710 S[243] 7336 187.5 531 S[64] 9842 312.5 591 S[124] 9002 312.5 651 S[184] 8162 312.5 711 S[244] 7322 312.5 532 S[65] 9828 187.5 592 S[125] 8988 187.5 652 S[185] 8148 187.5 712 S[245] 7308 187.5 533 S[66] 9814 312.5 593 S[126] 8974 312.5 653 S[186] 8134 312.5 713 S[246] 7294 312.5 534 S[67] 9800 187.5 594 S[127] 8960 187.5 654 S[187] 8120 187.5 714 S[247] 7280 187.5 535 S[68] 9786 312.5 595 S[128] 8946 312.5 655 S[188] 8106 312.5 715 S[248] 7266 312.5 536 S[69] 9772 187.5 596 S[129] 8932 187.5 656 S[189] 8092 187.5 716 S[249] 7252 187.5 537 S[70] 9758 312.5 597 S[130] 8918 312.5 657 S[190] 8078 312.5 717 S[250] 7238 312.5 538 S[71] 9744 187.5 598 S[131] 8904 187.5 658 S[191] 8064 187.5 718 S[251] 7224 187.5 539 S[72] 9730 312.5 599 S[132] 8890 312.5 659 S[192] 8050 312.5 719 S[252] 7210 312.5 540 S[73] 9716 187.5 600 S[133] 8876 187.5 660 S[193] 8036 187.5 720 S[253] 7196 187.5

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 33 of 328 No. Pad Name X Y No. Pad Name X Y No. Pad Name X Y No. Pad Name X Y 721 S[254] 7182 312.5 781 S[314] 6342 312.5 841 S[374] 5502 312.5 901 S[434] 4662 312.5 722 S[255] 7168 187.5 782 S[315] 6328 187.5 842 S[375] 5488 187.5 902 S[435] 4648 187.5 723 S[256] 7154 312.5 783 S[316] 6314 312.5 843 S[376] 5474 312.5 903 S[436] 4634 312.5 724 S[257] 7140 187.5 784 S[317] 6300 187.5 844 S[377] 5460 187.5 904 S[437] 4620 187.5 725 S[258] 7126 312.5 785 S[318] 6286 312.5 845 S[378] 5446 312.5 905 S[438] 4606 312.5 726 S[259] 7112 187.5 786 S[319] 6272 187.5 846 S[379] 5432 187.5 906 S[439] 4592 187.5 727 S[260] 7098 312.5 787 S[320] 6258 312.5 847 S[380] 5418 312.5 907 S[440] 4578 312.5 728 S[261] 7084 187.5 788 S[321] 6244 187.5 848 S[381] 5404 187.5 908 S[441] 4564 187.5 729 S[262] 7070 312.5 789 S[322] 6230 312.5 849 S[382] 5390 312.5 909 S[442] 4550 312.5 730 S[263] 7056 187.5 790 S[323] 6216 187.5 850 S[383] 5376 187.5 910 S[443] 4536 187.5 731 S[264] 7042 312.5 791 S[324] 6202 312.5 851 S[384] 5362 312.5 911 S[444] 4522 312.5 732 S[265] 7028 187.5 792 S[325] 6188 187.5 852 S[385] 5348 187.5 912 S[445] 4508 187.5 733 S[266] 7014 312.5 793 S[326] 6174 312.5 853 S[386] 5334 312.5 913 S[446] 4494 312.5 734 S[267] 7000 187.5 794 S[327] 6160 187.5 854 S[387] 5320 187.5 914 S[447] 4480 187.5 735 S[268] 6986 312.5 795 S[328] 6146 312.5 855 S[388] 5306 312.5 915 S[448] 4466 312.5 736 S[269] 6972 187.5 796 S[329] 6132 187.5 856 S[389] 5292 187.5 916 S[449] 4452 187.5 737 S[270] 6958 312.5 797 S[330] 6118 312.5 857 S[390] 5278 312.5 917 S[450] 4438 312.5 738 S[271] 6944 187.5 798 S[331] 6104 187.5 858 S[391] 5264 187.5 918 S[451] 4424 187.5 739 S[272] 6930 312.5 799 S[332] 6090 312.5 859 S[392] 5250 312.5 919 S[452] 4410 312.5 740 S[273] 6916 187.5 800 S[333] 6076 187.5 860 S[393] 5236 187.5 920 S[453] 4396 187.5 741 S[274] 6902 312.5 801 S[334] 6062 312.5 861 S[394] 5222 312.5 921 S[454] 4382 312.5 742 S[275] 6888 187.5 802 S[335] 6048 187.5 862 S[395] 5208 187.5 922 S[455] 4368 187.5 743 S[276] 6874 312.5 803 S[336] 6034 312.5 863 S[396] 5194 312.5 923 S[456] 4354 312.5 744 S[277] 6860 187.5 804 S[337] 6020 187.5 864 S[397] 5180 187.5 924 S[457] 4340 187.5 745 S[278] 6846 312.5 805 S[338] 6006 312.5 865 S[398] 5166 312.5 925 S[458] 4326 312.5 746 S[279] 6832 187.5 806 S[339] 5992 187.5 866 S[399] 5152 187.5 926 S[459] 4312 187.5 747 S[280] 6818 312.5 807 S[340] 5978 312.5 867 S[400] 5138 312.5 927 S[460] 4298 312.5 748 S[281] 6804 187.5 808 S[341] 5964 187.5 868 S[401] 5124 187.5 928 S[461] 4284 187.5 749 S[282] 6790 312.5 809 S[342] 5950 312.5 869 S[402] 5110 312.5 929 S[462] 4270 312.5 750 S[283] 6776 187.5 810 S[343] 5936 187.5 870 S[403] 5096 187.5 930 S[463] 4256 187.5 751 S[284] 6762 312.5 811 S[344] 5922 312.5 871 S[404] 5082 312.5 931 S[464] 4242 312.5 752 S[285] 6748 187.5 812 S[345] 5908 187.5 872 S[405] 5068 187.5 932 S[465] 4228 187.5 753 S[286] 6734 312.5 813 S[346] 5894 312.5 873 S[406] 5054 312.5 933 S[466] 4214 312.5 754 S[287] 6720 187.5 814 S[347] 5880 187.5 874 S[407] 5040 187.5 934 S[467] 4200 187.5 755 S[288] 6706 312.5 815 S[348] 5866 312.5 875 S[408] 5026 312.5 935 S[468] 4186 312.5 756 S[289] 6692 187.5 816 S[349] 5852 187.5 876 S[409] 5012 187.5 936 S[469] 4172 187.5 757 S[290] 6678 312.5 817 S[350] 5838 312.5 877 S[410] 4998 312.5 937 S[470] 4158 312.5 758 S[291] 6664 187.5 818 S[351] 5824 187.5 878 S[411] 4984 187.5 938 S[471] 4144 187.5 759 S[292] 6650 312.5 819 S[352] 5810 312.5 879 S[412] 4970 312.5 939 S[472] 4130 312.5 760 S[293] 6636 187.5 820 S[353] 5796 187.5 880 S[413] 4956 187.5 940 S[473] 4116 187.5 761 S[294] 6622 312.5 821 S[354] 5782 312.5 881 S[414] 4942 312.5 941 S[474] 4102 312.5 762 S[295] 6608 187.5 822 S[355] 5768 187.5 882 S[415] 4928 187.5 942 S[475] 4088 187.5 763 S[296] 6594 312.5 823 S[356] 5754 312.5 883 S[416] 4914 312.5 943 S[476] 4074 312.5 764 S[297] 6580 187.5 824 S[357] 5740 187.5 884 S[417] 4900 187.5 944 S[477] 4060 187.5 765 S[298] 6566 312.5 825 S[358] 5726 312.5 885 S[418] 4886 312.5 945 S[478] 4046 312.5 766 S[299] 6552 187.5 826 S[359] 5712 187.5 886 S[419] 4872 187.5 946 S[479] 4032 187.5 767 S[300] 6538 312.5 827 S[360] 5698 312.5 887 S[420] 4858 312.5 947 S[480] 4018 312.5 768 S[301] 6524 187.5 828 S[361] 5684 187.5 888 S[421] 4844 187.5 948 S[481] 4004 187.5 769 S[302] 6510 312.5 829 S[362] 5670 312.5 889 S[422] 4830 312.5 949 S[482] 3990 312.5 770 S[303] 6496 187.5 830 S[363] 5656 187.5 890 S[423] 4816 187.5 950 S[483] 3976 187.5 771 S[304] 6482 312.5 831 S[364] 5642 312.5 891 S[424] 4802 312.5 951 S[484] 3962 312.5 772 S[305] 6468 187.5 832 S[365] 5628 187.5 892 S[425] 4788 187.5 952 S[485] 3948 187.5 773 S[306] 6454 312.5 833 S[366] 5614 312.5 893 S[426] 4774 312.5 953 S[486] 3934 312.5 774 S[307] 6440 187.5 834 S[367] 5600 187.5 894 S[427] 4760 187.5 954 S[487] 3920 187.5 775 S[308] 6426 312.5 835 S[368] 5586 312.5 895 S[428] 4746 312.5 955 S[488] 3906 312.5 776 S[309] 6412 187.5 836 S[369] 5572 187.5 896 S[429] 4732 187.5 956 S[489] 3892 187.5 777 S[310] 6398 312.5 837 S[370] 5558 312.5 897 S[430] 4718 312.5 957 S[490] 3878 312.5 778 S[311] 6384 187.5 838 S[371] 5544 187.5 898 S[431] 4704 187.5 958 S[491] 3864 187.5 779 S[312] 6370 312.5 839 S[372] 5530 312.5 899 S[432] 4690 312.5 959 S[492] 3850 312.5 780 S[313] 6356 187.5 840 S[373] 5516 187.5 900 S[433] 4676 187.5 960 S[493] 3836 187.5

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 34 of 328 No. Pad Name X Y No. Pad Name X Y No. Pad Name X Y No. Pad Name X Y 961 S[494] 3822 312.5 1021 S[554] 2982 312.5 1081 S[614] 2142 312.5 1141 S[674] 1302 312.5 962 S[495] 3808 187.5 1022 S[555] 2968 187.5 1082 S[615] 2128 187.5 1142 S[675] 1288 187.5 963 S[496] 3794 312.5 1023 S[556] 2954 312.5 1083 S[616] 2114 312.5 1143 S[676] 1274 312.5 964 S[497] 3780 187.5 1024 S[557] 2940 187.5 1084 S[617] 2100 187.5 1144 S[677] 1260 187.5 965 S[498] 3766 312.5 1025 S[558] 2926 312.5 1085 S[618] 2086 312.5 1145 S[678] 1246 312.5 966 S[499] 3752 187.5 1026 S[559] 2912 187.5 1086 S[619] 2072 187.5 1146 S[679] 1232 187.5 967 S[500] 3738 312.5 1027 S[560] 2898 312.5 1087 S[620] 2058 312.5 1147 S[680] 1218 312.5 968 S[501] 3724 187.5 1028 S[561] 2884 187.5 1088 S[621] 2044 187.5 1148 S[681] 1204 187.5 969 S[502] 3710 312.5 1029 S[562] 2870 312.5 1089 S[622] 2030 312.5 1149 S[682] 1190 312.5 970 S[503] 3696 187.5 1030 S[563] 2856 187.5 1090 S[623] 2016 187.5 1150 S[683] 1176 187.5 971 S[504] 3682 312.5 1031 S[564] 2842 312.5 1091 S[624] 2002 312.5 1151 S[684] 1162 312.5 972 S[505] 3668 187.5 1032 S[565] 2828 187.5 1092 S[625] 1988 187.5 1152 S[685] 1148 187.5 973 S[506] 3654 312.5 1033 S[566] 2814 312.5 1093 S[626] 1974 312.5 1153 S[686] 1134 312.5 974 S[507] 3640 187.5 1034 S[567] 2800 187.5 1094 S[627] 1960 187.5 1154 S[687] 1120 187.5 975 S[508] 3626 312.5 1035 S[568] 2786 312.5 1095 S[628] 1946 312.5 1155 S[688] 1106 312.5 976 S[509] 3612 187.5 1036 S[569] 2772 187.5 1096 S[629] 1932 187.5 1156 S[689] 1092 187.5 977 S[510] 3598 312.5 1037 S[570] 2758 312.5 1097 S[630] 1918 312.5 1157 S[690] 1078 312.5 978 S[511] 3584 187.5 1038 S[571] 2744 187.5 1098 S[631] 1904 187.5 1158 S[691] 1064 187.5 979 S[512] 3570 312.5 1039 S[572] 2730 312.5 1099 S[632] 1890 312.5 1159 S[692] 1050 312.5 980 S[513] 3556 187.5 1040 S[573] 2716 187.5 1100 S[633] 1876 187.5 1160 S[693] 1036 187.5 981 S[514] 3542 312.5 1041 S[574] 2702 312.5 1101 S[634] 1862 312.5 1161 S[694] 1022 312.5 982 S[515] 3528 187.5 1042 S[575] 2688 187.5 1102 S[635] 1848 187.5 1162 S[695] 1008 187.5 983 S[516] 3514 312.5 1043 S[576] 2674 312.5 1103 S[636] 1834 312.5 1163 S[696] 994 312.5 984 S[517] 3500 187.5 1044 S[577] 2660 187.5 1104 S[637] 1820 187.5 1164 S[697] 980 187.5 985 S[518] 3486 312.5 1045 S[578] 2646 312.5 1105 S[638] 1806 312.5 1165 S[698] 966 312.5 986 S[519] 3472 187.5 1046 S[579] 2632 187.5 1106 S[639] 1792 187.5 1166 S[699] 952 187.5 987 S[520] 3458 312.5 1047 S[580] 2618 312.5 1107 S[640] 1778 312.5 1167 S[700] 938 312.5 988 S[521] 3444 187.5 1048 S[581] 2604 187.5 1108 S[641] 1764 187.5 1168 S[701] 924 187.5 989 S[522] 3430 312.5 1049 S[582] 2590 312.5 1109 S[642] 1750 312.5 1169 S[702] 910 312.5 990 S[523] 3416 187.5 1050 S[583] 2576 187.5 1110 S[643] 1736 187.5 1170 S[703] 896 187.5 991 S[524] 3402 312.5 1051 S[584] 2562 312.5 1111 S[644] 1722 312.5 1171 S[704] 882 312.5 992 S[525] 3388 187.5 1052 S[585] 2548 187.5 1112 S[645] 1708 187.5 1172 S[705] 868 187.5 993 S[526] 3374 312.5 1053 S[586] 2534 312.5 1113 S[646] 1694 312.5 1173 S[706] 854 312.5 994 S[527] 3360 187.5 1054 S[587] 2520 187.5 1114 S[647] 1680 187.5 1174 S[707] 840 187.5 995 S[528] 3346 312.5 1055 S[588] 2506 312.5 1115 S[648] 1666 312.5 1175 S[708] 826 312.5 996 S[529] 3332 187.5 1056 S[589] 2492 187.5 1116 S[649] 1652 187.5 1176 S[709] 812 187.5 997 S[530] 3318 312.5 1057 S[590] 2478 312.5 1117 S[650] 1638 312.5 1177 S[710] 798 312.5 998 S[531] 3304 187.5 1058 S[591] 2464 187.5 1118 S[651] 1624 187.5 1178 S[711] 784 187.5 999 S[532] 3290 312.5 1059 S[592] 2450 312.5 1119 S[652] 1610 312.5 1179 S[712] 770 312.5 1000 S[533] 3276 187.5 1060 S[593] 2436 187.5 1120 S[653] 1596 187.5 1180 S[713] 756 187.5 1001 S[534] 3262 312.5 1061 S[594] 2422 312.5 1121 S[654] 1582 312.5 1181 S[714] 742 312.5 1002 S[535] 3248 187.5 1062 S[595] 2408 187.5 1122 S[655] 1568 187.5 1182 S[715] 728 187.5 1003 S[536] 3234 312.5 1063 S[596] 2394 312.5 1123 S[656] 1554 312.5 1183 S[716] 714 312.5 1004 S[537] 3220 187.5 1064 S[597] 2380 187.5 1124 S[657] 1540 187.5 1184 S[717] 700 187.5 1005 S[538] 3206 312.5 1065 S[598] 2366 312.5 1125 S[658] 1526 312.5 1185 S[718] 686 312.5 1006 S[539] 3192 187.5 1066 S[599] 2352 187.5 1126 S[659] 1512 187.5 1186 S[719] 672 187.5 1007 S[540] 3178 312.5 1067 S[600] 2338 312.5 1127 S[660] 1498 312.5 1187 S[720] 658 312.5 1008 S[541] 3164 187.5 1068 S[601] 2324 187.5 1128 S[661] 1484 187.5 1188 DMY_VSS 644 187.5 1009 S[542] 3150 312.5 1069 S[602] 2310 312.5 1129 S[662] 1470 312.5 1189 DMY_VSS 630 312.5 1010 S[543] 3136 187.5 1070 S[603] 2296 187.5 1130 S[663] 1456 187.5 1190 DMY 616 187.5 1011 S[544] 3122 312.5 1071 S[604] 2282 312.5 1131 S[664] 1442 312.5 1191 DMY 602 312.5 1012 S[545] 3108 187.5 1072 S[605] 2268 187.5 1132 S[665] 1428 187.5 1192 DMY 588 187.5 1013 S[546] 3094 312.5 1073 S[606] 2254 312.5 1133 S[666] 1414 312.5 1193 DMY 574 312.5 1014 S[547] 3080 187.5 1074 S[607] 2240 187.5 1134 S[667] 1400 187.5 1194 DMY 560 187.5 1015 S[548] 3066 312.5 1075 S[608] 2226 312.5 1135 S[668] 1386 312.5 1195 DMY 546 312.5 1016 S[549] 3052 187.5 1076 S[609] 2212 187.5 1136 S[669] 1372 187.5 1196 DMY 532 187.5 1017 S[550] 3038 312.5 1077 S[610] 2198 312.5 1137 S[670] 1358 312.5 1197 DMY 518 312.5 1018 S[551] 3024 187.5 1078 S[611] 2184 187.5 1138 S[671] 1344 187.5 1198 DMY 504 187.5 1019 S[552] 3010 312.5 1079 S[612] 2170 312.5 1139 S[672] 1330 312.5 1199 DMY 490 312.5 1020 S[553] 2996 187.5 1080 S[613] 2156 187.5 1140 S[673] 1316 187.5 1200 DMY 476 187.5

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 35 of 328 No. Pad Name X Y No. Pad Name X Y No. Pad Name X Y No. Pad Name X Y 1201 DMY 462 312.5 1261 S[745] -378 312.5 1321 S[805] -1218 312.5 1381 S[865] -2058 312.5 1202 DMY 448 187.5 1262 S[746] -392 187.5 1322 S[806] -1232 187.5 1382 S[866] -2072 187.5 1203 DMY 434 312.5 1263 S[747] -406 312.5 1323 S[807] -1246 312.5 1383 S[867] -2086 312.5 1204 DMY 420 187.5 1264 S[748] -420 187.5 1324 S[808] -1260 187.5 1384 S[868] -2100 187.5 1205 DMY 406 312.5 1265 S[749] -434 312.5 1325 S[809] -1274 312.5 1385 S[869] -2114 312.5 1206 DMY 392 187.5 1266 S[750] -448 187.5 1326 S[810] -1288 187.5 1386 S[870] -2128 187.5 1207 DMY 378 312.5 1267 S[751] -462 312.5 1327 S[811] -1302 312.5 1387 S[871] -2142 312.5 1208 DMY 364 187.5 1268 S[752] -476 187.5 1328 S[812] -1316 187.5 1388 S[872] -2156 187.5 1209 DMY 350 312.5 1269 S[753] -490 312.5 1329 S[813] -1330 312.5 1389 S[873] -2170 312.5 1210 DMY 336 187.5 1270 S[754] -504 187.5 1330 S[814] -1344 187.5 1390 S[874] -2184 187.5 1211 DMY 322 312.5 1271 S[755] -518 312.5 1331 S[815] -1358 312.5 1391 S[875] -2198 312.5 1212 DMY 308 187.5 1272 S[756] -532 187.5 1332 S[816] -1372 187.5 1392 S[876] -2212 187.5 1213 DMY 294 312.5 1273 S[757] -546 312.5 1333 S[817] -1386 312.5 1393 S[877] -2226 312.5 1214 DMY 280 187.5 1274 S[758] -560 187.5 1334 S[818] -1400 187.5 1394 S[878] -2240 187.5 1215 DMY 266 312.5 1275 S[759] -574 312.5 1335 S[819] -1414 312.5 1395 S[879] -2254 312.5 1216 DMY 252 187.5 1276 S[760] -588 187.5 1336 S[820] -1428 187.5 1396 S[880] -2268 187.5 1217 DMY 238 312.5 1277 S[761] -602 312.5 1337 S[821] -1442 312.5 1397 S[881] -2282 312.5 1218 DMY 224 187.5 1278 S[762] -616 187.5 1338 S[822] -1456 187.5 1398 S[882] -2296 187.5 1219 DMY 210 312.5 1279 S[763] -630 312.5 1339 S[823] -1470 312.5 1399 S[883] -2310 312.5 1220 DMY 196 187.5 1280 S[764] -644 187.5 1340 S[824] -1484 187.5 1400 S[884] -2324 187.5 1221 DMY 182 312.5 1281 S[765] -658 312.5 1341 S[825] -1498 312.5 1401 S[885] -2338 312.5 1222 DMY 168 187.5 1282 S[766] -672 187.5 1342 S[826] -1512 187.5 1402 S[886] -2352 187.5 1223 DMY 154 312.5 1283 S[767] -686 312.5 1343 S[827] -1526 312.5 1403 S[887] -2366 312.5 1224 DMY 140 187.5 1284 S[768] -700 187.5 1344 S[828] -1540 187.5 1404 S[888] -2380 187.5 1225 DMY 126 312.5 1285 S[769] -714 312.5 1345 S[829] -1554 312.5 1405 S[889] -2394 312.5 1226 DMY 112 187.5 1286 S[770] -728 187.5 1346 S[830] -1568 187.5 1406 S[890] -2408 187.5 1227 DMY 98 312.5 1287 S[771] -742 312.5 1347 S[831] -1582 312.5 1407 S[891] -2422 312.5 1228 DMY 84 187.5 1288 S[772] -756 187.5 1348 S[832] -1596 187.5 1408 S[892] -2436 187.5 1229 DMY 70 312.5 1289 S[773] -770 312.5 1349 S[833] -1610 312.5 1409 S[893] -2450 312.5 1230 DMY 56 187.5 1290 S[774] -784 187.5 1350 S[834] -1624 187.5 1410 S[894] -2464 187.5 1231 DMY 42 312.5 1291 S[775] -798 312.5 1351 S[835] -1638 312.5 1411 S[895] -2478 312.5 1232 DMY 28 187.5 1292 S[776] -812 187.5 1352 S[836] -1652 187.5 1412 S[896] -2492 187.5 1233 DMY 14 312.5 1293 S[777] -826 312.5 1353 S[837] -1666 312.5 1413 S[897] -2506 312.5 1234 DMY 0 187.5 1294 S[778] -840 187.5 1354 S[838] -1680 187.5 1414 S[898] -2520 187.5 1235 DMY_VSS -14 312.5 1295 S[779] -854 312.5 1355 S[839] -1694 312.5 1415 S[899] -2534 312.5 1236 DMY_VSS -28 187.5 1296 S[780] -868 187.5 1356 S[840] -1708 187.5 1416 S[900] -2548 187.5 1237 S[721] -42 312.5 1297 S[781] -882 312.5 1357 S[841] -1722 312.5 1417 S[901] -2562 312.5 1238 S[722] -56 187.5 1298 S[782] -896 187.5 1358 S[842] -1736 187.5 1418 S[902] -2576 187.5 1239 S[723] -70 312.5 1299 S[783] -910 312.5 1359 S[843] -1750 312.5 1419 S[903] -2590 312.5 1240 S[724] -84 187.5 1300 S[784] -924 187.5 1360 S[844] -1764 187.5 1420 S[904] -2604 187.5 1241 S[725] -98 312.5 1301 S[785] -938 312.5 1361 S[845] -1778 312.5 1421 S[905] -2618 312.5 1242 S[726] -112 187.5 1302 S[786] -952 187.5 1362 S[846] -1792 187.5 1422 S[906] -2632 187.5 1243 S[727] -126 312.5 1303 S[787] -966 312.5 1363 S[847] -1806 312.5 1423 S[907] -2646 312.5 1244 S[728] -140 187.5 1304 S[788] -980 187.5 1364 S[848] -1820 187.5 1424 S[908] -2660 187.5 1245 S[729] -154 312.5 1305 S[789] -994 312.5 1365 S[849] -1834 312.5 1425 S[909] -2674 312.5 1246 S[730] -168 187.5 1306 S[790] -1008 187.5 1366 S[850] -1848 187.5 1426 S[910] -2688 187.5 1247 S[731] -182 312.5 1307 S[791] -1022 312.5 1367 S[851] -1862 312.5 1427 S[911] -2702 312.5 1248 S[732] -196 187.5 1308 S[792] -1036 187.5 1368 S[852] -1876 187.5 1428 S[912] -2716 187.5 1249 S[733] -210 312.5 1309 S[793] -1050 312.5 1369 S[853] -1890 312.5 1429 S[913] -2730 312.5 1250 S[734] -224 187.5 1310 S[794] -1064 187.5 1370 S[854] -1904 187.5 1430 S[914] -2744 187.5 1251 S[735] -238 312.5 1311 S[795] -1078 312.5 1371 S[855] -1918 312.5 1431 S[915] -2758 312.5 1252 S[736] -252 187.5 1312 S[796] -1092 187.5 1372 S[856] -1932 187.5 1432 S[916] -2772 187.5 1253 S[737] -266 312.5 1313 S[797] -1106 312.5 1373 S[857] -1946 312.5 1433 S[917] -2786 312.5 1254 S[738] -280 187.5 1314 S[798] -1120 187.5 1374 S[858] -1960 187.5 1434 S[918] -2800 187.5 1255 S[739] -294 312.5 1315 S[799] -1134 312.5 1375 S[859] -1974 312.5 1435 S[919] -2814 312.5 1256 S[740] -308 187.5 1316 S[800] -1148 187.5 1376 S[860] -1988 187.5 1436 S[920] -2828 187.5 1257 S[741] -322 312.5 1317 S[801] -1162 312.5 1377 S[861] -2002 312.5 1437 S[921] -2842 312.5 1258 S[742] -336 187.5 1318 S[802] -1176 187.5 1378 S[862] -2016 187.5 1438 S[922] -2856 187.5 1259 S[743] -350 312.5 1319 S[803] -1190 312.5 1379 S[863] -2030 312.5 1439 S[923] -2870 312.5 1260 S[744] -364 187.5 1320 S[804] -1204 187.5 1380 S[864] -2044 187.5 1440 S[924] -2884 187.5

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 36 of 328 No. Pad Name X Y No. Pad Name X Y No. Pad Name X Y No. Pad Name X Y 1441 S[925] -2898 312.5 1501 S[985] -3738 312.5 1561 S[1045] -4578 312.5 1621 S[1105] -5418 312.5 1442 S[926] -2912 187.5 1502 S[986] -3752 187.5 1562 S[1046] -4592 187.5 1622 S[1106] -5432 187.5 1443 S[927] -2926 312.5 1503 S[987] -3766 312.5 1563 S[1047] -4606 312.5 1623 S[1107] -5446 312.5 1444 S[928] -2940 187.5 1504 S[988] -3780 187.5 1564 S[1048] -4620 187.5 1624 S[1108] -5460 187.5 1445 S[929] -2954 312.5 1505 S[989] -3794 312.5 1565 S[1049] -4634 312.5 1625 S[1109] -5474 312.5 1446 S[930] -2968 187.5 1506 S[990] -3808 187.5 1566 S[1050] -4648 187.5 1626 S[1110] -5488 187.5 1447 S[931] -2982 312.5 1507 S[991] -3822 312.5 1567 S[1051] -4662 312.5 1627 S[1111] -5502 312.5 1448 S[932] -2996 187.5 1508 S[992] -3836 187.5 1568 S[1052] -4676 187.5 1628 S[1112] -5516 187.5 1449 S[933] -3010 312.5 1509 S[993] -3850 312.5 1569 S[1053] -4690 312.5 1629 S[1113] -5530 312.5 1450 S[934] -3024 187.5 1510 S[994] -3864 187.5 1570 S[1054] -4704 187.5 1630 S[1114] -5544 187.5 1451 S[935] -3038 312.5 1511 S[995] -3878 312.5 1571 S[1055] -4718 312.5 1631 S[1115] -5558 312.5 1452 S[936] -3052 187.5 1512 S[996] -3892 187.5 1572 S[1056] -4732 187.5 1632 S[1116] -5572 187.5 1453 S[937] -3066 312.5 1513 S[997] -3906 312.5 1573 S[1057] -4746 312.5 1633 S[1117] -5586 312.5 1454 S[938] -3080 187.5 1514 S[998] -3920 187.5 1574 S[1058] -4760 187.5 1634 S[1118] -5600 187.5 1455 S[939] -3094 312.5 1515 S[999] -3934 312.5 1575 S[1059] -4774 312.5 1635 S[1119] -5614 312.5 1456 S[940] -3108 187.5 1516 S[1000] -3948 187.5 1576 S[1060] -4788 187.5 1636 S[1120] -5628 187.5 1457 S[941] -3122 312.5 1517 S[1001] -3962 312.5 1577 S[1061] -4802 312.5 1637 S[1121] -5642 312.5 1458 S[942] -3136 187.5 1518 S[1002] -3976 187.5 1578 S[1062] -4816 187.5 1638 S[1122] -5656 187.5 1459 S[943] -3150 312.5 1519 S[1003] -3990 312.5 1579 S[1063] -4830 312.5 1639 S[1123] -5670 312.5 1460 S[944] -3164 187.5 1520 S[1004] -4004 187.5 1580 S[1064] -4844 187.5 1640 S[1124] -5684 187.5 1461 S[945] -3178 312.5 1521 S[1005] -4018 312.5 1581 S[1065] -4858 312.5 1641 S[1125] -5698 312.5 1462 S[946] -3192 187.5 1522 S[1006] -4032 187.5 1582 S[1066] -4872 187.5 1642 S[1126] -5712 187.5 1463 S[947] -3206 312.5 1523 S[1007] -4046 312.5 1583 S[1067] -4886 312.5 1643 S[1127] -5726 312.5 1464 S[948] -3220 187.5 1524 S[1008] -4060 187.5 1584 S[1068] -4900 187.5 1644 S[1128] -5740 187.5 1465 S[949] -3234 312.5 1525 S[1009] -4074 312.5 1585 S[1069] -4914 312.5 1645 S[1129] -5754 312.5 1466 S[950] -3248 187.5 1526 S[1010] -4088 187.5 1586 S[1070] -4928 187.5 1646 S[1130] -5768 187.5 1467 S[951] -3262 312.5 1527 S[1011] -4102 312.5 1587 S[1071] -4942 312.5 1647 S[1131] -5782 312.5 1468 S[952] -3276 187.5 1528 S[1012] -4116 187.5 1588 S[1072] -4956 187.5 1648 S[1132] -5796 187.5 1469 S[953] -3290 312.5 1529 S[1013] -4130 312.5 1589 S[1073] -4970 312.5 1649 S[1133] -5810 312.5 1470 S[954] -3304 187.5 1530 S[1014] -4144 187.5 1590 S[1074] -4984 187.5 1650 S[1134] -5824 187.5 1471 S[955] -3318 312.5 1531 S[1015] -4158 312.5 1591 S[1075] -4998 312.5 1651 S[1135] -5838 312.5 1472 S[956] -3332 187.5 1532 S[1016] -4172 187.5 1592 S[1076] -5012 187.5 1652 S[1136] -5852 187.5 1473 S[957] -3346 312.5 1533 S[1017] -4186 312.5 1593 S[1077] -5026 312.5 1653 S[1137] -5866 312.5 1474 S[958] -3360 187.5 1534 S[1018] -4200 187.5 1594 S[1078] -5040 187.5 1654 S[1138] -5880 187.5 1475 S[959] -3374 312.5 1535 S[1019] -4214 312.5 1595 S[1079] -5054 312.5 1655 S[1139] -5894 312.5 1476 S[960] -3388 187.5 1536 S[1020] -4228 187.5 1596 S[1080] -5068 187.5 1656 S[1140] -5908 187.5 1477 S[961] -3402 312.5 1537 S[1021] -4242 312.5 1597 S[1081] -5082 312.5 1657 S[1141] -5922 312.5 1478 S[962] -3416 187.5 1538 S[1022] -4256 187.5 1598 S[1082] -5096 187.5 1658 S[1142] -5936 187.5 1479 S[963] -3430 312.5 1539 S[1023] -4270 312.5 1599 S[1083] -5110 312.5 1659 S[1143] -5950 312.5 1480 S[964] -3444 187.5 1540 S[1024] -4284 187.5 1600 S[1084] -5124 187.5 1660 S[1144] -5964 187.5 1481 S[965] -3458 312.5 1541 S[1025] -4298 312.5 1601 S[1085] -5138 312.5 1661 S[1145] -5978 312.5 1482 S[966] -3472 187.5 1542 S[1026] -4312 187.5 1602 S[1086] -5152 187.5 1662 S[1146] -5992 187.5 1483 S[967] -3486 312.5 1543 S[1027] -4326 312.5 1603 S[1087] -5166 312.5 1663 S[1147] -6006 312.5 1484 S[968] -3500 187.5 1544 S[1028] -4340 187.5 1604 S[1088] -5180 187.5 1664 S[1148] -6020 187.5 1485 S[969] -3514 312.5 1545 S[1029] -4354 312.5 1605 S[1089] -5194 312.5 1665 S[1149] -6034 312.5 1486 S[970] -3528 187.5 1546 S[1030] -4368 187.5 1606 S[1090] -5208 187.5 1666 S[1150] -6048 187.5 1487 S[971] -3542 312.5 1547 S[1031] -4382 312.5 1607 S[1091] -5222 312.5 1667 S[1151] -6062 312.5 1488 S[972] -3556 187.5 1548 S[1032] -4396 187.5 1608 S[1092] -5236 187.5 1668 S[1152] -6076 187.5 1489 S[973] -3570 312.5 1549 S[1033] -4410 312.5 1609 S[1093] -5250 312.5 1669 S[1153] -6090 312.5 1490 S[974] -3584 187.5 1550 S[1034] -4424 187.5 1610 S[1094] -5264 187.5 1670 S[1154] -6104 187.5 1491 S[975] -3598 312.5 1551 S[1035] -4438 312.5 1611 S[1095] -5278 312.5 1671 S[1155] -6118 312.5 1492 S[976] -3612 187.5 1552 S[1036] -4452 187.5 1612 S[1096] -5292 187.5 1672 S[1156] -6132 187.5 1493 S[977] -3626 312.5 1553 S[1037] -4466 312.5 1613 S[1097] -5306 312.5 1673 S[1157] -6146 312.5 1494 S[978] -3640 187.5 1554 S[1038] -4480 187.5 1614 S[1098] -5320 187.5 1674 S[1158] -6160 187.5 1495 S[979] -3654 312.5 1555 S[1039] -4494 312.5 1615 S[1099] -5334 312.5 1675 S[1159] -6174 312.5 1496 S[980] -3668 187.5 1556 S[1040] -4508 187.5 1616 S[1100] -5348 187.5 1676 S[1160] -6188 187.5 1497 S[981] -3682 312.5 1557 S[1041] -4522 312.5 1617 S[1101] -5362 312.5 1677 S[1161] -6202 312.5 1498 S[982] -3696 187.5 1558 S[1042] -4536 187.5 1618 S[1102] -5376 187.5 1678 S[1162] -6216 187.5 1499 S[983] -3710 312.5 1559 S[1043] -4550 312.5 1619 S[1103] -5390 312.5 1679 S[1163] -6230 312.5 1500 S[984] -3724 187.5 1560 S[1044] -4564 187.5 1620 S[1104] -5404 187.5 1680 S[1164] -6244 187.5

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 37 of 328 No. Pad Name X Y No. Pad Name X Y No. Pad Name X Y No. Pad Name X Y 1681 S[1165] -6258 312.5 1741 S[1225] -7098 312.5 1801 S[1285] -7938 312.5 1861 S[1345] -8778 312.5 1682 S[1166] -6272 187.5 1742 S[1226] -7112 187.5 1802 S[1286] -7952 187.5 1862 S[1346] -8792 187.5 1683 S[1167] -6286 312.5 1743 S[1227] -7126 312.5 1803 S[1287] -7966 312.5 1863 S[1347] -8806 312.5 1684 S[1168] -6300 187.5 1744 S[1228] -7140 187.5 1804 S[1288] -7980 187.5 1864 S[1348] -8820 187.5 1685 S[1169] -6314 312.5 1745 S[1229] -7154 312.5 1805 S[1289] -7994 312.5 1865 S[1349] -8834 312.5 1686 S[1170] -6328 187.5 1746 S[1230] -7168 187.5 1806 S[1290] -8008 187.5 1866 S[1350] -8848 187.5 1687 S[1171] -6342 312.5 1747 S[1231] -7182 312.5 1807 S[1291] -8022 312.5 1867 S[1351] -8862 312.5 1688 S[1172] -6356 187.5 1748 S[1232] -7196 187.5 1808 S[1292] -8036 187.5 1868 S[1352] -8876 187.5 1689 S[1173] -6370 312.5 1749 S[1233] -7210 312.5 1809 S[1293] -8050 312.5 1869 S[1353] -8890 312.5 1690 S[1174] -6384 187.5 1750 S[1234] -7224 187.5 1810 S[1294] -8064 187.5 1870 S[1354] -8904 187.5 1691 S[1175] -6398 312.5 1751 S[1235] -7238 312.5 1811 S[1295] -8078 312.5 1871 S[1355] -8918 312.5 1692 S[1176] -6412 187.5 1752 S[1236] -7252 187.5 1812 S[1296] -8092 187.5 1872 S[1356] -8932 187.5 1693 S[1177] -6426 312.5 1753 S[1237] -7266 312.5 1813 S[1297] -8106 312.5 1873 S[1357] -8946 312.5 1694 S[1178] -6440 187.5 1754 S[1238] -7280 187.5 1814 S[1298] -8120 187.5 1874 S[1358] -8960 187.5 1695 S[1179] -6454 312.5 1755 S[1239] -7294 312.5 1815 S[1299] -8134 312.5 1875 S[1359] -8974 312.5 1696 S[1180] -6468 187.5 1756 S[1240] -7308 187.5 1816 S[1300] -8148 187.5 1876 S[1360] -8988 187.5 1697 S[1181] -6482 312.5 1757 S[1241] -7322 312.5 1817 S[1301] -8162 312.5 1877 S[1361] -9002 312.5 1698 S[1182] -6496 187.5 1758 S[1242] -7336 187.5 1818 S[1302] -8176 187.5 1878 S[1362] -9016 187.5 1699 S[1183] -6510 312.5 1759 S[1243] -7350 312.5 1819 S[1303] -8190 312.5 1879 S[1363] -9030 312.5 1700 S[1184] -6524 187.5 1760 S[1244] -7364 187.5 1820 S[1304] -8204 187.5 1880 S[1364] -9044 187.5 1701 S[1185] -6538 312.5 1761 S[1245] -7378 312.5 1821 S[1305] -8218 312.5 1881 S[1365] -9058 312.5 1702 S[1186] -6552 187.5 1762 S[1246] -7392 187.5 1822 S[1306] -8232 187.5 1882 S[1366] -9072 187.5 1703 S[1187] -6566 312.5 1763 S[1247] -7406 312.5 1823 S[1307] -8246 312.5 1883 S[1367] -9086 312.5 1704 S[1188] -6580 187.5 1764 S[1248] -7420 187.5 1824 S[1308] -8260 187.5 1884 S[1368] -9100 187.5 1705 S[1189] -6594 312.5 1765 S[1249] -7434 312.5 1825 S[1309] -8274 312.5 1885 S[1369] -9114 312.5 1706 S[1190] -6608 187.5 1766 S[1250] -7448 187.5 1826 S[1310] -8288 187.5 1886 S[1370] -9128 187.5 1707 S[1191] -6622 312.5 1767 S[1251] -7462 312.5 1827 S[1311] -8302 312.5 1887 S[1371] -9142 312.5 1708 S[1192] -6636 187.5 1768 S[1252] -7476 187.5 1828 S[1312] -8316 187.5 1888 S[1372] -9156 187.5 1709 S[1193] -6650 312.5 1769 S[1253] -7490 312.5 1829 S[1313] -8330 312.5 1889 S[1373] -9170 312.5 1710 S[1194] -6664 187.5 1770 S[1254] -7504 187.5 1830 S[1314] -8344 187.5 1890 S[1374] -9184 187.5 1711 S[1195] -6678 312.5 1771 S[1255] -7518 312.5 1831 S[1315] -8358 312.5 1891 S[1375] -9198 312.5 1712 S[1196] -6692 187.5 1772 S[1256] -7532 187.5 1832 S[1316] -8372 187.5 1892 S[1376] -9212 187.5 1713 S[1197] -6706 312.5 1773 S[1257] -7546 312.5 1833 S[1317] -8386 312.5 1893 S[1377] -9226 312.5 1714 S[1198] -6720 187.5 1774 S[1258] -7560 187.5 1834 S[1318] -8400 187.5 1894 S[1378] -9240 187.5 1715 S[1199] -6734 312.5 1775 S[1259] -7574 312.5 1835 S[1319] -8414 312.5 1895 S[1379] -9254 312.5 1716 S[1200] -6748 187.5 1776 S[1260] -7588 187.5 1836 S[1320] -8428 187.5 1896 S[1380] -9268 187.5 1717 S[1201] -6762 312.5 1777 S[1261] -7602 312.5 1837 S[1321] -8442 312.5 1897 S[1381] -9282 312.5 1718 S[1202] -6776 187.5 1778 S[1262] -7616 187.5 1838 S[1322] -8456 187.5 1898 S[1382] -9296 187.5 1719 S[1203] -6790 312.5 1779 S[1263] -7630 312.5 1839 S[1323] -8470 312.5 1899 S[1383] -9310 312.5 1720 S[1204] -6804 187.5 1780 S[1264] -7644 187.5 1840 S[1324] -8484 187.5 1900 S[1384] -9324 187.5 1721 S[1205] -6818 312.5 1781 S[1265] -7658 312.5 1841 S[1325] -8498 312.5 1901 S[1385] -9338 312.5 1722 S[1206] -6832 187.5 1782 S[1266] -7672 187.5 1842 S[1326] -8512 187.5 1902 S[1386] -9352 187.5 1723 S[1207] -6846 312.5 1783 S[1267] -7686 312.5 1843 S[1327] -8526 312.5 1903 S[1387] -9366 312.5 1724 S[1208] -6860 187.5 1784 S[1268] -7700 187.5 1844 S[1328] -8540 187.5 1904 S[1388] -9380 187.5 1725 S[1209] -6874 312.5 1785 S[1269] -7714 312.5 1845 S[1329] -8554 312.5 1905 S[1389] -9394 312.5 1726 S[1210] -6888 187.5 1786 S[1270] -7728 187.5 1846 S[1330] -8568 187.5 1906 S[1390] -9408 187.5 1727 S[1211] -6902 312.5 1787 S[1271] -7742 312.5 1847 S[1331] -8582 312.5 1907 S[1391] -9422 312.5 1728 S[1212] -6916 187.5 1788 S[1272] -7756 187.5 1848 S[1332] -8596 187.5 1908 S[1392] -9436 187.5 1729 S[1213] -6930 312.5 1789 S[1273] -7770 312.5 1849 S[1333] -8610 312.5 1909 S[1393] -9450 312.5 1730 S[1214] -6944 187.5 1790 S[1274] -7784 187.5 1850 S[1334] -8624 187.5 1910 S[1394] -9464 187.5 1731 S[1215] -6958 312.5 1791 S[1275] -7798 312.5 1851 S[1335] -8638 312.5 1911 S[1395] -9478 312.5 1732 S[1216] -6972 187.5 1792 S[1276] -7812 187.5 1852 S[1336] -8652 187.5 1912 S[1396] -9492 187.5 1733 S[1217] -6986 312.5 1793 S[1277] -7826 312.5 1853 S[1337] -8666 312.5 1913 S[1397] -9506 312.5 1734 S[1218] -7000 187.5 1794 S[1278] -7840 187.5 1854 S[1338] -8680 187.5 1914 S[1398] -9520 187.5 1735 S[1219] -7014 312.5 1795 S[1279] -7854 312.5 1855 S[1339] -8694 312.5 1915 S[1399] -9534 312.5 1736 S[1220] -7028 187.5 1796 S[1280] -7868 187.5 1856 S[1340] -8708 187.5 1916 S[1400] -9548 187.5 1737 S[1221] -7042 312.5 1797 S[1281] -7882 312.5 1857 S[1341] -8722 312.5 1917 S[1401] -9562 312.5 1738 S[1222] -7056 187.5 1798 S[1282] -7896 187.5 1858 S[1342] -8736 187.5 1918 S[1402] -9576 187.5 1739 S[1223] -7070 312.5 1799 S[1283] -7910 312.5 1859 S[1343] -8750 312.5 1919 S[1403] -9590 312.5 1740 S[1224] -7084 187.5 1800 S[1284] -7924 187.5 1860 S[1344] -8764 187.5 1920 S[1404] -9604 187.5

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 38 of 328 No. Pad Name X Y No. Pad Name X Y No. Pad Name X Y Pad Name X Y 1921 S[1405] -9618 312.5 1981 DMY -10514 312.5 2041 GOUT[28] -11354 312.5 ALMARK_R_T 11870 305 1922 S[1406] -9632 187.5 1982 DMY -10528 187.5 2042 GOUT[29] -11368 187.5 ALMARK_L_T -11870 305 1923 S[1407] -9646 312.5 1983 DMY -10542 312.5 2043 GOUT[29] -11382 312.5 1924 S[1408] -9660 187.5 1984 DMY -10556 187.5 2044 GOUT[30] -11396 187.5 1925 S[1409] -9674 312.5 1985 DMY -10570 312.5 2045 GOUT[30] -11410 312.5 1926 S[1410] -9688 187.5 1986 DMY - 10584 187.5 2046 GOUT_VGLO -11424 187.5 1927 S[1411] -9702 312.5 1987 DMY - 10598 312.5 2047 GOUT_VGLO -11438 312.5 1928 S[1412] -9716 187.5 1988 DMY - 10612 187.5 2048 GOUT_VGLO -11452 187.5 1929 S[1413] -9730 312.5 1989 DMY -10626 312.5 2049 VGH_REG -11466 312.5 1930 S[1414] -9744 187.5 1990 DMY -10640 187.5 2050 VGH_REG -11480 187.5 1931 S[1415] -9758 312.5 1991 DMY -10654 312.5 2051 VGH_REG -11494 312.5 1932 S[1416] -9772 187.5 1992 DMY -10668 187.5 2052 LVGL -11508 187.5 1933 S[1417] -9786 312.5 1993 DMY -10682 312.5 2053 LVGL -11522 312.5 1934 S[1418] -9800 187.5 1994 DMY -10696 187.5 2054 LVGL -11536 187.5 1935 S[1419] -9814 312.5 1995 DMY -10710 312.5 2055 GOUT[31] -11550 312.5 1936 S[1420] -9828 187.5 1996 DMY -10724 187.5 2056 GOUT[31] -11564 187.5 1937 S[1421] -9842 312.5 1997 DMY -10738 312.5 2057 GOUT[32] -11578 312.5 1938 S[1422] -9856 187.5 1998 DMY -10752 187.5 2058 GOUT[32] -11592 187.5 1939 S[1423] -9870 312.5 1999 DMY - 10766 312.5 2059 GOUT_VGLO -11606 312.5 1940 S[1424] -9884 187.5 2000 DMY - 10780 187.5 2060 GOUT_VGLO -11620 187.5 1941 S[1425] -9898 312.5 2001 DMY - 10794 312.5 2061 GOUT_VGLO -11634 312.5 1942 S[1426] -9912 187.5 2002 DMY - 10808 187.5 2062 GOUT_VGHO -11648 187.5 1943 S[1427] -9926 312.5 2003 DMY - 10822 312.5 2063 GOUT_VGHO -11662 312.5 1944 S[1428] -9940 187.5 2004 DMY - 10836 187.5 2064 GOUT_VGHO -11676 187.5 1945 S[1429] -9954 312.5 2005 DMY -10850 312.5 2065 PADA4 -11690 312.5 1946 S[1430] -9968 187.5 2006 DMY -10864 187.5 2066 PADB4 -11704 187.5 1947 S[1431] -9982 312.5 2007 DMY -10878 312.5 2067 DMY_VSS -11718 312.5 1948 S[1432] -9996 187.5 2008 DMY -10892 187.5 2068 DMY_VSS -11732 187.5 1949 S[1433] -10010 312.5 2009 DMY -10906 312.5 2069 DMY_VSS -11760 312.5 1950 S[1434] -10024 187.5 2010 DMY -10920 187.5 1951 S[1435] -10038 312.5 2011 DMY -10934 312.5 1952 S[1436] -10052 187.5 2012 DMY -10948 187.5 1953 S[1437] -10066 312.5 2013 DMY -10962 312.5 1954 S[1438] -10080 187.5 2014 DMY -10976 187.5 1955 S[1439] -10094 312.5 2015 DMY -10990 312.5 1956 S[1440] -10108 187.5 2016 DMY_VSS -11004 187.5 1957 S[1441] -10122 312.5 2017 DMY_VSS -11018 312.5 1958 DMY_VSS -10136 187.5 2018 GOUT[17] -11032 187.5 1959 DMY_VSS -10150 312.5 2019 GOUT[17] -11046 312.5 1960 GOUT_VGLO -10220 187.5 2020 GOUT[18] -11060 187.5 1961 GOUT_VGLO -10234 312.5 2021 GOUT[18] -11074 312.5 1962 GOUT_VGLO -10248 187.5 2022 GOUT[19] -11088 187.5 1963 GOUT_VGLO -10262 312.5 2023 GOUT[19] -11102 312.5 1964 GOUT_VGLO -10276 187.5 2024 GOUT[20] -11116 187.5 1965 GOUT_VGLO -10290 312.5 2025 GOUT[20] -11130 312.5 1966 DMY_VGH -10304 187.5 2026 GOUT[21] -11144 187.5 1967 DMY_VGH -10318 312.5 2027 GOUT[21] -11158 312.5 1968 GOUT_VGHO -10332 187.5 2028 GOUT[22] -11172 187.5 1969 GOUT_VGHO -10346 312.5 2029 GOUT[22] -11186 312.5 1970 GOUT_VGHO -10360 187.5 2030 GOUT[23] -11200 187.5 1971 GOUT_VGHO -10374 312.5 2031 GOUT[23] -11214 312.5 1972 GOUT_VGHO -10388 187.5 2032 GOUT[24] -11228 187.5 1973 GOUT_VGHO -10402 312.5 2033 GOUT[24] -11242 312.5 1974 DMY_VSS -10416 187.5 2034 GOUT[25] -11256 187.5 1975 DMY_VSS -10430 312.5 2035 GOUT[25] -11270 312.5 1976 DMY -10444 187.5 2036 GOUT[26] -11284 187.5 1977 DMY -10458 312.5 2037 GOUT[26] -11298 312.5 1978 DMY -10472 187.5 2038 GOUT[27] -11312 187.5 1979 DMY -10486 312.5 2039 GOUT[27] -11326 312.5 1980 DMY -10500 187.5 2040 GOUT[28] -11340 187.5

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 39 of 328 3. System Interface 3.1. SPI Interface The following is selection of interface decided by the IM [3:0] pins. See Table 8. Table 8 SPI Interface IM3 IM2 IM1 IM0 SPI Mode CSX SCL Function 0 0 1 1 3-line serial interface “L” Read/Write command, parameter. 1 0 0 1 “L” 1 0 1 0 “L” 1 0 1 1 “L” The ILI9806E uses a 3-line 9-bit serial interfac e for communication between the host and the ILI9806E. The 3-line serial interface consists of the chip enable input ( C S X ) , t h e s e r i a l c l o c k i n p u t ( S C L ) a n d s e r i a l d a t a Input/Output (SDA). If the data bus (DB [23:0]) is not used for the data transfer of DPI interface, the unused pins are unaffected. The Serial clock (SCL) is used only for the interface with the MPU, so it can be stopped when no communication is necessary. 3.1.1. Write Cycle Sequence In write mode of the interface, the host writes commands and data to the ILI9806E. The 3-line serial data packet contains a D/C (data/command) select bit and a transmission byte. If the D/C bit is “low”, the transmission byte is interpreted as a command byte. If the D/C bit is “high”, the transmission byte is stored in the command register as a parameter data. Any instruction can be sent in any order to the ILI9806E and the MSB is transmitted first. The serial interface is initialized when the CSX status is high. In this state, SCL clock pulse and SDI data are ineffective. A falling edge on CSX enables the serial interface and indicates the start of data transmission. See the detail of data format for 3-line serial interface. Figure 2 DBI data format

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 41 of 328 3.1.2. Read Cycle Sequence In read mode of the interface, the host reads the r egister value from the ILI9806E. The host sends a command (Read ID or register command), then a byte is (bytes are) transmitted in the opposite direction. The ILI9806E samples the SDI (input data) at the rising edges of the SC L (serial clock), and shifts SDO (output data) at the falling edges of the SCL (serial clock). The re ad mode has three types of transmitted command data (8-/24-/32-bit) according command code. MPUDriver Figure 4 SPI read cycle sequence (SCL rising edge example)

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 43 of 328 If a multiple parameter command is sent and a break occurs when a new command is sent before all the parameters are transferred, then the parameters that were successfu lly sent are stored and the remaining parameters of that command remain at the previous value. Figure 7 Data Transfer Break -Case 2

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 44 of 328 3.3. Data Transfer Pause It will be possible when transferring a Command, Multiple Parameter Data to invoke a pause in the data transmission. If the Chip Select pin (CSX) is released after Multiple Parameter Data has been completed, then the ILI9806E will wait and continue Parameter Data Tran smission from the point where it was paused. If the Chip Select pin is released after a whole byte of a command has been completely transmitted, then the display module will receive either the command’s parameters (if appropriate) or a new command when the Chip Select Line is next enabled as shown below. Figure 8 Data Transfer Pause

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 45 of 328 3.3.1. Serial Interface Pause Figure 9 SPI data transfer pause (SCL rising edge example) This applies to the following 4 conditions: 1) Command-Pause-Command 2) Command-Pause-Parameter 3) Parameter-Pause-Command 4) Parameter-Pause-Parameter

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 46 of 328 3.4. DPI (RGB) Interface The DPI interface displaying moving pictures is selected by the ILI9806E. 3.4.1. DPI Interface Selection The DPI interface is operated with VS, HS, DE PCLK, DB [23:0] lines. It supports several pixel formats that can be selected by DPI [2:0] bits in “Pixel Format Set (R3Ah)” of Page 0 command. The selection of a given interface is defined by DPI [2:0] as show in the Table 9 and Figure 10 below. Table 9 DPI (RGB) Interface Selection DPI [2:0] DPI (RGB) Interface Mode Used Pins 1 0 1 16-bit RGB interface VS, HS, DE, PCLK,DB [20:16] , DB [13:8], DB [4:0] 1 1 0 18-bit RGB interface VS, HS, DE, PCLK, DB [21:16] , DB [13:8], DB [5:0] 1 1 1 24-bit RGB interface VS, HS, DE, PCLK, DB [23:0] Others Setting prohibited Figure 10 DPI (RGB) Interface 16/18/24-bit pixel format selection

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 47 of 328 The Pixel clock (PCLK) is running all the time without stopping, it is used for entering VS, HS, DE and DB [23:0] states when there is a rising edge of the PCLK. The PCLK can not be used as the internal clock for other functions of the display module. Vertical synchronization (Vsync) is used to tell when t here is received a new frame of the display. This is low enable and its state is read to the display module by a rising edge of the PCLK signal. Horizontal synchronization (Hsync) is used to tell when t here is received a new line of the frame. This is low enable and its state is read to the display module by a rising edge of the PCLK signal. DE (Data Enable) is used to tell when there is re ceived RGB information that should be transferred on the display. This is a high enable and its state is read to the display module by a rising edge of the PCLK signal. DB [23:0] are used to tell what is the information of the image that is transferred on the display (When DE= ’0’ (low) and there is a rising edge of PCLK). DB [23:0] can be ‘0’ (low) or ‘1’ (high). These lines are read by a rising edge of the PCLK signal. HLW HBP HACT HFP VLW VFP (VACT + HACT) – Period when valid display data are transferred from host to display module (VLW + VBP) - Vertical interval when no valid display data is transferred from host to display (HLW + HBP) – Horizontal interval when no valid display data is sent from host to display VFP -- Vertical interval when no valid display data is transferred from host to display VBP VACT HS VS Figure 11 General DPI timing diagram

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 48 of 328 3.4.2. DPI Interface Timing The timing chart of 24-/18-/16-bit DPI (RGB) interface mode is illustrated in Figure 12. HSYNC VSYNC DCK ENABLE Vertical back porch VLW 1 frame Vertical front porch Valid data HLW 1H (1 Line time) DTST HSYNC DCK ENABLE DB[23:0] VLW : VSYNC Low pulse Width HLW : HSYNC Low pulse Width DTST : Data Transfer Startup Time Pn : pixel 1, pixel 2…, pixel n. P1 P2 P3 P4 P5 P6 ... Pn VBP HBP Horizontal back porch Horizontal front porch Invalid dataInvalid data Zoom in HFP HLW HBP VLW VLWVBP VACT HACT VBP Parameter Symbols Condition Min. Typ. Max. Units Frame Rate FR 54 66 fps Horizontal Low Pulse width HLW 1 - DOTCLK Horizontal Back Porch HBP 2 126 DOTCLK Horizontal Address HACT 480 DOTCLK Horizontal Front Porch HFP 2 - DOTCLK Vertical Low Pulse width VLW 1 126 Line Vertical Back Porch VBP 1 126 Line Vertical Address VACT 864 Line Vertical Front Porch VFP 1 255 Line Data Clock DCLK 16.6 35.7 MHz F i g u r e 1 2 D P I I n t e r f a c e T i m i n g d i a g r a mNote1,Note2 Note1. HLW+HBP+HFP >= 4.5us. Note2. VSPL=’0’, HSPL=’0’, DPL=’0’ and EPL=’0’ of “(Interface Mode Control 21h of the Page 1)” command.

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 49 of 328 3.5. DSI system interface 3.5.1. General Description The MIPI DSI is enabled or disabled by external IM[3:0] pin. Figure 13 DSI system interface diagram IM3 IM2 IM1 IM0 MPU Interface Data Pin in Use 0 1 0 1 DSI interface HS_CP, HS_CN HS_D0P, HS_D0N HS_D1P, HS_D1N 0 1 1 1 DSI+SPI interface HS_CP, HS_CN, HS_D0P, HS_D0N, HS_D1P, HS_D1N, SDI,SDO, SCL(rising edge), CSX 1 1 1 1 DSI+SPI interface HS_CP, HS_CN, HS_D0P, HS_D0N, HS_D1P, HS_D1N, SDI,SDO, SCL(falling edge), CSX The communication is separated into two different levels between the MPU and the display module:

• Low level communication is done on the interface level.
• High level communication is done on the packet level.

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 50 of 328 3.5.2. Interface Level Communication 3.5.3. General The display module uses data and clock lane differential pairs for DSI (DSI-2M). Both differential lane pairs can be driven Low Power (LP) or High Speed (HS) mode. Low Power mode means that each line of the different ial pair is used in single end mode and a differential receiver is disable (A termination resistor of the receiver is disable) and it can be driven into a low power mode. High Speed mode means that differential pairs (The termination resistor of the receiver is enable) are not used in the single end mode. There are used different modes and protocols in each mode when there are wanted to transfer information from the MPU to the display module and vice versa. The State Codes of the High Speed (HS) and Low Power (LP) lane pair are defined below. Table 10 High Speed and Low-Power Lane Pair State Codes Lane Pair State Code Line DC Voltage Levels High Speed (HS) Low Power DATA_P DATA_N Burst Mode Control Mode Escape Mode HS-0 Low (HS) High (HS) Differential – 0 Note 1 Note 1 HS-1 High (HS) Low (HS) Differential – 1 Note 1 Note 1 LP-00 Low (LP) Low (LP) Not Defined Bridge Space LP-01 Low (LP) High (LP) Not Defined HS – Request Mark - 0 LP-10 High (LP) Low (LP) Not Defined LP - Request Mark - 1 LP-11 High (LP) High (LP) Not Defined Stop Note 2 Note 1 Low-Power Receivers (LP-Rx) of the lane pair are checking the LP-00 state code, when the Lane Pair is in the High Speed (HS) mode. Note 2 If Low-Power Receivers (LP-Rx) of the lane pair recognizes LP-11 state code, the lane pair returns to LP-11 of the Control Mode. Note 3 n = 0 and 1 (D1+/- lanes only for HS-0 and HS-1)

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 51 of 328 3.5.4. DSI-CLK Lanes DSI-CLK+/- lanes can be driven into three different power modes: Low Power Mode (LPM), Ultra Low Power Mode (ULPM) or High Speed Clock Mode (HSCM). Clock lanes are in a single end mode (LP = Low Power) when there is entering or leaving Low Power Mode (LPM) or Ultra Low Power Mode (ULPM). Clock lanes are in the single end mode (LP = Low Power) when there is entering in or leaving out High Speed Clock Mode (HSCM). These entering and leaving protocols are using clock lane s in the single end mode to generate an entering or leaving sequences. The principal flow chart of the different clock lanes power modes is illustrated below. Figure 14 Clock Lanes Power Modes

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 53 of 328 All three mode changes are illustrated a flow chart below. Figure 17 All Three Mode Changes to LPM on the Flow Chart

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 56 of 328 The high speed clock (DSI-CLK+/-) is started before high s peed data is sent via DSI- D1+/- or DSI-D0+/- lanes. The high speed clock continues clocking after the high speed data sending has been stopped. The burst of the high speed clock consists of:

• Even number of transitions
• Start state is HS-0
• End state is HS-0 LP-11 LP-01 LP-00 Time LPM LP-11 CLK+ CLK- HSCM HS-0 LPM LP-11 Termination Resistor is disable Termination Resistor is enable HS-0 LP-11 Time LP-11 LP-11 Data lanes in High Speed Mode TLPX THS-PREPARE Preparation from Low Power Mode to High Speed Mode (TSOT=Start of the Transmission) THS-SETTLE Low Power Mode Disable Rx Line Termination High Speed Mode, Enable Rx Line Termination Tx Synchronization Rx SynchronizedLP-11 LP-01 LP-00 HS-0 000111 1 0 LP-11TEOT High Speed Data Transmission THS-EXIT THS-SKIP THS-TRAIL HS-0 or HS-1 High Speed Mode, Enable Rx Line Termination Low Power Mode, Disable Rx Line Termination Note Dn+ Dn- CLK+ CLK- Dn+ Dn- CLK+ CLK- Dn+ Dn_ The last load bit CLK+ CLK- CLK+ CLK- CLK+ CLK- Dn+ Dn- n=0 and 1 Dn+ Dn- n=0 and 1 Dn+ Dn- n=0 and 1 Figure 22 High Speed Clock BurstNote Note 1. If the last load bit is HS-0, the transmitter changes from HS-0 to HS-1. 2. If the last load bit is HS-1, the transmitter changes from HS-1 to HS-0.

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 57 of 328 3.5.8. DSI-D1 and DSI-D0 Data Lanes 3.5.9. General DSI-D1+/- and DSI-D0+/- Data Lanes can be driven in different modes which are:

• Escape Mode (Only DSI-D0+/- data lanes are used)
• High-Speed Data Transmission (DSI-D1+/- and DSI-D0+/- data lanes are used)
• Bus Turnaround Request (Only DSI-D0+/- data lanes are used) These modes and their entering codes are defined on the following table. Table 11 Entering and Leaving SequencesNote Mode Entering Mode Sequence Leaving Mode Sequence Escape Mode LP-11 Î LP-10 Î LP-00 Î LP-01 Î LP-00 LP-00 Î LP-10 Î LP-11 (Mark-1) High-Speed Data Transmission LP-11 Î LP-01 Î LP-00 Î HS-0 (HS-0 or HS-1 ) Î LP-11 Bus Turnaround Request LP-11 Î LP-10 Î LP-00 Î LP-10 Î LP-00 Hi-Z Note 1. DSI-D1+/- and DSI-D0+/- data lanes are used. 2. More information on chapter “Bus Turnaround ”.

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 58 of 328 3.5.10. Escape Modes DSI-D0+/- data lanes can be used in different Escape Modes when data lanes are in Low Power (LP) mode. These Escape Modes are used to:

• Send “Low-Power Data Transmission” (LPDT) e.g. from the MPU to the display module,
• Drive data lanes to “Ultra-Low Power State” (ULPS),
• Indicate “Remote Application Reset” (RAR), which is resetting the display module,
• Indicate “Acknowledge” (ACK), which is used for a non-error event from the display module to the MPU. The basic sequence of the Escape Mode is as follow
• Start: LP-11
• Escape Mode Entry (EME): LP-11 =>LP-10 =>LP-00 =>LP-01 =>LP-00
• Escape Command (EC), which is coded, when one of the data lanes is changing from low-to-high-to-low then this changed data lane is presenting a value of the current data bit (DSI-D0+ = 1, DSI-D0-= 0) e.g. when DSI-D0- is changing from low-to-high-to-low, the receiver is latching a data bit, which value is logical 0. The receiver is using this low-to-high-to-low transition for its internal clock.
• A load if it is needed
• Exit Escape (Mark-1) LP-00 =>LP-10 =>LP-11
• End: LP-11 This basic construction is illustrated below: Figure 23 General Escape Mode Sequence

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 59 of 328 There are a total of eight Escape Commands (EC) divided into two types, Modes and Triggers, see Table 12: Escape Commands. An example of a Mode type Escape Command is ‘Ultra-Low Power Mode’ where the MPU instructs the display module to enter it’s Ultra-Low Power Mode. Escape commands are defined on the next table. Table 12 Escape CommandsNote Escape command Command Type Mode / Trigger Entry command Pattern (First Bit Î Last Bit Transmitted) Dn D0 Low-Power Data Transmission Mode 1110 0001 b - X Ultra-Low Power Mode Mode 0001 1110 b X X Undefined-1, Note 1 Mode 1001 1111 b - - Undefined-2, Note 1 Mode 1101 1110 b - - Remote Application Reset Trigger 0110 0010 b - X Acknowledge Trigger 0010 0001 b - X Uknown-5, Note 1 Trigger 1010 0000 b - - Note 1. This Escape command support has not been implemented on the display module. 2. n = 1 3. x = Supported 4. - = Not Supported

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 61 of 328 3.5.12. Ultra-Low Po wer State (ULPS) The MPU can force data lanes in Ultra-Low Power State (ULPS) mode when data lanes are entering in Escape Mode. The Ultra-Low Power State (ULPS) is using a following sequence:

• Start: LP-11
• Escape Mode Entry (EME): LP-11 =>LP-10 =>LP-00 =>LP-01 =>LP-00
• Ultra-Low Power State (ULPS) command in Escape Mode: 0001 1110 (First to Last bit)
• Ultra-Low Power State (ULPS) when the MPU is keeping data lanes low
• Mark-1: LP-00 =>LP-10 =>LP-11
• End: LP-11 This sequence is illustrated for reference purposes below: Escape Mode Entry (EME) LP-11 LP-10 LP-00 LP-00 LP-01 Mark-1 LP-00 LP-10 LP-11 LP-11 1 1 10000 1L P - 1 1 Ultra-Low Power Status (ULPS) Escape Mode Entry (EME) Ultra-Low Power State Mark-1 Time D0+ D0- D0+ D0- Figure 26 Ultra-Low Power State (ULPS)

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 62 of 328 3.5.13. Remote Application Reset (RAR) The MPU can inform to the display module that it should be reset in Remote Application Reset (RAR) trigger when data lanes are entering in Escape Mode. The Remote Application Reset (RAR) is using a following sequence:

• Start: LP-11
• Escape Mode Entry (EME): LP-11 =>LP-10 =>LP-00 =>LP-01 =>LP-00
• Remote Application Reset (RAR) command in Escape Mode: 0110 0010 (First to Last bit)
• Mark-1: LP-00 =>LP-10 =>LP-11
• End: LP-11 This sequence is illustrated for reference purposes below: Escape Mode Entry (EME) LP-11 LP-10 LP-00 LP-00 LP-01 Mark-1 LP-00 LP-10 LP-11 LP-11 1 10 000 1L P - 1 1 Remote Application Reset (RAR) Escape Mode Entry (EME) Mark-1 Time D0+ D0- D0+ D0- Figure 27 Remote Application Reset (RAR)

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 63 of 328 3.5.14. Acknowledge (ACK) The display module can inform to the MPU when an error has not recognized on it by Acknowledge (ACK). The display module is sending the Acknowledge (ACK) what is using a following sequence:

• Start: LP-11
• Escape Mode Entry (EME): LP-11 =>LP-10 =>LP-00 =>LP-01 =>LP-00
• Acknowledge (ACK) command in Escape Mode: 0010 0001 (First to Last bit)
• Mark-1: LP-00 =>LP-10 =>LP-11
• End: LP-11 This sequence is illustrated for reference purposes below: Escape Mode Entry (EME) LP-11 LP-10 LP-00 LP-00 LP-01 Mark-1 LP-00 LP-10 LP-11 LP-11 1 00 001 0L P - 1 1 Acknowledge (ACK) Escape Mode Entry (EME) Mark-1 Time D0+ D0- D0+ D0- Figure 28 Acknowledge (ACK)

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 64 of 328 3.5.15. High-Speed Data Transmission (HSDT) 3.5.16. Entering High-Speed Data Transmission (TSOT of HSDT) The display module is entering High-Speed Data Transmission (HSDT) when Clock lanes DSI-CLK+/- have already been entered in the High-Speed Clock Mode (HSCM) by the MPU. See more information on chapter “High-Speed Clock Mode (HSCM)”. Data lanes DSI-D1+/- and DSI-D0+/- of the display module are entering (TSOT) in the High-Speed Data Transmission (HSDT) as follows

• Start: LP-11
• HS-Request: LP-01
• HS-Settle: LP-00 => HS-0 (Rx: Lane Termination Enable)
• Rx Synchronization: 011101 (Tx (= MPU) Synchronization: 0001 1101)
• End: High-Speed Data Transmission (HSDT) – Ready to receive High-Speed Data Load This same entering High-Speed Data Transmission (TSOT of HSDT) sequence is illustrated below TLPX THS-PREPARE Preparation from Low Power Mode to High Speed Mode (TSOT=Start of the Transmission) THS-SETTLE Low Power Mode Disable Rx Line Termination High Speed Mode, Enable Rx Line Termination Tx Synchronization Rx SynchronizedLP-11 LP-01 LP-00 HS-0 000111 1 0 CLK+ CLK- Dn+ Dn- CLK+ CLK- Dn+ Dn- HSDT n=0 and 1 Figure 29 Entering High-Speed Data Transmission (TSOT of HSDT)

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 65 of 328 3.5.17. Leaving High-Speed Data Transmission (TEOT of HSDT) The display module is leaving the High-Speed Data Transmission (TEOT of HSDT) when Clock lanes DSICLK+/- are in the High-Speed Clock Mode (HSCM) by the MPU and this HSCM is kept until data lanes DSI-D1+/- and DSI-D0+/- are in LP-11 mode. See more information on chapter “High-Speed Clock Mode (HSCM)”. Data lanes DSI-D1+/- and DSI-D0+/- of the display module are leaving from the High-Speed Data Transmission (TEOT of HSDT) as follows

• Start: High-Speed Data Transmission (HSDT)
• Stops High-Speed Data Transmission o MPU changes to HS-1, if the last load bit is HS-0 o MPU changes to HS-0, if the last load bit is HS-1
• End: LP-11 (Rx: Lane Termination Disable) This same leaving High-Speed Data Transmission (TEOT of HSDT) sequence is illustrated below LP-11TEOT High Speed Data Transmission THS-EXIT THS-SKIP THS-TRAIL HS-0 or HS-1 High Speed Mode, Enable Rx Line Termination Low Power Mode, Disable Rx Line Termination Note CLK+ CLK- Dn+ Dn- The last load bit CLK+ CLK- Dn+ Dn- n=0 and 1 Figure 30 Leaving High-Speed Data Transmission (TEOT of HSDT)Note Note 1. If the last load bit is HS-0, the transmitter changes from HS-0 to HS-1. 2. If the last load bit is HS-1, the transmitter changes from HS-1 to HS-0.

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 69 of 328 3.5.19. Bus Turnaround (BTA) The MPU or display module, which is controlling DSI-D0+/- Data Lanes, can start a bus turnaround procedure when it wants information from a receiver, which can be the MPU or display module. The MPU and display module are using the same sequence when this bus turnaround procedure is used. This sequence is described for reference purposes, when the MPU wants to do the bus turnaround procedure to the display module, as follows.

• Start (MPU): LP-11
• Turnaround Request (MPU): LP-11 =>LP-10 =>LP-00 => LP-10 => LP-00
• The MPU waits until the display module is starting to control DSI-D0+/- data lanes and the MPU stops to control DSI-D0+/- data lanes (= High-Z)
• The display module changes to the stop mode: LP-00 =>LP-10 =>LP-11 The same bus turnaround procedure (From the MPU to the display module) is illustrated below LP-11 LP-10 LP-00 LP-10 LP-00 LP-00 LP-10 LP-11 D0+ D0- Turnaround Request (TAR) LP-00 MCU Controls Data Lanes The MCU waits until the Display Module starts to control data lanes (its output drivers) when MCU can put output drivers in the high-Z mode LP-Requests Display Module Controls Data Lanes Bus Turnaround (BTA) Time D0+ D0- Figure 40 Bus Turnaround Procedure MPU and display module terms are switched on the Figure 40, if the Bus Turnaround (BTA) is from the display module to the MPU.

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 75 of 328 3.5.27. Data Type (DT) Data Type (DT) is a part of Data Identification (DI[5…0]) structure and it is used to define a type of the used data on a packet. Bits of the Data Type (DT) are illustrated for reference purposes below. Figure 51 Data Type (DT) on the Packet Header (PH) This Data Type (DT) also defines what the used packet is: Short Packet (SPa) or Long Packet (LPa). Data Types (DT) are different from the MPU to the display module (or other devices) and vice versa. These Data Type (DT) are defined on tables below. Table 14 Data Type (DT) from the MPU to the Display Module (ILI9806E) From the MPU to the Display Module (ILI9806E) Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex Description Short/Long Packet Abbreviation 0 0 1 0 0 0 08 End of Transmission Packet, Note 1 SPa (Short Packet) EoTP 0 0 0 1 0 1 05 DCS Write, No Parameter SPa (Short Packet) DCSWN-S 0 1 0 1 0 1 15 DCS Write, 1 Parameter SPa (Short Packet) DCSW1-S 0 0 0 1 1 0 06 DCS Read, No Parameter SPa (Short Packet) DCSRN-S 1 1 0 1 1 1 37 Set Maximum Return Packet Size SPa (Short Packet) SMRPS-S 0 0 1 0 0 1 09 Null Packet, No Data, Note 2 L P a ( L o n g P a c k e t ) N P - L 1 1 1 0 0 1 39 DCS Write Long LPa (Long Packet) DCSW-L Note 1 This can be used when the MPU wants to secure that there is the end of the transmission in High Speed Data Transferring (HSDT) mode. Note 2 This can be used when data lanes are wanted to keep in High Speed Data Transferring (HSDT) Mode.

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 76 of 328 Table 15 Data Type (DT) from the Display Module (ILI9806E) to the MPU From the Display Module (ILI9806E) to the MPU Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex Description Short/Long Packet Abbreviation 0 0 0 0 1 0 02 Acknowledge with Error Report SPa (Short Packet) AwER 0 1 1 1 0 0 1C DCS Read Long Response LPa (Long Packet) DCSRR-L 1 0 0 0 0 1 21 DCS Read Short Response, 1 byte returned SPa (Short Packet) DCSRR1-S 1 0 0 0 1 0 22 DCS Read Short Response, 2 byte returned SPa (Short Packet) DCSRR2-S The receiver is ignored other Data Type (DT) if they are not defined on tables: “ Table 14 Data Type (DT) from the MPU to the Display Module (or Other Devices)” or “ Table 15 Data Type (DT) from the Display Module (or Other Devices) to the MPU”.

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 80 of 328 Error Correction Code (ECC) can recognize one error or several errors and makes correction in one bit error case. Bits (P[7…0]) of the Error Correction Code (ECC) are defined, where the symbol ‘^’ is presenting XOR function (Pn is ‘1’ if there is odd number of ‘1’s and Pn is ‘0’ if there is even number of ‘1’s), as follows.

• P7 = 0
• P6 = 0 P7 and P6 are set to ‘0’ because Error Correction Code (ECC) is based on 64 bit value ([D63…0]), but this implementation is based on 24 bit value (D[23…0]). Therefore, there is only needed 6 bits (P[5…0]) for Error Correction Code (ECC). Figure 58 XOR Functionality on the Short Packet (SPa)

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 83 of 328 The received Error Correction Code (ECC) can be 00h when the Error Correction Code (ECC) functionality is not used for data values D[23…0] on the transmitter side. The number of the errors (one or more) can be defined when the value of the PO[7…0] is compared to values on the following table. Table 16 One Bit Error Value of the Error Correction Code (ECC) Data Bit PO7 PO6 PO5 PO4 PO3 PO2 PO1 PO0 Hex D[0] 0 0 0 0 0 1 1 1 07h D[1] 0 0 0 0 1 0 1 1 0Bh D[2] 0 0 0 0 1 1 0 1 0Dh D[3] 0 0 0 0 1 1 1 0 0Eh D[4] 0 0 0 1 0 0 1 1 13h D[5] 0 0 0 1 0 1 0 1 15h D[6] 0 0 0 1 0 1 1 0 16h D[7] 0 0 0 1 1 0 0 1 19h D[8] 0 0 0 1 1 0 1 0 1Ah D[9] 0 0 0 1 1 1 0 0 1Ch D[10] 0 0 1 0 0 0 1 1 23h D[11] 0 0 1 0 0 1 0 1 25h D[12] 0 0 1 0 0 1 1 0 26h D[13] 0 0 1 0 1 0 0 1 29h D[14] 0 0 1 0 1 0 1 0 2Ah D[15] 0 0 1 0 1 1 0 0 2Ch D[16] 0 0 1 1 0 0 0 1 31h D[17] 0 0 1 1 0 0 1 0 32h D[18] 0 0 1 1 0 1 0 0 34h D[19] 0 0 1 1 1 0 0 0 38h D[20] 0 0 0 1 1 1 1 1 1Fh D[21] 0 0 1 0 1 1 1 1 2Fh D[22] 0 0 1 1 0 1 1 1 37h D[23] 0 0 1 1 1 0 1 1 3Bh One error is detected if the value of the PO[7…0] is on Table 25: One Bit Error Value of the Error Correction Code (ECC) and the receiver can correct this one bit error because this found value also defines what is a location of the corrupt bit e.g.

• PO[7…0] = 0Eh
• The bit of the data (D[23…0]), what is not correct, is D[3] More than one error is detected if the value of the PO[7…0] is not on Table 25: One Bit Error Value of the Error Correction Code (ECC) e.g. PO[7…0] = 0Ch.

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 85 of 328 A value of the Packet Footer (PF) is 1E0Eh in this example. This example (Command 01h has been sent) is illustrated below. Packet Header (PH) DI (Data Identification) B B B B B B B B WC - LSB (Word Count - LSB) B B B B B B B B WC - MSB (Word Count - MSB) B B B B B B B B B B B B B B B B ECC (Error Correction Code) L S B L S B L S B M S B M S B M S B L S B M S B 0 1 8'b 39h 8'b 01h 8'b 00h 8'b 15h 01 0 0 01 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 000 Time Data 0 (Packet Data) B B B B B B B B CRC - LSB B B B B B B B B B B B B B B B B CRC - MSB L S B L S B M S B M S B L S B M S B 8'b 01h 8'b 0Eh 8'b 1Eh 0 0 01 0 0 0 0 0 0 1 1 1 0 0 0 0 0 1 1 1 1 00 Time Packet Data (PD) Packet Footer (PF) Figure 65 Packet Footer (PF) Example The receiver is calculated own checksum value from received Packet Data (PD). The receiver compares own checksum and the Packet Footer (PF) what the transmitter has sent. The received Packet Data (PD) and Packet Footer (PF) are correct if the own checksum of the receiver and Packet Footer (PF) are equal and vice versa the receiv ed Packet Data (PD) and Packet Footer (PF) are not correct if the own checksum of the receiver and Packet Footer (PF) are not equal.

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 86 of 328 3.5.33. Packet Transmissions 3.5.34. Packet from the MPU to the Display Module 3.5.35. Display Command Set (DCS) Display Command Set (DCS), which is defined on chapter “5.2. Command Description” is used from the MPU to the display module. This Display Command Set (DCS) is always defined on the Data 0 of the Packet Data (PD), which is included in Short Packet (SPa) and Long packet (LPa) as these are illustrated below. LP-11 SoT DI Data 0 Data 1 ECC EoT LP-11 Time Packet Header (PH) LP-11 : Low Power - Stop State SoT : Start of Transmission DI : 8-bit, Data Identification Data 0 / Data 1 : 8-bit, Packet Data ECC : 8-bit, Error Correction Code EoT : End of Transmission DCS : Display Command Set LP-11 SoT DI WC ECC EoT LP-11Data 0 Data 1 CSData(WC-2) Data(WC-1) Time Time LP-11 : Low Power - Stop State SoT : Start of Transmission DI : 8-bit, Data Identification WC : 16-bit, Word Count ECC : 8-bit, Error Correction Code Data 0 , Data(WC-1) : Packet Data (0~65535 bytes) CS : 16-bit, Check Sum = Packet Footer (PF) EoT : End of Transmission DCS : Display Command Set Packet Header (PH) Short Packet (SPa) Long Packet (LPa) Packet Data Packet DataDCS DCS Figure 66 Display Command Set (DCS) on Short Packet (SPa) and Long Packet (LPa)

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 87 of 328 3.5.36. Display Command Set (DCS) Write, No Parameter (DCSWN-S) “Display Command Set (DCS) Write, No Parameter” is always using a Short Packet (SPa), what is defined on Data Type (DT, 00 0101b), from the MPU to the display module. These commands are defined on a table below. (See chapter “Command Description”) Table 17 Display Command Set (DCS) Write, No Parameters (DCSWN-S) Page 0 Command NOP (00h) Software Reset (01h) Sleep In(10h) Sleep Out (11h) Normal Display Mode On (13h) All Pixel Off (22h) All Pixel On (23h) Display Off (28h) Display ON (29h) Short Packet (SPa) is defined e.g.

• Data Identification (DI) o Virtual Channel (VC, DI[7…6]): 00b o Data Type (DT, DI[5…0]): 00 0101b
• Packet Data (PD) o Data 0: “Sleep In (10h)”, Display Command Set (DCS) o Data 1: Always 00hex
• Error Correction Code (ECC) This is defined on the Short Packet (SPa) as follows. Figure 67 Display Command Set (DCS) Write, No Parameter (DCSWN-S) - Example

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 88 of 328 3.5.37. Display Command Set (DCS) Write, 1 Parameter (DCSW1-S) “Display Command Set (DCS) Write, 1 Parameter” (DCSW1-S) is always using a Short Packet (SPa), what is defined on Data Type (DT, 01 0101b), from the MPU to the display module. These commands are defined on a table (See chapter “Command Description”) below. Table 18 Display Command Set (DCS) Write, 1 Parameter (DCSW1-S) Page 0 Command Gamma Set (26h) Interface Pixel Format (3Ah) Write Display Brightness (51h) Write CTRL Display (53h) Write Content Adaptive Brightness control (55h) Write CABC Minimum Brightness (5Eh) Short Packet (SPa) is defined e.g.

• Data Identification (DI) o Virtual Channel (VC, DI[7…6]): 00b o Data Type (DT, DI[5…0]): 01 0101b
• Packet Data (PD) o Data 0: “Gamma Set (26h)”, Display Command Set (DCS) o Data 1: 01hex, Parameter of the DCS
• Error Correction Code (ECC) This is defined on the Short Packet (SPa) as follows. Figure 68 Display Command Set (DCS) Write, 1 Parameter (DCSW1-S) – Example

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 89 of 328 3.5.38. Display Command Set (DCS) Write Long (DCSW-L) “Display Command Set (DCS) Write Long” (DCSW-L) is always using a Long Packet (LPa), what is defined on Data Type (DT, 11 1001b), from the MPU to the display module. Command (No Parameters) and Write (1 or more parameters), are defined on a table (See chapter “Command Description”) below. Table 19 Display Command Set (DCS) Write Long (DCSW-L) Page 0 Command NOP (00h) , Note 1 Software Reset (01h) , Note 1 Sleep In(10h) , Note 1 Sleep Out (11h) , Note 1 Normal Display Mode On (13h) , Note 1 All Pixel Off (22h) All Pixel On (23h) Gamma Set (26h), Note 2 Display Off (28h) , Note 1 Display ON (29h) , Note 1 Interface Pixel Format (3Ah) Write Display Brightness (51h) , Note 2 Write CTRL Display (53h) , Note 2 Write Content Adaptive Brightness control (55h) , Note 2 Write CABC Minimum Brightness (5Eh) Note 1 Also Short Packet (SPa) can be used; See chapter “Display Command Set (DCS) Write, No Parameter” Note 2 Also Short Packet (SPa) can be used; See chapter “Display Command Set (DCS) Write, 1 Parameter”

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 90 of 328 Long Packet (LPa), when a command (No Parameter) was sent, is defined e.g.

• Data Identification (DI) o Virtual Channel (VC, DI[7…6]): 00b o Data Type (DT, DI[5…0]): 11 1001b
• Word Count (WC) o Word Count (WC): 0001h
• Error Correction Code (ECC)
• Packet Data (PD): Data 0: “Sleep In (10h)”, Display Command Set (DCS)
• Packet Footer (PF) This is defined on the Long Packet (LPa) as follows. Packet Header (PH) DI (Data Identification) B B B B B B B B WC - LSB (Word Count - LSB) B B B B B B B B WC - MSB (Word Count - MSB) B B B B B B B B B B B B B B B B ECC (Error Correction Code) L S B L S B L S B M S B M S B M S B L S B M S B 0 1 8'b 39h 8'b 01h 8'b 00h 8'b 15h 01 0 0 01 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 000 Time Data 0 (DCS) B B B B B B B B CRC - LSB B B B B B B B B B B B B B B B B CRC - MSB L S B L S B M S B M S B L S B M S B 8'b 10h 8'b 06h 8'b 1Fh 0 0 00 0 0 0 1 0 0 1 1 0 0 0 0 0 1 1 1 1 1 00 Time Packet Data (PD) Packet Footer (PF) Figure 69 Display Command Set (DCS) Write Long (DCSW-L) with DCS Only - Example

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 91 of 328 Long Packet (LPa), when a Write (1 parameter) was sent, is defined e.g.

• Data Identification (DI) o Virtual Channel (VC, DI[7…6]): 00b o Data Type (DT, DI[5…0]): 11 1001b
• Word Count (WC) o Word Count (WC): 0002h
• Error Correction Code (ECC)
• Packet Data (PD): o Data 0: “Gamma Set (26h)”, Display Command Set (DCS) o Data 1: 01hex, Parameter of the DCS
• Packet Footer (PF) This is defined on the Long Packet (LPa) as follows. Figure 70 Display Command Set (DCS) Write Long with DCS and 1 Parameter - Example

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 92 of 328 Long Packet (LPa), when a Write (4 parameters) was sent, is defined e.g.

• Data Identification (DI) o Virtual Channel (VC, DI[7…6]): 00b o Data Type (DT, DI[5…0]): 11 1001b
• Word Count (WC) o Word Count (WC): 0005h
• Error Correction Code (ECC)
• Packet Data (PD): o Data 0: “Column Address Set (2Ah)”, Display Command Set (DCS) o Data 1: 00hex, 1st Parameter of the DCS, Start Column SC[15…8] o Data 2: 12hex, 2nd Parameter of the DCS, Start Column SC[7…0] o Data 3: 01hex, 3rd Parameter of the DCS, End Column EC[15…8] o Data 4: EFhex, 4th Parameter of the DCS, End Column EC[7…0]
• Packet Footer (PF) This is defined on the Long Packet (LPa) as follows. Figure 71 Display Command Set (DCS) Write Long with DCS and 4 Parameters - Example

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 93 of 328 3.5.39. Display Command Set (DCS) Read, No Parameter (DCSRN-S) “Display Command Set (DCS) Read, No Parameter” (DCSRN-S) is always using a Short Packet (SPa), what is defined on Data Type (DT, 00 0110b), from the MPU to the display module. These commands are defined on a table (See chapter “5.2. Command Description”) below. Table 20 Display Command Set (DCS) Read, No Parameter (DCSRN-S) Page 0 Command Read Display Power Mode (0Ah) Read Display MADCTL (0Bh) Read Display Pixel Format (0Ch) Read Display Image Mode (0Dh) Read Display Signal Mode (0Eh) Read Display Self-Diagnostic Result (0Fh) Read Display Brightness Value (52h) Read CTRL Value Display (54h) Read Content Adaptive Brightness Control (56h) Read CABC Minimum Brightness (5Fh) Read ID1 (DAh) Read ID2 (DBh) Read ID3 (DCh)

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 94 of 328 The MPU has to define to the display module, what is the maximum size of the return packet. A command, what is used for this purpose, is “Set Maximum Return Packet Size” (SMRPS-S), which Data Type (DT) is 11 0111b and which is using Short Packet (SPa) before the MPU can send “Display Command Set (DCS) Read, No Parameter” to the display module. This same sequence is illustrated for reference purposes below. Step 1:

• The MPU sends “Set Maximum Return Packet Size” (Short Packet (SPa)) (SMRPS-S) to the display module when it wants to return one byte from the display module
• Data Identification (DI) o Virtual Channel (VC, DI[7…6]): 00b o Data Type (DT, DI[5…0]): 11 0111b
• Maximum Return Packet Size (MRPS) o Data 0: 01hex o Data 1: 00hex
• Error Correction Code (ECC) Figure 72 Set Maximum Return Packet Size (SMRPS-S) - Example Step 2:
• The MPU wants to receive a value of the “Read ID1 (DAh)” from the display module when the MPU sends “Display Command Set (DCS) Read, No Parameter” to the display module
• Data Identification (DI) o Virtual Channel (VC, DI[7…6]): 00b o Data Type (DT, DI[5…0]): 00 0110b
• Packet Data (PD) o Data 0: “Read ID1 (DAh)”, Display Command Set (DCS) o Data 1: Always 00hex
• Error Correction Code (ECC)

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 95 of 328 Figure 73 Display Command Set (DCS) Read, No Parameter (DCSRN-S) - Example Step 3: The display module can send 2 different information to the MPU after Bus Turnaround (BTA) 1. An acknowledge with Error Report (AwER), which is using a Short Packet (SPa), if there is an error to receive a command, See chapter “Acknowledge with Error Report (AwER)” 2. Information of the received command. S hort Packet (SPa) or Long Packet (LPa)

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 96 of 328 3.5.40. Null Packet, No Data (NP-L) “Null Packet, No Data” (NP-L) is always using a Long Packet (LPa), what is defined on Data Type (DT, 001001b), from the MPU to the display module. The purpose of this command is keeping data lanes in the high speed mode (HSDT), if it is needed. The display module is ignored Packet Data (PD) what the MPU is sending. Long Packet (LPa), when 5 random data bytes of the Packet Data (PD) were sent, is defined e.g.

• Data Identification (DI) o Virtual Channel (VC, DI[7…6]): 00b o Data Type (DT, DI[5…0]): 00 1001b
• Word Count (WC) o Word Count (WC): 0005hex
• Error Correction Code (ECC)
• Packet Data (PD): o Data 0: 89hex (Random data) o Data 1: 23hex (Random data) o Data 2: 12hex (Random data) o Data 3: A2hex (Random data) o Data 4: E2hex (Random data)
• Packet Footer (PF) This is defined on the Long Packet (LPa) as follows.

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 97 of 328 Figure 74 Null Packet, No Data (NP-L) - Example

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 98 of 328 3.5.41. End of Transmission Packet (EoTP) “End of Transmission Packet” (EoTP) is always using a Short Packet (SPa), what is defined on Data Type (DT, 00 1000b), from the MPU to the display module. The purposes of this command is terminated the high Speed Data Transmission (HSDT) mode properly when there is added this extra packet after the last payload packet before “End of Transmission” (EoT), which is an interface level functionality. The MPU can decide if it wants to use the “End of Transmission Packet” (EoTP) or not. The display shall have the capability to support both: i.e. If the MPU applies the EoTP, it shall report the “DSI Protocol Violation Error” when the EoTP is not detected in the High-Speed (HS). The display module error reporting shall be enabled/disabled statistically, according to the module application. The display module is or isn’t receiving “End of Transmission Packet” (EoTP) from the MPU during the Low Power Data Transmission (LPDT) mode before “Mark-1” (= Leaving Escape mode) what ends the Low Power Data Transmission (LPDT) mode. The display module is not allowed to send “End of Transmission Packet” (EoTP) to the MPU during the Low Power Data Transmission (LPDT) mode. The summary of the receiving and transmitting EoTP is listed below. Table 21 Receiving and Transmitting EoTP during LPDT Direction Display Module (DM) in High Speed Data Transmission (HSDT) Display Module (DM) in Low Power Data Transmission (LPDT) MPU => Display Module With or Without EoTP is Supported With or Without EoTP is Supported Display Module => MPU HS Mode is not available (EoTP is not available) EoTP cannot be sent by the Display Module (DM) Short Packet (SPa) is using a fixed format as follows

• Data Identification (DI) o Virtual Channel (VC, DI[7…6]): 00b o Data Type (DT, DI[5…0]): 00 1000b
• Packet Data (PD) o Data 0: 0Fhex o Data 1: 0Fhex
• Error Correction Code (ECC) o ECC: 01hex This is defined on the Short Packet (SPa) as follows.

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 101 of 328 Exception: The display module is returning 2 packets (1st packet: Data, 2nd Packet: Acknowledge with Error Report) to the MPU when the display module has received a read command (See chapter “Display Command Set (DCS) Read, No Parameter (DCSRN-S)”) where has been detected and corrected a single bit error by the EEC (See bit 8 on “Table 22: Acknowledge with Error Report (AwER) for Short Packet (SPa) Response”). These return packets are illustrated for reference purposes below. Figure 79 Exception when Return Bytes on Several Packets AwER = Acknowledge with Error Report

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 102 of 328 3.5.44. Acknowledge with Error Report (AwER) “Acknowledge with Error Report” (AwER) is always using a Short Packet (SPa), what is defined on Data Type (DT, 00 0010b), from the display module to the MPU. The Packet Data (PD) can include bits, which are defining the current error, when a corresponding bit is set to ‘1’, as they are defined on the following table. Table 22 Acknowledge with Error Report (AwER) for Long Packet (LPa) Response Bit Description

0 SoT Error

1 SoT Sync Error

2 EoT Sync Error

3 Escape Mode Entry Command Error

4 Low-Power Transmit Sync Error

5 Any Protocol Timer Time-Out

6 False Control Error

7 Contention is Detected on the Display Module

8 ECC Error, single-bit ( detected and corrected)

9 ECC Error, multi-bit ( detected, not corrected)

10 Checksum Error

11 DSI Data Type (DT) Not Recognized

12 DSI Virtual Channel (VC) ID Invalid

13 Invalid Transmission Length

14 Reserved, Set to ‘0’ internally

15 DSI Protocol Violation

Table 23 Acknowledge with Error Report (AwER) for Short Packet (SPa) Response Bit Description

10 Reserved, Set to ‘0’ internally Set to ‘0’ internally (Only for Long Packet (LP)

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 103 of 328 These errors are included from all packages what has been received from the MPU to the display module, before Bus Turnaround (BTA). The display module ignores the received packet which includes error or errors. Acknowledge with Error Report (AwER) of the Short Packet (SPa) is defined e.g.

• Data Identification (DI) o Virtual Channel (VC, DI[7…6]): 00b o Data Type (DT, DI[5…0]): 00 0010b
• Packet Data (PD) o Bit 8: ECC Error, single-bit (detected and corrected) o AwER: 0100h
• Error Correction Code (ECC) This is defined on the Short Packet (SPa) as follows. Figure 80 Acknowledge with Error Report (AwER) – Example

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 105 of 328 3.5.45. DCS Read Long Response (DCSRR-L) “DCS Read Long Response” (DCSRR-L) is always using a Long Packet (LPa), what is defined on Data Type (DT, 011100b), from the display module to the MPU.“DCS Read Long Response” (DCSRR-L) is used when the display module wants to response a DCS Read command, which the MPU has sent to the display module. Long Packet (LPa), which includes 5 data bytes of the Packet Data (PD), is defined e.g.

• Data Identification (DI) o Virtual Channel (VC, DI[7…6]): 00b o Data Type (DT, DI[5…0]): 01 1100b
• Word Count (WC) o Word Count (WC): 0005hex
• Error Correction Code (ECC)
• Packet Data (PD): o Data 0: 89hex o Data 1: 23hex o Data 2: 12hex o Data 3: A2hex o Data 4: E2hex
• Packet Footer (PF) This is defined on the Long Packet (LP) as follows.

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 106 of 328 Figure 83 DCS Read Long Response (DCSRR-L) - Example

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 107 of 328 3.5.46. DCS Read Short Response, 1 Byte Returned (DCSRR1-S) “DCS Read Short Response, 1 Byte Returned” (DCSRR1-S) is always using a Short Packet (SPa), what is defined on Data Type (DT, 10 0001b), from the display module to the MPU.“DCS Read Short Response, 1 Byte Returned (DCSRR1-S) is used when the display module wants to response a DCS Read command, which the MPU has sent to the display module. Short Packet (SPa) is defined e.g.

• Data Identification (DI) o Virtual Channel (VC, DI[7…6]): 00b o Data Type (DT, DI[5…0]): 10 0001b
• Packet Data (PD) o Data 0: 45hex o Data 1: 00hex (Always)
• Error Correction Code (ECC) This is defined on the Short Packet (SP) as follows. Figure 84 DCS Read Short Response, 1 Byte Returned (DCSRR1-S) - Example

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 108 of 328 3.5.47. DCS Read Short Response, 2 Bytes Returned (DCSRR2-S) “DCS Read Short Response, 2 Bytes Returned” (DCSRR2-S) is always using a Short Packet (SPa), what is defined on Data Type (DT, 10 0010b), from the display module to the MPU.“DCS Read Short Response, 2 Bytes Returned” (DCSRR2-S) is used when the display module wants to response a DCS Read command, which the MPU has sent to the display module. Short Packet (SPa) is defined e.g.

• Data Identification (DI) o Virtual Channel (VC, DI[7…6]): 00b o Data Type (DT, DI[5…0]): 10 0010b
• Packet Data (PD) o Data 0: 45hex o Data 1: 32hex
• Error Correction Code (ECC) This is defined on the Short Packet (SPa) as follows. Figure 85 DCS Read Short Response, 2 Bytes Returned (DCSRR2-S) - Example

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 109 of 328 3.5.48. Communication Sequences 3.5.49. General The communication sequences can be done on interface or packet levels between the MPU and the display module. See chapters “Interface Level Communication” and “Packet Level Communication”. This communication sequence description is for DSI data lanes (DSI-D0+/- and DSI-D1+/-) and it has been assumed that the needed low level communication is done on DSI clock lanes (DSI-CLK+/-) automatically. See chapter “DSI-CLK Lanes”. Functions of the interface level communication is described on the following table. Table 24 Interface Level Communication Interface Mode Abbreviation Interface Action Description Low Power LP-11 Stop State LPDT Low Power Data Transmission ULPS Ultra-Low Power State RAR Remote Application Reset ACK Acknowledge (No Error) BTA Bus Turnaround High Speed HSDT High speed Data Transmission Functions of the packet level communication are described on the following table. Table 25 Packet Level Communication Interface Mode Abbreviation Packet Size Interface Action Description MPU DCSW1-S Short Packet DCS Write, 1 Parameter DCSWN-S Short Packet DCS Write, No Parameter DCSW-L Long Packet DCS Write Long DCSRN-S Short Packet DCS Read, No Parameter SMRPS-S Short Packet Set Ma ximum Return Packet Size NP-L Long Packet Null Packet, No Data EoTP Short Packet End of Transmission Packet Display Module (ILI9806E) AwER Short Packet Acknowl edge with Error Packet DCSRR-L Long Packet DCS Read Long Response DCSRR1-S Short Packet DCS Read Short Response DCSRR2-S Short Packet DCS Read Short Response

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 110 of 328 3.5.50. Sequences 3.5.51. DCS Write, 1 Parameter Sequence A Short Packet (SPa) of “Display Command Set (DCS) Write, 1 Parameter (DCSW1-S)” is defined on chapter “Display Command Set (DCS) Write, 1 Parameter (DCSW1-S)” and example sequences, how this packet is used, is described on following tables. Table 26 DCS Write, 1 Parameter Sequence – Example 1 DCS Write, 1 Parameter Sequence – Example 1 Line MPU Information Direction Display Module (ILI9806E) Comment Packet Sender Interface Mode Control Interface Mode Control Packet Sender 1 -- LP-11 Î -- -- Start

2 DCSW1-S LPDT Î -- --

3 -- LP-11 Î -- -- End Table 27 DCS Write, 1 Parameter Sequence – Example 2 DCS Write, 1 Parameter Sequence – Example 2 Line MPU Information Direction Display Module (ILI9806E) Comment Packet Sender Interface Mode Control Interface Mode Control Packet Sender 1 -- LP-11 Î -- -- Start

2 DCSW1-S HSDT Î -- --

3 EoTP HSDT Î -- -- End of Transmission Packet

4 -- LP-11 Î -- -- End Table 28 DCS Write, 1 Parameter Sequence – Example 3 DCS Write, 1 Parameter Sequence – Example 3 Line MPU Information Direction Display Module (ILI9806E) Comment Packet Sender Interface Mode Control Interface Mode Control Packet Sender 1 -- LP-11 Î -- -- Start 4 -- LP-11 Î -- -- 5 -- BTA Ù BTA -- Interface Control Change from MPU to the display module 6 -- -- Í LP-11 -- If No Error Î Go to Line 8 If Error Occurs Î Go to Line 13 8 -- -- Í ACK -- No Error 9 -- -- Í LP-11 -- 10 -- BTA Ù BTA -- Interface Control Change from the display module to MPU 11 -- LP-11 Î -- -- End 13 -- -- Í LPDT AwER Error Report 15 -- BTA Ù BTA -- 16 -- LP-11 Î -- -- End

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 111 of 328 3.5.52. DCS Write, No Parameter Sequence A Short Packet (SPa) of “Display Command Set (DCS) Write, No Parameter (DCSWN-S)” is defined on chapter “Display Command Set (DCS) Write, No Parameter (DCSWN-S)” and example sequences, how this packet is used, is described on following tables. Table 29 DCS Write, No Parameter Sequence – Example 1 DCS Write, No Parameter Sequence – Example 1 Line MPU Information Direction Display Module (ILI9806E) Comment Packet Sender Interface Mode Control Interface Mode Control Packet Sender 1 -- LP-11 Î -- -- Start

2 DCSWN-S LPDT Î -- --

3 -- LP-11 Î -- -- End Table 30 DCS Write, No Parameter Sequence – Example 2 DCS Write, No Parameter Sequence – Example 2 Line MPU Information Direction Display Module (ILI9806E) Comment Packet Sender Interface Mode Control Interface Mode Control Packet Sender 1 -- LP-11 Î -- -- Start

2 DCSWN-S HSDT Î -- --

4 -- LP-11 Î -- -- End Table 31 DCS Write, No Parameter Sequence – Example 3 DCS Write, 1 Parameter Sequence – Example 3 Line MPU Information Direction Display Module (ILI9806E) Comment Packet Sender Interface Mode Control Interface Mode Control Packet Sender 1 -- LP-11 Î -- -- Start 4 -- LP-11 Î -- -- 5 -- BTA Ù BTA -- Interface Control Change from MPU to the display module 6 -- -- Í LP-11 -- If No Error Î Go to Line 8 If Error Occurs Î Go to Line 13 8 -- -- Í ACK -- No Error 9 -- -- Í LP-11 -- 10 -- BTA Ù BTA -- Interface Control Change from the display module to MPU 11 -- LP-11 Î -- -- End 13 -- -- Í LPDT AwER Error Report 15 -- BTA Ù BTA -- 16 -- LP-11 Î -- -- End

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 112 of 328 3.5.53. DCS Write Long Sequence A Long Packet (LPa) of “Display Command Set (DCS) Write Long (DCSW-L)” is defined on chapter “Display Command Set (DCS) Write Long (DCSW-L)” and example sequences, how this packet is used, is described on following tables. Table 32 DCS Write Long Sequence – Example 1 DCS Write Long Sequence – Example 1 Line MPU Informatio n Direction Display Module (ILI9806E) Comment Packet Sender Interface Mode Control Interface Mode Control Packet Sender 1 -- LP-11 Î -- -- Start

2 DCSW-L LPDT Î -- --

3 -- LP-11 Î -- -- End Table 33 DCS Write Long Sequence – Example 2 DCS Write Long Sequence – Example 2 Line MPU Information Direction Display Module (ILI9806E) Comment Packet Sender Interface Mode Control Interface Mode Control Packet Sender 1 -- LP-11 Î -- -- Start

2 DCSRN-S HSDT Î -- --

4 -- LP-11 Î -- -- End Table 34 DCS Write Long Sequence – Example 3 DCS Write Long Sequence – Example 3 Line MPU Information Direction Display Module (ILI9806E) Comment Packet Sender Interface Mode Control Interface Mode Control Packet Sender 1 -- LP-11 Î -- -- Start 4 -- LP-11 Î -- -- 5 -- BTA Ù BTA -- Interface Control Change from MPU to the display module 6 -- -- Í LP-11 -- If No Error Î Go to Line 8 If Error Occurs Î Go to Line 13 8 -- -- Í ACK -- No Error 9 -- -- Í LP-11 -- 10 -- BTA Ù BTA -- Interface Control Change from the display module to MPU 11 -- LP-11 Î -- -- End 13 -- -- Í LPDT AwER Error Report 15 -- BTA Ù BTA -- 16 -- LP-11 Î -- -- End

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 113 of 328 3.5.54. DCS Read, No Parameter Sequence A Short Packet (SPa) of “Display Command Set (DCS) Read, No Parameter (DCSRN-S)” is defined on chapter “Display Command Set (DCS) Read, No Parameter (DCSRN-S)” and example sequences, how this packet is used, is described on following tables. Table 35 DCS Read, No Parameter Sequence – Example 1 DCS Read, No Parameter Sequence – Example 1 Line MPU Information Direction Display Module (ILI9806E) Comment Packet Sender Interface Mode Control Interface Mode Control Packet Sender 1 -- LP-11 Î -- -- Start

2 SMRPS-S HSDT Î -- -- Defined how many data byte is wanted to read :

3 DCSRN-S HSDT Î -- -- Wanted to get a response ID1 (DAh)

4 EoTP HSDT Î -- -- End of Transmission Packet

5 -- LP-11 Î -- -- 6 -- BTA Ù BTA -- Interface Control Change from MPU to the display module 7 -- -- Í LP-11 -- If No Error Î Go to Line 9 If Error Occurs Î Go to Line 14 If Error is Corrected by ECC Î Go to Line 19 9 -- -- Í LPDT DCSRR1-S Response 1 byte return 11 -- BTA Ù BTA -- Interface Control Change from the display module to MPU 12 -- LP-11 Î -- -- End 14 -- -- Í LPDT AwER Error Report 16 -- BTA Ù BTA -- Interface Control Change from the display module to MPU 17 -- LP-11 Î -- -- End 19 -- -- Í LPDT DCSRR1-S Response 1 byte return 20 -- -- Í LPDT AwER Error Report (Error is corrected by ECC) 21 Í LP-11 -- 22 -- BTA Ù BTA -- Interface Control Change from the display module to MPU 23 -- LP-11 Î -- -- End

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 114 of 328 Table 36 DCS Read, No Parameter Sequence – Example 2 DCS Read, No Parameter Sequence – Example 2 Line MPU Information Direction Display Module (ILI9806E) Comment Packet Sender Interface Mode Control Interface Mode Control Packet Sender 1 -- LP-11 Î -- -- Start

3 DCSRN-S HSDT Î -- -- Wanted to get a response ID1(DAh)

5 -- LP-11 Î -- -- 6 -- BTA Ù BTA -- Interface Control Change from MPU to the display module 7 -- -- Í LP-11 -- If No Error Î Go to Line 9 If Error Occurs Î Go to Line 14 If Error is Corrected by ECC Î Go to Line 19 9 -- -- Í LPDT DCSRR-L Response 200 byte return 11 -- BTA Ù BTA -- Interface Control Change from the display module to MPU 12 -- LP-11 Î -- -- End 14 -- -- Í LPDT AwER Error Report 16 -- BTA Ù BTA -- Interface Control Change from the display module to MPU 17 -- LP-11 Î -- -- End 19 -- -- Í LPDT DCSRR-S Response 200 byte return 20 -- -- Í LPDT AwER Error Report (Error is corrected by ECC) 21 Í LP-11 -- 22 -- BTA Ù BTA -- Interface Control Change from the display module to MPU 23 -- LP-11 Î -- -- End

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 115 of 328 3.5.55. Null Packet, No Data Sequence A Long Packet (LPa) of “Null Packet, No Data (NP-L)” is defined on chapter “Null Packet, No Data (NP-L)” and an example sequence, how this packet is used, is described on the following table. Table 37 Null Packet, No Data Sequence - Example Null Packet, No Data Sequence – Example Line MPU Information Direction Display Module (ILI9806E) Comment Packet Sender Interface Mode Control Interface Mode Control Packet Sender 1 -- LP-11 Î -- -- Start

2 NP-L HSDT Î -- -- Only High Speed Data Transmission is used

4 -- LP-11 Î -- -- End 3.5.56. End of Transmission Packet Packet (EoTP)” and an example sequence, how this packet is used, is described on the following table. Table 38 End of Transmission Packet – Example End of Transmission Packet – Example Line MPU Information Direction Display Module (ILI9806E) Comment Packet Sender Interface Mode Control Interface Mode Control Packet Sender 1 -- LP-11 Î -- -- Start 4 -- LP-11 Î -- -- End

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 116 of 328 3.6. Display Data Format 3.6.1. DPI (RGB) Interface 3.6.2. 16-bit / pixel 65K colors order on the DPI Interface The 16-bit RGB interface is selected by setting the DPI[2:0] bits to “101”. The display operation is synchronized with VS, HS and PCLK signals. Figure 86 16-bit / pixel 65K colors order on the DPI Interface Note: 1. The data order is as follows, MSB=DB23, LSB=DB0 and picture data is MSB=Bit 5, LSB=Bit 0 for Green, MSB=Bit 4, LSB=Bit 0 for Red and Blue data. 2. 1-times transfer is used to transmit 1 pixel data to the 16-bit color depth information. 3. ‘-‘= void

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 117 of 328 3.6.3. 18-bit / pixel 262K colo rs order on the DPI Interface The 18-bit RGB interface is selected by setting the DPI[2:0] bits to “110”. The display operation is synchronized with VS, HS and PCLK signals. Figure 87 18-bit / pixel 262K colors order on the DPI Interface Note: 1. The data order is as follows, MSB=DB23, LSB=DB0 and picture data is MSB=Bit 5, LSB=Bit 0 for Green, Red and Blue data. 2. 1-times transfer is used to transmit 1 pixel data to the 18-bit color depth information. 3. ‘-‘= void

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 118 of 328 3.6.4. 24-bit / pixel 16.7M colors order on the DPI Interface The 24-bit RGB interface is selected by setting the DPI[2:0] bits to “111”. The display operation is synchronized with VS, HS and PCLK signals. Figure 88 24-bit / pixel 16.7M colors order on the DPI Interface Note: 1. The data order is as follows, MSB=DB23, LSB=DB0 and picture data is MSB=Bit 7, LSB=Bit 0 for Green, Red and Blue data. 2. 1-times transfer is used to transmit 1 pixel data to the 24-bit color depth information.

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 119 of 328 3.6.5. DSI transmission data format 3.6.6. 16-bit per Pixel, Long packet, Data Type 00 1110 (0Eh) Packed Pixel Stream 16-Bit Format is a Long Packet used to transmit image data formatted as 16-bit pixels to a Video Mode display module. The packet consists of the DI byte, a two-byte WC, an ECC byte, a payload of length WC bytes and a two-byte checksum. Pixel format is r ed (5 bits), green (6 bits), and blue (5 bits), in that order. Note that the “Green” component is split across two bytes. Within a color component, the LSB is sent first, the MSB last. With this format, pixel boundaries align with byte boundaries every two bytes. The total line width (displayed plus non-displayed pixels) should be a multiple of two bytes. Normally, ILI9806E has no frame buffer of its own, so all image data shall be supplied by the host processor at a sufficiently high rate to avoid flicker or other visible artifice. Figure 89 16-bit per Pixel, Data Type 00 1110 (0Eh)

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 120 of 328 3.6.7. 18-bit per Pixel, Long packet, Data Type = 01 1110 (1Eh) Packed Pixel Stream 18-Bit Format (Packed) is a Long packet. It is used to transmit RGB image data formatted as pixels to a Video Mode display module that displays 18-bit pixels The packet consists of the DI byte, a two-byte WC, an ECC byte, a payload of length WC bytes and a two-byte Checksum. Pixel format is red (6 bits), green (6 bits) and blue (6 bits), in that order. Within a color component, the LSB is sent first, the MSB last. Note that pixel boundaries only align with byte boundaries every four pixels (nine bytes). Preferably, display modules employing this format have a hor izontal extent (width in pixels) ev enly divisible by four, so no partial bytes remain at the end of the display line data. If the active (displayed) horizontal width is not a multiple of four pixels, the transmitter shall send additional fill pixels at the end of the display line to make the transmitted width a multiple of four pixels. The receiving peripheral shall not display the fill pixels when refreshing the display device. For example, if a display device has an active display width of 399 pixels, the transmitter should send 400 pixels in one or more packets. The receiver should display the first 399 pixels and discard the last pixel of the transmission. With this format, the total line width (displayed plus non-displayed pixels) should be a multiple of four 1246 pixels (nine bytes). Figure 90 18-bit per Pixel, Data Type = 01 1110 (1Eh)

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 121 of 328 3.6.8. 18-bit per Pixel, Long packet, Data Type = 10 1110 (2Eh) In the 18-bit Pixel Loosely Packed format, each R, G, or B color component is six bits but is shifted to the upper bits of the byte, such that the valid pixel bits occupy bits [7:2] of each byte. Bits [1:0] of each payload byte representing active pixels are ignored. As a result, each pixel requires three bytes as it is transmitted across the link. This requires more bandwidth than the “packed” format, but requires less shifting and multiplexing logic in the packing and unpacking functions on each end of the Link. This format is used to transmit RGB image data formatted as pixels to a Video Mode display module that displays 18-bit pixels. The packet consists of the DI byte, a two-byte WC, an ECC byte, a payload of length WC bytes and a two-byte Checksum. The pixel format is red (6 bits), green (6 bits) and blue (6 bits) in that order. Within a color component, the LSB is sent first, the MSB last. With this format, pixel boundaries align with byte boundaries every three bytes. The total line width (displayed plus non-displayed pixels) should be a multiple of three bytes. Figure 91 18-bit per Pixel, Data Type = 10 1110 (2Eh)

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 122 of 328 3.6.9. 24-bit per Pixel, Long packet, Data Type = 11 1110 (3Eh) Packed Pixel Stream 24-Bit Format is a Long packet. It is used to transmit image data formatted as 24-bit pixels to a Video Mode display module. The packet consists of the DI byte, a two-byte WC, an ECC byte, a payload of length WC bytes and a two-byte Checksum. The pixel format is red (8 bits), green (8 bits) and blue (8 bits), in that order. Each color component occupies one byte in the pixel stream; no components are split across byte boundaries. Within a color component, the LSB is sent first, the MSB last. With this format, pixel boundaries align with byte boundaries every three bytes. The total line width (displayed plus non-displayed pixels) should be a multiple of three bytes. Figure 92 24-bit per Pixel, Data Type = 11 1110 (3Eh)

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 123 of 328 4. Command 4.1. Command Flow Exit Page 3 To Page 2 Exit Page 2 To Page 1 Exit Page 1 Exit Page 0 To Page 0 To Page 4 To Page 3 Hardware Reset or Page 0_Software Reset : General Command Set , Page 0 Default Page 0 Exit Page 4 : Extend Command Set , Page 1 Note 3 : Read FFh 5th parameter “Page_select”= 01h , means the driver IC is in Page 1. : 00h~FFh 00h~FFh : belong to ILITEK’s definition 00h~FCh : “Single Parameter”only FEh~FFh : The two functions are same as page 0 (Note 2, Note 3 ) : 00h~FFh , 00h~FCh : are following General’s command definition , FEh~FFh : belong to ILITEK’s definition,(Note 1, Note 2) 00h~FCh : “No Parameter”, “Single Parameter” FEh : “Single Parameter” FFh : “Multi-Parameters” Note 1 : Read FFh 5th parameter “Page_select”= 00h , means the driver IC is in Page 0. Note 2 : In SPI I/F access, write FEh=8Xh entry “SPI Read Mode” and write FEh=0Xh entry “SPI Write Mode” : Extend Command Set , Page 2 Note 4 : Read FFh 5th parameter “Page_select”= 02h , means the driver IC is in Page 2. : 00h~FFh 00h~FFh : belong to ILITEK’s definition : Extend Command Set , Page 3 Note 5 : Read FFh 5th parameter “Page_select”= 03h , means the driver IC is in Page 3. : 00h~FFh 00h~FFh : belong to ILITEK’s definition : Extend Command Set , Page 4 Note 6 : Read FFh 5th parameter “Page_select”= 04h , means the driver IC is in Page 4. : 00h~FFh 00h~FFh : belong to ILITEK’s definition 00h~FCh : “Single Parameter”only FEh~FFh : The two functions are same as page 0 (Note 2, Note 4 ) 00h~FCh : “Single Parameter”only FEh~FFh : The two functions are same as page 0 (Note 2, Note 5 ) 00h~FCh : “Single Parameter”only FEh~FFh : The two functions are same as page 0 (Note 2, Note 6 ) 00h Register Address 1st parameter Protect Key 2nd parameter Device code 1 3rd parameter Device code 2 4th parameter Device code 3 5th parameter Page_select 00h 00h 00h00hFFh 98h Register Address 1st parameter Protect Key 2nd parameter Device code 1 3rd parameter Device code 2 4th parameter Device code 3 5th parameter Page_select 06h 04h 00hFFhFFh 98h Register Address 1st parameter Protect Key 2nd parameter Device code 1 3rd parameter Device code 2 4th parameter Device code 3 5th parameter Page_select 06h 04h 01hFFhFFh 98h Register Address 1st parameter Protect Key 2nd parameter Device code 1 3rd parameter Device code 2 4th parameter Device code 3 5th parameter Page_select 06h 04h 02hFFhFFh 98h Register Address 1st parameter Protect Key 2nd parameter Device code 1 3rd parameter Device code 2 4th parameter Device code 3 5th parameter Page_select 06h 04h 03hFFhFFh 98h Register Address 1st parameter Protect Key 2nd parameter Device code 1 3rd parameter Device code 2 4th parameter Device code 3 5th parameter Page_select 06h 04h 04hFFhFFh Figure 93 Command Flow

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 124 of 328 4.2. Command List 4.2.1. Page 0 Command List Page 0 Command Set 00h : NOP (No Operation) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 0 0 0 0 0 0 00h Page 0 Command Set 01h : SWRESET (Software Reset) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 0 0 0 0 0 1 01h Page 0 Command Set 05h : RDNUMED (Read Number of the Errors on DSI) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 0 0 0 1 0 1 05h st Parameter Read P [7:0] XXh Page 0 Command Set 0Ah : RDDPM (Read Display Power Mode) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 0 0 1 0 1 0 0Ah st Parameter Read BSTON 0 0 SLPOUT NORON DISON 0 0 XXh Page 0 Command Set 0Bh : RDDMADCTL (Read Display MADCTL) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 0 0 1 0 1 1 0Bh st Parameter Read 0 0 0 0 BGR 0 SS GS XXh Page 0 Command Set 0Ch : RDDCOLMOD (Read Display COLMOD ) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 0 0 1 1 0 0 0Ch st Parameter Read 0 DPI [2:0] 0 0 0 0 XXh Page 0 Command Set 0Dh : RDDIM (Read Display Image Mode) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 0 0 1 1 0 1 0Dh st Parameter Read 0 0 INVON ALLPON ALLPOFF GCS [2:0] XXh Page 0 Command Set 0Eh : RDDSM (Read Display Signal Mode) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 0 0 1 1 1 0 0Eh st Parameter Read TEON 0 HSON VSON PCLKON DEON 0 EODSI XXh Page 0 Command Set 0Fh : RDDSDR (Read Display Self-Diagnostic Result) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 0 0 1 1 1 1 0Fh st Parameter Read REGLD FUNDT 0 0 0 0 0 0 XXh Page 0 Command Set 10h : SLPIN (Sleep In) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 0 1 0 0 0 0 10h

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 125 of 328 Page 0 Command Set 11h : SLPOUT (Sleep Out) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 0 1 0 0 0 1 11h Page 0 Command Set 13h : NORON (Normal Display Mode On) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 0 1 0 0 1 1 13h Page 0 Command Set 20h : INVOFF (Display Inversion Off) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 1 0 0 0 0 0 20h Page 0 Command Set 21h : INVON (Display Inversion ON) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 1 0 0 0 0 1 21h Page 0 Command Set 22h : ALLPOFF (All pixels off) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 1 0 0 0 1 0 22h Page 0 Command Set 23h : ALLPON (All pixels on) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 1 0 0 0 1 1 23h Page 0 Command Set 26h : GAMSET (Gamma Set) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 1 0 0 1 1 0 26h st Parameter Write GC[7:0] 01h Page 0 Command Set 28h : DISPOFF (Display Off) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 1 0 1 0 0 0 28h Page 0 Command Set 29h : DISPON (Display ON) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 1 0 1 0 0 1 29h Page 0 Command Set 34h : TEOFF (Tearing Effect Line OFF) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 1 1 0 1 0 0 34h Page 0 Command Set 35h : TEON (Tearing Effect Line ON) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 1 1 0 1 0 1 35h Page 0 Command Set 36h : MADCTL (Display Access Control) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 1 1 0 1 1 0 36h st Parameter Write 0 0 0 0 BGR 0 SS GS xx

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 126 of 328 Page 0 Command Set 3Ah : COLMOD (Interface Pixel Format) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 1 1 1 0 1 0 3Ah st Parameter Write 0 DPI[2:0] 0 0 0 0 70h Page 0 Command Set 51h : WRDISBV (Write Display Brightness) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 1 0 1 0 0 0 1 51h st Parameter Write DBV[7:0] xx Page 0 Command Set 52h : RDDISBV (Read Display Brightness Value) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 1 0 1 0 0 1 0 52h st Parameter Read DBV[7:0] xx Page 0 Command Set 53h : WRCTRLD (Write Control Display) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 1 0 1 0 0 1 1 53h st Parameter Write 0 0 BCTRL 0 DD BL 0 0 xx Page 0 Command Set 54h : RDCTRLD (Read Control Display Value) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 1 0 1 0 1 0 0 54h st Parameter Read 0 0 BCTRL 0 DD BL 0 0 xx Page 0 Command Set 55h : WRCABC (Write Content Adaptive Brightness Control) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 1 0 1 0 1 0 1 55h st Parameter Write C[7:4] C[3:0] x x Page 0 Command Set 56h : RDCABC (Read Content Adaptive Brightness Control) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 1 0 1 0 1 1 0 56h st Parameter Read C[7:4] C[3:0] xx Page 0 Command Set 5Eh : WRCABCMB (Write CABC Minimum Brightness) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 1 0 1 1 1 1 0 5Eh st Parameter Write CMB[7:0] xx Page 0 Command Set 5Fh : RDCABCMB (Read CABC Minimum Brightness) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 1 0 1 1 1 1 1 5Fh st Parameter Read CMB[7:0] x x Page 0 Command Set 68h : RDABCSDR (Read automatic brightness control self-diagnostic result) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 1 1 0 1 0 0 0 68h st Parameter Read D[7:6] 0 0 0 0 0 0 xx

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 127 of 328 Page 0 Command Set DAh : RDID1 (Read ID1) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 1 1 0 1 1 0 1 0 DAh st Parameter Read ID1[7:0] xx Page 0 Command Set DBh : RDID2 (Read ID2) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 1 1 0 1 1 0 1 1 DBh st Parameter Read ID2[7:0] xx Page 0 Command Set DCh : RDID3 (Read ID3) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 1 1 0 1 1 1 0 0 DCh st Parameter Read ID3[7:0] xx Page 0 Command Set FEh : RDEXTCSPI(Read EXTC command In SPI) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 1 1 1 1 1 1 1 0 FEh st Parameter Write EXT_SP I_R_EN EXT_SPI_CNT[6:0] 00h Page 0 Command Set FFh : ENEXTC (EXTC command set enable register) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 1 1 1 1 1 1 1 1 FFh st Parameter Write 1 1 1 1 1 1 1 1 FFh nd Parameter Write 1 0 0 1 1 0 0 0 98h rd Parameter Write 0 0 0 0 0 1 1 0 06h th Parameter Write 0 0 0 0 0 1 0 0 04h th Parameter Write / Read PAGE[7:0] 00h Note: 1. Undefined commands are treated as NOP (00h) command. 2. FEh to FFh are display supplier for usage of factory . 3. Commands 10h, 13h, 26h, 28h, 29h, 36h (only Bit D4) are updated during V-SYNC,when module is in Sleep Out mode ,to avoid abnormal visual effects. During Sleep In mode, these commands are updated immediately. Read display power mode (0Ah), Read display MADCTL (0Bh), Read display pixel format (0Ch), Read display image mode (0Dh), Read display signal mode (0Eh) and Read display self diagnostic result (0Fh) of these commands are updated immediately both in Sleep In mode and Sleep Out mode.

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 128 of 328 4.2.2. Page 1 Command List Page 1 Command Set 00h : RDID4 (Read ID 4) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 0 0 0 0 0 0 00h st Parameter Read ID4[23:16] 98h Page 1 Command Set 01h : RDID4 (Read ID 4) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 0 0 0 0 0 1 01h st Parameter Read ID4[15:8] 06h Page 1 Command Set 02h : RDID4 (Read ID 4) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 0 0 0 0 1 0 02h st Parameter Read ID4[7:0] 04h Page 1 Command Set 08h : IFMODE.1 (Interface Mode Control 1) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 0 0 1 0 0 0 08h st Parameter Write / Read 0 0 0 SDO_S TATUS SEPT_S DIO 0 0 0 08h Page 1 Command Set 0Ah : IFMODE 2 (Interface Mode Control 2) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 0 0 1 0 1 0 0Ah st Parameter Write / Read 0 0 0 0 0 0 0 2LANE_ En 00h Page 1 Command Set 20h : DISCTRL1 (Display Function Control 1) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 1 0 0 0 0 0 20H st Parameter Write / Read 0 0 0 0 0 0 0 SYNC MODE 00h Page 1 Command Set 21h : DISCTRL2 (Display Function Control 2) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 1 0 0 0 0 1 21h st Parameter Write / Read 0 0 0 0 VSPL HSPL DPL EPL 01h Page 1 Command Set 22h : PANELCTRL1 (Set panel operation mode1) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 1 0 0 0 1 0 22h st Parameter Write / Read 0 0 0 0 BGR_ PANEL 0 SS_ PANEL GS_ PANEL 00h Page 1 Command Set 23h : PANELCTRL2 (Set panel operation mode2) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 1 0 0 0 1 1 23h st Parameter Write / Read 0 0 0 0 0 0 REV 0 00h

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 129 of 328 Page 1 Command Set 24h : Data Complement Setting Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 1 0 0 1 0 0 24h st Parameter Write / Read 0 0 0 0 0 0 EPF[1:0] 03h Page 1 Command Set 25h : BLKPRH 1 (Blanking Porch 1) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 1 0 0 1 0 1 25H st Parameter Write / Read 0 VFP[6:0] 14h Page 1 Command Set 26h : BLKPRH 2 (Blanking Porch 2) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 1 0 0 1 1 0 26H st Parameter Write / Read 0 VBP[6:0] 14h Page 1 Command Set 27h : BLKPRH 3 (Blanking Porch 3) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 1 0 0 1 1 1 27H st Parameter Write / Read HBP[7:0] 05h Page 1 Command Set 28h : BLKPRH 4 (Blanking Porch 4) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 1 0 1 0 0 0 28H st Parameter Write / Read 0 0 0 0 0 0 HBP[9:8] 00h Page 1 Command Set 30h : RESCTRL (Resolution Control ) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 1 1 0 0 0 0 30h st Parameter Write / Read 0 0 0 0 0 RES[2:0] 02h Page 1 Command Set 31h : INVTR (Display Inversion Control) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 1 1 0 0 0 1 31H st Parameter Write / Read 0 0 0 0 NLA[3:0] 00h Page 1 Command Set 34h : DITHE (Dithering Enable) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 1 1 0 1 0 0 34h st Parameter Write / Read 0 0 0 0 0 0 0 DITH_EN 00h Page 1 Command Set 35h : Source Signal Adjust Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 1 1 0 1 0 1 35h st Parameter Write / Read 0 0 0 0 0 CHOPPER SEL_REG[2:0] 06h Page 1 Command Set 40h : PWCTRL 1 (Power Control 1) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 1 0 0 0 0 0 0 40h st Parameter Write / Read EXB1T 0 EXT_CPCK_SEL[1:0] BT [3:0] 15h

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 130 of 328 Page 1 Command Set 41h : PWCTRL 2 (Power Control 2) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 1 0 0 0 0 0 1 41h st Parameter Write / Read 0 DDVDH_CLP[2:0] 0 DDVDL_CLP[2:0] 22h Page 1 Command Set 42h : PWCTRL 3 (Power Control 3) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 1 0 0 0 0 1 0 42h st Parameter Write / Read 0 0 VGH_CP[1:0] 0 0 VGL_CP[1:0] 02h Page 1 Command Set 43h : PWCTRL 4 (Power Control 4) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 1 0 0 0 0 1 1 43h st Parameter Write / Read VGH_CLP EN 0 0 0 VGH_CLP[3:0] 09h Page 1 Command Set 44h : PWCTRL 5 (Power Control 5) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 1 0 0 0 1 0 0 44h st Parameter Write / Read VGL_CLP EN 0 0 0 VGL_CLP[3:0] 86h Page 1 Command Set 45h : PWCTRL 6 (Power Control 6) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 1 0 0 0 1 0 1 45h st Parameter Write / Read VGH_REG[3:0] VGL_REG[3:0] 00h Page 1 Command Set 46h : PWCTRL 7 (Power Control 7) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 1 0 0 0 1 1 0 46h st Parameter Write / Read 0 DDVDH_PK1[2:0] 0 DDVDL_PK2[2:0] 33h Page 1 Command Set 47h : PWCTRL 8 (Power Control 8) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 1 0 0 0 1 1 1 47h st Parameter Write / Read 0 VCL_PK3[2:0] 0 VGHL_PK4[2:0] 33h Page 1 Command Set 50h : PWCTRL 9 (Power Control 9) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 1 0 1 0 0 0 0 50h st Parameter Write / Read VREG1[7:0] 78h Page 1 Command Set 51h : PWCTRL 10 (Power Control 10) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 1 0 1 0 0 0 1 51h st Parameter Write / Read VREG2[7:0] 78h

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 131 of 328 Page 1 Command Set 52h : VMCTRL1 (VCOM Control 1) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 1 0 1 0 0 1 0 52h st Parameter Write / Read 0 0 0 0 0 0 0 VCM1[8] 00h Page 1 Command Set 53h : VMCTRL2 (VCOM Control 2) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 1 0 1 0 0 1 1 53h st Parameter Write / Read VCM1[7:0] 6Fh Page 1 Command Set 54h : VMCTRL3 (VCOM Control 3) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 1 0 1 0 1 0 0 54h st Parameter Write / Read 0 0 0 0 0 0 0 VCM2[8] 00h Page 1 Command Set 55h : VMCTRL4 (VCOM Control 4) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 1 0 1 0 1 0 1 55h st Parameter Write / Read VCM2[7:0] 6Fh Page 1 Command Set 56h : VMCTRL5 (VCOM Control 5) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 1 0 1 0 1 1 0 56h st Parameter Write / Read 0 0 0 NVM2 0 0 0 NVM1 00h Page 1 Command Set 57h : LVD (Low Voltage Detection) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 1 0 1 0 1 1 1 57h st Parameter Write / Read 0 VDET[2:0] 0 VCORE_VD[2:0] 20h Page 1 Command Set 58h : ETMOD (Entry Mode Set) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 1 0 1 1 0 0 0 58h st Parameter Write / Read LVD 0 0 1 0 0 0 DSTB 90h Page 1 Command Set 60h : Source Timing Adjust 1 Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 1 1 0 0 0 0 0 60h st Parameter Write / Read 0 0 SDTI[5:0] 05h Page 1 Command Set 61h : Source Timing Adjust 2 Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 1 1 0 0 0 0 1 61h st Parameter Write / Read 0 0 CRTI[5:0] 05h Page 1 Command Set 62h : Source Timing Adjust 3 Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 1 1 0 0 0 1 0 62h st Parameter Write / Read 0 0 EQTI[5:0] 0Eh

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 132 of 328 Page 1 Command Set 63h : Source Timing Adjust 4 Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 1 1 0 0 0 1 1 63h st Parameter Write / Read 0 0 PCTI[5:0] 05h Page 1 Command Set 80h : Synchronization Timing Adjust 1 Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 1 0 0 0 0 0 0 0 80h st Parameter Write / Read TOUCH_OPT[1:0] VSOD[1:0] HOSM[1:0] HS_OPT 0 00h Page 1 Command Set 81h : Synchronization Timing Adjust 2 Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 1 0 0 0 0 0 0 1 81h st Parameter Write / Read 0 HSOD[6:0] 05h Page 1 Command Set 82h : Synchronization Timing Adjust 3 Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 1 0 0 0 0 0 1 0 82h st Parameter Write / Read HSOHW[7:0] 19h Page 1 Command Set A0h~AFh : PGAMCTRL1~16 (Positive Gamma Control 1~16) Command Write / Read Parameter Default (Hex)D7 D6 D5 D4 D3 D2 D1 D0 A0h Write / Read 0 0 VP0[5:0] 00h A1h Write / Read 0 0 VP4[5:0] 0Fh A2h Write / Read 0 0 VP8[5:0] 19h A3h Write / Read 0 0 0 VP16[4:0] 12h A4h Write / Read 0 0 0 VP24[4:0] 13h A5h Write / Read 0 0 0 VP52[4:0] 1Ah A6h Write / Read 0 0 0 0 VP80[3:0] 0Dh A7h Write / Read 0 0 0 0 VP108[3:0] 0Ch A8h Write / Read 0 0 0 0 VP147[3:0] 00h A9h Write / Read 0 0 0 0 VP175[3:0] 04h AAh Write / Read 0 0 0 VP203[4:0] 04h ABh Write / Read 0 0 0 VP231[4:0] 0Dh ACh Write / Read 0 0 0 VP239[4:0] 0Bh ADh Write / Read 0 0 VP247[5:0] 2Ah AEh Write / Read 0 0 VP251[5:0] 20h AFh Write / Read 0 0 VP255 [5:0] 00h

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 133 of 328 Page 1 Command Set C0h~CFh : NGAMCTRL1~16(Negative Gamma Correction 1~16) Command Write / Read Parameter Default (Hex)D7 D6 D5 D4 D3 D2 D1 D0 C0h Write / Read 0 0 VN0[5:0] 00h C1h Write / Read 0 0 VN4[5:0] 0Fh C2h Write / Read 0 0 VN8[5:0] 19h C3h Write / Read 0 0 0 VN16[4:0] 12h C4h Write / Read 0 0 0 VN24[4:0] 13h C5h Write / Read 0 0 0 VN52[4:0] 1Ah C6h Write / Read 0 0 0 0 VN80[3:0] 0Dh C7h Write / Read 0 0 0 0 VN108[3:0] 0Ch C8h Write / Read 0 0 0 0 VN147[3:0] 00h C9h Write / Read 0 0 0 0 VN175[3:0] 04h CAh Write / Read 0 0 0 VN203[4:0] 04h CBh Write / Read 0 0 0 VN231[4:0] 0Dh CCh Write / Read 0 0 0 VN239[4:0] 0Bh CDh Write / Read 0 0 VN247[5:0] 2Ah CEh Write / Read 0 0 VN251[5:0] 20h CFh Write / Read 0 0 VN255 [5:0] 00h Page 1 Command Set E0h : NVMWR 1 (NV Memory Write 1 ) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 1 1 1 0 0 0 0 0 E0h st Parameter Write PGM_DATA[7:0] 00h Page 1 Command Set E1h : NVMWR 2 (NV Memory Write 2 ) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 1 1 1 0 0 0 0 1 E1h st Parameter Write PGM_ADR[7:0] / NVM_READ_ADR[7:0] 00h Page 1 Command Set E3h : NVMPKEY 1(NV Memory Protection Key 1) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 1 1 1 0 0 0 1 1 E3h st Parameter Write KEY[23:16] XXh Page 1 Command Set E4h : NVMPKEY 2(NV Memory Protection Key 2) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 1 1 1 0 0 1 0 0 E4h st Parameter Write KEY[15:8] XXh Page 1 Command Set E5h : NVMPKEY 3(NV Memory Protection Key 3) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 1 1 1 0 0 1 0 1 E5h st Parameter Write KEY[7:0] XXh Page 1 Command Set E6h : RDNVM1 (NV Memory Status Read 1 ) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 1 1 1 0 0 1 1 0 E6h st Parameter Read 0 0 ID2_MK[2:0] ID1_ MK [2:0] 00h

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 134 of 328 Page 1 Command Set E7h : RDNVM2 (NV Memory Status Read 2 ) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 1 1 1 0 0 1 1 1 E7h st Parameter Read 0 0 0 0 0 ID3_MK[2:0] 00h Page 1 Command Set E8h : RDNVM3 (NV Memory Status Read 3 ) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 1 1 1 0 1 0 0 0 E8h st Parameter Read GMAP_ MK GMAN_ MK VCM2_MARK[2:0] VCM1_MARK[2:0] 00h Page 1 Command Set E9h : RDNVM4 (NV Memory Status Read 4 ) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 1 1 1 0 1 0 0 1 E9h st Parameter Read OTP_B USY 0 0 0 0 0 0 0 00h Page 1 Command Set EAh : RDNVM5 (NV Memory Status Read 5 ) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 1 1 1 0 1 0 1 0 EAh st Parameter Read NVM_READ_DATA[7:0] 00h

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 135 of 328 4.2.3. Page 2 Command List Page 2 Command Set 00h~3Fh : DGAMCTRL (Digital Gamma Control 1) Command Write / Read Parameter Default (Hex)D7 D6 D5 D4 D3 D2 D1 D0 00h Write RCA0 [3:0] BCA0 [3:0] - 01h Write RCA1 [3:0] BCA1 [3:0] - 02h Write RCA2 [3:0] BCA2 [3:0] - : : : : - XXh Write RCAXX [3:0] BCAXX [3:0] - XX+1h Write RCAXX+1 [3:0] BCAXX+1 [3:0] - XX+2h Write RCAXX+2 [3:0] BCAXX+2 [3:0] - : : : : - 3Dh Write RCA61 [3:0] BCA61 [3:0] - 3Eh Write RCA62 [3:0] BCA62 [3:0] - 3Fh Write RCA63 [3:0] BCA63 [3:0] - Page 2 Command Set 40h : D3GE (Digital 3 Gamma Enable) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 1 0 0 0 0 0 0 40h st Parameter Write / Read 0 0 0 0 0 0 0 EN_3G 00h 4.2.4. Page 3 Command List Page 3 Command Set 00h~7Fh : DGAMCTRL (Digital Gamma Control 2) Command Write / Read Parameter Default (Hex)D7 D6 D5 D4 D3 D2 D1 D0 00h Write RFA0 [3:0] BFA0 [3:0] - 01h Write RFA1 [3:0] BFA1 [3:0] - 02h Write RFA2 [3:0] BFA2 [3:0] - : : : : - XXh Write RFAXX [3:0] BFAXX [3:0] - XX+1h Write RFA XX+1 [3:0] BFA XX+1 [3:0] - XX+2h Write RFA XX+2 [3:0] BFA XX+2 [3:0] - : : : : - 7Dh Write RFA125 [3:0] BFA125 [3:0] - 7Eh Write RFA126 [3:0] BFA126 [3:0] - 7Fh Write RFA127 [3:0] BFA127 [3:0] -

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 136 of 328 4.2.5. Page 4 Command List Page 4 Command Set 00h~7Fh : DGAMCTRL (Digital Gamma Control 3) Command Write / Read Parameter Default (Hex)D7 D6 D5 D4 D3 D2 D1 D0 00h Write RFA128 [3:0] BFA128 [3:0] - 01h Write RFA129 [3:0] BFA129 [3:0] - 02h Write RFA130 [3:0] BFA130 [3:0] - : : : : - XXh Write RFAXX [3:0] BFAXX [3:0] - XX+1h Write RFA XX+1 [3:0] BFA XX+1 [3:0] - XX+2h Write RFA XX+2 [3:0] BFA XX+2 [3:0] - : : : : - 7Dh Write RFA253 [3:0] BFA253 [3:0] - 7Eh Write RFA254 [3:0] BFA254 [3:0] - 7Fh Write RFA255 [3:0] BFA255 [3:0] - 4.2.6. Page 5 Command List Page 5 Command Set 00h : BLCTRL1 (Backlight Control 1) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 0 0 0 0 0 0 00h st Parameter Write / Read PWM_DIV[7:0] E8h Page 5 Command Set 01h : BLCTRL2 (Backlight Control 2) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 0 0 0 0 0 1 01h st Parameter Write / Read THRES_MOV[3:0] THRES_STILL[3:0] BBh Page 5 Command Set 02h : BLCTRL3 (Backlight Control 3) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 0 0 0 0 1 0 02h st Parameter Write / Read 0 0 0 0 THRES_UI[3:0] 0Bh Page 5 Command Set 03h : BLCTRL4 (Backlight Control 4) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 0 0 0 0 1 1 03h st Parameter Write / Read DTH_MOV[3:0] DTH_STILL[3:0] A8h Page 5 Command Set 04h : BLCTRL5 (Backlight Control 5) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 0 0 0 1 0 0 04h st Parameter Write / Read 0 0 0 0 DTH_UI[3:0] 04h Page 5 Command Set 05h : BLCTRL6 (Backlight Control 6) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 0 0 0 1 0 1 05h st Parameter Write / Read 0 DIM_MOV[2:0] 0 DIM_STILL[2:0] 43h

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 137 of 328 Page 5 Command Set 06h : BLCTRL7 (Backlight Control 7) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 0 0 0 1 1 0 06h st Parameter Write / Read DIM_MIN[3:0] 0 DIM_UI[2:0] 02h Page 5 Command Set 07h : BLCTRL8 (Backlight Control 8) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 0 0 0 1 1 1 07h st Parameter Write / Read LABC_SRE_THR[3:0] LABC SRE_ ENABLE LEDONR LEDON POL PWM POL B0h Page 5 Command Set 09h : BLCTRL9 (Backlight Control 9) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 0 0 1 0 0 1 09h st Parameter Write / Read SRECABC BOOSTEN 1 1 1 SRECABC EN 1 0 0 74h Page 5 Command Set 0Ch : BLCTRL10 (Backlight Control 10) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 0 0 1 1 0 0 0Ch st Parameter Write / Read ALS8BIT[7:0] A0h Page 5 Command Set 25h~3Ch : CECTRL 1~24 (Color Enhancement Control 1~24 ) Command Write / Read Parameter Default (Hex)D7 D6 D5 D4 D3 D2 D1 D0 25h Write / Read 0 0 0 FIRST_AXIS_1[4:0] 00h 26h Write / Read 0 0 0 FIRST_AXIS _2[4:0] 00h 27h Write / Read 0 0 0 FIRST_AXIS _3[4:0] 00h 28h Write / Read 0 0 0 FIRST_AXIS _4[4:0] 00h 29h Write / Read 0 0 0 SECOND_AXIS 1[4:0] 00h 2Ah Write / Read 0 0 0 SECOND_AXIS _2[4:0] 00h 2Bh Write / Read 0 0 0 SECOND_AXIS _3[4:0] 00h 2Ch Write / Read 0 0 0 SECOND_AXIS _4[4:0] 00h 2Dh Write / Read 0 0 0 THIRD_ AXIS _1[4:0] 00h 2Eh Write / Read 0 0 0 THIRD _ AXIS _2[4:0] 00h 2Fh Write / Read 0 0 0 THIRD _ AXIS _3[4:0] 00h 30h Write / Read 0 0 0 THIRD _ AXIS _4[4:0] 00h 31h Write / Read 0 0 0 FOURTH_ AXIS _1[4:0] 00h 32h Write / Read 0 0 0 FOURTH _ AXIS _2[4:0] 00h 33h Write / Read 0 0 0 FOURTH _ AXIS _3[4:0] 00h 34h Write / Read 0 0 0 FOURTH _ AXIS _4[4:0] 00h 35h Write / Read 0 0 0 FIFTH_ AXIS _1[4:0] 00h 36h Write / Read 0 0 0 FIFTH _ AXIS _2[4:0] 00h 37h Write / Read 0 0 0 FIFTH _ AXIS _3[4:0] 00h 38h Write / Read 0 0 0 FIFTH _ AXIS _4[4:0] 00h 39h Write / Read 0 0 0 SIXTH_ AXIS _1[4:0] 00h 3Ah Write / Read 0 0 0 SIXTH_ AXIS _2[4:0] 00h 3Bh Write / Read 0 0 0 SIXTH_ AXIS _3[4:0] 00h 3Ch Write / Read 0 0 0 SIXTH_ AXIS _4[4:0] 00h

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 138 of 328 4.2.7. Page 6 Command List Page 6 Command Set 00h~1Dh : GIPCTRL1 (GIP Control 1) Command Write / Read Parameter Default (Hex)D7 D6 D5 D4 D3 D2 D1 D0 00h Write / Read F_TIME_O PT STV_A_Rise[ 9:8] GIP_0_SET0 - 01h Write / Read STV_A_Rise[ 7:0] - 02h Write / Read GIP_0_SET1 - 03h Write / Read GIP_0_SET2 - 04h Write / Read GIP_0_SET3 - 05h Write / Read GIP_0_SET4 - 06h Write / Read CLK_A_Rise[10:8] GIP_0_SET5 - 07h Write / Read CLK_A_Rise[ 7:0] - 08h Write / Read GIP_0_SET6 - 09h Write / Read GIP_0_SET7 - 0Ah Write / Read GIP_0_SET8 - 0Bh Write / Read GIP_0_SET9 - 0Ch Write / Read GIP_0_SET10 - 0Dh Write / Read GIP_0_SET11 - 0Eh Write / Read GIP_0_SET12 - 0Fh Write / Read GIP_0_SET13 - 10h Write / Read GIP_0_SET14 - 11h Write / Read GIP_0_SET15 - 12h Write / Read GIP_0_SET16 - 13h Write / Read GIP_0_SET17 - 14h Write / Read GIP_0_SET18 - 15h Write / Read GIP_0_SET19 - 16h Write / Read GIP_0_SET20 - 17h Write / Read GIP_0_SET21 - 18h Write / Read GIP_0_SET22 - 19h Write / Read GIP_0_SET23 - 1Ah Write / Read GIP_0_SET24 - 1Bh Write / Read GIP_0_SET25 - 1Ch Write / Read GIP_0_SET26 - 1Dh Write / Read GIP_0_SET27 - Page 6 Command Set 20h~27h : GIPCTRL2 (GIP Control 2) Command Write / Read Parameter Default (Hex)D7 D6 D5 D4 D3 D2 D1 D0 20h Write / Read GIP_1_SET0 - 21h Write / Read GIP_1_SET1 - 22h Write / Read GIP_1_SET2 - 23h Write / Read GIP_1_SET3 - 24h Write / Read GIP_1_SET4 - 25h Write / Read GIP_1_SET5 - 26h Write / Read GIP_1_SET6 - 27h Write / Read GIP_1_SET7 -

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 139 of 328 Page 6 Command Set 30h~40h : GIPCTRL3 (GIP Control 3) Command Write / Read Parameter Default (Hex)D7 D6 D5 D4 D3 D2 D1 D0 30h Write / Read GIP_2_SET0 - 31h Write / Read GIP_2_SET1 - 32h Write / Read GIP_2_SET2 - 33h Write / Read GIP_2_SET3 - 34h Write / Read GIP_2_SET4 - 35h Write / Read GIP_2_SET5 - 36h Write / Read GIP_2_SET6 - 37h Write / Read GIP_2_SET7 - 38h Write / Read GIP_2_SET8 - 39h Write / Read GIP_2_SET9 - 3Ah Write / Read GIP_2_SET10 - 3Bh Write / Read GIP_2_SET11 - 3Ch Write / Read GIP_2_SET12 - 3Dh Write / Read GIP_2_SET13 - 3Eh Write / Read GIP_2_SET14 - 3Fh Write / Read GIP_2_SET15 - 40h Write / Read GIP_2_SET16 - Page 6 Command Set 52h : GVLOCTRL 1(GOUT_VGLO Control 1) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 1 0 1 0 0 1 0 52h st Parameter Write / Read 0 0 0 1 GOUT_VGLO_SO [3:0] 11h Page 6 Command Set 53h : GVLOCTRL 2(GOUT_VGLO Control 2) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 1 0 1 0 0 1 1 53h st Parameter Write / Read 0 0 0 1 GOUT_VGLO_DSP[3:0] 10h Page 6 Command Set 54h : GVHOCTRL (GOUT_VGHO Control) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 1 0 1 0 1 0 0 54h st Parameter Write / Read 0 GOUT_VGHO[2:0] 0 0 0 1 11h

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 140 of 328 4.2.8. Page 7 Command List Page 7 Command Set 02h : PWBCTRL (Power Bias control ) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 0 0 0 0 1 0 02h st Parameter Write / Read 0 DDVDL_CLP_ISC [2:0] 0 DDVDH_CLP_ISC [2:0] 01h Page 7 Command Set 06h : VCLCTRL (VCL Control ) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 0 0 0 1 1 0 06h st Parameter Write / Read 0 0 0 VCLOPT 0 0 VCL_CLP[1:0] 01h Page 7 Command Set 17h : VGLREGEN (VGL_REG EN) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 0 1 0 1 1 1 17h st Parameter Write / Read 0 0 1 VGLREG_ EN 0 0 1 0 22h Page 7 Command Set 18h : VREG12EN (VREG1/2OUT ENABLE) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 0 1 1 0 0 0 18h st Parameter Write / Read 0 0 0 VREG EN 1 1 0 1 0Dh Page 7 Command Set E1h : TIMECTRL (TIME CONTROL) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 1 1 1 0 0 0 0 1 E1h st Parameter Write / Read TIME_SHIFT_ERR[3:0] 1 0 0 1 09h

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 141 of 328 4.3. Page 0 Command Description 4.3.1. NOP (00h) Page 0 Command Set 00h : NOP (No Operation) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 0 0 0 0 0 0 00h st Parameter - No parameter - This command is an empty command; it does not have any effect on the ILI9806E. X = void Restriction To enable this command, “Page 0 Command Set enable register (FFh) ” must set first. Register Availability Status Availability Normal Mode On, Sleep Out Yes Sleep Out Yes Sleep In Yes Default Status Default Value Power On Sequence N/A S/W Reset N/A H/W Reset N/A

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 142 of 328 4.3.2. Software Reset (01h) Page 0 Command Set 01h : SWRESET (Software Reset) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 0 0 0 0 0 1 01h st Parameter - No parameter - When the Software Reset command is written, it causes software reset. It resets the commands and parameters to their S/W Reset default values. (See default tables in each command description.) X = void Restriction 1. To enable this command, “Page 0 Command Set enable register (FFh) ” must set first. 2. It is necessary to wait 5msec before sending a new command following software reset. The display module loads all display suppliers’ factory default values to the registers during this 5msec. If Software Reset is applied during Sleep Out mode, it will be necessary to wait 120msec before sending Sleep Out command. The Software Reset command cannot be sent during Sleep Out sequence. Register Availability Status Availability Normal Mode On, Sleep Out Yes Sleep Out Yes Sleep In Yes Default Status Default Value Power On Sequence N/A S/W Reset N/A H/W Reset N/A

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 143 of 328 4.3.3. Read Number of the Errors on DSI (05h) Page 0 Command Set 05h : RDNUMED (Read Number of the Errors on DSI) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 0 0 0 1 0 1 05h st Parameter Read P[7:0] XXh The parameter tells the number of errors on DSI. The more details of the bits are described as below. P [7...0] bits are set to ‘0’s (as well as RDDSM(0Eh)’s D0 is set ‘0’ at the same time) after the second parameter information is X = void Restriction To read this command, “Page 0 Command Set enable register (FFh) ” must set first. Register Availability Status Availability Normal Mode On, Sleep Out Yes Sleep Out Yes Sleep In Yes Default Status Default Value Power On Sequence 8’h00 S/W Reset 8’h00 H/W Reset 8’h00

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 144 of 328 4.3.4. Read Display Power Mode (0Ah) Page 0 Command Set 0Ah : RDDPM (Read Display Power Mode) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 0 0 1 0 1 0 0Ah st Parameter Read BSTON 0 0 SLPOUT NORON DISON 0 0 XXh This command indicates the current status of the display as described in the table below. Bit Description Value Status D7 Booster Voltage Status 0 Booster Off or has a fault.

1 Booster On and working OK

D6 Not Defined -- Set to ‘0’ D5 Not Defined -- Set to ‘0’ D4 Sleep In/Out 0 Sleep In Mode

1 Sleep Out Mode

D3 Display Normal Mode On/Off 0 Display Normal Mode Off.

1 Display Normal Mode On

D2 Display On/Off 0 Display is Off.

1 Display is On

D1 Not Defined -- Set to ‘0’ D0 Not Defined -- Set to ‘0’ X = void Restriction To read this command, “Page 0 Command Set enable register (FFh) ” must set first. Register Availability Status Availability Normal Mode On, Sleep Out Yes Sleep Out Yes Sleep In Yes Default Status Default Value Power On Sequence 8’h08 S/W Reset 8’h08 H/W Reset 8’h08

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 145 of 328 4.3.5. Read Display MADCTL (0Bh) Page 0 Command Set 0Bh : RDDMADCTL (Read Display MADCTL) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 0 0 1 0 1 1 0Bh st Parameter Read 0 0 0 0 BGR 0 SS GS XXh This command indicates the current status of the display as described in the table below. Bit Description Value Status D7 Reserved 0 Reserved, so it is set to ‘0’ D6 Reserved 0 Reserved, so it is set to ‘0’ D5 Reserved 0 Reserved, so it is set to ‘0’ D4 Reserved 0 Reserved, so it is set to ‘0’ D3 RGB/BGR Order 0 RGB (When MADCTL D3=’0’) 1 BGR (When MADCTL D3=’1’). D2 Reserved 0 Reserved, so it is set to ‘0’ D1 Source scan sequence 0 Source output Left to Right

1 Source output Right to Left

D0 Gate scan sequence 0 Gate output Top to Bottom

1 Gate output Bottom to Top

X = void. Restriction To read this command, “Page 0 Command Set enable register (FFh) ” must set first. Register Availability Status Availability Normal Mode On, Sleep Out Yes Sleep Out Yes Sleep In Yes Default Status Default Value Power On Sequence 8’h00 S/W Reset 8’h00 H/W Reset 8’h00

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 146 of 328 4.3.6. Read Display Pixel Format (0Ch) Page 0 Command Set 0Ch : RDDCOLMOD (Read Display COLMOD) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 0 0 0 0 0 0 00h st Parameter Read 0 DPI [2:0] 0 0 0 0 XXh This command indicates the current status of the display as described in the table below: DPI [2:0] RGB Interface Format 1 0 1 16-bit / pixel 1 1 0 18-bit / pixel 1 1 1 24-bit / pixel Others Reserved X = void. Restriction To read this command, “Page 0 Command Set enable register (FFh) ” must set first. Register Availability Status Availability Normal Mode On, Sleep Out Yes Sleep Out Yes Sleep In Yes Default Status Default Value Power On Sequence 8’h70 S/W Reset 8’h70 H/W Reset 8’h70

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 147 of 328 4.3.7. Read Display Image Mode (0Dh) Page 0 Command Set 0Dh : RDDIM (Read Display Image Mode) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 0 0 1 1 0 1 0Dh st Parameter Read 0 0 INVON ALLPON ALLPOFF GCS[2:0] XXh This command indicates the Image Mode status of the display as described : Bit Description Value Status D5 Inversion On/Off 0 Inversion is Off. 1 Inversion is On. D4 All Pixels On 0 Normal Display

1 White Display

D3 All Pixels Off 0 Normal Display

1 Black Display

D[2:0] Gamma Cure Selection Gamma Set (26h) Parameter 000 Gamma curve 1 GC0(G2.2) Others Not defined Not defined X = void. Restriction To read this command, “Page 0 Command Set enable register (FFh) ” must set first. Register Availability Status Availability Normal Mode On, Sleep Out Yes Sleep Out Yes Sleep In Yes Default Status Default Value Power On Sequence 8’h00 S/W Reset 8’h00 H/W Reset 8’h00

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 148 of 328 4.3.8. Read Display Signal Mode (0Eh) Page 0 Command Set 0Eh : RDDSM (Read Display Signal Mode) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 0 0 1 1 1 0 0Eh st Parameter Read TEON 0 HSON VSON PCLKON DEON 0 EODSI XXh This command indicates the current status of the display as described in the table below: Bit Description Value Status D7 Tearing Effect Line On/Off 0 Tearing Effect Line Off. 1 Tearing Effect Line On. D6 Reserved 0 Reserved, so it is set to ‘0’ D5 Horizontal Sync. (RGB I/F) On/Off 0 HS line is low

1 HS line is high

D4 Vertical Sync. (RGB I/F) On/Off 0 VS line is low

1 VS line is high

D3 Pixel Clock (PCLK, RGB I/F) On/Off 0 PCLK line is low

1 PCLK line is high

D2 DE (Data Enable, RGB I/F) On/Off 0 DE Line is low

1 DE Line is high

D1 Reserved 0 Reserved, so it is set to ‘0’ D0 Error on DSI, 0 No Error on DSI

1 Error on DSI

X = void. Restriction To read this command, “Page 0 Command Set enable register (FFh) ” must set first. Register Availability Status Availability Normal Mode On, Sleep Out Yes Sleep Out Yes Sleep In Yes Default Status Default Value Power On Sequence 8’h00 S/W Reset 8’h00 H/W Reset 8’h00

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 149 of 328 4.3.9. Read Display Sel f-Diagnostic Result (0Fh) Page 0 Command Set 0Fh : RDDSDR (Read Display Self-Diagnostic Result) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 0 0 1 1 1 1 0Fh st Parameter Read REGLD FUNDT 0 0 0 0 0 0 XXh This command indicates the status of the display self-diagnostic results after Sleep Out command as described: Bit Description Action D7 Register Loading Detection Invert the D7 bit when the OTP and register values are same. D6 Functionality Detection Invert the D6 bit wh en the chip met User’s functionality requirements D5 Not Used Set to ‘0’ D4 Not Used Set to ‘0’ D3 Not Used Set to ‘0’ D2 Not Used Set to ‘0’ D1 Not Used Set to ‘0’ D0 Not Used Set to ‘0’ X = void. Restriction To read this command, “Page 0 Command Set enable register (FFh) ” must set first. Register Availability Status Availability Normal Mode On, Sleep Out Yes Sleep Out Yes Sleep In Yes Default Status Default Value Power On Sequence 8’h00 S/W Reset 8’h00 H/W Reset 8’h00

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 150 of 328 4.3.10. Sleep In (10h) Page 0 Command Set 10h : SLPIN (Sleep In) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 0 1 0 0 0 0 10h st Parameter - No parameter - This command causes the ILI9806E to enter the minimum power consumption mode. In this mode the ILI4002 and ILI4003 control signal is stopped, Internal oscillator is stopped, and panel scanning is stopped. X = Void Restriction 1. To enable this command, “Page 0 Command Set enable register (FFh) ” must set first. 2. This command has no effect when module is already in Sleep In mode. Sleep In Mode can only be left by the Sleep Out Command (11h). It is necessary to wait 5msec before sending the next command; this is to allow time for the supply voltages and clock circuits to stabilize. It is necessary to wait 120msec after sending Sleep Out command (when in Sleep In Mode) before the Sleep In command can be sent. Register Availability Status Availability Normal Mode On, Sleep Out Yes Sleep Out Yes Sleep In Yes Default Status Default Value Power On Sequence Sleep In Mode S/W Reset Sleep In Mode H/W Reset Sleep In Mode

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 151 of 328 4.3.11. Sleep Out (11h) Page 0 Command Set 11h : SLPOUT (Sleep Out) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 0 1 0 0 0 1 11h st Parameter - No parameter - This command turns off sleep mode. In this mode e.g. the ILI4002 and ILI4003 control signal is enabled, Internal oscillator is started, and panel scanning is started. X = Void Restriction 1. To enable this command, “Page 0 Command Set enable register (FFh) ” must set first. 2. This command has no effect when module is already in Sleep Out mode. Sleep Out mode can be left by the Sleep In command (10h), S/W reset command (01h) or H/W reset. It is necessary to wait 5msec before sending next command; this is to allow time for the supply voltages and clock circuits to stabilize. The ILI9806E loads all display supplier’s factory default values to the registers during this 5msec and there cannot be any abnormal visual effect on the display image if factory default and register values are same when this load is done and when the ILI9806E is already Sleep Out mode. During this 5msec, ILI9806E is running self-diagnostic functions. It is necessary to wait 120msec after sending the Sleep In command (when in Sleep Out mode) before the Sleep Out command can be sent. Register Availability Status Availability Normal Mode On, Sleep Out Yes Sleep Out Yes Sleep In Yes Default Status Default Value Power On Sequence Sleep In Mode S/W Reset Sleep In Mode H/W Reset Sleep In Mode

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 152 of 328 4.3.12. Normal Display Mode On (13h) Page 0 Command Set 13h : NORON (Normal Display Mode On) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 0 1 0 0 1 1 13h st Parameter - No parameter - This command returns the display to Normal Display Mode. X = Void Restriction 1. To enable this command, “Page 0 Command Set enable register (FFh) ” must set first. 2. This command has no effect when Normal Display Mode is active. Register Availability Status Availability Normal Mode On, Sleep Out Yes Sleep Out Yes Sleep In Yes Default Status Default Value Power On Sequence Normal Display Mode On S/W Reset Normal Display Mode On H/W Reset Normal Display Mode On

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 153 of 328 4.3.13. Display Inversion Off (20h) Page 0 Command Set 20h : INVOFF (Display Inversion Off) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 1 0 0 0 0 0 20h st Parameter - No parameter - This command is used to recover from Display Inversion On mode. This command doesn’t change any other status. X = Void Restriction 1. To enable this command, “Page 0 Command Set enable register (FFh) ” must set first. 2. This command has no effect when module is already in Display Inversion Off mode. Register Availability Status Availability Normal Mode On, Sleep Out Yes Sleep Out Yes Sleep In Yes Default Status Default Value Power On Sequence Display Inversion Off S/W Reset Display Inversion Off H/W Reset Display Inversion Off

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 154 of 328 4.3.14. Display Inversion On (21h) Page 0 Command Set 21h : INVON (Display Inversion ON) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 1 0 0 0 0 1 21h st Parameter - No parameter - This command is used to enter into Display Inversion On mode. This command doesn’t change any other status. To exit Display Inversion On mode, the Display Inversion Off command (20h) should be written. X = Void Restriction 1. To enable this command, “Page 0 Command Set enable register (FFh) ” must set first. 2. This command has no effect when the ILI9806E is already in Inversion On mode. Register Availability Status Availability Normal Mode On, Sleep Out Yes Sleep Out Yes Sleep In Yes Default Status Default Value Power On Sequence Display Inversion Off S/W Reset Display Inversion Off H/W Reset Display Inversion Off

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 155 of 328 4.3.15. All Pixel Off (22h) Page 0 Command Set 22h : ALLPOFF (All pixels off) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 1 0 0 0 1 0 22h st Parameter - No parameter - This command turns the display panel black in ‘Sleep Out’ mode and a status of the’ Display On/Off’ register can be ‘on’ or ‘off’. This command does not change any other status ‘All Pixels On’, ’Normal Display Mode On’ commands are used to leave this mode. Restriction 1. To enable this command, “Page 0 Command Set enable register (FFh) ” must set first. 2. This command has no effect when the ILI9806E is already in All Pixels Off mode. Register Availability Status Availability Normal Mode On, Sleep Out Yes Sleep Out Yes Sleep In Yes Default Status Default Value Power On Sequence OFF S/W Reset OFF H/W Reset OFF

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 156 of 328 4.3.16. All Pixel On (23h) Page 0 Command Set 23h : ALLPON (All pixels on) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 1 0 0 0 1 1 23h st Parameter - No parameter - This command turns the display panel white in ‘Sleep Out ‘ mode and a status of the ‘Display On/Off’ register can be ‘on’ or ‘off’. This command does not change any other status. ‘All Pixels Off’, ’Normal Display Mode On’– commands are used to leave this mode. Restriction 1. To enable this command, “Page 0 Command Set enable register (FFh) ” must set first. 2. This command has no effect when ILI9806E is already in All Pixels On mode. Register Availability Status Availability Normal Mode On, Sleep Out Yes Sleep Out Yes Sleep In Yes Default Status Default Value Power On Sequence OFF S/W Reset OFF H/W Reset OFF

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 157 of 328 4.3.17. Gamma Set (26h) Page 0 Command Set 26h : GAMSET (Gamma Set) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 1 0 0 1 1 0 26h st Parameter Write GC[7:0] 01h This command is used to select the desired Gamma curve for the current display. A maximum of 1 fixed Gamma curves can be selected. The curve is selected by setting the appropriate bit in the parameter as described in the Table: GC[7:0] Parameter Curve Selected 01h GC0 Gamma curve 1 (G2.2) Others Not defined Not defined Note: All others value are undefined. X = Void Restriction 1. To enable this command, “Page 0 Command Set enable register (FFh) ” must set first. 2. Values of GC [7:0] not shown in table above are invalid and will not change the current selected Gamma curve until valid value is received. Register Availability Status Availability Normal Mode On, Sleep Out Yes Sleep Out Yes Sleep In Yes Default Status Default Value Power On Sequence 8’h01 S/W Reset 8’h01 H/W Reset 8’h01

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 158 of 328 4.3.18. Display Off (28h) Page 0 Command Set 28h : DISOFF (Display Off) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 1 0 1 0 0 0 28h st Parameter - No parameter - This command is used to enter into Display Off mode. In this mode, the output data is disabled and blank page inserted. This command makes no change any other status. There will be no abnormal visible effect on the display. X = Void Restriction 1. To enable this command, “Page 0 Command Set enable register (FFh) ” must set first. 2. This command has no effect when module is already in Display Off mode. Register Availability Status Availability Normal Mode On, Sleep Out Yes Sleep Out Yes Sleep In Yes Default Status Default Value Power On Sequence Display Off S/W Reset Display Off H/W Reset Display Off

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 159 of 328 4.3.19. Display ON (29h) Page 0 Command Set 29h : DISON (Display ON) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 1 0 1 0 0 1 29h st Parameter - No parameter - This command is used to recover from Display Off mode. Output data is enabled. This command does not change any other status. X = Void Restriction 1. To enable this command, “Page 0 Command Set enable register (FFh) ” must set first. 2. This command has no effect when the ILI9806E is already in Display on mode. Register Availability Status Availability Normal Mode On, Sleep Out Yes Sleep Out Yes Sleep In Yes Default Status Default Value Power On Sequence Display Off S/W Reset Display Off H/W Reset Display Off

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 160 of 328 4.3.20. Tearing Eff ect Line Off (34h) Page 0 Command Set 34h : TEOFF (Tearing Effect Line Off) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 1 1 0 1 0 0 34h st Parameter - No parameter - Description This command is used to turn off the Display module’ s Tearing Effect output signal (Active Low) from the TE signal line. Restriction 1. To enable this command, “Page 0 Command Set enable register (FFh) ” must set first. 2. This command has no effect when the Tearing Effect output is already off. Register Availability Status Availability Normal Mode On, Sleep Out Yes Sleep Out Yes Sleep In Yes Default Status Default Value Power On Sequence Tearing Effect Line Off S/W Reset Tearing Effect Line Off H/W Reset Tearing Effect Line Off

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 161 of 328 4.3.21. Tearing Eff ect Line On (35h) Page 0 Command Set 35h : TEON (Tearing Effect Line On) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 1 1 0 1 0 1 35h st Parameter - No parameter - This command is used to turn ON the Tearing Effect output signal from the TE signal line. X = Void Restriction 1. To enable this command, “Page 0 Command Set enable register (FFh) ” must set first. 2. This command has no effect when the Tearing Effect output is already ON. Register Availability Status Availability Normal Mode On, Sleep Out Yes Sleep Out Yes Sleep In Yes Default Status Default Value Power On Sequence Tearing Effect Line Off S/W Reset Tearing Effect Line Off H/W Reset Tearing Effect Line Off

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 162 of 328 4.3.22. Display Access Control (36h) Page 0 Command Set 36h : Display Access Control Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 1 1 0 1 1 0 36h st Parameter Write 0 0 0 0 BGR 0 SS GS 00h This command defines the panel operation mode Symbol Name Description BGR Panel RGB-BGR Order Color selector switch control (0=RGB color filter panel, 1=BGR color filter panel) SS Panel Flip Horizontal Select the S ource driver scan direction on panel module GS Panel Flip Vertical Select the Gate driver scan direction on panel module Note : GS scan direction depend on panel’s design. Top-Left (0,0) means the physical panel location Restriction To enable this command, “Page 0 Command Set enable register (FFh) ” must set first.

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 163 of 328 Register Availability Status Availability Normal Mode On, Sleep Out Yes Sleep Out Yes Sleep In Yes Default Status Default Value BGR_ SS GS Power On Sequence 1b’0 1b’0 1b’0 S/W Reset 1b’0 1b’0 1b’0 H/W Reset 1b’0 1b’0 1b’0

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 164 of 328 4.3.23. Interface Pixel Format (3Ah) Page 0 Command Set 3Ah : COLMOD (Interface Pixel Format) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 1 1 1 0 1 0 3Ah st Parameter Write 0 DPI[2:0] 0 0 0 0 70h This command sets the pixel format. DPI [3:0] selects the pixel format of RGB interface. DPI[2:0] RGB Interface Format 101 1 6 - b i t / p i x e l 110 1 8 - b i t / p i x e l 111 2 4 - b i t / p i x e l X = void Restriction To enable this command, “Page 0 Command Set enable register (FFh) ” must set first. Register Availability Status Availability Normal Mode On, Sleep Out Yes Sleep Out Yes Sleep In Yes Default Status Default Value Power On Sequence 8’h70 S/W Reset 8’h70 H/W Reset 8’h70

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 165 of 328 4.3.24. Write Display Brightness Value (51h) Page 0 Command Set 51h : WRDISBV (Write Display Brightness) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 1 0 1 0 0 0 1 51h st Parameter Write DBV[7:0] XXh This command is used to adjust the brightness value of the display. DBV[7:0]: 8 bit, for display brightness of manual brightness setting and CABC in the ILI9806E. There is a PWM output signal, LEDPWM pin, to control the LED driver IC in order to control display brightness. Restriction To enable this command, “Page 0 Command Set enable register (FFh) ” must set first. Register Availability Status Availability Normal Mode On, Sleep Out Yes Sleep Out Yes Sleep In Yes Default Status Default Value Power On Sequence 8’h00 S/W Reset 8’h00 H/W Reset 8’h00

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 166 of 328 4.3.25. Read Display Brightness Value (52h) Page 0 Command Set 52h : RDDISBV (Read Display Brightness Value) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 1 0 1 0 0 1 0 52h st Parameter Read DBV[7:0] XXh This command is used to return the brightness value of the display. DBV[7:0] is reset when display is in Sleep In mode. DBV[7:0] is ‘0’ when bit BCTRL of “Write CTRL Display (53h)” command is ‘0’. DBV[7:0] is manual set brightness specified with “Write CTRL Display (53h)” command when BCTRL bit is ‘1’. When bit BCTRL of “Write CTRL Display (53h)” command is ‘1’ and D1/D0 bit of “Write Content Adaptive Brightness Control (55h)” command are ‘0’, DBV[7:0] output is the brightness value specified with “ Write Display Brightness (51h)” command. Restriction To read this command, “Page 0 Command Set enable register (FFh) ” must set first. Register Availability Status Availability Normal Mode On, Sleep Out Yes Sleep Out Yes Sleep In Yes Default Status Default Value Power On Sequence 8’h00 S/W Reset 8’h00 H/W Reset 8’h00

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 167 of 328 4.3.26. Write CTRL Display Value (53h) Page 0 Command Set 53h : WRCTRLD (Write Control Display) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 1 0 1 0 0 1 1 53h st Parameter Write X X BCTRL X DD BL X X XXh This command is used to control display brightness. BCTRL: Brightness Control Block On/Off, This bit is always used to switch brightness for display. BCTRL Description

0 Brightness Control Block Off (DBV 7:0]=00h)

1 Brightness Control Block On (DBV[7:0] is active)

DD: Display Dimming Control. This function is only for manual brightness setting. DD Description

0 Display Dimming Off

1 Display Dimming On

BL: Backlight Control On/Off BL Description

0 Backlight Control Off

1 Backlight Control On

Dimming function is adapted to the brightness registers for display when bit BCTRL is changed at DD=1, e.g. BCTRL: 0 -> 1 or 1-> 0. When BL bit change from “On” to “Off”, backlight is turned off without gradual dimming, even if Display Dimming On (DD=1) are selected. X = void Restriction To enable this command, “Page 0 Command Set enable register (FFh) ” must set first. Register Availability Status Availability Normal Mode On, Sleep Out Yes Sleep Out Yes Sleep In Yes Default Status Default Value Power On Sequence 8’h00 S/W Reset 8’h00 H/W Reset 8’h00

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 168 of 328 4.3.27. Read CTRL Display Value (54h) Page 0 Command Set 54h : RDCTRLD (Read Control Display Value) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 1 0 1 0 1 0 0 54h st Parameter Read X X BCTRL X DD BL X X XXh This command is used to control display brightness. BCTRL: Brightness Control Block On/Off, This bit is always used to switch brightness for display. BCTRL Description

0 Brightness Control Block Off (DBV[7:0]=00h)

DD: Display Dimming Control. This function is only for manual brightness setting. DD Description BL: Backlight Control On/Off BL Description X = Void Restriction To read this command, “Page 0 Command Set enable register (FFh) ” must set first. Register Availability Status Availability Normal Mode On, Sleep Out Yes Sleep Out Yes Sleep In Yes Default Status Default Value Power On Sequence 8’h00 S/W Reset 8’h00 H/W Reset 8’h00

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 169 of 328 4.3.28. Write Content Adaptive Brightness Control Value (55h) Page 0 Command Set 55h : WRCABC (Write Content Adaptive Brightness Control) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 1 0 1 0 1 0 1 55h st Parameter Write C[7:4] C[3:0] XXh This command is used to set parameters for image content based adaptive brightness control functionality. There are 4 different modes for content adaptive image functionality. These mode are defined in the table below. C[3:0] Description 0 0 0 0 CABC Off 0 0 0 1 User Interface Image mode 0 0 1 0 Still Picture mode 0 0 1 1 Moving Image mode Other Setting Prohibited Color enhancement level selection. C [7:4] Description 0 0 0 0 Enhancement Disable 1 0 0 0 Low Enhancement 1 0 0 1 Medium Enhancement 1 0 1 1 High Enhancement Other Setting Prohibited X = Void Restriction To enable this command, “Page 0 Command Set enable register (FFh) ” must set first. Register Availability Status Availability Normal Mode On, Sleep Out Yes Sleep Out Yes Sleep In Yes Default Status Default Value C[7:4] C[3:0] Power On Sequence 4’h0 4’h0 S/W Reset 4’h0 4’h0 H/W Reset 4’h0 4’h0

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 170 of 328 4.3.29. Read Content Adaptive Brightness Control Value (56h) Page 0 Command Set 56h : RDCABC (Read Content Adaptive Brightness Control) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 1 0 1 0 1 1 0 56h st Parameter Read C[7:4] C[3:0] XXh This command is used to read the settings for image content based adaptive brightness control functionality. There are 4 different modes for content adaptive image functionality. These modes are defined in the table below. C[3:0] Description 0 0 0 0 CABC Off 0 0 0 1 User Interface Image mode 0 0 1 0 Still Picture mode 0 0 1 1 Moving Image mode Others Prohibited C [7:4] Description 0 0 0 0 Enhancement Disable 1 0 0 0 Low Enhancement 1 0 0 1 Medium Enhancement 1 0 1 1 High Enhancement Others Prohibited X = Void Restriction To read this command, “Page 0 Command Set enable register (FFh) ” must set first. Register Availability Status Availability Normal Mode On, Sleep Out Yes Sleep Out Yes Sleep In Yes Default Status Default Value C[7:4] C[3:0] Power On Sequence 4’h0 4’h0 S/W Reset 4’h0 4’h0 H/W Reset 4’h0 4’h0

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 171 of 328 4.3.30. Write CABC Mini mum Brightness (5Eh) Page 0 Command Set 5Eh : WRCABCMB (Write CABC Minimum Brightness) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 1 0 1 1 1 1 0 5Eh st Parameter Write CMB[7:0] XXh This command is used to set the minimum brightness value of the display for CABC function. CMB[7:0]: CABC minimum brightness control, this parameter is used to set a limit to the amount of brightness reduction allowed. When CABC is active, CABC can not reduce the display br ightness to less than CABC minimum brightness setting. Image processing function works as normal, even if the brightness can not be changed. This function does not affect manual brightness setting. M anual brightness setting does not have a limit on allowable brightness reduction; display brightness can be set less t han CABC minimum brightness. Smooth transition and dimming function work as normal. When display brightness is turned off (BCTRL=0 of “Write CTRL Display (53h)”), CABC minimum brightness setting is ignored. The principle relationship is such that 00h value means the lowest brightness for CABC and FFh value means the highest brightness for CABC. Restriction To enable this command, “Page 0 Command Set enable register (FFh) ” must set first. Register Availability Status Availability Normal Mode On, Sleep Out Yes Sleep Out Yes Sleep In Yes Default Status Default Value Power On Sequence 8’h00 S/W Reset 8’h00 H/W Reset 8’h00

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 172 of 328 4.3.31. Read CABC Minimum Brightness (5Fh) Page 0 Command Set 5Fh : RDCABCMB (Read CABC Minimum Brightness) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 1 0 1 1 1 1 1 5Fh st Parameter Read CMB[7:0] XXh This command returns the minimum brightness value of CABC function. The principle relationship is such that 00h value means the lowest brightness and FFh value means the highest brightness. CMB[7:0] is CABC minimum brightness specified with “Write CABC minimum brightness (5Eh)” command. Restriction To read this command, “Page 0 Command Set enable register (FFh) ” must set first. Register Availability Status Availability Normal Mode On, Sleep Out Yes Sleep Out Yes Sleep In Yes Default Status Default Value Power On Sequence 8’h00 S/W Reset 8’h00 H/W Reset 8’h00

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 173 of 328 4.3.32. Read automatic brightness co ntrol self-diagnostic result (68h) Page 0 Command Set 68h : RDABCSDR (Read automatic brightness control self-diagnostic result) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 1 1 0 1 0 0 0 68h st Parameter Read D[7:6] 0 0 0 0 0 0 XXh This command indicates the status of the display self-diagnostic results for automatic brightness control after Sleep Out command as described in the table below: Bit D7 – Register Loading Detection, see section “Register loading Detection ”. Bit D6 – Functionality Detection, see section “Functionality Detection “. Bits D5, D4, D3, D2, D1 and D0 are for future use and are set to ‘0’. Restriction To read this command, “Page 0 Command Set enable register (FFh) ” must set first. Register Availability Status Availability Normal Mode On, Sleep Out Yes Sleep Out Yes Sleep In Yes Default Status Default Value Power On Sequence 2’h0 S/W Reset 2’h0 H/W Reset 2’h0

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 174 of 328 4.3.33. Read ID1 (DAh) Page 0 Command Set DAh : RDID1 (Read ID1) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 1 1 0 1 1 0 1 0 DAh st Parameter Read ID1[7:0] XXh This read byte is used to track the LCD module/driver version. It is defined by the display supplier (with User’s agreement) and changes each time a revision is made to the display, material or construction specifications. The 1 st parameter is LCD module/driver version ID. The ID1 is programmed by OTP function. X = Void Restriction To read this command, “Page 0 Command Set enable register (FFh) ” must set first. Register Availability Status Availability Normal Mode On, Sleep Out Yes Sleep Out Yes Sleep In Yes Default Status Default Value (Before OTP program) Default Value (After OTP program) Power On Sequence 8’h00 OTP value H/W Reset 8’h00 OTP value

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 175 of 328 4.3.34. Read ID2 (DBh) Page 0 Command Set DBh : RDID2 (Read ID2) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 1 1 0 1 1 0 1 1 DBh st Parameter Read ID2[7:0] XXh This read byte is used to track the LCD module/driver version. It is defined by the display supplier (with User’s agreement) and changes each time a revision is made to the display, material or construction specifications. The 1 st parameter is LCD module/driver version ID. The ID parameter range is from 80h to FFh. The ID2 is programmed by OTP function. X = Void Restriction To read this command, “Page 0 Command Set enable register (FFh) ” must set first. Register Availability Status Availability Normal Mode On, Sleep Out Yes Sleep Out Yes Sleep In Yes Default Status Default Value (Before OTP program) Default Value (After OTP program) Power On Sequence 8’h80 OTP value H/W Reset 8’h80 OTP value

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 176 of 328 4.3.35. Read ID3 (DCh) Page 0 Command Set DCh : RDID3 (Read ID3) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 1 1 0 1 1 1 0 0 DCh st Parameter Read ID3[7:0] XXh This read byte identifies the LCD module/driver. It is specified by User. The 1 st parameter is LCD module/driver ID. The ID3 is programmed by OTP function. X = Void Restriction To read this command, “Page 0 Command Set enable register (FFh) ” must set first. Register Availability Status Availability Normal Mode On, Sleep Out Yes Sleep Out Yes Sleep In Yes Default Status Default Value (Before OTP program) Default Value (After OTP program) Power On Sequence 8’h00 OTP value H/W Reset 8’h00 OTP value

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 177 of 328 4.3.36. Read EXTC Command In SPI Mode (FEh) Page 0 Command Set FEh : RDEXTCSPI(Read EXTC command In SPI) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 1 1 1 1 1 1 1 0 FEh st Parameter Write ext_spi_read_en ext_spi_cnt[6:0] 00h ext_spi_read_en: enable the read function of Page 1/2/3/4/5/6/7 Command and Command FFh in SPI operation mode ext_spi_cnt[6:0]: the Nth parameter which wants to be read out Set Register FEh 1. enable SPI read (ext_spi_read_en=1) 2. Nth parameter to be read out (ext_spi_cnt[6:0]) (Example: Register FEh=81h read 1st parameter) (Example: Register FEh=85h read 5th parameter) Set Register XXh command and read out the Nth Parameter (Ex:read Page1 Register 00h=98h (1st parameter) (Ex:read Register FFh=01~07h (5th parameter) START Read the Command value of Page1~7 in SPI operation mode END SPI read Set Register FEh Disable SPI read (ext_spi_read_en=0) (Register FEh=0xh to enable SPI write mode) Read other command / Parameter in the same page Entry the Page 1 (or Page 2 / 3 / 4 / 5 / 6 / 7) 98h Register Address 1st parameter Protect Key 2nd parameter Device code 1 3rd parameter Device code 2 4th parameter Device code 3 5th parameter Page_select 06h 04h 01h~07hFFhFFh Read command / Parameter in the other page Restriction None

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 178 of 328 Register Availability Status Availability Normal Mode On, Sleep Out Yes Sleep Out Yes Sleep In Yes Default Status Default Value Power ON Sequence 8’h00 S/W Reset 8’h00 H/W Reset 8’h00

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 179 of 328 4.3.37. EXTC Command Set enable register (FFh) Page 0 Command Set FFh : ENEXTC (EXTC command set enable register) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 1 1 1 1 1 1 1 1 FFh st Parameter Write 1 1 1 1 1 1 1 1 FFh nd Parameter Write 1 0 0 1 1 0 0 0 98h rd Parameter Write 0 0 0 0 0 1 1 0 06h th Parameter Write 0 0 0 0 0 1 0 0 04h th Parameter Write / Read Page [7:0] 00h Set the register, 1 st Parameter=FFh, 2 nd Parameter=98h, 3 rd Parameter=06h , 4 th Parameter=04h , 5 th Parameter= Page value to enable “Page command set” available Set the register, 1 st Parameter= any value except for FFh, 2 nd Parameter= any value except for 98h, 3 rd Parameter= any value except for 06h , 4 th Parameter= any value except for 04h , 5 th Parameter= any value, The “Page command set” is unanailable. See Figure 94. “Command Flow”. Restriction None Register Availability Status Availability Normal Mode On, Sleep Out Yes Sleep Out Yes Sleep In Yes Default Status Default Value Power ON Sequence 40’h0000000000 S/W Reset 40’h0000000000 H/W Reset 40’h0000000000

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 180 of 328 4.4. Page 1 Command Description 4.4.1. Read Device Code (00h~02h) Page 1 Command Set 00h :RDID4 (Read ID 4) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 0 0 0 0 0 0 00h st Parameter Read ID4 [23 :16] 98h Page 1 Command Set 01h : RDID4 (Read ID 4) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 0 0 0 0 0 1 01h st Parameter Read ID4 [15 :8] 06h Page 1 Command Set 02h : RDID4 (Read ID 4) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 0 0 0 0 1 0 02h st Parameter Read ID4 [7 :0] 04h Description ID4 [23:0] : mean the IC model name. Restriction To enable this command, “Page 1 Command Set enable register (FFh) ” must set first. Register Availability Status Availability Normal Mode On, Sleep Out Yes Sleep Out Yes Sleep In Yes Default Status Default Value ID4 [23 :0] Power ON Sequence 24’h980604 S/W Reset 24’h980604 H/W Reset 24’h980604

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 181 of 328 4.4.2. Interface Mode Control 1 (08h) Page 1 Command Set 08h : IFMODE 1(Interface Mode Control 1) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 0 0 1 0 0 0 08h st Parameter Write / Read 0 0 0 SDO_STATUS SEPT_SDIO 0 0 0 08h SEPT_SDIO : SEPT_SDIO =0: SPI interface transfer data through SDA pin. SEPT_SDIO =1: SPI interface transfer data through SDI and SDO pins. SDO_STATUS : SDO_STATUS =0: SDO has output enable , SDO pin output tri-state after data hold time period (timing “toh”). SDO_STATUS =1: always output , but without output tri-state. Restriction To enable this command, “Page 1 Command Set enable register (FFh) ” must set first. Register Availability Status Availability Normal Mode On, Sleep Out Yes Sleep Out Yes Sleep In Yes Default Status Default Value SDO_STATUS SEPT_SDIO Power ON Sequence 1’h0 1’h1 S/W Reset No Change No Change H/W Reset 1’h0 1’h1

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 182 of 328 4.4.3. Interface Mode Control 2 (0Ah) Page 1 Command Set 0Ah : IFMODE 2(Interface Mode Control 2) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 0 0 1 0 1 0 0Ah st Parameter Write / Read 0 0 0 0 0 0 0 2LANE_En 00h 2LANE_EN : Enable Data Lane1 LANSEL 2LANE_En Description

0 Disable Data Lane1

1 Enable Data Lane1

0 Enable Data Lane1

1. To enable this command, “Page 1 Command Set enable register (FFh) ” must set first. 2. In MIPI Interface, when user writes this command, must in the LP mode. Register Availability Status Availability Normal Mode On, Sleep Out Yes Sleep Out Yes Sleep In Yes Default Status Default Value 2LANE_En Power ON Sequence 1’h0 S/W Reset No Change H/W Reset 1’h0

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 183 of 328 4.4.4. Display Function Control 1 (20h) Page 1 Command Set 20h : DISCTRL1 (Display Function Control 1) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 1 0 0 0 0 0 20h st Parameter Write / Read 0 0 0 0 0 0 0 SYNC MODE 00h SYNC_MODE: Select the operation mode of RGB interface SYNC_MODE RGB interface selection

0 DE mode

1 SYNC mode

Restriction To enable this command, “Page 1 Command Set enable register (FFh) ” must set first. Register Availability Status Availability Normal Mode On, Sleep Out Yes Sleep Out Yes Sleep In Yes Default Status Default Value SYNC Mode Power ON Sequence 1’h0 S/W Reset No Change H/W Reset 1’h0

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 184 of 328 4.4.5. Display Function Control 2 (21h) Page 1 Command Set 21h : DISCTRL2 (Display Function Control 2) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 1 0 0 0 0 1 21h st Parameter Write / Read 0 0 0 0 VSPL HSPL DPL EPL 01h Sets the operation status of the RGB interface. The setting becomes effective as soon as the command is received. EPL: DE polarity (“0”= Low enable, “1”= High enable) DPL: PCLK polarity set (“0”=data fetched at the rising time, “1”=data fetched at the falling time) HSPL: HS polarity (“0”=Low level sync clock, “1”=High level sync clock) VSPL: VS polarity (“0”= Low level sync clock, “1”= High level sync clock) Restriction To enable this command, “Page 1 Command Set enable register (FFh) ” must set first. Register Availability Status Availability Normal Mode On, Sleep Out Yes Sleep Out Yes Sleep In Yes Default Status Default Value VSPL HSPL DPL EPL Power ON Sequence 1’h0 1’h0 1’h0 1’h1 S/W Reset No Change No Change No Change No Change H/W Reset 1’h0 1’h0 1’h0 1’h1

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 185 of 328 4.4.6. Panel Control 1 (22h) Page 1 Command Set 22h : PANELCTRL1 (Set panel operation mode1) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 1 0 0 0 1 0 22h st Parameter Write / Read 0 0 0 0 BGR_ Panel 0 SS_ Panel GS_ Panel 00h This command defines the panel operation mode BGR_Panel: Symbol Name Description BGR_ Panel Panel RGB-BGR Order Color selector switch control (0=RGB color filter panel, 1=BGR color filter panel) SS_ Panel: Select the shift direction of outputs from the source driver. SS_ Panel Source Output Scan Direction

0 S0 Æ S1441

1 S1441 Æ S0

GS_ Panel: Select the shift direction of outputs from the gate driver. GS_ Panel Gate Output Scan Direction

0 Top Æ Bottom

1 Bottom Æ Top

Note : GS_Panel scan direction depends on panel’s design. Restriction To enable this command, “Page 1 Command Set enable register (FFh) ” must set first. Register Availability Status Availability Normal Mode On, Sleep Out Yes Sleep Out Yes Sleep In Yes Default Status Default Value BGR_ Panel SS_ Panel GS_ Panel Power On Sequence 1’h0 1’h0 1’h0 S/W Reset No Change No Change No Change H/W Reset 1’h0 1’h0 1’h0

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 186 of 328 4.4.7. Panel Control 2 (23h) Page 1 Command Set 23h : PANELCTRL2 (Set panel operation mode2) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 1 0 0 0 1 1 23h st Parameter Write / Read 0 0 0 0 0 0 REV 0 00h This command defines the panel operation mode REV: Normally white or normally black panel select. NBWSEL REV Panel Data Color Source 0 normally white 0x00 Black Largest gamma voltage 0xFF White Smallest gamma voltage

1 Normally black

0x00 Black Smallest gamma voltage 0xFF White Largest gamma voltage

0 Normally black

0x00 Black Smallest gamma voltage 0xFF White Largest gamma voltage 0x00 Black Smallest gamma voltage 0xFF White Largest gamma voltage Restriction To enable this command, “Page 1 Command Set enable register (FFh) ” must set first. Register Availability Status Availability Normal Mode On, Sleep Out Yes Sleep Out Yes Sleep In Yes Default Status Default Value REV Power On Sequence 1’h0 S/W Reset No Change H/W Reset 1’h0

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 187 of 328 4.4.8. Data Complement Setting (24h) Page 1 Command Set 24h : Data Complement Setting Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 1 0 0 1 0 0 24h st Parameter Write / Read 0 0 0 0 0 0 EPF[1:0] 03h EPF[1:0]: Set the data format from 16/18-bit (R,G,B) to 24-bit (r, g, b) that is mapping into the internal circuit. Restriction To enable this command, “Page 1 Command Set enable register (FFh) ” must set first. Register Availability Status Availability Normal Mode On, Sleep Out Yes Sleep Out Yes Sleep In Yes Default Status Default Value EPF[1:0] Power ON Sequence 2’h3 S/W Reset No Change H/W Reset 2’h3

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 188 of 328 4.4.9. Blanking Porch Control1 (25h) Page 1 Command Set 25h : BLKPRH 1 (Blanking Porch 1) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 1 0 0 1 0 1 25h st Parameter Write / Read 0 VFP[6:0] 14h VFP[6:0] : The VFP[6:0] bits specify the line number of vertical front porch period respectively. VFP[6:0] Number of HS of front porch (Dec.)

0000000 Setting prohibited

0000001 Setting prohibited

: : 001110 14 : : 1111101 125 1111110 126 1111111 127 Restriction 1. To enable this command, “Page 1 Command Set enable register (FFh) ” must set first. 2. Vertical porch : Minimum VLW>=1H, VBP>=1H, VFP>=1H Register Availability Status Availability Normal Mode On, Sleep Out Yes Sleep Out Yes Sleep In Yes Default Status Default Value VFP[6:0] Power ON Sequence 7’h14 S/W Reset No Change H/W Reset 7’h14

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 189 of 328 4.4.10. Blanking Porch Control 2 (26h) Page 1 Command Set 26h : BLKPRH 2 (Blanking Porch 2) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 1 0 0 1 1 0 26h st Parameter Write / Read 0 VBP[6:0] 14h VBP[6:0] : The VBP[6:0] bits specify the line number of vertical back porch period respectively. VBP[6:0] Number of HS of back porch(Dec.) : : 001110 14 : : 1111101 125 1111110 126 1111111 127 We give a illustration of VBP[6:0] setting as below. VS VBP[6:0] Blanking porch setting VLW VBP VBP[6:0]=(VLW+VBP) line number Restriction 1. To enable this command, “Page 1 Command Set enable register (FFh) ” must set first. 2. Vertical porch : Minimum VLW>=1H, VBP>=1H, VFP>=1H Register Availability Status Availability Normal Mode On, Sleep Out Yes Sleep Out Yes Sleep In Yes Default Status Default Value VBP[6:0] Power ON Sequence 7’h14 S/W Reset No Change H/W Reset 7’h14

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 190 of 328 4.4.11. Blanking Porch Control 3~4 (27h~28h) Page 1 Command Set 27h : BLKPRH 3 (Blanking Porch 3) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 1 0 0 1 1 1 27h st Parameter Write / Read HBP[7:0] 05h Page 1 Command Set 28h : BLKPRH 4 (Blanking Porch 4) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 1 0 1 0 0 0 28h st Parameter Write / Read 0 0 0 0 0 0 HBP[9:8] 00h HBP[9:0]: The HBP [9:0] bits specify the pclk number of horizontal back porch period respectively. HBP[9:0] Number of PCLK of the back porch (Dec.)

0000000000 Setting prohibited

0000000001 Setting prohibited

0000000010 Setting prohibited

0000000011 Setting prohibited

0000000100 Setting prohibited

0000000101 5 (HBP [9:0] default) : : 0000010100 20 : : 0010011110 158 1111111101 1021 1111111110 1022 1111111111 1023 We give a illustration of HBP[9:0] setting as below. HS HBP[9:0] Blanking porch setting HLW HBP HBP[9:0]=(HLW+HBP) line number Restriction 1. To enable this command, “Page 1 Command Set enable register (FFh) ” must set first. 2. Horizontal porch : Minimum HLW>=1 clock, HBP>=2 clocks , HFP>=2 clocks Register Availability Status Availability Normal Mode On, Sleep Out Yes Sleep Out Yes Sleep In Yes

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 191 of 328 Default Status Default Value HBP[9:0] Power ON Sequence 10’h005 S/W Reset No Change H/W Reset 10’h005

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 192 of 328 4.4.12. Resolution Control (30h) Page 1 Command Set 30h : RESCTRL (Resolution Control ) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 1 1 0 0 0 0 30h st Parameter Write / Read 0 0 0 0 0 RES[2:0] 02h RES[2:0]: These bits are used to select panel resolution. T h e r e l a t i o n b e t w e e n b i t s e t t i n g a n d r e s o l u t i o n i s i l l u s t r a t e d a s b e l o w t a b l e . RES[2:0] Resolution 000 480X864 001 480X854 010 480X800 011 480X640 100 480X720 Other setting are inhibited Restriction To enable this command, “Page 1 Command Set enable register (FFh) ” must set first. Register Availability Status Availability Normal Mode On, Sleep Out Yes Sleep Out Yes Sleep In Yes Default Status Default Value Res[2:0] Power ON Sequence 3’h2 S/W Reset No Change H/W Reset 3’h2

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 193 of 328 4.4.13. Display Inversion Control (31h) Page 1 Command Set 31h : INVTR (Display Inversion Control) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 1 1 0 0 0 1 31h st Parameter Write / Read 0 0 0 0 NLA[3:0] 00h Display inversion mode setting NLA[3:0]: Inversion setting in full colors normal mode (Normal Mode On) NLA [3:0] Inversion 0 0 0 0 Column inversion 0 0 1 0 2 dot inversion Other setting are inhibited Column Inversion 1st frame 2 line 1 line 3 line 4 line 2nd frame 2 line 1 line 3 line 4 line - + - + - - + - + - - - - + - + - - + - + - - - 1st frame 2 line 1 line 3 line 4 line 2nd frame 2 line 1 line 3 line 4 line - + - + - - +- + - - - - + - + - - +- + - 2-Dot Inversion Restriction To enable this command, “Page 1 Command Set enable register (FFh) ” must set first. Register Availability Status Availability Normal Mode On, Sleep Out Yes Sleep Out Yes Sleep In Yes

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 194 of 328 Default Status Default Value NLA [3:0] Power ON Sequence 4’h0 S/W Reset No Change H/W Reset 4’h0

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 195 of 328 4.4.14. Dithering Enable (34h) Page 1 Command Set 34h : DITHE (Dithering Enable) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 1 1 0 1 0 0 34h st Parameter Write / Read 0 0 0 0 0 0 0 Dith_en 00h Dith_en: 0 : dithering function disable 1 : dithering function enable Restriction To enable this command, “Page 1 Command Set enable register (FFh) ” must set first. Register Availability Status Availability Normal Mode On, Sleep Out Yes Sleep Out Yes Sleep In Yes Default Status Default Value Dith_en Power ON Sequence 1’h0 S/W Reset No Change H/W Reset 1’h0

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 196 of 328 4.4.15. Source Signal Adjust (35h) Page 1 Command Set 35h : Source Signal Adjust Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 1 1 0 1 0 1 35h st Parameter Write / Read 0 0 0 0 0 CHOPPER_SEL_REG[2:0] 06h CHOPPER_SEL_REG [2:0]: Source Op-amp chopper function option. Chopper_SEL_REG [2] Chopper_SEL_REG [1] Chopper_SEL_REG [0] Description 0 0 0 chopper disable 0 0 1 1 frame chopper 0 1 0 2 frame chopper 0 1 1 3 frame chopper 1 0 0 1 line chopper (1 frame chopper polarity change) 1 0 1 2 line chopper ( 1 f r a m e c h o p p e r p o l a r i t y c h a n g e ) 1 1 0 1 line chopper ( 2 f r a m e c h o p p e r p o l a r i t y c h a n g e ) 1 1 1 2 line chopper ( 2 f r a m e c h o p p e r p o l a r i t y c h a n g e ) Note: TOP_CLK : 4* TOSC_CLK = 0.22us Restriction To enable this command, “Page 1 Command Set enable register (FFh) ” must set first. Register Availability Status Availability Normal Mode On, Sleep Out Yes Sleep Out Yes Sleep In Yes Default Status Default Value CHOPPER_SEL_REG [2:0] Power On Sequence 3’h6 S/W Reset No Change H/W Reset 3’h6

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 197 of 328 4.4.16. Power Control 1 (40h) Page 1 Command Set 40h : PWCTRL 1 (Power Control 1) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 1 0 0 0 0 0 0 40h st Parameter Write / Read EXB1T 0 EXT_CPCK_SEL[1:0] BT [3:0] 15h EXB1T : Selects the external charge pump circuit control for DDVDH and DDVDL. EXB1T DDVDH / DDVDL

0 Internal charge pump circuit

1 External charge pump circuit control

(ILI4002 and ILI4003) EXT_CPCK_SEL[1:0] : Pumping clock control signals selection to external control IC (ILI4002 and ILI4003).Set the register before Sleep Out(R11h), when external pumping control is used. EXT_CPCK_SEL[1:0] EXTP & EXTN Output 0 0 Output x 1.5 waveform 0 1 Output x 2 waveform 1 0 Output x 3 waveform 1 1 Output Low (power down) BT[3:0] : DDVDH / DDVDL voltage control BT[3:0] DDVDH / DDVDL voltage

0000 V C I X 2 / V C I X - 2

0001 V C I X 2 / V C I X - 2 . 5

0010 V C I X 2 / V C I X - 3

0011 V C I X 2 / V C I X - 3

0100 V C I X 2 . 5 / V C I X - 2 0101 V C I X 2 . 5 / V C I X - 2 . 5 0110 V C I X 2 . 5 / V C I X - 3 0111 V C I X 2 . 5 / V C I X - 3

1000 V C I X 3 / V C I X - 2

1001 V C I X 3 / V C I X - 2 . 5

1010 V C I X 3 / V C I X - 3

1011 V C I X 3 / V C I X - 3

Other setting are inhibited Restriction To enable this command, “Page 1 Command Set enable register (FFh) ” must set first. Register Availability Status Availability Normal Mode On, Sleep Out Yes Sleep Out Yes Sleep In Yes

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 198 of 328 Default Status Default Value EXB1T EXT_CPCK_SEL [1:0] BT [3:0] Power ON Sequence 1’h0 2’h1 4’h5 S/W Reset No Change No Change No Change H/W Reset 1’h0 2’h1 4’h5

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 199 of 328 4.4.17. Power Control 2 (41h) Page 1 Command Set 41h : PWCTRL 2 (Power Control 2) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 1 0 0 0 0 0 1 41h st Parameter Write / Read 0 DDVDH_CLP[2:0] 0 DDVDL_CLP [2:0] 22h DDVDH_CLP [2:0] : Sets the DDVDH clamp level. DDVDH_CLP [2:0] DDVDH clamp level (V) 0 0 0 4.6 0 0 1 4.8 0 1 0 5.0 0 1 1 5.2 1 0 0 5.4 1 0 1 5.6 1 1 0 5.8 1 1 1 6.0 DDVDL_CLP [2:0]: Sets the DDVDL clamp level DDVDL_CLP [2:0] DDVDL clamp level (V) 0 0 0 -4.6 0 0 1 -4.8 0 1 0 -5.0 0 1 1 -5.2 1 0 0 -5.4 1 0 1 -5.6 1 1 0 -5.8 1 1 1 -6.0 Restriction To enable this command, “Page 1 Command Set enable register (FFh) ” must set first.

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 200 of 328 Register Availability Status Availability Normal Mode On, Sleep Out Yes Sleep Out Yes Sleep In Yes Default Status Default Value D D V D H _ C L P [ 2 : 0 ] D D V D L _ C L P [ 2 : 0 ] Power ON Sequence 3’h2 3’h2 S/W Reset No Change No Change H/W Reset 3’h2 3’h2

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 201 of 328 4.4.18. Power Control 3 (42h) Page 1 Command Set 42h : PWCTRL 3 (Power Control 3) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 1 0 0 0 0 1 0 42h st Parameter Write / Read 0 0 VGH_CP[1:0] 0 0 VGL_CP[1:0] 02h VGH_CP [1:0]: Sets the factor used in the step-up circuits for VGH. Select the optimal step-up factor for the operating voltage. To reduce power consumption, set a smaller factor. VGH_CP [1:0] VGH Output 0 0 2DDVDH-DDVDL 0 1 D D V D H + V C I P - D D V D L 1 0 D D V D H + V C I P - V C L 1 1 2DDVDH-DDVDL VGL_CP [1:0]: Sets the factor used in the step-up circuits for VGL. Select the optimal step-up factor for the operating voltage. To reduce power consumption, set a smaller factor. VGL_CP [1:0] VGL Output 0 0 2DDVDL-DDVDH 0 1 2 D D V D L - V C I P 1 0 D D V D L + V C L - V C I P 1 1 DDVDL-DDVDH Restriction To enable this command, “Page 1 Command Set enable register (FFh) ” must set first. Register Availability Status Availability Normal Mode On, Sleep Out Yes Sleep Out Yes Sleep In Yes Default Status Default Value VGH_CP[1:0] VGL_CP[1:0] Power ON Sequence 2’h0 2’h2 S/W Reset No Change No Change H/W Reset 2’h0 2’h2

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 202 of 328 4.4.19. Power Control 4 (43h) Page 1 Command Set 43h : PWCTRL 4 (Power Control 4) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 1 0 0 0 0 1 1 43h st Parameter Write / Read VGH_CLPEN 0 0 0 VGH_CLP[3:0] 09h VGH _CLPEN: Enable VGH clamp level VGH _CLPEN VGH clamp function

0 Disable

1 Enable

VGH_CLP[3:0]: Sets the VGH clamp level VGH_CLP[3:0] VGH clamp level (V) 0000 1 0 . 5 0001 1 1 . 0 0010 1 1 . 5 0011 1 2 . 0 0100 1 2 . 5 0101 1 3 . 0 0110 1 3 . 5 0111 1 4 . 0 1000 1 4 . 5 1001 1 5 . 0 1010 1 5 . 5 1011 1 6 . 0 1100 1 6 . 5 1101 1 7 . 0 1110 1 7 . 5 1111 1 8 . 0 Restriction To enable this command, “Page 1 Command Set enable register (FFh) ” must set first. Register Availability Status Availability Normal Mode On, Sleep Out Yes Sleep Out Yes Sleep In Yes Default Status Default Value VGH_CLPEN VGH_CLP[3:0] Power ON Sequence 1’h0 4’h9 S/W Reset No Change No Change H/W Reset 1’h0 4’h9

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 203 of 328 4.4.20. Power Control 5 (44h) Page 1 Command Set 44h : PWCTRL 5 (Power Control 5) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 1 0 0 0 1 0 0 44h st Parameter Write / Read VGL_CLPEN 0 0 0 VGL_CLP[3:0] 86h VGL _CLPEN: Enable VGL clamp level VGL _CLPEN VGL clamp function VGL_CLP[3:0]: Sets the VGL clamp level VGL_CLP[3:0] VGL clamp level (V) 0000 - 7 . 0 0001 - 7 . 5 0010 - 8 . 0 0011 - 8 . 5 0100 - 9 . 0 0101 - 9 . 5 0110 - 1 0 . 0 0111 - 1 1 . 0 1000 - 1 1 . 5 1001 - 1 2 . 0 1010 - 1 2 . 5 1011 - 1 3 . 0 1100 - 1 4 . 0 1101 - 1 4 . 5 1110 - 1 5 . 0 1111 - 1 5 . 5 Note: The restricted setting VGH – VGL < 32 V. Restriction To enable this command, “Page 1 Command Set enable register (FFh) ” must set first. Register Availability Status Availability Normal Mode On, Sleep Out Yes Sleep Out Yes Sleep In Yes Default Status Default Value VGL_CLPEN VGL_CLP[3:0] Power ON Sequence 1’h1 4’h6 S/W Reset No Change No Change H/W Reset 1’h1 4’h6

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 204 of 328 4.4.21. Power Control 6 (45h) Page 1 Command Set 45h : PWCTRL 6 (Power Control 6) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 1 0 0 0 1 0 1 45h st Parameter Write / Read VGH_REG[3:0] VGL_REG[3:0] 00h VGH_REG[3:0]: Sets the VGH_REG operating voltage. VGH_REG[3:0] . VGH_REG operation voltage (V) 0 0 0 0 8.5 0 0 0 1 9.0 0 0 1 0 9.5 0 0 1 1 10.0 0 1 0 0 10.5 0 1 0 1 11.0 0 1 1 0 11.5 0 1 1 1 12.0 1 0 0 0 12.5 1 0 0 1 13.0 1 0 1 0 13.5 1 0 1 1 14.0 1 1 0 0 14.5 1 1 0 1 15.0 1 1 1 0 15.5 1 1 1 1 16.0 VGL_REG[3:0]: Sets the VGL_REG operating voltage. VGL_REG[3:0] . VGL_REG operation voltage (V) 0 0 0 0 -7.0 0 0 0 1 -7.5 0 0 1 0 -8.0 0 0 1 1 -8.5 0 1 0 0 -9.0 0 1 0 1 -9.5 0 1 1 0 -10.0 0 1 1 1 -11.0 1 0 0 0 -11.5 1 0 0 1 -12.0 1 0 1 0 -12.5 1 0 1 1 -13.0 1 1 0 0 -14.0 1 1 0 1 -14.5 1 1 1 0 -15.0 1 1 1 1 -15.5 Note : The voltage enable of VGL_REG in Section 4.10.2

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 205 of 328 Restriction To enable this command, “Page 1 Command Set enable register (FFh) ” must set first. Register Availability Status Availability Normal Mode On, Sleep Out Yes Sleep Out Yes Sleep In Yes Default Status Default Value VGH_REG[3:0] VGL_REG[3:0] Power ON Sequence 4’h0 4’h0 S/W Reset No Change No Change H/W Reset 4’h0 4’h0

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 206 of 328 4.4.22. Power Control 7 (46h) Page 1 Command Set 46h : PWCTRL 7 (Power Control 7) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 1 0 0 0 1 1 0 46h st Parameter Write / Read 0 DDVDH_PK1[2:0] 0 DDVDL_PK 2[2:0] 33h DDVDH_PK1[2:0]: Selects the operating frequency of the step-up circuit 1. The higher step-up operating frequency enhances the drivability of the step-up circuit and the quality of display but increases the current consumption. Adjust the frequency taking into account the trade-off between the display quality and the current consumption. DDVDH_PK 1[2:0] Step-up cycle for step-up circuit 1 0 0 0 16 0 0 1 8 0 1 0 4 0 1 1 2 1 0 0 1 1 0 1 1/2 1 1 0 1/4 1 1 1 Other setting inhibit DDVDL_PK 2[2:0]: Selects the operating frequency of the step-up circuit 2. The higher step-up operating frequency enhances the drivability of the step-up circuit and the quality of display but increases the current consumption. Adjust the frequency taking into account the trade-off between the display quality and the current consumption. DDVDL_PK 2[2:0] Step-up cycle for step-up circuit 2 0 0 0 16 0 0 1 8 0 1 0 4 0 1 1 2 1 0 0 1 1 0 1 1/2 1 1 0 1/4 1 1 1 Other setting inhibit Restriction To enable this command, “Page 1 Command Set enable register (FFh) ” must set first.

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 207 of 328 Register Availability Status Availability Normal Mode On, Sleep Out Yes Sleep Out Yes Sleep In Yes Default Status Default Value DDVDH_PK1[2:0] DDVDL_PK 2[2:0] Power ON Sequence 3’h3 3’h3 S/W Reset No Change No Change H/W Reset 3’h3 3’h3

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 208 of 328 4.4.23. Power Control 8 (47h) Page 1 Command Set 47h : PWCTRL 8 (Power Control 8) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 1 0 0 0 1 1 1 47h st Parameter Write / Read 0 VCL_PK3[2:0] 0 VGHL_PK4[2:0] 33h VCL_PK3[2:0]: Selects the operating frequency of the step-up circuit 3. The higher step-up operating frequency enhances the drivability of the step-up circuit and the quality of display but increases the current consumption. Adjust the frequency taking into account the trade-off between the display quality and the current consumption. VCL_PK 3[2:0] Step-up cycle for step-up circuit 3 0 0 0 16 0 0 1 8 0 1 0 4 0 1 1 2 1 0 0 1 1 0 1 1/2 1 1 0 1/4 1 1 1 Other setting inhibit VGHL_PK4[2:0]: Selects the operating frequency of the step-up circuit 4/5. The higher step-up operating frequency enhances the drivability of the step-up circuit and the quality of display but increases the current consumption. Adjust the frequency taking into account the trade-off between the display quality and the current consumption. VGHL_PK 4[2:0] Step-up cycle for step-up circuit 4/5 0 0 0 16 0 0 1 8 0 1 0 4 0 1 1 2 1 0 0 1 1 0 1 1/2 1 1 0 1/4 1 1 1 Other setting inhibit Restriction To enable this command, “Page 1 Command Set enable register (FFh) ” must set first. Register Availability Status Availability Normal Mode On, Sleep Out Yes Sleep Out Yes Sleep In Yes

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 209 of 328 Default Status Default Value VCL_PK3[2:0] VGHL_PK4[2:0] Power ON Sequence 3’h3 3’h3 S/W Reset No Change No Change H/W Reset 3’h3 3’h3

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 210 of 328 4.4.24. Power Control 9 (50h) Page 1 Command Set 50h : PWCTRL 9 (Power Control 9) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 1 0 1 0 0 0 0 50h st Parameter Write / Read VREG1[7:0] 78h VREG1[7:0]: Sets the VREG1OUT voltage for positive Gamma VREG1[7:0] VREG1OUT (V) VREG1[7:0] VREG1OUT (V) VREG1[7:0] VREG1OUT (V) VREG1[7:0] VREG1OUT (V) 8’h00 3.0000 8’h40 3.8000 8’h80 4.6000 8’hC0 5.4000 8’h01 3.0125 8’h41 3.8125 8’h81 4.6125 8’hC1 5.4125 8’h02 3.0250 8’h42 3.8250 8’h82 4.6250 8’hC2 5.4250 8’h03 3.0375 8’h43 3.8375 8’h83 4.6375 8’hC3 5.4375 8’h04 3.0500 8’h44 3.8500 8’h84 4.6500 8’hC4 5.4500 8’h05 3.0625 8’h45 3.8625 8’h85 4.6625 8’hC5 5.4625 8’h06 3.0750 8’h46 3.8750 8’h86 4.6750 8’hC6 5.4750 8’h07 3.0875 8’h47 3.8875 8’h87 4.6875 8’hC7 5.4875 8’h08 3.1000 8’h48 3.9000 8’h88 4.7000 8’hC8 5.5000 8’h09 3.1125 8’h49 3.9125 8’h89 4.7125 8’hC9 5.5125 8’h0A 3.1250 8’h4A 3.9250 8’h8A 4.7250 8’hCA 5.5250 8’h0B 3.1375 8’h4B 3.9375 8’h8B 4.7375 8’hCB 5.5375 8’h0C 3.1500 8’h4C 3.9500 8’h8C 4.7500 8’hCC 5.5500 8’h0D 3.1625 8’h4D 3.9625 8 ’ h 8 D 4 . 7 6 2 5 8 ’ h C D 5 . 5 6 2 5 8’h0E 3.1750 8’h4E 3.9750 8’h8E 4.7750 8’hCE 5.5750 8’h0F 3.1875 8’h4F 3.9875 8 ’ h 8 F 4 . 7 8 7 5 8 ’ h C F 5 . 5 8 7 5 8’h10 3.2000 8’h50 4.0000 8’h90 4.8000 8’hD0 5.6000 8’h11 3.2125 8’h51 4.0125 8’h91 4.8125 8’hD1 5.6125 8’h12 3.2250 8’h52 4.0250 8’h92 4.8250 8’hD2 5.6250 8’h13 3.2375 8’h53 4.0375 8’h93 4.8375 8’hD3 5.6375 8’h14 3.2500 8’h54 4.0500 8’h94 4.8500 8’hD4 5.6500 8’h15 3.2625 8’h55 4.0625 8’h95 4.8625 8’hD5 5.6625 8’h16 3.2750 8’h56 4.0750 8’h96 4.8750 8’hD6 5.6750 8’h17 3.2875 8’h57 4.0875 8’h97 4.8875 8’hD7 5.6875 8’h18 3.3000 8’h58 4.1000 8’h98 4.9000 8’hD8 5.7000 8’h19 3.3125 8’h59 4.1125 8’h99 4.9125 8’hD9 5.7125 8’h1A 3.3250 8’h5A 4.1250 8’h9A 4.9250 8’hDA 5.7250 8’h1B 3.3375 8’h5B 4.1375 8’h9B 4.9375 8’hDB 5.7375 8’h1C 3.3500 8’h5C 4.1500 8’h9C 4.9500 8’hDC 5.7500 8’h1D 3.3625 8’h5D 4.1625 8 ’ h 9 D 4 . 9 6 2 5 8 ’ h D D 5 . 7 6 2 5 8’h1E 3.3750 8’h5E 4.1750 8’h9E 4.9750 8’hDE 5.7750 8’h1F 3.3875 8’h5F 4.1875 8 ’ h 9 F 4 . 9 8 7 5 8 ’ h D F 5 . 7 8 7 5 8’h20 3.4000 8’h60 4.2000 8’hA0 5.0000 8’hE0 5.8000 8’h21 3.4125 8’h61 4.2125 8’hA1 5.0125 8’hE1 5.8125 8’h22 3.4250 8’h62 4.2250 8’hA2 5.0250 8’hE2 5.8250 8’h23 3.4375 8’h63 4.2375 8’hA3 5.0375 8’hE3 5.8375 8’h24 3.4500 8’h64 4.2500 8’hA4 5.0500 8’hE4 5.8500 8’h25 3.4625 8’h65 4.2625 8’hA5 5.0625 8’hE5 5.8625 8’h26 3.4750 8’h66 4.2750 8’hA6 5.0750 8’hE6 5.8750 8’h27 3.4875 8’h67 4.2875 8’hA7 5.0875 8’hE7 5.8875 8’h28 3.5000 8’h68 4.3000 8’hA8 5.1000 8’hE8 5.9000 8’h29 3.5125 8’h69 4.3125 8’hA9 5.1125 8’hE9 5.9125 8’h2A 3.5250 8’h6A 4.3250 8’hAA 5.1250 8’hEA 5.9250 8’h2B 3.5375 8’h6B 4.3375 8’hAB 5.1375 8’hEB 5.9375 8’h2C 3.5500 8’h6C 4.3500 8’hAC 5.1500 8’hEC 5.9500 8’h2D 3.5625 8’h6D 4.3625 8 ’ h A D 5 . 1 6 2 5 8 ’ h E D 5 . 9 6 2 5 8’h2E 3.5750 8’h6E 4.3750 8’hAE 5.1750 8’hEE 5.9750 8’h2F 3.5875 8’h6F 4.3875 8 ’ h A F 5 . 1 8 7 5 8 ’ h E F 5 . 9 8 7 5 8’h30 3.6000 8’h70 4.4000 8’hB0 5.2000 8’hF0 6.0000 8’h31 3.6125 8’h71 4.4125 8’hB1 5.2125 8’hF1 6.0125 8’h32 3.6250 8’h72 4.4250 8’hB2 5.2250 8’hF2 6.0250 8’h33 3.6375 8’h73 4.4375 8’hB3 5.2375 8’hF3 6.0375 8’h34 3.6500 8’h74 4.4500 8’hB4 5.2500 8’hF4 6.0500 8’h35 3.6625 8’h75 4.4625 8’hB5 5.2625 8’hF5 6.0625 8’h36 3.6750 8’h76 4.4750 8’hB6 5.2750 8’hF6 6.0750 8’h37 3.6875 8’h77 4.4875 8’hB7 5.2875 8’hF7 6.0875 8’h38 3.7000 8’h78 4.5000 8’hB8 5.3000 8’hF8 6.1000 8’h39 3.7125 8’h79 4.5125 8’hB9 5.3125 8’hF9 6.1125 8’h3A 3.7250 8’h7A 4.5250 8’hBA 5.3250 8’hFA 6.1250 8’h3B 3.7375 8’h7B 4.5375 8’hBB 5.3375 8’hFB 6.1375 8’h3C 3.7500 8’h7C 4.5500 8’hBC 5.3500 8’hFC 6.1500 8’h3D 3.7625 8’h7D 4.5625 8 ’ h B D 5 . 3 6 2 5 8 ’ h F D 6 . 1 6 2 5 8’h3E 3.7750 8’h7E 4.5750 8’hBE 5.3750 8’hFE 6.1750 8’h3F 3.7875 8’h7F 4.5875 8 ’ h B F 5 . 3 8 7 5 8 ’ h F F 6 . 1 8 7 5 Note : The voltage enable of VREG1OUT and VREG2OUT is in Sections 4.10.3

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 211 of 328 Restriction To enable this command, “Page 1 Command Set enable register (FFh) ” must set first. Register Availability Status Availability Normal Mode On, Sleep Out Yes Sleep Out Yes Sleep In Yes Default Status Default Value VREG1[7:0] Power ON Sequence 8’h78 S/W Reset N o C h a n g e H/W Reset 8’h78

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 212 of 328 4.4.25. Power Control 10 (51h) Page 1 Command Set 51h : PWCTRL 10 (Power Control 10) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 1 0 1 0 0 0 1 51h st Parameter Write / Read VREG2[7:0] 78h VREG2[7:0]: Sets the VREG2OUT voltage for negative Gamma VREG2[7:0] VREG2OUT (V) VREG2[7:0] VREG2OUT (V) VREG2[7:0] VREG2OUT (V) VREG2[7:0] VREG2OUT (V) 8’h00 -3.0000 8’h40 -3.8000 8’h80 -4.6000 8’hC0 -5.4000 8’h01 -3.0125 8’h41 -3.8125 8’h81 -4.6125 8’hC1 -5.4125 8’h02 -3.0250 8’h42 -3.8250 8’h82 -4.6250 8’hC2 -5.4250 8’h03 -3.0375 8’h43 -3.8375 8’h83 -4.6375 8’hC3 -5.4375 8’h04 -3.0500 8’h44 -3.8500 8’h84 -4.6500 8’hC4 -5.4500 8’h05 -3.0625 8’h45 -3.8625 8’h85 -4.6625 8’hC5 -5.4625 8’h06 -3.0750 8’h46 -3.8750 8’h86 -4.6750 8’hC6 -5.4750 8’h07 -3.0875 8’h47 -3.8875 8’h87 -4.6875 8’hC7 -5.4875 8’h08 -3.1000 8’h48 -3.9000 8’h88 -4.7000 8’hC8 -5.5000 8’h09 -3.1125 8’h49 -3.9125 8’h89 -4.7125 8’hC9 -5.5125 8’h0A -3.1250 8’h4A -3.9250 8’h8A -4.7250 8’hCA -5.5250 8’h0B -3.1375 8’h4B -3.9375 8’h8B -4.7375 8’hCB -5.5375 8’h0C -3.1500 8’h4C -3.9500 8’h8C -4.7500 8’hCC -5.5500 8’h0D -3.1625 8’h4D -3.9625 8 ’ h 8 D - 4 . 7 6 2 5 8 ’ h C D - 5 . 5 6 2 5 8’h0E -3.1750 8’h4E -3.9750 8’h8E -4.7750 8’hCE -5.5750 8’h0F -3.1875 8’h4F -3.9875 8 ’ h 8 F - 4 . 7 8 7 5 8 ’ h C F - 5 . 5 8 7 5 8’h10 -3.2000 8’h50 -4.0000 8’h90 -4.8000 8’hD0 -5.6000 8’h11 -3.2125 8’h51 -4.0125 8’h91 -4.8125 8’hD1 -5.6125 8’h12 -3.2250 8’h52 -4.0250 8’h92 -4.8250 8’hD2 -5.6250 8’h13 -3.2375 8’h53 -4.0375 8’h93 -4.8375 8’hD3 -5.6375 8’h14 -3.2500 8’h54 -4.0500 8’h94 -4.8500 8’hD4 -5.6500 8’h15 -3.2625 8’h55 -4.0625 8’h95 -4.8625 8’hD5 -5.6625 8’h16 -3.2750 8’h56 -4.0750 8’h96 -4.8750 8’hD6 -5.6750 8’h17 -3.2875 8’h57 -4.0875 8’h97 -4.8875 8’hD7 -5.6875 8’h18 -3.3000 8’h58 -4.1000 8’h98 -4.9000 8’hD8 -5.7000 8’h19 -3.3125 8’h59 -4.1125 8’h99 -4.9125 8’hD9 -5.7125 8’h1A -3.3250 8’h5A -4.1250 8’h9A -4.9250 8’hDA -5.7250 8’h1B -3.3375 8’h5B -4.1375 8’h9B -4.9375 8’hDB -5.7375 8’h1C -3.3500 8’h5C -4.1500 8’h9C -4.9500 8’hDC -5.7500 8’h1D -3.3625 8’h5D -4.1625 8 ’ h 9 D - 4 . 9 6 2 5 8 ’ h D D - 5 . 7 6 2 5 8’h1E -3.3750 8’h5E -4.1750 8’h9E -4.9750 8’hDE -5.7750 8’h1F -3.3875 8’h5F -4.1875 8 ’ h 9 F - 4 . 9 8 7 5 8 ’ h D F - 5 . 7 8 7 5 8’h20 -3.4000 8’h60 -4.2000 8’hA0 -5.0000 8’hE0 -5.8000 8’h21 -3.4125 8’h61 -4.2125 8’hA1 -5.0125 8’hE1 -5.8125 8’h22 -3.4250 8’h62 -4.2250 8’hA2 -5.0250 8’hE2 -5.8250 8’h23 -3.4375 8’h63 -4.2375 8’hA3 -5.0375 8’hE3 -5.8375 8’h24 -3.4500 8’h64 -4.2500 8’hA4 -5.0500 8’hE4 -5.8500 8’h25 -3.4625 8’h65 -4.2625 8’hA5 -5.0625 8’hE5 -5.8625 8’h26 -3.4750 8’h66 -4.2750 8’hA6 -5.0750 8’hE6 -5.8750 8’h27 -3.4875 8’h67 -4.2875 8’hA7 -5.0875 8’hE7 -5.8875 8’h28 -3.5000 8’h68 -4.3000 8’hA8 -5.1000 8’hE8 -5.9000 8’h29 -3.5125 8’h69 -4.3125 8’hA9 -5.1125 8’hE9 -5.9125 8’h2A -3.5250 8’h6A -4.3250 8’hAA -5.1250 8’hEA -5.9250 8’h2B -3.5375 8’h6B -4.3375 8’hAB -5.1375 8’hEB -5.9375 8’h2C -3.5500 8’h6C -4.3500 8’hAC -5.1500 8’hEC -5.9500 8’h2D -3.5625 8’h6D -4.3625 8 ’ h A D - 5 . 1 6 2 5 8 ’ h E D - 5 . 9 6 2 5 8’h2E -3.5750 8’h6E -4.3750 8’hAE -5.1750 8’hEE -5.9750 8’h2F -3.5875 8’h6F -4.3875 8 ’ h A F - 5 . 1 8 7 5 8 ’ h E F - 5 . 9 8 7 5 8’h30 -3.6000 8’h70 -4.4000 8’hB0 -5.2000 8’hF0 -6.0000 8’h31 -3.6125 8’h71 -4.4125 8’hB1 -5.2125 8’hF1 -6.0125 8’h32 -3.6250 8’h72 -4.4250 8’hB2 -5.2250 8’hF2 -6.0250 8’h33 -3.6375 8’h73 -4.4375 8’hB3 -5.2375 8’hF3 -6.0375 8’h34 -3.6500 8’h74 -4.4500 8’hB4 -5.2500 8’hF4 -6.0500 8’h35 -3.6625 8’h75 -4.4625 8’hB5 -5.2625 8’hF5 -6.0625 8’h36 -3.6750 8’h76 -4.4750 8’hB6 -5.2750 8’hF6 -6.0750 8’h37 -3.6875 8’h77 -4.4875 8’hB7 -5.2875 8’hF7 -6.0875 8’h38 -3.7000 8’h78 -4.5000 8’hB8 -5.3000 8’hF8 -6.1000 8’h39 -3.7125 8’h79 -4.5125 8’hB9 -5.3125 8’hF9 -6.1125 8’h3A -3.7250 8’h7A -4.5250 8’hBA -5.3250 8’hFA -6.1250 8’h3B -3.7375 8’h7B -4.5375 8’hBB -5.3375 8’hFB -6.1375 8’h3C -3.7500 8’h7C -4.5500 8’hBC -5.3500 8’hFC -6.1500 8’h3D -3.7625 8’h7D -4.5625 8 ’ h B D - 5 . 3 6 2 5 8 ’ h F D - 6 . 1 6 2 5 8’h3E -3.7750 8’h7E -4.5750 8’hBE -5.3750 8’hFE -6.1750 8’h3F -3.7875 8’h7F -4.5875 8 ’ h B F - 5 . 3 8 7 5 8 ’ h F F - 6 . 1 8 7 5 Note : The voltage enable of VREG1OUT and VREG2OUT is in Sections 4.10.3

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 213 of 328 Restriction To enable this command, “Page 1 Command Set enable register (FFh) ” must set first. Register Availability Status Availability Normal Mode On, Sleep Out Yes Sleep Out Yes Sleep In Yes Default Status Default Value VREG2[7:0] Power ON Sequence 8’h78 S/W Reset N o C h a n g e H/W Reset 8’h78

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 214 of 328 4.4.26. VCOM Control 1~2 (52h~53h) Page 1 Command Set 52h : VMCTRL1 (VCOM Control 1) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 1 0 1 0 0 1 0 52h st Parameter Write / Read 0 0 0 0 0 0 0 VCM1[8] 00h Page 1 Command Set 53h : VMCTRL2 (VCOM Control 2) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 1 0 1 0 0 1 1 53h st Parameter Write / Read VCM1[7:0] 6Fh VCM1 [8:0] is used to set factor to generate VCOM voltage. VCM1[8:0] VCOM (V) VCM1[8:0] VCOM (V) VCM1[8:0] VCOM (V) VCM1[8:0] VCOM (V) VCM1[8:0] VCOM (V) 9’h032 -0.8125 9’h072 -1.6125 9’h0B2 -2.4125 9’h0F2 -3.2125 9’h132 Setting inhibit 9’h033 -0.8250 9’h073 -1.6250 9’h0B3 -2.4250 9’h0F3 -3.2250 9’h133 Setting inhibit 9’h034 -0.8375 9’h074 -1.6375 9’h0B4 -2.4375 9’h0F4 -3.2375 9’h134 Setting inhibit 9’h035 -0.8500 9’h075 -1.6500 9’h0B5 -2.4500 9’h0F5 -3.2500 9’h135 Setting inhibit 9’h036 -0.8625 9’h076 -1.6625 9’h0B6 -2.4625 9’h0F6 -3.2625 9’h136 Setting inhibit 9’h037 -0.8750 9’h077 -1.6750 9’h0B7 -2.4750 9’h0F7 -3.2750 9’h137 Setting inhibit 9’h038 -0.8875 9’h078 -1.6875 9’h0B8 -2.4875 9’h0F8 -3.2875 9’h138 Setting inhibit 9’h039 -0.9000 9’h079 -1.7000 9’h0B9 -2.5000 9’h0F9 -3.3000 9’h139 Setting inhibit 9’h03A -0.9125 9’h07A -1.7125 9’h0BA -2.5125 9’h0FA -3.3125 9’h13A Setting inhibit 9’h03B -0.9250 9’h07B -1.7250 9’h0BB -2.5250 9’h0FB -3.3250 9’h13B Setting inhibit 9’h03C -0.9375 9’h07C -1.7375 9’h0BC -2.5375 9 ’ h 0 F C - 3 . 3 3 7 5 9 ’ h 1 3 C S e t t i n g i n h i b i t

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 215 of 328 9’h03D -0.9500 9’h07D -1.7500 9’h0BD -2.5500 9 ’ h 0 F D - 3 . 3 5 0 0 9 ’ h 1 3 D S e t t i n g i n h i b i t 9’h03E -0.9625 9’h07E -1.7625 9’h0BE -2.5625 9’h0FE -3.3625 9’h13E Setting inhibit 9’h03F -0.9750 9’h07F -1.7750 9’h0BF -2.5750 9 ’ h 0 F F - 3 . 3 7 5 0 9 ’ h 1 3 F S e t t i n g i n h i b i t Note 1: VCOM ≧ V C L + 0 . 3 V Note 2: GS = 1’b0 , VCOM voltage = VCM1[8:0] setting, GS = 1’b1 VCOM voltage = VCM2[8:0] Restriction To enable this command, “Page 1 Command Set enable register (FFh) ” must set first. Register Availability Status Availability Normal Mode On, Sleep Out Yes Sleep Out Yes Sleep In Yes Default Status Default Value VCM1[8] VCM1[7:0] Power ON Sequence 1’h0 8’h6F S/W Reset No Change No Change H/W Reset 1’h0 8’h6F

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 216 of 328 4.4.27. VCOM Control 3~4 (54h~55h) Page 1 Command Set 54h : VMCTRL3 (VCOM Control 3) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 1 0 1 0 1 0 0 54h st Parameter Write / Read 0 0 0 0 0 0 0 VCM2[8] 00h Page 1 Command Set 55h : VMCTRL4 (VCOM Control 4) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 1 0 1 0 1 0 1 55h st Parameter Write / Read VCM2[7:0] 6Fh VCM2 [8:0] is used to set factor to generate VCOM voltage. VCM2[8:0] VCOM (V) VCM2[8:0] VCOM (V) VCM2[8:0] VCOM (V) VCM2[8:0] VCOM (V) VCM2[8:0] VCOM (V) 9’h032 -0.8125 9’h072 -1.6125 9’h0B2 -2.4125 9’h0F2 -3.2125 9’h132 Setting inhibit 9’h033 -0.8250 9’h073 -1.6250 9’h0B3 -2.4250 9’h0F3 -3.2250 9’h133 Setting inhibit 9’h034 -0.8375 9’h074 -1.6375 9’h0B4 -2.4375 9’h0F4 -3.2375 9’h134 Setting inhibit 9’h035 -0.8500 9’h075 -1.6500 9’h0B5 -2.4500 9’h0F5 -3.2500 9’h135 Setting inhibit 9’h036 -0.8625 9’h076 -1.6625 9’h0B6 -2.4625 9’h0F6 -3.2625 9’h136 Setting inhibit 9’h037 -0.8750 9’h077 -1.6750 9’h0B7 -2.4750 9’h0F7 -3.2750 9’h137 Setting inhibit 9’h038 -0.8875 9’h078 -1.6875 9’h0B8 -2.4875 9’h0F8 -3.2875 9’h138 Setting inhibit 9’h039 -0.9000 9’h079 -1.7000 9’h0B9 -2.5000 9’h0F9 -3.3000 9’h139 Setting inhibit 9’h03A -0.9125 9’h07A -1.7125 9’h0BA -2.5125 9’h0FA -3.3125 9’h13A Setting inhibit 9’h03B -0.9250 9’h07B -1.7250 9’h0BB -2.5250 9’h0FB -3.3250 9’h13B Setting inhibit 9’h03C -0.9375 9’h07C -1.7375 9’h0BC -2.5375 9 ’ h 0 F C - 3 . 3 3 7 5 9 ’ h 1 3 C S e t t i n g i n h i b i t

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 217 of 328 9’h03D -0.9500 9’h07D -1.7500 9’h0BD -2.5500 9 ’ h 0 F D - 3 . 3 5 0 0 9 ’ h 1 3 D S e t t i n g i n h i b i t 9’h03E -0.9625 9’h07E -1.7625 9’h0BE -2.5625 9’h0FE -3.3625 9’h13E Setting inhibit 9’h03F -0.9750 9’h07F -1.7750 9’h0BF -2.5750 9 ’ h 0 F F - 3 . 3 7 5 0 9 ’ h 1 3 F S e t t i n g i n h i b i t Note 1: VCOM ≧ V C L + 0 . 3 V Note 2: GS = 1’b0 , VCOM voltage = VCM1[8:0] setting, GS = 1’b1 VCOM voltage = VCM2[8:0] Restriction To enable this command, “Page 1 Command Set enable register (FFh) ” must set first. Register Availability Status Availability Normal Mode On, Sleep Out Yes Sleep Out Yes Sleep In Yes Default Status Default Value VCM2[8] VCM2[7:0] Power ON Sequence 1’h0 8’h6F S/W Reset No Change No Change H/W Reset 1’h0 8’h6F

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 218 of 328 4.4.28. VCOM Control 5 (56h) Page 1 Command Set 56h : VMCTRL5 (VCOM Control 5) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 1 0 1 0 1 1 0 56h st Parameter Write / Read 0 0 0 NVM2 0 0 0 NVM1 00h NVM1 : Selection of the VCM1 setting. Program NV Memory for VCM1[8:0] NVM1 Description Before 1’b0 Register 52h and 53h for VCM1 setting 1’b1 Setting inhibit After 1’b0 NV Memory selected for VCM1 setting 1’b1 Register 52h and 53h for VCM1 setting NVM2 : Selection of the VCM2 setting. Program NV Memory for VCM2[8:0] NVM2 Description Before 1’b0 Register 54h and 55h for VCM2 setting 1’b1 Setting inhibit After 1’b0 NV Memory selected for VCM2 setting 1’b1 Register 54h and 55h for VCM2 setting Restriction 1. To enable this command, “Page 1 Command Set enable register (FFh) ” must set first. 2. Before the NV memory is programmed, it is prohibited from setting NVM1 / NVM2=1’b1. Register Availability Status Availability Normal Mode On, Sleep Out Yes Sleep Out Yes Sleep In Yes Default Status Default Value NVM2 NVM1 Power ON Sequence 1’h0 1’h0 S/W Reset No Change No Change H/W Reset 1’h0 1’h0

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 219 of 328 4.4.29. LVD Detect (57h) Page 1 Command Set 57h : LVD (Low Voltage Detection) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 1 0 1 0 1 1 1 57h st Parameter Write / Read 0 VDET[2:0] 0 VCORE_VD[2:0] 20h VCORE_VD[2:0]: Set Vcore voltage adjustment VCORE_VD[2:0] Value (V) 000 1.50 001 1.45 010 1.40 011 1.35 100 1.55 101 1.60 110 1.65 111 1.7 VDET[2:0]: Low voltage detection for voltage level setting is defined as below table VDET[2:0] Value (V) 000 1.6 001 1.7 010 1.8 011 1.9 100 2.0 101 2.1 110 2.3 111 2.4 Restriction To enable this command, “Page 1 Command Set enable register (FFh) ” must set first. Register Availability Status Availability Normal Mode On, Sleep Out Yes Sleep Out Yes Sleep In Yes Default Status Default Value VDET[2:0] VCORE_VD[2:0] Power ON Sequence 3’h2 3’h0 S/W Reset No Change No Change H/W Reset 3’h2 3’h0

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 220 of 328 4.4.30. Entry Mode Set (58h) Page 1 Command Set 58h : ETMOD (Entry Mode Set) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 1 0 1 1 0 0 0 58h st Parameter Write / Read LVD 0 0 1 0 0 0 DSTB 90h DSTB:The ILI9806E driver enters the Deep Standby Mode when DSTB is set to high (“1”). In Deep Standby mode, when internal logic power is turned off, the structions are not sa ved. After exiting the Deep Standby Mode , the display pattern and structions need to be rewrited. The ILI9806E provides two ways to exit Deep Standby Mode: (1) Exit Deep Standby Mode by pulling down CSX to low (“0”) 6 times. (2) Input a RESX pulse with effectively low level duration to start up the inside logic regulator and make a transition to the initial state. Note : See Section 12 Deep Standby Mode Setting LVD: Low voltage detection control. LVD Low voltage detection Restriction To enable this command, “Page 1 Command Set enable register (FFh) ” must set first. Register Availability Status Availability Normal Mode On, Sleep Out Yes Sleep Out Yes Sleep In Yes Default Status Default Value LVD DSTB Power ON Sequence 1’h1 1’h0 S/W Reset No Change No Change H/W Reset 1’h1 1’h0

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 221 of 328 4.4.31. Source Timing Adjust 1 (60h) Page 1 Command Set 60h : Source Timing Adjust 1 Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 1 1 0 0 0 0 0 60h st Parameter Write / Read 0 0 SDTI[5:0] 05h SDTI [5:0]: Source SDT timing adjustment (time scale: internal TOP_CLK). The timing can be adjusted from 0 to 63 time scales. Note: TOP_CLK : 4* TOSC_CLK = 0.22us Restriction To enable this command, “Page 1 Command Set enable register (FFh) ” must set first. Register Availability Status Availability Normal Mode On, Sleep Out Yes Sleep Out Yes Sleep In Yes Default Status Default Value SDTI[5:0] Power ON Sequence 6’h05 S/W Reset No Change H/W Reset 6’h05

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 222 of 328 4.4.32. Source Timing Adjust 2 (61h) Page 1 Command Set 61h : Source Timing Adjust 2 Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 1 1 0 0 0 0 1 61h st Parameter Write / Read 0 0 CRTI[5:0] 05h CRTI [5:0]: Source CR timing adjustment (time scale: internal TOP_CLK). The timing can be adjusted from 0 to 63 time scales. Note: TOP_CLK : 4* TOSC_CLK = 0.22us Restriction To enable this command, “Page 1 Command Set enable register (FFh) ” must set first. Register Availability Status Availability Normal Mode On, Sleep Out Yes Sleep Out Yes Sleep In Yes Default Status Default Value CRTI[5:0] Power ON Sequence 6’h05 S/W Reset No Change H/W Reset 6’h05

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 223 of 328 4.4.33. Source Timing Adjust 3 (62h) Page 1 Command Set 62h : Source Timing Adjust 3 Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 1 1 0 0 0 1 0 62h st Parameter Write / Read 0 0 EQTI[5:0] 0Eh EQTI [5:0]: Source EQ timing adjustment (time scale: internal TOP_CLK). The timing can be adjusted from 5 to 63 time scales. Note: TOP_CLK : 4* TOSC_CLK = 0.22us Restriction 1. To enable this command, “Page 1 Command Set enable register (FFh) ” must set first. 2. The function setting can not be less than 1us. Register Availability Status Availability Normal Mode On, Sleep Out Yes Sleep Out Yes Sleep In Yes Default Status Default Value EQTI[5:0] Power ON Sequence 6’h0E S/W Reset No Change H/W Reset 6’h0E

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 224 of 328 4.4.34. Source Timing Adjust 4 (63h) Page 1 Command Set 63h : Source Timing Adjust 4 Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 1 1 0 0 0 1 1 63h st Parameter Write / Read 0 0 PCTI[5:0] 05h PCTI [5:0]: Source PC timing adjustment (time scale: internal TOP_CLK). The timing can be adjusted from 0 to 63 time scales. Note: TOP_CLK : 4* TOSC_CLK = 0.22us Restriction To enable this command, “Page 1 Command Set enable register (FFh) ” must set first. Register Availability Status Availability Normal Mode On, Sleep Out Yes Sleep Out Yes Sleep In Yes Default Status Default Value PCTI[5:0] Power ON Sequence 6’h05 S/W Reset No Change H/W Reset 6’h05

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 225 of 328 4.4.35. Synchronization Timing Adjust 1 (80h) Page 1 Command Set 80h : Synchronization Time Adjust 1 Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 1 0 0 0 0 0 0 0 80h st Parameter Write / Read TOUCH_OPT[1:0] VSOD[1:0] HOSM[1:0] HS_OPT 0 00h This command controls the synchronization output . HS_OPT : Select the output source for HSOUT. HS_OPT Description

0 Prebuf-Source

1 HSOUT

(Note 2) HOSM [1:0] : Set the HSOUT active period (time scale: internal TOP_CLK). HOSM [1:0] Description 0 0 VACT Period + VFP+VBP 0 1 VACT Period 1 0 VFP+VBP 1 1 Inhibited VSOD [1:0] : Set the VSOUT timing (time scale: internal TOP_CLK). VSOD [1:0] Description 0 0 0 line(First line of back porch) 0 1 1 line 1 0 2 line 1 1 3 line TOUCH_OPT[1:0] : Select the Output Mode of synchronization (time scale: internal TOP_CLK). TOUCH_OPT [1:0] Description 0 0 Off 0 1 VFP+VBP 1 0 Adjustable for VSOUT / HSOUT (Note 2)_ 1 1 VFP+VBP / HFP+HBP Note1 : TOP_CLK : 4* TOSC_CLK = 0.22us Note2 : When use this setting, please reference to Chapter 13. Restriction 1. To enable this command, “Page 1 Command Set enable register (FFh) ” must set first. 2. When use this function, the data of input must match the resolution thatwas set in Chapter 4.4.12. (P1_ R30h) Register Availability Status Availability Normal Mode On, Sleep Out Yes Sleep Out Yes Sleep In Yes

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 226 of 328 Default Status Default Value TOUCH_OPT [1:0] VSOD [1:0] HOSM [1:0] HS_OPT Power ON Sequence 2’h0 2’h0 2’h0 1’h0 S/W Reset No Change No Change No Change No Change H/W Reset 2’h0 2’h0 2’h0 1’h0

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 227 of 328 4.4.36. Synchronization Timing Adjust 2 (81h) Page 1 Command Set 81h : Synchronization Time Adjust 2 Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 1 0 0 0 0 0 0 1 81h st Parameter Write / Read 0 HSOD[6:0] 05h HSOD [6:0] : Set the HSOUT timing (time scale: internal TOP_CLK). HSOD[6:0] Description 7’h00 0clk 7’h01 1clk 7’h02 2clk : : 7’h7D 125clk 7’h7E 126clk 7’h7F 127clk Note1 : TOP_CLK : 4* TOSC_CLK = 0.22us Note2 : When use the setting, please reference to Chapter 13 Restriction 1. To enable this command, “Page 1 Command Set enable register (FFh) ” must set first. 2. When use this function, the data of input must match the resolution thatwas set in Chapter 4.4.12. (P1_ R30h) Register Availability Status Availability Normal Mode On, Sleep Out Yes Sleep Out Yes Sleep In Yes Default Status Default Value HSOD[6:0] Power ON Sequence 7’h05 S/W Reset No Change H/W Reset 7’h05

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 228 of 328 4.4.37. Synchronization Timing Adjust 3 (82h) Page 1 Command Set 82h : Synchronization Time Adjust 3 Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 1 0 0 0 0 0 1 0 82h st Parameter Write / Read HSOHW[7:0] 19h HSOHW [7:0] : Set the high width of HSOUT (time scale: internal TOP_CLK). HSOHW[7:0] Description 8’h00 0clk 8’h01 1clk 8’h02 2clk : : 8’hFD 253clk 8’hFE 254clk 8’hFF 255clk Note1 : TOP_CLK : 4* TOSC_CLK = 0.22us Note2 : When use the setting, please reference to Chapter 13 Restriction 1. To enable this command, “Page 1 Command Set enable register (FFh) ” must set first. 2. When use this function, the data of input must match the resolution thatwas set in Chapter 4.4.12. (P1_ R30h) Register Availability Status Availability Normal Mode On, Sleep Out Yes Sleep Out Yes Sleep In Yes Default Status Default Value HSOHW[7:0] Power ON Sequence 8’h19 S/W Reset No Change H/W Reset 8’h19

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 229 of 328 4.4.38. Positive Gamma Control 1~16 (A0h~AFh) Page 1 Command Set Command Write / Read Parameter Default (Hex)D7 D6 D5 D4 D3 D2 D1 D0 A0h Write 0 0 REGAM0_P [5:0] 00h A1h Write 0 0 REGAM4_P [5:0] 0Fh A2h Write 0 0 REGAM8_P [5:0] 19h A3h Write 0 0 0 REGAM16_P [4:0] 12h A4h Write 0 0 0 REGAM24_P [4:0] 13h A5h Write 0 0 0 REGAM52_P [4:0] 1Ah A6h Write 0 0 0 0 REGAM80_P [3:0] 0Dh A7h Write 0 0 0 0 REGAM108_P [3:0] 0Ch A8h Write 0 0 0 0 REGAM147_P [3:0] 00h A9h Write 0 0 0 0 REGAM175_P [3:0] 04h AAh Write 0 0 0 REGAM203_P [4:0] 04h ABh Write 0 0 0 REGAM231_P [4:0] 0Dh ACh Write 0 0 0 REGAM239_P [4:0] 0Bh ADh Write 0 0 REGAM247_P [5:0] 2Ah AEh Write 0 0 REGAM251_P [5:0] 20h AFh Write 0 0 REGAM255_P [5:0] 00h Description Set the gray scale voltage to adjust the Gamma characteristics of the TFT panel. Restriction To enable this command, “Page 1 Command Set enable register (FFh) ” must set first. Register Availability Status Availability Normal Mode On, Sleep Out Yes Sleep Out Yes Sleep In Yes

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 230 of 328 4.4.39. Negative Gamma Co rrection 1~16 (C0h~CFh) Page 1 Command Set Command Write / Read Parameter Default (Hex)D7 D6 D5 D4 D3 D2 D1 D0 C0h Write 0 0 REGAM0_N[5:0] 00h C1h Write 0 0 REGAM4_N[5:0] 0Fh C2h Write 0 0 REGAM8_N [5:0] 19h C3h Write 0 0 0 REGAM16_N [4:0] 12h C4h Write 0 0 0 REGAM24_N [4:0] 13h C5h Write 0 0 0 REGAM52_N [4:0] 1Ah C6h Write 0 0 0 0 REGAM80_N[3:0] 0Dh C7h Write 0 0 0 0 REGAM108_N [3:0] 0Ch C8h Write 0 0 0 0 REGAM147_N [3:0] 00h C9h Write 0 0 0 0 REGAM175_N [3:0] 04h CAh Write 0 0 0 REGAM203_N [4:0] 04h CBh Write 0 0 0 REGAM231_N [4:0] 0Dh CCh Write 0 0 0 REGAM239_N [4:0] 0Bh CDh Write 0 0 REGAM247_N [5:0] 2Ah CEh Write 0 0 REGAM251_N [5:0] 20h CFh Write 0 0 REGAM255_N [5:0] 00h Description Set the gray scale voltage to adjust the Gamma characteristics of the TFT panel. Restriction To enable this command, “Page 1 Command Set enable register (FFh) ” must set first. Register Availability Status Availability Normal Mode On, Sleep Out Yes Sleep Out Yes Sleep In Yes

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 231 of 328 4.4.40. NV Memory Write1~2 (E0h~ E1h) Page 1 Command Set E0h : NVMWR1 (NV Memory Write1) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 1 1 1 0 0 0 0 0 E0h st Parameter Write PGM_DATA [7:0] 00 Page 1 Command Set E1h : NVMWR2 (NV Memory Write2) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 1 1 1 0 0 0 0 1 E1h st Parameter Write PGM_ADR [7:0] / NVM_READ_ADR [7:0] 00 This command is used to program or read the NV memory data. After a successful OTP operation, the information of PGM_DATA [7:0] will be programmed to the NV memory. PGM_DATA [7:0]: The programmed data. PGM_ADR [7:0] / NVM_READ_ADR [7:0] : Set the address of the NV memory for programming or read data. See “NV Memory Programming flow” and “NV Memory Read flow”. PGM_ADR [7:0] NVM_READ_ADR [7:0] Programming data 1 st time 2 nd time 3 rd time 8’h01 8’h09 8’h0A 8’h0C ID1 8’h 02 8’h0D 8’h0E 8’h10 ID2 8’h 03 8’h11 8’h12 8’h14 ID3 8’h 04 8’h15 8’h15 8’h15 VCM1[8] 8’h 05 8’h16 8’h18 8’h19 VCM1[7:0] 8’h 06 8’h15 8’h15 8’h15 VCM2[8] 8’h 07 8’h1A 8’h1C 8’h1D VCM2[7:0] 8’h 08 8’h1E 8’h20 - VREG1[7:0] 8’h 09 8’h21 8’h22 - VREG2[7:0] 8’h 29(Note) 8’h 29 - - REGAM0_P 8’h 2A(Note) 8’h 2A - - REGAM4_P 8’h 2C(Note) 8’h 2C - - REGAM8_P 8’h 2D(Note) 8’h 2D - - REGAM16_P 8’h 2E(Note) 8’h 2E - - REGAM24_P 8’h 30(Note) 8’h 30 - - REGAM52_P 8’h 31(Note) 8’h 31 - - REGAM80_P 8’h 32(Note) 8’h 32 - - REGAM108_P 8’h 34(Note) 8’h 34 - - REGAM147_P 8’h 35(Note) 8’h 35 - - REGAM175_P 8’h 36(Note) 8’h 36 - - REGAM203_P 8’h 38(Note) 8’h 38 - - REGAM231_P 8’h 39(Note) 8’h 39 - - REGAM239_P 8’h 3A(Note) 8’h 3A - - REGAM247_P 8’h 3C(Note) 8’h 3C - - REGAM251_P 8’h 3D(Note) 8’h 3D - - REGAM255_P 8’h 3E(Note) 8’h 3E - - REGAM0_N 8’h 40(Note) 8’h 40 - - REGAM4_N 8’h 41(Note) 8’h 41 - - REGAM8_N 8’h 42(Note) 8’h 42 - - REGAM16_N 8’h 44(Note) 8’h 44 - - REGAM24_N 8’h 45(Note) 8’h 45 - - REGAM52_N 8’h 46(Note) 8’h 46 - - REGAM80_N 8’h 48(Note) 8’h 48 - - REGAM108_N 8’h 49(Note) 8’h 49 - - REGAM147_N 8’h 4A(Note) 8’h 4A - - REGAM175_N

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 232 of 328 8’h 4C(Note) 8’h 4C - - REGAM203_N 8’h 4D(Note) 8’h 4D - - REGAM231_N 8’h 4E(Note) 8’h 4E - - REGAM239_N 8’h 50(Note) 8’h 50 - - REGAM247_N 8’h 51(Note) 8’h 51 - - REGAM251_N 8’h 52(Note) 8’h 52 - - REGAM255_N Note : The program, REGAM0_P~ REGAM255_P and REGAM0_N~ REGAM255_N, are completed after all addresses must finish. Restriction To enable this command, “Page 1 Command Set enable register (FFh) ” must set first. Register Availability Status Availability Normal Mode On, Sleep Out Yes Sleep Out Yes Sleep In Yes Default Status Default Value PGM_ADR [7:0] / NVM_READ_ADR[7:0] PGM_DATA [7:0] Power ON Sequence 8’h00 8’h00 S/W Reset No change No change H/W Reset 8’h00 8’h00

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 233 of 328 4.4.41. NV Memory Protect ion Key1~3 (E3h~ E5h) Page 1 Command Set E3h : NVMPKEY1 (NV Memory Protection Key1) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 1 1 1 0 0 0 1 1 E3h st Parameter Write KEY[23:16] XXh Page 1 Command Set E4h : NVMPKEY2 (NV Memory Protection Key2) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 1 1 1 0 0 1 0 0 E4h st Parameter Write KEY[15:8] XXh Page 1 Command Set E5h : NVMPKEY3 (NV Memory Protection Key3) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 1 1 1 0 0 1 0 1 E5h st Parameter Write KEY[7:0] XXh KEY [23:0]: NV memory programming protection key. Write an OTP data to E0h, this KEY[23:0] must set 0x55AA66h to enable OTP programming, And set 0x116688h to enable OTP read. If the KEY[23:0] is not 0x55AA66h and 0x116688h, the NV Memory program will be failed. Restriction To enable this command, “Page 1 Command Set enable register (FFh) ” must set first. Register Availability Status Availability Normal Mode On, Sleep Out Yes Sleep Out Yes Sleep In Yes Default Status Default Value Power ON Sequence 24’h000000 S/W Reset 24’h000000

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 234 of 328 4.4.42. NV Memory Status Read1 (E6h) Page 1 Command Set E6h : RDNVM1 (NV Memory Status Read1) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 1 1 1 0 0 1 1 0 E6h st Parameter Read 0 0 ID2_ MK [2:0] ID1_ MK [2:0] 00h The register uses a mark to record the NV memory programmed time. The bits are increase “+1” automatically after writing the PGM_DATA [7:0] to the NV memory. ID1_MK [2:0]/ID2_MK [2:0]: ID1_MK [2:0]/ID2_MK [2:0] Description 0 0 0 No Programmed 0 0 1 Programmed 1 time already 0 1 1 Programmed 2 times already 1 1 1 Programmed 3 times already Restriction To enable this command, “Page 1 Command Set enable register (FFh) ” must set first. Register Availability Status Availability Normal Mode On, Sleep Out Yes Sleep Out Yes Sleep In Yes Default Status Default Value ID2_ MK [2:0] ID1_ MK [2:0] Power ON Sequence 3’h0 3’h0 S/W Reset 3’h0 3’h0

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 235 of 328 4.4.43. NV Memory Status Read2 (E7h) Page 1 Command Set E7h : RDNVM2 (NV Memory Status Read2) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 1 1 1 0 0 1 1 1 E7h st Parameter Read 0 0 0 0 0 ID3_ MK [2:0] 00h The register uses a mark to record the NV memory programmed time. The bits are increase “+1” automatically after writing the PGM_DATA [7:0] to the NV memory. ID3_MK [2:0]: ID3_MK [2:0] Description 0 0 0 No Programmed 0 0 1 Programmed 1 time already 0 1 1 Programmed 2 times already 1 1 1 Programmed 3 times already Restriction To enable this command, “Page 1 Command Set enable register (FFh) ” must set first. Register Availability Status Availability Normal Mode On, Sleep Out Yes Sleep Out Yes Sleep In Yes Default Status Default Value ID3_ MK [2:0] Power ON Sequence 3’h0 S/W Reset 3’h0

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 236 of 328 4.4.44. NV Memory Status Read3 (E8h) Page 1 Command Set E8h : RDNVM3 (NV Memory Status Read3) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 1 1 1 0 1 0 0 0 E8h st Parameter Read GMAP_MK GMAN_MK VCM2_MK [2:0] VCM1_MK [2:0] 00h The register uses a mark to record the NV memory programmed time. The bits are increase “+1” automatically after writing the PGM_DATA [7:0] to the NV memory. VCM1_MK [2:0] /VCM2_MK [2:0]: VCM1_MK [2:0] /VCM2_MK [2:0] Description 0 0 0 No Programmed 0 0 1 Programmed 1 time already 0 1 1 Programmed 2 times already 1 1 1 Programmed 3 times already GAMP_MK / GAMN_MK : GAMP_MK / GAMN_MK Description

0 No Programmed

1 Programmed 1 time already

Restriction To enable this command, “Page 1 Command Set enable register (FFh) ” must set first. Register Availability Status Availability Normal Mode On, Sleep Out Yes Sleep Out Yes Sleep In Yes Default Status Default Value GAMP_MK GAMN_MK VCM2_MK [2:0] VCM1_MK [2:0] Power ON Sequence 1’h0 1’h0 3’h0 3’h0 S/W Reset 1’h0 1’h0 3’h0 3’h0

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 237 of 328 4.4.45. NV Memory Status Read4 (E9h) Page 1 Command Set E9h : RDNVM4 (NV Memory Status Read4) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 1 1 1 0 1 0 0 1 E9h st Parameter Read OTP BUSY 0 0 0 0 0 0 0 00h The register uses a mark to record the NV memory programmed time. The bits are increase “+1” automatically after writing the PGM_DATA [7:0] to the NV memory. OTP BUSY: The status bit of the NV memory programming. BUSY The Status of NV Memory

0 Idle

1 Busy

Restriction To enable this command, “Page 1 Command Set enable register (FFh) ” must set first. Register Availability Status Availability Normal Mode On, Sleep Out Yes Sleep Out Yes Sleep In Yes Default Status Default Value OTP BUSY Power ON Sequence 1’h0 S/W Reset 1’h0

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 238 of 328 4.4.46. NV Memory Status Read5 (EAh) Page 1 Command Set EAh : RDNVM5 (NV Memory Status Read5) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 1 1 1 0 1 0 1 0 EAh st Parameter Read NVM_READ_DATA [7:0] XXh NVM_READ_DATA[7:0]: The NV memory data of the “NVM_READ_ADR[7:0]” address is read out. See figure “NV Memory Read flow”.. Restriction To enable this command, “Page 1 Command Set enable register (FFh) ” must set first. Register Availability Status Availability Normal Mode On, Sleep Out Yes Sleep Out Yes Sleep In Yes Default Status Default Value NVM_READ_DATA [7:0] Power ON Sequence 8’h00 S/W Reset 8’h00

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 239 of 328 4.5. Page 2 Command Description 4.5.1. Digital Gamma Control 1 (00h~3Fh) Page 2 Command Set Command Write / Read Parameter Default (Hex)D7 D6 D5 D4 D3 D2 D1 D0 00h Write RCA0 [3:0] BCA0 [3:0] - 01h Write RCA1 [3:0] BCA1 [3:0] - 02h Write RCA2 [3:0] BCA2 [3:0] - 03h Write RCA3 [3:0] BCA3 [3:0] - 04h Write RCA4 [3:0] BCA4 [3:0] - 05h Write RCA5 [3:0] BCA5 [3:0] - 06h Write RCA6 [3:0] BCA6 [3:0] - 07h Write RCA7 [3:0] BCA7 [3:0] - 08h Write RCA8 [3:0] BCA8 [3:0] - 09h Write RCA9 [3:0] BCA9 [3:0] - 0Ah Write RCA10 [3:0] BCA10 [3:0] - 0Bh Write RCA11 [3:0] BCA11 [3:0] - 0Ch Write RCA12 [3:0] BCA12 [3:0] - 0Dh Write RCA13 [3:0] BCA13 [3:0] - 0Eh Write RCA14 [3:0] BCA14 [3:0] - 0Fh Write RCA15 [3:0] BCA15 [3:0] - 10h Write RCA16 [3:0] BCA16 [3:0] - 11h Write RCA17 [3:0] BCA17 [3:0] - 12h Write RCA18 [3:0] BCA18 [3:0] - 13h Write RCA19 [3:0] BCA19 [3:0] - 14h Write RCA20 [3:0] BCA20 [3:0] - 15h Write RCA21 [3:0] BCA21 [3:0] - 16h Write RCA22 [3:0] BCA22 [3:0] - 17h Write RCA23 [3:0] BCA23 [3:0] - 18h Write RCA24 [3:0] BCA24 [3:0] - 19h Write RCA25 [3:0] BCA25 [3:0] - 1Ah Write RCA26 [3:0] BCA26 [3:0] - 1Bh Write RCA27 [3:0] BCA27 [3:0] - 1Ch Write RCA28 [3:0] BCA28 [3:0] - 1Dh Write RCA29 [3:0] BCA29 [3:0] - 1Eh Write RCA30 [3:0] BCA30 [3:0] - 1Fh Write RCA31 [3:0] BCA31 [3:0] - 20h Write RCA32 [3:0] BCA32 [3:0] - 21h Write RCA33 [3:0] BCA33 [3:0] - 22h Write RCA34 [3:0] BCA34 [3:0] - 23h Write RCA35 [3:0] BCA35 [3:0] - 24h Write RCA36 [3:0] BCA36 [3:0] - 25h Write RCA37 [3:0] BCA37 [3:0] - 26h Write RCA38 [3:0] BCA38 [3:0] - 27h Write RCA39 [3:0] BCA39 [3:0] - 28h Write RCA40 [3:0] BCA40 [3:0] - 29h Write RCA41 [3:0] BCA41 [3:0] - 2Ah Write RCA42 [3:0] BCA42 [3:0] - 2Bh Write RCA43 [3:0] BCA43 [3:0] - 2Ch Write RCA44 [3:0] BCA44 [3:0] - 2Dh Write RCA45 [3:0] BCA45 [3:0] - 2Eh Write RCA46 [3:0] BCA46 [3:0] - 2Fh Write RCA47 [3:0] BCA47 [3:0] - 30h Write RCA48 [3:0] BCA48 [3:0] -

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 240 of 328 31h Write RCA49 [3:0] BCA49 [3:0] - 32h Write RCA50 [3:0] BCA50 [3:0] - 33h Write RCA51 [3:0] BCA51 [3:0] - 34h Write RCA52 [3:0] BCA52 [3:0] - 35h Write RCA53 [3:0] BCA53 [3:0] - 36h Write RCA54 [3:0] BCA54 [3:0] - 37h Write RCA55 [3:0] BCA55 [3:0] - 38h Write RCA56 [3:0] BCA56 [3:0] - 39h Write RCA57 [3:0] BCA57 [3:0] - 3Ah Write RCA58 [3:0] BCA58 [3:0] - 3Bh Write RCA59 [3:0] BCA59 [3:0] - 3Ch Write RCA60 [3:0] BCA60 [3:0] - 3Dh Write RCA61 [3:0] BCA61 [3:0] - 3Eh Write RCA62 [3:0] BCA62 [3:0] - 3Fh Write RCA63 [3:0] BCA63 [3:0] - RCAx [3:0]: Gamma Macro-adjustment registers for red Gamma curve. BCAx [3:0]: Gamma Macro-adjustment registers for blue Gamma curve. Restriction To enable this command, “Page 2 Command Set enable register (FFh) ” must set first.

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 241 of 328 Register Availability Status Availability Normal Mode On, Sleep Out Yes Sleep Out Yes Sleep In Yes

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 242 of 328 4.5.2. Digital 3 Gamma Enable (40h) Page 2 Command Set 40h : D3GE (Digital 3 Gamma Enable) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 1 0 0 0 0 0 0 40h st Parameter Write / Read 0 0 0 0 0 0 0 En_3G 00h En_3G: 0 : digital 3 gamma disable 1 : digital 3 gamma enable Restriction To enable this command, “Page 2 Command Set enable register (FFh) ” must set first. Register Availability Status Availability Normal Mode On, Sleep Out Yes Sleep Out Yes Sleep In Yes Default Status Default Value En_3G Power ON Sequence 1’h0 S/W Reset No change H/W Reset 1’h0

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 243 of 328 4.6. Page 3 Command Description 4.6.1. Digital Gamma Control 2 (00h~7Fh) Page 3 Command Set Command Write / Read Parameter Default (Hex)D7 D6 D5 D4 D3 D2 D1 D0 00h Write RFA0 [3:0] BFA0 [3:0] - 01h Write RFA1 [3:0] BFA1 [3:0] - 02h Write RFA2 [3:0] BFA2 [3:0] - 03h Write RFA3 [3:0] BFA3 [3:0] - 04h Write RFA4 [3:0] BFA4 [3:0] - 05h Write RFA5 [3:0] BFA5 [3:0] - 06h Write RFA6 [3:0] BFA6 [3:0] - 07h Write RFA7 [3:0] BFA7 [3:0] - 08h Write RFA8 [3:0] BFA8 [3:0] - 09h Write RFA9 [3:0] BFA9 [3:0] - 0Ah Write RFA10 [3:0] BFA10 [3:0] - 0Bh Write RFA11 [3:0] BFA11 [3:0] - 0Ch Write RFA12 [3:0] BFA12 [3:0] - 0Dh Write RFA13 [3:0] BFA13 [3:0] - 0Eh Write RFA14 [3:0] BFA14 [3:0] - 0Fh Write RFA15 [3:0] BFA15 [3:0] - 10h Write RFA16 [3:0] BFA16 [3:0] - 11h Write RFA17 [3:0] BFA17 [3:0] - 12h Write RFA18 [3:0] BFA18 [3:0] - 13h Write RFA19 [3:0] BFA19 [3:0] - 14h Write RFA20 [3:0] BFA20 [3:0] - 15h Write RFA21 [3:0] BFA21 [3:0] - 16h Write RFA22 [3:0] BFA22 [3:0] - 17h Write RFA23 [3:0] BFA23 [3:0] - 18h Write RFA24 [3:0] BFA24 [3:0] - 19h Write RFA25 [3:0] BFA25 [3:0] - 1Ah Write RFA26 [3:0] BFA26 [3:0] - 1Bh Write RFA27 [3:0] BFA27 [3:0] - 1Ch Write RFA28 [3:0] BFA28 [3:0] - 1Dh Write RFA29 [3:0] BFA29 [3:0] - 1Eh Write RFA30 [3:0] BFA30 [3:0] - 1Fh Write RFA31 [3:0] BFA31 [3:0] - 20h Write RFA32 [3:0] BFA32 [3:0] - 21h Write RFA33 [3:0] BFA33 [3:0] - 22h Write RFA34 [3:0] BFA34 [3:0] - 23h Write RFA35 [3:0] BFA35 [3:0] - 24h Write RFA36 [3:0] BFA36 [3:0] - 25h Write RFA37 [3:0] BFA37 [3:0] - 26h Write RFA38 [3:0] BFA38 [3:0] - 27h Write RFA39 [3:0] BFA39 [3:0] - 28h Write RFA40 [3:0] BFA40 [3:0] - 29h Write RFA41 [3:0] BFA41 [3:0] - 2Ah Write RFA42 [3:0] BFA42 [3:0] - 2Bh Write RFA43 [3:0] BFA43 [3:0] - 2Ch Write RFA44 [3:0] BFA44 [3:0] - 2Dh Write RFA45 [3:0] BFA45 [3:0] - 2Eh Write RFA46 [3:0] BFA46 [3:0] - 2Fh Write RFA47 [3:0] BFA47 [3:0] - 30h Write RFA48 [3:0] BFA48 [3:0] -

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 244 of 328 31h Write RFA49 [3:0] BFA49 [3:0] - 32h Write RFA50 [3:0] BFA50 [3:0] - 33h Write RFA51 [3:0] BFA51 [3:0] - 34h Write RFA52 [3:0] BFA52 [3:0] - 35h Write RFA53 [3:0] BFA53 [3:0] - 36h Write RFA54 [3:0] BFA54 [3:0] - 37h Write RFA55 [3:0] BFA55 [3:0] - 38h Write RFA56 [3:0] BFA56 [3:0] - 39h Write RFA57 [3:0] BFA57 [3:0] - 3Ah Write RFA58 [3:0] BFA58 [3:0] - 3Bh Write RFA59 [3:0] BFA59 [3:0] - 3Ch Write RFA60 [3:0] BFA60 [3:0] - 3Dh Write RFA61 [3:0] BFA61 [3:0] - 3Eh Write RFA62 [3:0] BFA62 [3:0] - 3Fh Write RFA63 [3:0] BFA63 [3:0] - 40h Write RFA64 [3:0] BFA64 [3:0] - 41h Write RFA65 [3:0] BFA65 [3:0] - 42h Write RFA66 [3:0] BFA66 [3:0] - 43h Write RFA67 [3:0] BFA67 [3:0] - 44h Write RFA68 [3:0] BFA68 [3:0] - 45h Write RFA69 [3:0] BFA69 [3:0] - 46h Write RFA70 [3:0] BFA70 [3:0] - 47h Write RFA71 [3:0] BFA71 [3:0] - 48h Write RFA72 [3:0] BFA72 [3:0] - 49h Write RFA73 [3:0] BFA73 [3:0] - 4Ah Write RFA74 [3:0] BFA74 [3:0] - 4Bh Write RFA75 [3:0] BFA75 [3:0] - 4Ch Write RFA76 [3:0] BFA76 [3:0] - 4Dh Write RFA77 [3:0] BFA77 [3:0] - 4Eh Write RFA78 [3:0] BFA78 [3:0] - 4Fh Write RFA79 [3:0] BFA79 [3:0] - 50h Write RFA80 [3:0] BFA80 [3:0] - 51h Write RFA81 [3:0] BFA81 [3:0] - 52h Write RFA82 [3:0] BFA82 [3:0] - 53h Write RFA83 [3:0] BFA83 [3:0] - 54h Write RFA84 [3:0] BFA84 [3:0] - 55h Write RFA85 [3:0] BFA85 [3:0] - 56h Write RFA86 [3:0] BFA86 [3:0] - 57h Write RFA87 [3:0] BFA87 [3:0] - 58h Write RFA88 [3:0] BFA88 [3:0] - 59h Write RFA89 [3:0] BFA89 [3:0] - 5Ah Write RFA90 [3:0] BFA90 [3:0] - 5Bh Write RFA91 [3:0] BFA91 [3:0] - 5Ch Write RFA92 [3:0] BFA92 [3:0] - 5Dh Write RFA93 [3:0] BFA93 [3:0] - 5Eh Write RFA94 [3:0] BFA94 [3:0] - 5Fh Write RFA95 [3:0] BFA95 [3:0] - 60h Write RFA96 [3:0] BFA96 [3:0] - 61h Write RFA97 [3:0] BFA97 [3:0] - 62h Write RFA98 [3:0] BFA98 [3:0] - 63h Write RFA99 [3:0] BFA99 [3:0] - 64h Write RFA100 [3:0] BFA100 [3:0] - 65h Write RFA101 [3:0] BFA101 [3:0] - 66h Write RFA102 [3:0] BFA102 [3:0] - 67h Write RFA103 [3:0] BFA103 [3:0] -

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 245 of 328 68h Write RFA104 [3:0] BFA104 [3:0] - 69h Write RFA105 [3:0] BFA105 [3:0] - 6Ah Write RFA106 [3:0] BFA106 [3:0] - 6Bh Write RFA107 [3:0] BFA107 [3:0] - 6Ch Write RFA108 [3:0] BFA108 [3:0] - 6Dh Write RFA109 [3:0] BFA109 [3:0] - 6Eh Write RFA110 [3:0] BFA110 [3:0] - 6Fh Write RFA111 [3:0] BFA111 [3:0] - 70h Write RFA112 [3:0] BFA112 [3:0] - 71h Write RFA113 [3:0] BFA113 [3:0] - 72h Write RFA114 [3:0] BFA114 [3:0] - 73h Write RFA115 [3:0] BFA115 [3:0] - 74h Write RFA116 [3:0] BFA116 [3:0] - 75h Write RFA117 [3:0] BFA117 [3:0] - 76h Write RFA118 [3:0] BFA118 [3:0] - 77h Write RFA119 [3:0] BFA119 [3:0] - 78h Write RFA120 [3:0] BFA120 [3:0] - 79h Write RFA121 [3:0] BFA121 [3:0] - 7Ah Write RFA122 [3:0] BFA122 [3:0] - 7Bh Write RFA123 [3:0] BFA123 [3:0] - 7Ch Write RFA124 [3:0] BFA124 [3:0] - 7Dh Write RFA125 [3:0] BFA125 [3:0] - 7Eh Write RFA126 [3:0] BFA126 [3:0] - 7Fh Write RFA127 [3:0] BFA127 [3:0] - RFAx [3:0]: Gamma Micro-adjustment register for red Gamma curve. BFAx [3:0]: Gamma Micro-adjustment register for blue Gamma curve.

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 246 of 328 Restriction To enable this command, “Page 3 Command Set enable register (FFh) ” must set first. Register Availability Status Availability Normal Mode On, Sleep Out Yes Sleep Out Yes Sleep In Yes

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 247 of 328 4.7. Page 4 Command Description 4.7.1. Digital Gamma Control 3 (00h~7Fh) Page 4 Command Set Command Write / Read Parameter Default (Hex)D7 D6 D5 D4 D3 D2 D1 D0 00h Write RFA128 [3:0] BFA128 [3:0] - 01h Write RFA129 [3:0] BFA129 [3:0] - 02h Write RFA130 [3:0] BFA130 [3:0] - 03h Write RFA131 [3:0] BFA131 [3:0] - 04h Write RFA132 [3:0] BFA132 [3:0] - 05h Write RFA133 [3:0] BFA133 [3:0] - 06h Write RFA134 [3:0] BFA134 [3:0] - 07h Write RFA135 [3:0] BFA135 [3:0] - 08h Write RFA136 [3:0] BFA136 [3:0] - 09h Write RFA137 [3:0] BFA137 [3:0] - 0Ah Write RFA138 [3:0] BFA138 [3:0] - 0Bh Write RFA139 [3:0] BFA139 [3:0] - 0Ch Write RFA140 [3:0] BFA140 [3:0] - 0Dh Write RFA141 [3:0] BFA141 [3:0] - 0Eh Write RFA142 [3:0] BFA142 [3:0] - 0Fh Write RFA143 [3:0] BFA143 [3:0] - 10h Write RFA144 [3:0] BFA144 [3:0] - 11h Write RFA145 [3:0] BFA145 [3:0] - 12h Write RFA146 [3:0] BFA146 [3:0] - 13h Write RFA147 [3:0] BFA147 [3:0] - 14h Write RFA148 [3:0] BFA148 [3:0] - 15h Write RFA149 [3:0] BFA149 [3:0] - 16h Write RFA150 [3:0] BFA150 [3:0] - 17h Write RFA151 [3:0] BFA151 [3:0] - 18h Write RFA152 [3:0] BFA152 [3:0] - 19h Write RFA153 [3:0] BFA153 [3:0] - 1Ah Write RFA154 [3:0] BFA154 [3:0] - 1Bh Write RFA155 [3:0] BFA155 [3:0] - 1Ch Write RFA156 [3:0] BFA156 [3:0] - 1Dh Write RFA157 [3:0] BFA157 [3:0] - 1Eh Write RFA158 [3:0] BFA158 [3:0] - 1Fh Write RFA159 [3:0] BFA159 [3:0] - 20h Write RFA160 [3:0] BFA160 [3:0] - 21h Write RFA161 [3:0] BFA161 [3:0] - 22h Write RFA162 [3:0] BFA162 [3:0] - 23h Write RFA163 [3:0] BFA163 [3:0] - 24h Write RFA164 [3:0] BFA164 [3:0] - 25h Write RFA165 [3:0] BFA165 [3:0] - 26h Write RFA166 [3:0] BFA166 [3:0] - 27h Write RFA167 [3:0] BFA167 [3:0] - 28h Write RFA168 [3:0] BFA168 [3:0] - 29h Write RFA169 [3:0] BFA169 [3:0] - 2Ah Write RFA170 [3:0] BFA170 [3:0] - 2Bh Write RFA171 [3:0] BFA171 [3:0] - 2Ch Write RFA172 [3:0] BFA172 [3:0] - 2Dh Write RFA173 [3:0] BFA173 [3:0] - 2Eh Write RFA174 [3:0] BFA174 [3:0] - 2Fh Write RFA175 [3:0] BFA175 [3:0] - 30h Write RFA176 [3:0] BFA176 [3:0] -

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 248 of 328 31h Write RFA177 [3:0] BFA177 [3:0] - 32h Write RFA178 [3:0] BFA178 [3:0] - 33h Write RFA179 [3:0] BFA179 [3:0] - 34h Write RFA180 [3:0] BFA180 [3:0] - 35h Write RFA181 [3:0] BFA181 [3:0] - 36h Write RFA182 [3:0] BFA182 [3:0] - 37h Write RFA183 [3:0] BFA183 [3:0] - 38h Write RFA184 [3:0] BFA184 [3:0] - 39h Write RFA185 [3:0] BFA185 [3:0] - 3Ah Write RFA186 [3:0] BFA186 [3:0] - 3Bh Write RFA187 [3:0] BFA187 [3:0] - 3Ch Write RFA188 [3:0] BFA188 [3:0] - 3Dh Write RFA189 [3:0] BFA189 [3:0] - 3Eh Write RFA190 [3:0] BFA190 [3:0] - 3Fh Write RFA191 [3:0] BFA191 [3:0] - 40h Write RFA192 [3:0] BFA192 [3:0] - 41h Write RFA193 [3:0] BFA193 [3:0] - 42h Write RFA194 [3:0] BFA194 [3:0] - 43h Write RFA195 [3:0] BFA195 [3:0] - 44h Write RFA196 [3:0] BFA196 [3:0] - 45h Write RFA197 [3:0] BFA197 [3:0] - 46h Write RFA198 [3:0] BFA198 [3:0] - 47h Write RFA199 [3:0] BFA199 [3:0] - 48h Write RFA200 [3:0] BFA200 [3:0] - 49h Write RFA201 [3:0] BFA201 [3:0] - 4Ah Write RFA202 [3:0] BFA202 [3:0] - 4Bh Write RFA203 [3:0] BFA203 [3:0] - 4Ch Write RFA204 [3:0] BFA204 [3:0] - 4Dh Write RFA205 [3:0] BFA205 [3:0] - 4Eh Write RFA206 [3:0] BFA206 [3:0] - 4Fh Write RFA207 [3:0] BFA207 [3:0] - 50h Write RFA208 [3:0] BFA208 [3:0] - 51h Write RFA209 [3:0] BFA209 [3:0] - 52h Write RFA210 [3:0] BFA210 [3:0] - 53h Write RFA211 [3:0] BFA211 [3:0] - 54h Write RFA212 [3:0] BFA212 [3:0] - 55h Write RFA213 [3:0] BFA213 [3:0] - 56h Write RFA214 [3:0] BFA214 [3:0] - 57h Write RFA215 [3:0] BFA215 [3:0] - 58h Write RFA216 [3:0] BFA216 [3:0] - 59h Write RFA217 [3:0] BFA217 [3:0] - 5Ah Write RFA218 [3:0] BFA218 [3:0] - 5Bh Write RFA219 [3:0] BFA219 [3:0] - 5Ch Write RFA220 [3:0] BFA220 [3:0] - 5Dh Write RFA221 [3:0] BFA221 [3:0] - 5Eh Write RFA222 [3:0] BFA222 [3:0] - 5Fh Write RFA223 [3:0] BFA223 [3:0] - 60h Write RFA224 [3:0] BFA224 [3:0] - 61h Write RFA225 [3:0] BFA225 [3:0] - 62h Write RFA226 [3:0] BFA226 [3:0] - 63h Write RFA227 [3:0] BFA227 [3:0] - 64h Write RFA228 [3:0] BFA228 [3:0] - 65h Write RFA229 [3:0] BFA229 [3:0] - 66h Write RFA230 [3:0] BFA230 [3:0] - 67h Write RFA231 [3:0] BFA231 [3:0] -

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 249 of 328 68h Write RFA232 [3:0] BFA232 [3:0] - 69h Write RFA233 [3:0] BFA233 [3:0] - 6Ah Write RFA234 [3:0] BFA234 [3:0] - 6Bh Write RFA235 [3:0] BFA235 [3:0] - 6Ch Write RFA236 [3:0] BFA236 [3:0] - 6Dh Write RFA237 [3:0] BFA237 [3:0] - 6Eh Write RFA238 [3:0] BFA238 [3:0] - 6Fh Write RFA239 [3:0] BFA239 [3:0] - 70h Write RFA240 [3:0] BFA240 [3:0] - 71h Write RFA241 [3:0] BFA241 [3:0] - 72h Write RFA242 [3:0] BFA242 [3:0] - 73h Write RFA243 [3:0] BFA243 [3:0] - 74h Write RFA244 [3:0] BFA244 [3:0] - 75h Write RFA245 [3:0] BFA245 [3:0] - 76h Write RFA246 [3:0] BFA246 [3:0] - 77h Write RFA247 [3:0] BFA247 [3:0] - 78h Write RFA248 [3:0] BFA248 [3:0] - 79h Write RFA249 [3:0] BFA249 [3:0] - 7Ah Write RFA250 [3:0] BFA250 [3:0] - 7Bh Write RFA251 [3:0] BFA251 [3:0] - 7Ch Write RFA252 [3:0] BFA252 [3:0] - 7Dh Write RFA253 [3:0] BFA253 [3:0] - 7Eh Write RFA254 [3:0] BFA254 [3:0] - 7Fh Write RFA255 [3:0] BFA255 [3:0] - RFAx [3:0]: Gamma Micro-adjustment register for red Gamma curve. BFAx [3:0]: Gamma Micro-adjustment register for blue Gamma curve.

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 250 of 328 Restriction To enable this command, “Page 4 Command Set enable register (FFh) ” must set first. Register Availability Status Availability Normal Mode On, Sleep Out Yes Sleep Out Yes Sleep In Yes

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 251 of 328 4.8. Page 5 Command Description 4.8.1. Backlight Control 1 (00h) Page 5 Command Set 00h : BLCTRL1 (Backlight Control 1) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 0 0 0 0 0 0 00h st Parameter Write / Read PWM_DIV[7:0] E8h PWM_DIV [7:0]: LEDPWM output period control. This command is used to adjust the PWM waveform period of LEDPWM. The PWM period is calculated by using the following equation. ( _ [7 : 0] 1) 255 LEDPWM MHzf PWM DIV= +× PWM_DIV[7:0 FLEDPWM D7 D6 D D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 70.58 KHz 0 0 0 0 0 0 0 1 35.29 KHz 0 0 0 0 0 0 1 0 23.53 KHz 0 0 0 0 0 0 1 1 17.65 KHz 0 0 0 0 0 1 0 0 14.12 KHz 1 1 1 1 1 0 1 1 280.1 Hz 1 1 1 1 1 1 0 0 279.0 Hz 1 1 1 1 1 1 0 1 277.9 Hz 1 1 1 1 1 1 1 0 276.8 Hz 1 1 1 1 1 1 1 1 275.7 Hz Note : The output frequency tolerance of internal frequency divider in CABC is ±10% Restriction To enable this command, “Page 5 Command Set enable register (FFh) ” must set first. Register Availability Status Availability Normal Mode On, Sleep Out Yes Sleep Out Yes Sleep In Yes Default Status Default Value PWM_DIV[7:0] Power ON Sequence 8’hE8 S/W Reset No change H/W Reset 8’hE8

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 252 of 328 4.8.2. Backlight Control 2 (01h) Page 5 Command Set 01h : BLCTRL2 (Backlight Control 2) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 0 0 0 0 0 1 01h st Parameter Write / Read THRES_MOV[3:0] THRES_STILL[3:0] BBh THRES_MOV [3:0]: This parameter is used to set the ratio (percentage) of the maximum number of pixels that makes display image white (data=”63) to the total number of pixels by image process in Moving Image mode. After this parameter sets the number of pixels that makes display image white, then the threshold grayscale value (DTH) that makes display image white is set so that the number of the pixels set by this parameter does not change. THRES_MOV[3:0] Description THRES_MOV[3:0] Description D3 D2 D1 D0 D3 D2 D1 D0 0 0 0 0 99 % 1 0 0 0 84 % 0 0 0 1 98 % 1 0 0 1 82 % 0 0 1 0 96 % 1 0 1 0 80 % 0 0 1 1 94 % 1 0 1 1 78 % 0 1 0 0 92 % 1 1 0 0 76 % 0 1 0 1 90 % 1 1 0 1 74 % 0 1 1 0 88 % 1 1 1 0 72 % 0 1 1 1 86 % 1 1 1 1 70 % THRES_STILL [3:0]: This parameter is used to set the ratio (percentage) of the maximum number of pixels that makes display image white (data=”63) to the total number of pixels by image process in Still Picture mode. After this parameter sets the number of pixels that makes display image white, then the threshold grayscale value (DTH) that makes display image white is set so that the number of the pixels set by this parameter does not change. THRES_STILL[3:0] Description THRES_STILL[3:0] Description D3 D2 D1 D0 D3 D2 D1 D0 0 0 0 0 99 % 1 0 0 0 84 % 0 0 0 1 98 % 1 0 0 1 82 % 0 0 1 0 96 % 1 0 1 0 80 % 0 0 1 1 94 % 1 0 1 1 78 % 0 1 0 0 92 % 1 1 0 0 76 % 0 1 0 1 90 % 1 1 0 1 74 % 0 1 1 0 88 % 1 1 1 0 72 % 0 1 1 1 86 % 1 1 1 1 70 % Restriction To enable this command, “Page 5 Command Set enable register (FFh) ” must set first.

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 253 of 328 Register Availability Status Availability Normal Mode On, Sleep Out Yes Sleep Out Yes Sleep In Yes Default Status Default Value THRES_MOV[3:0] THRES_STILL[3:0] Power ON Sequence 4’hB 4’hB S/W Reset No change No change H/W Reset 4’hB 4’hB

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 254 of 328 4.8.3. Backlight Control 3 (02h) Page 5 Command Set 02h : BLCTRL3 (Backlight Control 3) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 0 0 0 0 1 0 02h st Parameter Write / Read 0 0 0 0 THRES_UI[3:0] 0Bh THRES_UI [3:0]: This parameter is used to set the ratio (percentage) of the maximum number of pixels that makes display image white (data=”63) to the total number of pixels by image process in UI (User Interface Image mode). After this parameter sets the number of pixels that makes display image white, then the threshold grayscale value (DTH) that makes display image white is set so that the number of the pixels set by this parameter does not change. THRES_UI[3:0] Description THRES_UI[3:0] Description D3 D2 D1 D0 D3 D2 D1 D0 0 0 0 0 99 % 1 0 0 0 84 % 0 0 0 1 98 % 1 0 0 1 82 % 0 0 1 0 96 % 1 0 1 0 80 % 0 0 1 1 94 % 1 0 1 1 78 % 0 1 0 0 92 % 1 1 0 0 76 % 0 1 0 1 90 % 1 1 0 1 74 % 0 1 1 0 88 % 1 1 1 0 72 % 0 1 1 1 86 % 1 1 1 1 70 % Restriction To enable this command, “Page 5 Command Set enable register (FFh) ” must set first. Register Availability Status Availability Normal Mode On, Sleep Out Yes Sleep Out Yes Sleep In Yes Default Status Default Value THRES_UI Power ON Sequence 4’hB S/W Reset No change H/W Reset 4’hB

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 255 of 328 4.8.4. Backlight Control 4 (03h) Page 5 Command Set 03h : BLCTRL4 (Backlight Control 4) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 0 0 0 0 1 1 03h st Parameter Write / Read DTH_MOV[3:0] DTH_STILL[3:0] A8h DTH_MOV [3:0]: This parameter is used to set the minimum limitation of grayscale threshold value in Moving Image mode. DTH_MOV[3:0] Description DTH_MOV[3:0] Description D3 D2 D1 D0 D3 D2 D1 D0 0 0 0 0 224 1000 192 0 0 0 1 220 1001 188 0 0 1 0 216 1010 184 0 0 1 1 212 1011 180 0 1 0 0 208 1100 176 0 1 0 1 204 1101 172 0 1 1 0 200 1110 168 0 1 1 1 196 1111 164 DTH_STILL [3:0]: This parameter is used to set the minimum limitation of grayscale threshold value in Still Picture mode. DTH_STILL[3:0] Description DTH_STILL[3:0] Description D3 D2 D1 D0 D3 D2 D1 D0 0 0 0 0 224 1000 192 0 0 0 1 220 1001 188 0 0 1 0 216 1010 184 0 0 1 1 212 1011 180 0 1 0 0 208 1100 176 0 1 0 1 204 1101 172 0 1 1 0 200 1110 168 0 1 1 1 196 1111 164 Transmittance DTH02 5 5 Gray scale Restriction To enable this command, “Page 5 Command Set enable register (FFh) ” must set first.

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 256 of 328 Register Availability Status Availability Normal Mode On, Sleep Out Yes Sleep Out Yes Sleep In Yes Default Status Default Value DTH_MOV[3:0] DTH_STILL[3:0] Power ON Sequence 4’hA 4’h8 S/W Reset No change No change H/W Reset 4’hA 4’h8

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 257 of 328 4.8.5. Backlight Control 5 (04h) Page 5 Command Set 04h : BLCTRL5 (Backlight Control 5) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 0 0 0 1 0 0 04h st Parameter Write / Read 0 0 0 0 DTH_UI[3:0] 04h DTH_UI [3:0]: This parameter is used to set the minimum limitation of grayscale threshold value in UI (User Interface Image mode). DTH_UI[3:0] Description DTH_UI[3:0] Description D3 D D1 D0 D3 D2 D1 D0 0 0 0 0 252 1 0 0 0 220 0 0 0 1 248 1 0 0 1 216 0 0 1 0 244 1 0 1 0 212 0 0 1 1 240 1 0 1 1 208 0 1 0 0 236 1 1 0 0 204 0 1 0 1 232 1 1 0 1 200 0 1 1 0 228 1 1 1 0 196 0 1 1 1 224 1 1 1 1 192 Transmittance DTH02 5 5 Gray scale Restriction To enable this command, “Page 5 Command Set enable register (FFh) ” must set first. Register Availability Status Availability Normal Mode On, Sleep Out Yes Sleep Out Yes Sleep In Yes Default Status Default Value DTH_UI Power ON Sequence 4’h4 S/W Reset No change H/W Reset 4’h4

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 258 of 328 4.8.6. Backlight Control 6 (05h) Page 5 Command Set 05h : BLCTRL6 (Backlight Control 6) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 0 0 0 1 0 1 05h st Parameter Write / Read 0 DIM_MOV[2:0] 0 DIM_STILL[2:0] 43h DIM_STILL[2:0]: This parameter is used to set the transition time of brightness level change to avoid the sharp brightness change on vision in Still Picture mode. DIM_MOV[2:0]: This parameter is used to set the transition time of brightness level change to avoid the sharp brightness change on vision in Moving Image mode. DIM_MOV[2 :0]/ DIM_STILL[2 :0] Description D2 D1 D0 0 0 0 2 frame 0 0 1 3 frame 0 1 0 4 frames 0 1 1 6 frames 1 0 0 10 frames 1 0 1 18 frames 1 1 0 34 frames 1 1 1 66 frames Time DIM1[2:0] DIM1[2:0] Brightness =A Brightness =B Brightness =C Transition time Transition time DIM2[2:0] Note: DIM1[2:0] mean DIM_MOV[2:0] or DIM_STILL[2:0] or DIM_UI[2:0] in different mode. Restriction To enable this command, “Page 5 Command Set enable register (FFh) ” must set first. Register Availability Status Availability Normal Mode On, Sleep Out Yes Sleep Out Yes Sleep In Yes Default Status Default Value DIM_MOV[2:0] DIM_STILL[2:0] Power ON Sequence 3’h4 3’h3 S/W Reset No change No change H/W Reset 3’h4 3’h3

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 259 of 328 4.8.7. Backlight Control 7 (06h) Page 5 Command Set 06h : BLCTRL7 (Backlight Control 7) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 0 0 0 1 1 0 06h st Parameter Write / Read DIM_MIN[3:0] 0 DIM_UI[2:0] 02h DIM_UI[2:0]: This parameter is used to set the transition time of brightness level change to avoid the sharp brightness change on vision in UI mode (User Interface Image mode). DIM_UI[2:0] Description D2 D1 D0 000 2 f r a m e 001 3 f r a m e 010 4 f r a m e s 011 6 f r a m e s 100 1 0 f r a m e s 101 1 8 f r a m e s 110 3 4 f r a m e s 111 6 6 f r a m e s Note1: DIM1[2:0] means DIM_MOV[2:0] or DIM_STILL[2:0] or DIM_UI[2:0] in different mode. Note2: DIM2[3:0] means DIM_MIN[3:0]. DIM_MIN [3:0]: This parameter is used to set the imitation of minimum brightness change. If this parameter is large than the difference between target brightness and current brightness, then the brightness will not change. Restriction To enable this command, “Page 5 Command Set enable register (FFh) ” must set first. Register Availability Status Availability Normal Mode On, Sleep Out Yes Sleep Out Yes Sleep In Yes Default Status Default Value DIM_MIN[3:0] DIM_UI[2:0] Power ON Sequence 4’h0 3’h2 S/W Reset No change No change H/W Reset 4’h0 3’h2

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 260 of 328 4.8.8. Backlight Control 8 (07h) Page 5 Command Set 07h : BLCTRL8 (Backlight Control 8) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 0 0 0 1 1 1 07h st Parameter Write / Read LABS_SRE_THR[3:0] LABC SRE ENABLE LEDONR LEDONPOL PWMPOL B0h PWMPOL: The bit is used to define polarity of LEDPWM signal. BL PWMPOL LEDPWM pin 0 0 Always low 0 1 Always high 1 0 Original polarity of PWM signal 1 1 I n v e r s e d p o l a r i t y o f P W M s i g n a l LEDONPOL: This bit is used to control LEDON pin. BL LEDONPOL LEDON pin 0 0 0 0 1 1 1 0 LEDONR 1 1 Inversed LEDONR LEDONR: This bit is used to control LEDON pin. LEDONR Description

0 Low

1 High

LABCSREENABLE: The bit enables SRE function. LABS_SRE_THR[3:0]: The threshold value of LABC to turn-on SRE with hysteresis if LABC_SRE_ENABLE=1 AmbientLightSensor[7:0]>=LABC_SRE_THE[3:0]*16, turn-on SRE AmbientLightSensor[7:0]<=(LABC_SRE_THE[3:0]-1)*16, turn-off SRE Restriction 1. To enable this command, “Page 5 Command Set enable register (FFh) ” must set first. 2. The setting of LABC_SRE_THE[3:0] must be over 1 hex or equal 1 hex. Register Availability Status Availability Normal Mode On, Sleep Out Yes Sleep Out Yes Sleep In Yes Default Status Default Value LABS_SRE_THR[3:0] LABCSRE ENABLE LEDONR LEDONPOL PWMPOL Power On Sequence 4’ hB 1’h0 1’h0 1’h0 1’h0 S/W Reset No change No change No change No change No change H/W Reset 4’hB 1’h0 1’h0 1’h0 1’h0

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 261 of 328 4.8.9. Backlight Control 9 (09h) Page 5 Command Set 09h : BLCTRL9 (Backlight Control 9) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 0 0 1 0 0 1 09h st Parameter Write / Read SRECABC BOOSTEN 1 1 1 SRECABC EN 1 0 0 74h SRECABCBOOSTEN: The bit boosts the SRE function. SRECABCEN: The bit enables SRE function. Restriction To enable this command, “Page 5 Co mmand Set enable register (FFh) ” must set first. Register Availability Status Availability Normal Mode On, Sleep Out Yes Sleep Out Yes Sleep In Yes Default Status Default Value SRECABC BOOSTEN SRECABC EN Power On Sequence 1’h0 1’h0 S/W Reset No change No change H/W Reset 1’h0 1’h0

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 262 of 328 4.8.10. Backlight Control 10 (0Ch) Page 5 Command Set 0Ch : BLCTRL10 (Backlight Control 10) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 0 0 1 1 0 0 0Ch st Parameter Write / Read ALS8BIT[7:0] A0h ALS8BIT[7:0]: This command is used to give an ambient light information. Restriction To enable this command, “Page 5 Co mmand Set enable register (FFh) ” must set first. Register Availability Status Availability Normal Mode On, Sleep Out Yes Sleep Out Yes Sleep In Yes Default Status Default Value ALS8BIT[7:0] Power On Sequence 8’hA0 S/W Reset No change H/W Reset 8’hA0

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 263 of 328 4.8.11. Color Enhacement Control 1~24 (25h~3Ch) Page 5 Command Set Command Write / Read Parameter Default (Hex)D7 D6 D5 D4 D3 D2 D1 D0 25h Write / Read 0 0 0 FIRST_AXIS_1[4:0] 00h 26h Write / Read 0 0 0 FIRST_AXIS _2[4:0] 00h 27h Write / Read 0 0 0 FIRST_AXIS _3[4:0] 00h 28h Write / Read 0 0 0 FIRST_AXIS _4[4:0] 00h 29h Write / Read 0 0 0 SECOND_AXIS 1[4:0] 00h 2Ah Write / Read 0 0 0 SECOND_AXIS _2[4:0] 00h 2Bh Write / Read 0 0 0 SECOND_AXIS _3[4:0] 00h 2Ch Write / Read 0 0 0 SECOND_AXIS _4[4:0] 00h 2Dh Write / Read 0 0 0 THIRD_ AXIS _1[4:0] 00h 2Eh Write / Read 0 0 0 THIRD _ AXIS _2[4:0] 00h 2Fh Write / Read 0 0 0 THIRD _ AXIS _3[4:0] 00h 30h Write / Read 0 0 0 THIRD _ AXIS _4[4:0] 00h 31h Write / Read 0 0 0 FOURTH_ AXIS _1[4:0] 00h 32h Write / Read 0 0 0 FOURTH _ AXIS _2[4:0] 00h 33h Write / Read 0 0 0 FOURTH _ AXIS _3[4:0] 00h 34h Write / Read 0 0 0 FOURTH _ AXIS _4[4:0] 00h 35h Write / Read 0 0 0 FIFTH_ AXIS _1[4:0] 00h 36h Write / Read 0 0 0 FIFTH _ AXIS _2[4:0] 00h 37h Write / Read 0 0 0 FIFTH _ AXIS _3[4:0] 00h 38h Write / Read 0 0 0 FIFTH _ AXIS _4[4:0] 00h 39h Write / Read 0 0 0 SIXTH_ AXIS _1[4:0] 00h 3Ah Write / Read 0 0 0 SIXTH_ AXIS _2[4:0] 00h 3Bh Write / Read 0 0 0 SIXTH_ AXIS _3[4:0] 00h 3Ch Write / Read 0 0 0 SIXTH_ AXIS _4[4:0] 00h Each command is based on value 00h, the localizable saturation ratio is calculated as below: Axis setting value = 0~31 (00~1Fh) Saturation Ratio = 0~7.75 eFIRST_AXIS_1[4:0] : Mapping to Figure 95(b) axis1 FIRST_AXIS_2[4:0] : Mapping to Figure 95(b) axis2 FIRST_AXIS_3[4:0] : Mapping to Figure 95(b) axis3 FIRST_AXIS_4[4:0] : Mapping to Figure 95(b) axis4 SECOND _AXIS_1[4:0] : Mapping to Figure 95(b) axis5 SECOND _AXIS_2[4:0] : Mapping to Figure 95(b) axis6 SECOND _AXIS_3[4:0] : Mapping to Figure 95(b) axis7 SECOND _AXIS_4[4:0] : Mapping to Figure 95(b) axis8 THIRD _AXIS_1[4:0] : Mapping to Figure 95(b) axis9 THIRD _AXIS_2[4:0] : Mapping to Figure 95(b) axis10 THIRD _AXIS_3[4:0] : Mapping to Figure 95(b) axis11 THIRD _AXIS_4[4:0] : Mapping to Figure 95(b) axis12 FOURTH _AXIS_1[4:0] : Mapping to Figure 95(b) axis13 FOURTH _AXIS_2[4:0] : Mapping to Figure 95(b) axis14 FOURTH _AXIS_3[4:0] : Mapping to Figure 95(b) axis15 FOURTH _AXIS_4[4:0] : Mapping to Figure 95(b) axis16 FIFTH _AXIS_1[4:0] : Mapping to Figure 95(b) axis17 FIFTH _AXIS_2[4:0] : Mapping to Figure 95(b) axis18 FIFTH _AXIS_3[4:0] : Mapping to Figure 95(b) axis19 FIFTH _AXIS_4[4:0] : Mapping to Figure 95(b) axis20 SIXTH _AXIS_1[4:0] : Mapping to Figure 95(b) axis21 SIXTH _AXIS_2[4:0] : Mapping to Figure 95(b) axis22 SIXTH _AXIS_3[4:0] : Mapping to Figure 95(b) axis23 SIXTH _AXIS_4[4:0] : Mapping to Figure 95(b) axis24

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 264 of 328 Restriction To enable this command, “Page 5 Command Set enable register (FFh) ” must set first. Register Availability Status Availability Normal Mode On, Sleep Out Yes Sleep Out Yes Sleep In Yes

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 265 of 328 4.9. Page 6 Command Description 4.9.1. GIP Setting (00h~1Dh / 20h~27h / 30h~40h) Page 6 Command Set Command Write / Read Parameter Default (Hex)D7 D6 D5 D4 D3 D2 D1 D0 00h Write / Read F_TIME_OPT STV_A_Rise[ 9:8] GIP_0_SET0 01h Write / Read STV_A_Rise[ 7:0] - 02h Write / Read GIP_0_SET1 - 03h Write / Read GIP_0_SET2 - 04h Write / Read GIP_0_SET3 - 05h Write / Read GIP_0_SET4 - 06h Write / Read CLK_A_Rise[10:8] GIP_0_SET5 - 07h Write / Read CLK_A_Rise[ 7:0] - 08h Write / Read GIP_0_SET6 - 09h Write / Read GIP_0_SET7 - 0Ah Write / Read GIP_0_SET8 - 0Bh Write / Read GIP_0_SET9 - 0Ch Write / Read GIP_0_SET10 - 0Dh Write / Read GIP_0_SET11 - 0Eh Write / Read GIP_0_SET12 - 0Fh Write / Read GIP_0_SET13 - 10h Write / Read GIP_0_SET14 - 11h Write / Read GIP_0_SET15 - 12h Write / Read GIP_0_SET16 - 13h Write / Read GIP_0_SET17 - 14h Write / Read GIP_0_SET18 - 15h Write / Read GIP_0_SET19 - 16h Write / Read GIP_0_SET20 - 17h Write / Read GIP_0_SET21 - 18h Write / Read GIP_0_SET22 - 19h Write / Read GIP_0_SET23 - 1Ah Write / Read GIP_0_SET24 - 1Bh Write / Read GIP_0_SET25 - 1Ch Write / Read GIP_0_SET26 - 1Dh Write / Read GIP_0_SET27 - Page 6 Command Set Command Write / Read Parameter Default (Hex)D7 D6 D5 D4 D3 D2 D1 D0 20h Write / Read GIP_1_SET0 - 21h Write / Read GIP_1_SET1 - 22h Write / Read GIP_1_SET2 - 23h Write / Read GIP_1_SET3 - 24h Write / Read GIP_1_SET4 - 25h Write / Read GIP_1_SET5 - 26h Write / Read GIP_1_SET6 - 27h Write / Read GIP_1_SET7 -

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 266 of 328 Page 6 Command Set Command Write / Read Parameter Default (Hex)D7 D6 D5 D4 D3 D2 D1 D0 30h Write / Read GIP_2_SET0 - 31h Write / Read GIP_2_SET1 - 32h Write / Read GIP_2_SET2 - 33h Write / Read GIP_2_SET3 - 34h Write / Read GIP_2_SET4 - 35h Write / Read GIP_2_SET5 - 36h Write / Read GIP_2_SET6 - 37h Write / Read GIP_2_SET7 - 38h Write / Read GIP_2_SET8 - 39h Write / Read GIP_2_SET9 - 3Ah Write / Read GIP_2_SET10 - 3Bh Write / Read GIP_2_SET11 - 3Ch Write / Read GIP_2_SET12 - 3Dh Write / Read GIP_2_SET13 - 3Eh Write / Read GIP_2_SET14 - 3Fh Write / Read GIP_2_SET15 - 40h Write / Read GIP_2_SET16 - F_TIME_OPT: The command set the GIP timing Mode. F_TIME_OPT Description 0 refer to internal OSC counter 1 refer to Hsync Restriction To enable this command, “Page 6 Command Set enable register (FFh) ” must set first.

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 267 of 328 Register Availability Status Availability Normal Mode On, Sleep Out Yes Sleep Out Yes Sleep In Yes

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 268 of 328 4.9.2. GOUT_VGLO Control 1 (52h) Page 6 Command Set 52h : GVLOCTRL 1(GOUT_VGLO Control 1) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 1 0 1 0 0 1 0 52h st Parameter Write / Read 0 0 0 1 GOUT_VGLO_SO[3:0] 11h GOUT_VGLO_SO [3:0]: The command sets the GIP power source of GOUT_VGLO at Sleep-Out Mode. GOUT_VGLO_SO [3:0] Description 0 0 0 0 VGL 0 0 0 1 GND 0 0 1 0 VGL_REG 0 0 1 1 Inhibited 0 1 0 0 Inhibited 0 1 0 1 Inhibited 0 1 1 0 Inhibited 0 1 1 1 Inhibited Restriction To enable this command, “Page 6 Command Set enable register (FFh) ” must set first. Register Availability Status Availability Normal Mode On, Sleep Out Yes Sleep Out Yes Sleep In Yes Default Status Default Value GOUT_VGLO_SO [3:0] Power ON Sequence 4’h0 S/W Reset No change H/W Reset 4’h0

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 269 of 328 4.9.3. GOUT_VGLO Control 2(53h) Page 6 Command Set 53h : GVLOCTRL 2(GOUT_VGLO Control 2) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 1 0 1 0 0 1 1 53h st Parameter Write / Read 0 0 0 1 GOUT_VGLO_DSP[3:0] 10h GOUT_VGLO_DSP [3:0]: The command sets the GIP power source of GOUT_VGLO at Display On Mode. GOUT_VGLO_DSP [3:0] Description 0 0 0 0 VGL 0 0 0 1 GND 0 0 1 0 VGL_REG 0 0 1 1 Inhibited 0 1 0 0 Inhibited 0 1 0 1 Inhibited 0 1 1 0 Inhibited 0 1 1 1 Inhibited Restriction To enable this command, “Page 6 Command Set enable register (FFh) ” must set first. Register Availability Status Availability Normal Mode On, Sleep Out Yes Sleep Out Yes Sleep In Yes Default Status Default Value GOUT_VGLO_DSP [3:0] Power ON Sequence 4’h0 S/W Reset No change H/W Reset 4’h0

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 270 of 328 4.9.4. GOUT_VGHO Control (54h) Page 6 Command Set 54h : GVHOCTRL (GOUT_VGHO Control) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 1 0 1 0 1 0 0 54h st Parameter Write / Read 0 GOUT_VGHO[2:0] 0 0 0 1 11h GOUT_VGHO [2:0]: The command sets the GIP power source of GOUT_VGHO. GOUT_VGHO [2:0] Description 0 0 0 VGH_REG 0 0 1 VGH 0 1 0 Inhibited 0 1 1 Inhibited 1 0 0 Inhibited 1 0 1 Inhibited 1 1 0 Inhibited 1 1 1 Inhibited Restriction To enable this command, “Page 6 Command Set enable register (FFh) ” must set first. Register Availability Status Availability Normal Mode On, Sleep Out Yes Sleep Out Yes Sleep In Yes Default Status Default Value GOUT_VGHO [2:0] Power ON Sequence 3’h1 S/W Reset No change H/W Reset 3’h1

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 271 of 328 4.10. Page 7 Command Description 4.10.1. Power Bias Control (02h) Page 7 Command Set 02h : PWBCTRL (Power Bias Control) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 0 0 0 0 1 0 02h st Parameter Write / Read 0 DDVDL_CLP_ISC [2:0] 0 DDVDH_CLP_ISC [2:0] 00h DDVDL_CLP_ISC [2:0] : DDVDL Clamp OP bias control. DDVDL_CLP _ISC [2:0] DDVDL clamp bias (uA) 0 0 0 2 0 0 1 4 0 1 0 6 0 1 1 8 1 0 0 10 1 0 1 12 1 1 0 14 1 1 1 16 DDVDH_CLP _ISC [2:0] : DDVDH Clamp OP bias control. DDVDH_CLP_ISC [2:0] DDVDH clamp bias (uA) 0 0 0 2 0 0 1 4 0 1 0 6 0 1 1 8 1 0 0 10 1 0 1 12 1 1 0 14 1 1 1 16 Restriction To enable this command, “Page 7 Command Set enable register (FFh) ” must set first. Register Availability Status Availability Normal Mode On, Sleep Out Yes Sleep Out Yes Sleep In Yes Default Status Default Value DDVDL_CLP _ISC [2:0] DDVDH_CLP _ISC [2:0] Power ON Sequence 3’h0 3’h0 S/W Reset No change No change H/W Reset 3’h0 3’h0

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 272 of 328 4.10.2. VCL Control (06h) Page 7 Command Set 06h : VCLCTRL (VCL Control) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 0 0 0 1 1 0 06h st Parameter Write / Read 0 0 0 VCLOPT 0 0 VCL_CLP[1:0] 01h VCLOPT : VCL voltage control. VCLOPT VCL Voltage

0 VCI X -1

1 VCI X -2

VCL_CLP[1:0] : Sets the VCL clamp level. VCL_CLP[1:0] VCL clamp level (V) 0 0 -2.8 0 1 -3.0 1 0 -3.2 1 1 -3.4 Restriction To enable this command, “Page 7 Command Set enable register (FFh) ” must set first. Register Availability Status Availability Normal Mode On, Sleep Out Yes Sleep Out Yes Sleep In Yes Default Status Default Value VCLOPT VCL_CLP[1:0] Power ON Sequence 1’h0 2’h1 S/W Reset No change No change H/W Reset 1’h0 2’h1

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 273 of 328 4.10.3. VGL_REG ENABLE (17h) Page 7 Command Set 17h : VGLREGEN (VGL_REG EN) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 0 1 0 1 1 1 17h st Parameter Write / Read 0 0 1 VGLREG_EN 0 0 1 0 22h VGLREG_EN : The bit is enable the VGL_REG. VGLREG_EN Description Note : The voltage setting of VGL_REG in Section 4.4.21 Restriction To enable this command, “Page 7 Command Set enable register (FFh) ” must set first. Register Availability Status Availability Normal Mode On, Sleep Out Yes Sleep Out Yes Sleep In Yes Default Status Default Value GOUT_VGHO [2:0] Power ON Sequence 3’h1 S/W Reset No change H/W Reset 3’h1

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 274 of 328 4.10.4. VREG1/2OUT ENABLE (18h) Page 7 Command Set 18h : VREG12EN (VREG1/2OUT ENABLE) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 0 0 0 1 1 0 0 0 18h st Parameter Write / Read 0 0 0 VREG EN 1 1 0 1 0Dh VREGEN : The bit enables VREG1OUT and VREG2OUT . VREGEN Description Note : The voltage setting of VREG1OUT and VREG2OUT is in Sections 4.4.24 and 4.4.25 Restriction To enable this command, “Page 7 Command Set enable register (FFh) ” must set first. Register Availability Status Availability Normal Mode On, Sleep Out Yes Sleep Out Yes Sleep In Yes Default Status Default Value VREG EN Power ON Sequence 1’h0 S/W Reset No change H/W Reset 1’h0

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 275 of 328 4.10.5. TIME CONTROL (E1h) Page 7 Command Set E1h : TIMECTRL (TIME CONTROL) Write / Read D7 D6 D5 D4 D3 D2 D1 D0 Default (Hex) Command Write 1 1 1 0 0 0 0 1 E1h st Parameter Write / Read TIME_SHIFT_ERR[3:0] 1 0 0 1 09h TIME_SHIFT_ERR[3:0] : Timming Option. Restriction To enable this command, “Page 7 Command Set enable register (FFh) ” must set first. Register Availability Status Availability Normal Mode On, Sleep Out Yes Sleep Out Yes Sleep In Yes Default Status Default Value TIME_SHIFT_ERR [3:0] Power ON Sequence 4’h0 S/W Reset No change H/W Reset 4’h0

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 277 of 328 (a) (b) (c) (d) Figure 96 ：(a)Original, (b)Low Level, (c)Medium Level, (d) High Level.

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 278 of 328 6. Sleep Out Command and Self-Diagnostic Functions 6.1. Register loading Detection Sleep Out command (See “Sleep Out (11h of the Page 0)”) is a trigger for an internal function of the display module, which indicates that if the display module loading function of factory default values from OTP (or similar device) to registers of the display controller does work properly. There are compared factory values of the OTP and register values of the display controller by the display controller (1st step: Compares register and OTP values, 2nd step: Loads OTP value to register). If both values (OTP and register values) are the same, there is inverted (= increased by 1) bit, which is defined in command Read Display Self-Diagnostic Result (0Fh)” (= RDDSDR) (The used bit of this command is D7). If these values are not same, this bit (D7) is not inverted (= not increased by 1). The flow chart for this internal function is following: YES Figure 97 Register loading Detection Note : 1. If the OTP and register values are not compared and loaded, they can be changed by commands 00h to AFh and DAh to DDh.. 2. This information is only used if TE line is used.

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 279 of 328 6.2. Functionality Detection The Sleep Out command (See “Sleep Out (11h of the Page 0)”) is a trigger for an internal function of the display module. It indicates if the display module is still running and meets functionality requirements. The internal function (= the display controller) is co mparing, if the display module still meets functionality requirements (e.g. booster voltage levels, timings, etc.). If functionality requirements are met, a bit is inverted (= increased by 1), which defined in the command “Read Di splay Self-Diagnostic Result (0Fh)” (RDDSDR) (The used bit of this command is D6). If functionality requi rement is not same, this bit (D6) is not inverted (not increased by 1).The flow chart for this internal function is following: Figure 98 Functionality Detection Note: 1. When changing from the Sleep In mode to the Sleep Out mode, 120msec are needed after the Sleep Out command before it is able to check if functionality requirements are met and the value of RDDSDR’s D6 is valid. Otherwise, there will be 5msec delay for the D6’s value to be valid when the Sleep Out command is sent in the Sleep Out mode. 2. This function is only used if TE-line is used.

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 280 of 328 7. Power ON/OFF Sequence IOVCC and VCI can be applied (or powered down) in any order. During the power off sequences, if LCD is in the Sleep Out mode, VCI and IOVCC must be powered down with minimum 120msec, and if LCD is in the Sleep In mode, VCI and IOVCC can be powered down with minimum 0msec after RESX has been released. CSX can be applied at any timing or can be permanently grounded. RESX has priority over CSX. Note: 1. There will be no damage to ILI9806E if the power sequences are not met. 2. There will be no abnormal visible effects on the display panel during the Power On/Off Sequences. 3. There will be no abnormal visible effects on the display between end of Power On Sequence and before receiving Sleep Out command. Also between receiving Sleep In command and Power Off Sequence. 4. If RESX line is not held stable by host during Power On Sequence as defined in Sections 7.1 and 7.2, then it will be necessary to apply a Hardware Reset (RESX) after Host Power On Sequence is complete to ensure correct operation. Otherwise function is not guaranteed. 5. Keep data pins DB[23:0] at low level, when VCIP or IOVCC comes later IOVCC VCI Keep Data pins DB[23:0] at low level , When VCIP or IOVCC comes later. This time is defined at the cross point of 90% of 2.8V DB[23:0] VCI IOVCC Case 1 Case 2

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 281 of 328 7.1. Case 1 –RESX line is held High or Unstable by Host at Power ON If the RESX line is held high or unstable by the host during Power On, then a Hardware Reset must be applied after both VCI and IOVCC have been applied – otherwise correct functionality is not guaranteed. There is no timing restriction upon this hardware reset. IOVCC VCI CSX RESX RESX H or L 30% 30% trPW=+/- no limit trPW=+/- no limit trPWCSX=+/- no limittrPWCSX=+/- no limit trPWRESX=+/- no limit trPWRESX=+/- no limit trPWRESX1=min 120ms trPWRESX2=min 0 ns trPWRESX2 is applied to RESX falling in the Sleep In Mode Time when the latter signal rises up to 90% of its Typical Value. e.g. When VCI comes later. This time is defined at the cross point of 90% of 2.8V, not 90% of 2.6V Time when the latter signal falls down to 90% of its Typical Value. e.g. When VCI falls earlier. This time is defined at the cross point of 90% of 2.8V, not 90% of 2.6V (Power down in Sleep Out mode) (Power down in Sleep In mode) trPWRESX1 is applied to RESX falling in the Sleep Out Mode

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 282 of 328 7.2. Case 2 – RESX line is held Low by Host at Power ON If the RESX line is held Low (and stable) by the host during Power On, then the RESX must be held low for minimum 10μsec after both VCI and IOVCC have been applied. Figure 99 Case 2 – RESX line is held Low by Host at Power ON Note: 1. Unless otherwise specified, timings herein show cross point at 50% of signal power level.

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 283 of 328 7.3. Abnormal Power Off The abnormal power off means a situation when e.g. ther e is removed a battery without the normal power off sequence. There will not be any damages for the display module or the display module will not cause any damages for the host or lines of the interface. At an abnormal power off event, ILI9806E will force the display to blank and will not be any abnormal visible effects with in 1 second on the display and remains blank until “Power On Sequence” powers it up.

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 284 of 328 8. Power Level Definition 8.1. LCM Voltage Generation Figure 100 Power Stage Diagram Note: 1. The DDVDH, DDVDL, VCOM, VGH, VGL and VCL output voltage levels are lower than their theoretical levels (Ideal voltage levels) due to current consumption at respective outputs.

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 285 of 328 8.2. Gamma Curves 8.2.1. Gamma Curve 1 (GC0) , applies the function y=x^2.2 Figure 101 Gamma Curve 1 (GC0)

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 286 of 328 9. Reset 9.1. Driver IC Input and Output pins 9.1.1. Output Pins, I/O Pins Table 39 Output and I/O Pins Pin/Line After Power ON After Hardware Reset After Software Reset DB [23:0] Hi-Z (Inactive) Hi-Z (Inactive) Hi -Z (Inactive) SDA (Output direction), SDO Hi-Z (Inact ive) Hi-Z (Inactive) H i - Z ( I n a c t i v e ) HS_D0P Hi-Z (Inactive) Hi-Z (Inactive) Hi-Z (Inactive) HS_D0N Hi-Z (Inactive) Hi-Z (Inactive) Hi-Z (Inactive) TE_L, TE_R Low Low Low LEDPWM Low Low Low Note: 1. There will be no output from DB [23:0], SDA, SDO, LEDPWM, TE, D0_P, D0_N, during Power ON/OFF sequence, hardware reset and software reset. 9.1.2. Input Pins Table 40 Input Pins Pin/Line During Power ON Process After Power ON After Hardware Reset After Software Reset During Power OFF Process RESX See Chapter 7 Input valid Input valid Input valid See Chapter 7 CSX Input invalid Input valid Input valid Input valid Input invalid DCX Input invalid Input valid Input valid Input valid Input invalid SCL Input invalid Input valid Input valid Input valid Input invalid DE Input invalid Input valid Input valid Input valid Input invalid HS Input invalid Input valid Input valid Input valid Input invalid VS Input invalid Input valid Input valid Input valid Input invalid PCLK Input invalid Input valid Input valid Input valid Input invalid DB [23:0] Input invalid Input valid Input valid Input valid Input invalid SDA (input direction), SDI Input invalid I nput valid Input valid Input valid Input invalid HS_CP Input invalid Input valid Input valid Input valid Input invalid HS_CN Input invalid Input valid Input valid Input valid Input invalid HS_D0P Input invalid Input valid I nput valid Input valid Input invalid HS_D0N Input invalid Input valid I nput valid Input valid Input invalid HS_D1P Input invalid Input valid I nput valid Input valid Input invalid HS_D1N Input invalid Input valid I nput valid Input valid Input invalid

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 288 of 328 10. NV Memory Programming 10.1. NV Memory Programming flow Figure 104 NV Memory Programming Flow

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 289 of 328 10.2. NV Memory Read flow Start NV Memory Read End Register E1h : Set PGM_ADR[7:0] address index for NV Memory Read Entry the Page 1 98h Register Address 1st parameter Protect Key 2nd parameter Device code 1 3rd parameter Device code 2 4th parameter Device code 3 5th parameter Page_select 06h 04h 01hFFhFFh NV Memory Read protection key Register E3h : 11h Register E4h : 66h Register E5h : 88h Note 1: In SPI operation mode, set register FEh “ext_spi_read_en”=1 to enable the read function of extend command and “ext_spi_read_en”=0 to return to the write mode NV Memory Data Read Register EAh : otp_read_one_byte_1 [7:0] (Note 1) Figure 105 NV Memory Read Flow

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 290 of 328 11. Gamma Correction Positive Gamma Control (Page1_A0h~AFh) VGAMMAP0 70R 64 6-bit DAC 6-bit DAC 5-bit DAC 5-bit DAC 126R 126R 31R 31R 12R 12R 5-bit DAC 5-bit DAC 4-bit DAC 4-bit DAC 5-bit DAC 15R 15R 15R 49R 15R 5-bit DAC VGAMMAP8 VGAMMAP16 VGAMMAP24 VGAMMAP52 VGAMMAP80 VGAMMAP108 VGAMMAP147 VGAMMAP175 VGAMMAP203 VGAMMAP231 VGAMMAP239 VGAMMAP[17:23] VGAMMAP[25:51] VGAMMAP[53:79] VGAMMAP[81:107] VGAMMAP[109:146] VGAMMAP[148:174] VGAMMAP[176:202] VGAMMAP[204:230] VGAMMAP[232:238] VGAMMAP[240:246] VGAMMAP[1:3] 15R 15R VGAMMAP464 6-bit DAC Nonlinear Res. VGAMMA[5:7] 49R 4-bit DAC 4-bit DAC VGAMMAP247 6-bit DAC VGAMMAP255 VGAMMAP[248:250] VGAMMAP251 64 6-bit DAC VGAMMAP[252:254] 6-bit DAC VGAMMAP[9:15] 51R 75R 51R VREG1OUT AGND 2R x 28 2R x 28 2R x 39 2R x 28 2R x 28 REG[0] REG[4] REG[8] REG[247] REG[251] REG[255] REG[203 REG[52] Nonlinear Res. Nonlinear Res. 6R x 8 Nonlinear Res. x28 Nonlinear Res. x28 Nonlinear Res. x28 Nonlinear Res. 6R x 8 Nonlinear Res. x28 Figure 106 Positive Gamma Control (Page1_A0h~AFh)

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 291 of 328 Negative Gamma Control (Page1_C0h~CFh) 70R 64 6-bit DAC 6-bit DAC 5-bit DAC 5-bit DAC 126R 126R 31R 31R 12R 12R 5-bit DAC 5-bit DAC 4-bit DAC 4-bit DAC 5-bit DAC 15R 15R 15R 49R 15R 5-bit DAC VGAMMAN8 VGAMMAN16 VGAMMAN24 VGAMMAN52 VGAMMAN80 VGAMMAN108 VGAMMAN147 VGAMMAN175 VGAMMAN203 VGAMMAN231 VGAMMAN239 VGAMMAN[17:23] VGAMMAN[25:51] VGAMMAN[53:79] VGAMMAN[81:107] VGAMMAN[109:146] VGAMMAN[148:174] VGAMMAN[176:202] VGAMMAN[204:230] VGAMMAN[232:238] VGAMMAN[240:246] VGAMMAN[1:3] 15R 15R VGAMMAN4 64 6-bit DAC VGAMMN[5:7] 49R 4-bit DAC 4-bit DAC VGAMMAN247 6-bit DAC VGAMMAN[248:250] VGAMMAN251 64 6-bit DAC VGAMMAN[252:254] 6-bit DAC VGAMMAN[9:15] 51R 75R 51R VREG2OUT AGND 3R x 28 3R x 28 3R x 39 3R x 28 3R x 28 REG[0] REG[4] REG[8] REG[16] REG[32] REG[52] REG[203] REG[80] REG[108] REG[147] REG[175] REG[223] REG[239] REG[247] REG[251] REG[255] VGAMMAN0 VGAMMAN255 Nonlinear Res. x28 Nonlinear Res. x28 Nonlinear Res. 6R x 8 Nonlinear Res. x28 Nonlinear Res. Nonlinear Res. Nonlinear Res. 6R x 8 Nonlinear Res. x28 Figure 107 Negative Gamma Control (Page1_C0h~CFh)

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 292 of 328 Positive polarity Resister stream Gamma 256 grayscale voltage calculation formula VGAMMAP0 0R AGND+ΔVDHP(322R-2R*VP0[5:0])/322R , ΔVDHP=(VREG1OUT-AGND) VGAMMAP1 21R VGAMMAP4+(VGAMMP0-VGAMMAP4)*(57R)/(78R) VGAMMAP2 21R VGAMMAP4+(VGAMMP0-VGAMMAP4)*(36R)/(78R) VGAMMAP3 18R VGAMMAP4+(VGAMMP0-VGAMMAP4)*(18R)/(78R) VGAMMAP4 18R AGND+ΔVDHP(322R-2R*VP4[5:0])/322R , ΔVDHP=(VREG1OUT-AGND) VGAMMAP5 30R VGAMMAP8+((VGAMMAP4-VGAMMAP8)*(90R/120R) VGAMMAP6 30R VGAMMAP8+((VGAMMAP4-VGAMMAP8)*(60R/120R) VGAMMAP7 30R VGAMMAP8+((VGAMMAP4-VGAMMAP8)*(30R/120R) VGAMMAP8 30R AGND+ΔVDHP(322R-2R*VP8[5:0])/322R , ΔVDHP=(VREG1OUT-AGND) VGAMMAP9 24R VGAMMAP16+((VGAMMAP8-VGAMMAP16)*(136R/160R) VGAMMAP10 22R VGAMMAP16+((VGAMMAP8-VGAMMAP16)*(114R/160R) VGAMMAP11 20R VGAMMAP16+((VGAMMAP8-VGAMMAP16)*(94R/160R) VGAMMAP12 20R VGAMMAP16+((VGAMMAP8-VGAMMAP16)*(74R/160R) VGAMMAP13 20R VGAMMAP16+((VGAMMAP8-VGAMMAP16)*(54R/160R) VGAMMAP14 18R VGAMMAP16+((VGAMMAP8-VGAMMAP16)*(36R/160R) VGAMMAP15 18R VGAMMAP16+((VGAMMAP8-VGAMMAP16)*(18R/160R) VGAMMAP16 18R VGAMMAP52+(VGAMMAP8-VGAMMAP52)*((50R-1R*VP16[4:0])/51R) VGAMMAP17 12R VGAMMAP24+((VGAMMAP16-VGAMMAP24)*(84R/96R) VGAMMAP18 12R VGAMMAP24+((VGAMMAP16-VGAMMAP24)*(72R/96R) VGAMMAP19 12R VGAMMAP24+((VGAMMAP16-VGAMMAP24)*(60R/96R) VGAMMAP20 12R VGAMMAP24+((VGAMMAP16-VGAMMAP24)*(48R/96R) VGAMMAP21 12R VGAMMAP24+((VGAMMAP16-VGAMMAP24)*(36R/96R) VGAMMAP22 12R VGAMMAP24+((VGAMMAP16-VGAMMAP24)*(24R/96R) VGAMMAP23 12R VGAMMAP24+((VGAMMAP16-VGAMMAP24)*(12R/96R) VGAMMAP24 12R VGAMMAP52+(VGAMMAP8-VGAMMAP52)*((32R-1R*VP24[4:0])/51R) VGAMMAP25 12R VGAMMAP52+((VGAMMAP24-VGAMMAP52)*(268R/280R) VGAMMAP26 12R VGAMMAP52+((VGAMMAP24-VGAMMAP52)*(256R/280R) VGAMMAP27 12R VGAMMAP52+((VGAMMAP24-VGAMMAP52)*(244R/280R) VGAMMAP28 12R VGAMMAP52+((VGAMMAP24-VGAMMAP52)*(232R/280R) VGAMMAP29 12R VGAMMAP52+((VGAMMAP24-VGAMMAP52)*(220R/280R) VGAMMAP30 12R VGAMMAP52+((VGAMMAP24-VGAMMAP52)*(208R/280R) VGAMMAP31 12R VGAMMAP52+((VGAMMAP24-VGAMMAP52)*(196R/280R) VGAMMAP31 12R VGAMMAP52+((VGAMMAP24-VGAMMAP52)*(184R/280R) VGAMMAP33 10R VGAMMAP52+((VGAMMAP24-VGAMMAP52)*(174R/280R) VGAMMAP34 10R VGAMMAP52+((VGAMMAP24-VGAMMAP52)*(164R/280R) VGAMMAP35 10R VGAMMAP52+((VGAMMAP24-VGAMMAP52)*(154R/280R)

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 293 of 328 VGAMMAP36 10R VGAMMAP52+((VGAMMAP24-VGAMMAP52)*(144R/280R) VGAMMAP31 12R VGAMMAP52+((VGAMMAP24-VGAMMAP52)*(134R/280R) VGAMMAP38 10R VGAMMAP52+((VGAMMAP24-VGAMMAP52)*(124R/280R) VGAMMAP39 10R VGAMMAP52+((VGAMMAP24-VGAMMAP52)*(114R/280R) VGAMMAP40 10R VGAMMAP52+((VGAMMAP24-VGAMMAP52)*(104R/280R) VGAMMAP41 10R VGAMMAP52+((VGAMMAP24-VGAMMAP52)*(94R/280R) VGAMMAP42 10R VGAMMAP52+((VGAMMAP24-VGAMMAP52)*(84R/280R) VGAMMAP43 10R VGAMMAP52+((VGAMMAP24-VGAMMAP52)*(74R/280R) VGAMMAP44 10R VGAMMAP52+((VGAMMAP24-VGAMMAP52)*(64R/280R) VGAMMAP45 8R VGAMMAP52+((VGAMMAP24-VGAMMAP52)*(56R/280R) VGAMMAP46 8R VGAMMAP52+((VGAMMAP24-VGAMMAP52)*(48R/280R) VGAMMAP47 8R VGAMMAP52+((VGAMMAP24-VGAMMAP52)*(40R/280R) VGAMMAP48 8R VGAMMAP52+((VGAMMAP24-VGAMMAP52)*(32R/280R) VGAMMAP49 8R VGAMMAP52+((VGAMMAP24-VGAMMAP52)*(24R/280R) VGAMMAP50 8R VGAMMAP52+((VGAMMAP24-VGAMMAP52)*(16R/280R) VGAMMAP51 8R VGAMMAP52+((VGAMMAP24-VGAMMAP52)*(8R/280R) VGAMMAP52 8R VGAMMAP247+(VGAMMAP8-VGAMMAP247)*((77R-0R)/90R)) , VP52[4:0] =0(Dec) VGAMMAP247+(VGAMMAP8-VGAMMAP247)*((77R-2R)/90R)) , VP52[4:0] =1(Dec) VGAMMAP247+(VGAMMAP8-VGAMMAP247)*((77R-4R)/90R)) , VP52[4:0] =2(Dec) VGAMMAP247+(VGAMMAP8-VGAMMAP247)*((74R-1R*VP VGAMMAP53 4R VGAMMAP80+((VGAMMAP52-VGAMMAP80)*(81R/84R) VGAMMAP54 4R VGAMMAP80+((VGAMMAP52-VGAMMAP80)*(78R/84R) VGAMMAP55 4R VGAMMAP80+((VGAMMAP52-VGAMMAP80)*(75R/84R) VGAMMAP56 4R VGAMMAP80+((VGAMMAP52-VGAMMAP80)*(72R/84R) VGAMMAP57 4R VGAMMAP80+((VGAMMAP52-VGAMMAP80)*(69R/84R) VGAMMAP58 4R VGAMMAP80+((VGAMMAP52-VGAMMAP80)*(66R/84R) VGAMMAP59 4R VGAMMAP80+((VGAMMAP52-VGAMMAP80)*(63R/84R) VGAMMAP60 4R VGAMMAP80+((VGAMMAP52-VGAMMAP80)*(60R/84R) VGAMMAP61 4R VGAMMAP80+((VGAMMAP52-VGAMMAP80)*(57R/84R) VGAMMAP62 4R VGAMMAP80+((VGAMMAP52-VGAMMAP80)*(54R/84R) VGAMMAP63 4R VGAMMAP80+((VGAMMAP52-VGAMMAP80)*(51R/84R) VGAMMAP64 4R VGAMMAP80+((VGAMMAP52-VGAMMAP80)*(48R/84R) VGAMMAP65 4R VGAMMAP80+((VGAMMAP52-VGAMMAP80)*(45R/84R) VGAMMAP66 4R VGAMMAP80+((VGAMMAP52-VGAMMAP80)*(42R/84R) VGAMMAP67 4R VGAMMAP80+((VGAMMAP52-VGAMMAP80)*(39R/84R) VGAMMAP68 4R VGAMMAP80+((VGAMMAP52-VGAMMAP80)*(36R/84R) VGAMMAP69 4R VGAMMAP80+((VGAMMAP52-VGAMMAP80)*(33R/84R)

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 294 of 328 VGAMMAP70 4R VGAMMAP80+((VGAMMAP52-VGAMMAP80)*(30R/84R) VGAMMAP71 4R VGAMMAP80+((VGAMMAP52-VGAMMAP80)*(27R/84R) VGAMMAP72 4R VGAMMAP80+((VGAMMAP52-VGAMMAP80)*(24R/84R) VGAMMAP73 4R VGAMMAP80+((VGAMMAP52-VGAMMAP80)*(21R/84R) VGAMMAP74 4R VGAMMAP80+((VGAMMAP52-VGAMMAP80)*(18R/84R) VGAMMAP75 4R VGAMMAP80+((VGAMMAP52-VGAMMAP80)*(15R/84R) VGAMMAP76 4R VGAMMAP80+((VGAMMAP52-VGAMMAP80)*(12R/84R) VGAMMAP77 4R VGAMMAP80+((VGAMMAP52-VGAMMAP80)*(9R/84R) VGAMMAP78 4R VGAMMAP80+((VGAMMAP52-VGAMMAP80)*(6R/84R) VGAMMAP79 4R VGAMMAP80+((VGAMMAP52-VGAMMAP80)*(3R/84R) VGAMMAP80 4R VGAMMAP203+(VGAMMAP52-VGAMMAP203)*((68R-0R)/75R) , VP80[3:0] =0(Dec) VGAMMAP203+(VGAMMAP52-VGAMMAP203)*((68R-2R)/75R) , VP80[3:0] =1(Dec) VGAMMAP203+(VGAMMAP52-VGAMMAP203)*((68R-4R)/75R) , VP80[3:0] =2(Dec) VGAMMAP203+(VGAMMAP52-VGAMMAP203)*((65R-1R*VP80[ VGAMMAP81 4R VGAMMAP108+((VGAMMAP80-VGAMMAP108)*(81R+/84R) VGAMMAP82 4R VGAMMAP108+((VGAMMAP80-VGAMMAP108)*(78R/84R) VGAMMAP83 4R VGAMMAP108+((VGAMMAP80-VGAMMAP108)*(75R/84R) VGAMMAP84 4R VGAMMAP108+((VGAMMAP80-VGAMMAP108)*(72R/84R) VGAMMAP85 4R VGAMMAP108+((VGAMMAP80-VGAMMAP108)*(69R/84R) VGAMMAP86 4R VGAMMAP108+((VGAMMAP80-VGAMMAP108)*(66R/84R) VGAMMAP87 4R VGAMMAP108+((VGAMMAP80-VGAMMAP108)*(63R/84R) VGAMMAP88 4R VGAMMAP108+((VGAMMAP80-VGAMMAP108)*(60R/84R) VGAMMAP89 4R VGAMMAP108+((VGAMMAP80-VGAMMAP108)*(57R/84R) VGAMMAP90 4R VGAMMAP108+((VGAMMAP80-VGAMMAP108)*(54R/84R) VGAMMAP91 4R VGAMMAP108+((VGAMMAP80-VGAMMAP108)*(51R/84R) VGAMMAP92 4R VGAMMAP108+((VGAMMAP80-VGAMMAP108)*(48R/84R) VGAMMAP93 4R VGAMMAP108+((VGAMMAP80-VGAMMAP108)*(45R/84R) VGAMMAP94 4R VGAMMAP108+((VGAMMAP80-VGAMMAP108)*(42R/84R) VGAMMAP95 4R VGAMMAP108+((VGAMMAP80-VGAMMAP108)*(39R/84R) VGAMMAP96 4R VGAMMAP108+((VGAMMAP80-VGAMMAP108)*(36R/84R) VGAMMAP97 4R VGAMMAP108+((VGAMMAP80-VGAMMAP108)*(33R/84R) VGAMMAP98 4R VGAMMAP108+((VGAMMAP80-VGAMMAP108)*(30R/84R) VGAMMAP99 4R VGAMMAP108+((VGAMMAP80-VGAMMAP108)*(27R/84R) VGAMMAP100 4R VGAMMAP108+((VGAMMAP80-VGAMMAP108)*(24R/84R) VGAMMAP101 4R VGAMMAP108+((VGAMMAP80-VGAMMAP108)*(21R/84R) VGAMMAP102 4R VGAMMAP108+((VGAMMAP80-VGAMMAP108)*(18R/84R) VGAMMAP103 4R VGAMMAP108+((VGAMMAP80-VGAMMAP108)*(15R/84R)

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 295 of 328 VGAMMAP104 4R VGAMMAP108+((VGAMMAP80-VGAMMAP108)*(12R/84R) VGAMMAP105 4R VGAMMAP108+((VGAMMAP80-VGAMMAP108)*(9R/84R) VGAMMAP106 4R VGAMMAP108+((VGAMMAP80-VGAMMAP108)*(6R/84R) VGAMMAP107 4R VGAMMAP108+((VGAMMAP80-VGAMMAP108)*(3R/84R) VGAMMAP108 4R VGAMMAP203+(VGAMMAP52-VGAMMAP203)*((52R-0R/75R) , VP108[3:0] =0(Dec) VGAMMAP203+(VGAMMAP52-VGAMMAP203)*((52R-2R/75R) , VP108[3:0] =1(Dec) VGAMMAP203+(VGAMMAP52-VGAMMAP203)*((52R-4R/75R) , VP108[3:0] =2(Dec) VGAMMAP203+(VGAMMAP52-VGAMMAP203)*((49R-1R*VP108 VGAMMAP109 4R VGAMMAP147+((VGAMMAP108-VGAMMAP147)*(114R/117R) VGAMMAP110 4R VGAMMAP147+((VGAMMAP108-VGAMMAP147)*(111R/117R) VGAMMAP111 4R VGAMMAP147+((VGAMMAP108-VGAMMAP147)*(108R/117R) VGAMMAP112 4R VGAMMAP147+((VGAMMAP108-VGAMMAP147)*(105R/117R) VGAMMAP113 4R VGAMMAP147+((VGAMMAP108-VGAMMAP147)*(102R/117R) VGAMMAP114 4R VGAMMAP147+((VGAMMAP108-VGAMMAP147)*(99R/117R) VGAMMAP115 4R VGAMMAP147+((VGAMMAP108-VGAMMAP147)*(96R/117R) VGAMMAP116 4R VGAMMAP147+((VGAMMAP108-VGAMMAP147)*(93R/117R) VGAMMAP117 4R VGAMMAP147+((VGAMMAP108-VGAMMAP147)*(90R/117R) VGAMMAP118 4R VGAMMAP147+((VGAMMAP108-VGAMMAP147)*(87R/117R) VGAMMAP119 4R VGAMMAP147+((VGAMMAP108-VGAMMAP147)*(84R/117R) VGAMMAP120 4R VGAMMAP147+((VGAMMAP108-VGAMMAP147)*(81R/117R) VGAMMAP121 4R VGAMMAP147+((VGAMMAP108-VGAMMAP147)*(78R/117R) VGAMMAP122 4R VGAMMAP147+((VGAMMAP108-VGAMMAP147)*(75R/117R) VGAMMAP123 4R VGAMMAP147+((VGAMMAP108-VGAMMAP147)*(72R/117R) VGAMMAP124 4R VGAMMAP147+((VGAMMAP108-VGAMMAP147)*(69R/117R) VGAMMAP125 4R VGAMMAP147+((VGAMMAP108-VGAMMAP147)*(66R/117R) VGAMMAP126 4R VGAMMAP147+((VGAMMAP108-VGAMMAP147)*(63R/117R) VGAMMAP127 4R VGAMMAP147+((VGAMMAP108-VGAMMAP147)*(60R/117R) VGAMMAP128 4R VGAMMAP147+((VGAMMAP108-VGAMMAP147)*(57R/117R) VGAMMAP129 4R VGAMMAP147+((VGAMMAP108-VGAMMAP147)*(54R/117R) VGAMMAP130 4R VGAMMAP147+((VGAMMAP108-VGAMMAP147)*(51R/117R) VGAMMAP131 4R VGAMMAP147+((VGAMMAP108-VGAMMAP147)*(48R/117R) VGAMMAP132 4R VGAMMAP147+((VGAMMAP108-VGAMMAP147)*(45R/117R) VGAMMAP133 4R VGAMMAP147+((VGAMMAP108-VGAMMAP147)*(42R/117R) VGAMMAP134 4R VGAMMAP147+((VGAMMAP108-VGAMMAP147)*(39R/117R) VGAMMAP135 4R VGAMMAP147+((VGAMMAP108-VGAMMAP147)*(36R/117R) VGAMMAP136 4R VGAMMAP147+((VGAMMAP108-VGAMMAP147)*(33R/117R) VGAMMAP137 4R VGAMMAP147+((VGAMMAP108-VGAMMAP147)*(30R/117R)

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 296 of 328 VGAMMAP138 4R VGAMMAP147+((VGAMMAP108-VGAMMAP147)*(27R/117R) VGAMMAP139 4R VGAMMAP147+((VGAMMAP108-VGAMMAP147)*(24R/117R) VGAMMAP140 4R VGAMMAP147+((VGAMMAP108-VGAMMAP147)*(21R/117R) VGAMMAP141 4R VGAMMAP147+((VGAMMAP108-VGAMMAP147)*(18R/117R) VGAMMAP142 4R VGAMMAP147+((VGAMMAP108-VGAMMAP147)*(15R/117R) VGAMMAP143 4R VGAMMAP147+((VGAMMAP108-VGAMMAP147)*(12R/117R) VGAMMAP144 4R VGAMMAP147+((VGAMMAP108-VGAMMAP147)*(9R/117R) VGAMMAP145 4R VGAMMAP147+((VGAMMAP108-VGAMMAP147)*(6R/117R) VGAMMAP146 4R VGAMMAP147+((VGAMMAP108-VGAMMAP147)*(3R/117R) VGAMMAP147 4R VGAMMAP203+(VGAMMAP52-VGAMMAP203)*((17R+1R*VP147[3:0])/75R) , else VGAMMAP203+(VGAMMAP52-VGAMMAP203)*((17R+31R/75R) , VP147[3:0] =13(Dec) VGAMMAP203+(VGAMMAP52-VGAMMAP203)*((17R+33R/75R) , VP147[3:0] =14(Dec) VGAMMAP203+(VGAMMAP52-VGAMMAP203)*((17R+35R/75 VGAMMAP148 4R VGAMMAP175+((VGAMMAP147-VGAMMAP175)*(81R/84R) VGAMMAP149 4R VGAMMAP175+((VGAMMAP147-VGAMMAP175)*(78R/84R) VGAMMAP150 4R VGAMMAP175+((VGAMMAP147-VGAMMAP175)*(75R/84R) VGAMMAP151 4R VGAMMAP175+((VGAMMAP147-VGAMMAP175)*(72R/84R) VGAMMAP152 4R VGAMMAP175+((VGAMMAP147-VGAMMAP175)*(69R/84R) VGAMMAP153 4R VGAMMAP175+((VGAMMAP147-VGAMMAP175)*(66R/84R) VGAMMAP154 4R VGAMMAP175+((VGAMMAP147-VGAMMAP175)*(63R/84R) VGAMMAP155 4R VGAMMAP175+((VGAMMAP147-VGAMMAP175)*(60R/84R) VGAMMAP156 4R VGAMMAP175+((VGAMMAP147-VGAMMAP175)*(57R/84R) VGAMMAP157 4R VGAMMAP175+((VGAMMAP147-VGAMMAP175)*(54R/84R) VGAMMAP158 4R VGAMMAP175+((VGAMMAP147-VGAMMAP175)*(51R/84R) VGAMMAP159 4R VGAMMAP175+((VGAMMAP147-VGAMMAP175)*(48R/84R) VGAMMAP160 4R VGAMMAP175+((VGAMMAP147-VGAMMAP175)*(45R/84R) VGAMMAP161 4R VGAMMAP175+((VGAMMAP147-VGAMMAP175)*(42R/84R) VGAMMAP162 4R VGAMMAP175+((VGAMMAP147-VGAMMAP175)*(39R/84R) VGAMMAP163 4R VGAMMAP175+((VGAMMAP147-VGAMMAP175)*(36R/84R) VGAMMAP164 4R VGAMMAP175+((VGAMMAP147-VGAMMAP175)*(33R/84R) VGAMMAP165 4R VGAMMAP175+((VGAMMAP147-VGAMMAP175)*(30R/84R) VGAMMAP166 4R VGAMMAP175+((VGAMMAP147-VGAMMAP175)*(27R/84R) VGAMMAP167 4R VGAMMAP175+((VGAMMAP147-VGAMMAP175)*(24R/84R) VGAMMAP168 4R VGAMMAP175+((VGAMMAP147-VGAMMAP175)*(21R/84R) VGAMMAP169 4R VGAMMAP175+((VGAMMAP147-VGAMMAP175)*(18R/84R) VGAMMAP170 4R VGAMMAP175+((VGAMMAP147-VGAMMAP175)*(15R/84R) VGAMMAP171 4R VGAMMAP175+((VGAMMAP147-VGAMMAP175)*(12R/84R)

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 297 of 328 VGAMMAP172 4R VGAMMAP175+((VGAMMAP147-VGAMMAP175)*(9R/84R) VGAMMAP173 4R VGAMMAP175+((VGAMMAP147-VGAMMAP175)*(6R/84R) VGAMMAP174 4R VGAMMAP175+((VGAMMAP147-VGAMMAP175)*(3R/84R) VGAMMAP175 4R VGAMMAP203+(VGAMMAP52-VGAMMAP203)*((1R+1R*VP175[3:0])/75R) , else VGAMMAP203+(VGAMMAP52-VGAMMAP203)*((1R+15R/75R) , VP175[3:0] =13(Dec) VGAMMAP203+(VGAMMAP52-VGAMMAP203)*((1R+17R/75R) , VP175[3:0] =14(Dec) VGAMMAP203+(VGAMMAP52-VGAMMAP203)*((1R+19R/75R) , VGAMMAP176 4R VGAMMAP203+((VGAMMAP175-VGAMMAP203)*(81R/84R) VGAMMAP177 4R VGAMMAP203+((VGAMMAP175-VGAMMAP203)*(78R/84R) VGAMMAP178 4R VGAMMAP203+((VGAMMAP175-VGAMMAP203)*(75R/84R) VGAMMAP179 4R VGAMMAP203+((VGAMMAP175-VGAMMAP203)*(72R/84R) VGAMMAP180 4R VGAMMAP203+((VGAMMAP175-VGAMMAP203)*(69R/84R) VGAMMAP181 4R VGAMMAP203+((VGAMMAP175-VGAMMAP203)*(66R/84R) VGAMMAP182 4R VGAMMAP203+((VGAMMAP175-VGAMMAP203)*(63R/84R) VGAMMAP183 4R VGAMMAP203+((VGAMMAP175-VGAMMAP203)*(60R/84R) VGAMMAP184 4R VGAMMAP203+((VGAMMAP175-VGAMMAP203)*(57R/84R) VGAMMAP185 4R VGAMMAP203+((VGAMMAP175-VGAMMAP203)*(54R/84R) VGAMMAP186 4R VGAMMAP203+((VGAMMAP175-VGAMMAP203)*(51R/84R) VGAMMAP187 4R VGAMMAP203+((VGAMMAP175-VGAMMAP203)*(48R/84R) VGAMMAP188 4R VGAMMAP203+((VGAMMAP175-VGAMMAP203)*(45R/84R) VGAMMAP189 4R VGAMMAP203+((VGAMMAP175-VGAMMAP203)*(42R/84R) VGAMMAP190 4R VGAMMAP203+((VGAMMAP175-VGAMMAP203)*(39R/84R) VGAMMAP191 4R VGAMMAP203+((VGAMMAP175-VGAMMAP203)*(36R/84R) VGAMMAP192 4R VGAMMAP203+((VGAMMAP175-VGAMMAP203)*(33R/84R) VGAMMAP193 4R VGAMMAP203+((VGAMMAP175-VGAMMAP203)*(30R/84R) VGAMMAP194 4R VGAMMAP203+((VGAMMAP175-VGAMMAP203)*(27R/84R) VGAMMAP195 4R VGAMMAP203+((VGAMMAP175-VGAMMAP203)*(24R/84R) VGAMMAP196 4R VGAMMAP203+((VGAMMAP175-VGAMMAP203)*(21R/84R) VGAMMAP197 4R VGAMMAP203+((VGAMMAP175-VGAMMAP203)*(18R/84R) VGAMMAP198 4R VGAMMAP203+((VGAMMAP175-VGAMMAP203)*(15R/84R) VGAMMAP199 4R VGAMMAP203+((VGAMMAP175-VGAMMAP203)*(12R/84R) VGAMMAP200 4R VGAMMAP203+((VGAMMAP175-VGAMMAP203)*(9R/84R) VGAMMAP201 4R VGAMMAP203+((VGAMMAP175-VGAMMAP203)*(6R/84R) VGAMMAP202 4R VGAMMAP203+((VGAMMAP175-VGAMMAP203)*(3R/84R) VGAMMAP203 4R VGAMMAP247+(VGAMMAP8-VGAMMAP247)*((8R+1R*VP203[4:0])/90R)) , else VGAMMAP247+(VGAMMAP8-VGAMMAP247)*((8R+38R/90R)) , VP203[4:0] =29(Dec) VGAMMAP247+(VGAMMAP8-VGAMMAP247)*((8R+40R/90R)) , VP203[4:0] =30(Dec)

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 298 of 328 VGAMMAP247+(VGAMMAP8-VGAMMAP247)*((8R+42R/90R)) VGAMMAP204 4R VGAMMAP231+((VGAMMAP203-VGAMMAP231)*(136R/140R) VGAMMAP205 4R VGAMMAP231+((VGAMMAP203-VGAMMAP231)*(132R/140R) VGAMMAP206 4R VGAMMAP231+((VGAMMAP203-VGAMMAP231)*(128R/140R) VGAMMAP207 4R VGAMMAP231+((VGAMMAP203-VGAMMAP231)*(124R/140R) VGAMMAP208 4R VGAMMAP231+((VGAMMAP203-VGAMMAP231)*(120R/140R) VGAMMAP209 4R VGAMMAP231+((VGAMMAP203-VGAMMAP231)*(116R/140R) VGAMMAP210 4R VGAMMAP231+((VGAMMAP203-VGAMMAP231)*(112R/140R) VGAMMAP211 4R VGAMMAP231+((VGAMMAP203-VGAMMAP231)*(108R/140R) VGAMMAP212 5R VGAMMAP231+((VGAMMAP203-VGAMMAP231)*(103R/140R) VGAMMAP213 5R VGAMMAP231+((VGAMMAP203-VGAMMAP231)*(98R/140R) VGAMMAP214 5R VGAMMAP231+((VGAMMAP203-VGAMMAP231)*(93R/140R) VGAMMAP215 5R VGAMMAP231+((VGAMMAP203-VGAMMAP231)*(88R/140R) VGAMMAP216 5R VGAMMAP231+((VGAMMAP203-VGAMMAP231)*(83R/140R) VGAMMAP217 5R VGAMMAP231+((VGAMMAP203-VGAMMAP231)*(78R/140R) VGAMMAP218 5R VGAMMAP231+((VGAMMAP203-VGAMMAP231)*(73R/140R) VGAMMAP219 5R VGAMMAP231+((VGAMMAP203-VGAMMAP231)*(68R/140R) VGAMMAP220 5R VGAMMAP231+((VGAMMAP203-VGAMMAP231)*(63R/140R) VGAMMAP221 5R VGAMMAP231+((VGAMMAP203-VGAMMAP231)*(58R/140R) VGAMMAP222 5R VGAMMAP231+((VGAMMAP203-VGAMMAP231)*(53R/140R) VGAMMAP223 5R VGAMMAP231+((VGAMMAP203-VGAMMAP231)*(48R/140R) VGAMMAP224 6R VGAMMAP231+((VGAMMAP203-VGAMMAP231)*(42R/140R) VGAMMAP225 6R VGAMMAP231+((VGAMMAP203-VGAMMAP231)*(36R/140R) VGAMMAP226 6R VGAMMAP231+((VGAMMAP203-VGAMMAP231)*(30R/140R) VGAMMAP227 6R VGAMMAP231+((VGAMMAP203-VGAMMAP231)*(24R/140R) VGAMMAP228 6R VGAMMAP231+((VGAMMAP203-VGAMMAP231)*(18R/140R) VGAMMAP229 6R VGAMMAP231+((VGAMMAP203-VGAMMAP231)*(12R/140R) VGAMMAP230 6R VGAMMAP231+((VGAMMAP203-VGAMMAP231)*(6R/140R) VGAMMAP231 6R VGAMMAP247+(VGAMMAP203-VGAMMAP247)*((1R+1R*VP231[4:0])/51R) VGAMMAP232 6R VGAMMAP239+((VGAMMAP231-VGAMMAP239)*(42R/48R) VGAMMAP233 6R VGAMMAP239+((VGAMMAP231-VGAMMAP239)*(36R/48R) VGAMMAP234 6R VGAMMAP239+((VGAMMAP231-VGAMMAP239)*(30R/48R) VGAMMAP235 6R VGAMMAP239+((VGAMMAP231-VGAMMAP239)*(24R/48R) VGAMMAP236 6R VGAMMAP239+((VGAMMAP231-VGAMMAP239)*(18R/48R) VGAMMAP237 6R VGAMMAP239+((VGAMMAP231-VGAMMAP239)*(12R/48R) VGAMMAP238 6R VGAMMAP239+((VGAMMAP231-VGAMMAP239)*(6R/48R) VGAMMAP239 15R VGAMMAP247+(VGAMMAP203-VGAMMAP247)*((1R+1R*VP239[4:0])/51R)

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 299 of 328 VGAMMAP240 6R VGAMMAP247+((VGAMMAP239-VGAMMAP247)*(74R/80R) VGAMMAP241 7R VGAMMAP247+((VGAMMAP239-VGAMMAP247)*(67R/80R) VGAMMAP242 9R VGAMMAP247+((VGAMMAP239-VGAMMAP247)*(58R/80R) VGAMMAP243 8R VGAMMAP247+((VGAMMAP239-VGAMMAP247)*(50R/80R) VGAMMAP244 11R VGAMMAP247+((VGAMMAP239-VGAMMAP247)*(39R/80R) VGAMMAP245 12R VGAMMAP247+((VGAMMAP239-VGAMMAP247)*(27R/80R) VGAMMAP246 12R VGAMMAP247+((VGAMMAP239-VGAMMAP247)*(15R/80R) VGAMMAP247 15R AGND+ΔVDHP(3R*VP247[5:0])/322R , ΔVDHP=(VREG1OUT-AGND) VGAMMAP248 12R VGAMMAP251+((VGAMMAP247-VGAMMAP251)*(68R/80R) VGAMMAP249 16R VGAMMAP251+((VGAMMAP247-VGAMMAP251)*(52R/80R) VGAMMAP250 24R VGAMMAP251+((VGAMMAP247-VGAMMAP251)*(28R/80R) VGAMMAP251 28R AGND+ΔVDHP(3R*VP251[5:0])/322R , ΔVDHP=(VREG1OUT-AGND) VGAMMAP252 25R VGAMMAP255+(VGAMMP251-VGAMMAP255)*(105R/130R) VGAMMAP253 45R VGAMMAP255+(VGAMMP251-VGAMMAP255)*(60R/130R) VGAMMAP254 20R VGAMMAP255+(VGAMMP251-VGAMMAP255)*(40R/130R) VGAMMAP255 10R AGND+ΔVDHP(3R*VP255[5:0])/322R , ΔVDHP=(VREG1OUT-AGND)

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 300 of 328 Negative polarity Resister stream Gamma 256 grayscale voltage calculation formula VGAMMAN0 0R AGND+ΔVDHN(322R-2R*VN0[5:0])/322R , ΔVDHN=(VREG2OUT-AGND) VGAMMAN1 21R VGAMMAN4+(VGAMMN0-VGAMMAN4)*(57R)/(78R) VGAMMAN2 21R VGAMMAN4+(VGAMMN0-VGAMMAN4)*(36R)/(78R) VGAMMAN3 18R VGAMMAN4+(VGAMMN0-VGAMMAN4)*(18R)/(78R) VGAMMAN4 18R AGND+ΔVDHN(322R-2R*VN4[5:0])/322R , ΔVDHN=(VREG2OUT-AGND) VGAMMAN5 30R VGAMMAN8+((VGAMMAN4-VGAMMAN8)*(90R/120R) VGAMMAN6 30R VGAMMAN8+((VGAMMAN4-VGAMMAN8)*(60R/120R) VGAMMAN7 30R VGAMMAN8+((VGAMMAN4-VGAMMAN8)*(30R/120R) VGAMMAN8 30R AGND+ΔVDHN(322R-2R*VN8[5:0])/322R , ΔVDHN=(VREG2OUT-AGND) VGAMMAN9 24R VGAMMAN16+((VGAMMAN8-VGAMMAN16)*(136R/160R) VGAMMAN10 22R VGAMMAN16+((VGAMMAN8-VGAMMAN16)*(114R/160R) VGAMMAN11 20R VGAMMAN16+((VGAMMAN8-VGAMMAN16)*(94R/160R) VGAMMAN12 20R VGAMMAN16+((VGAMMAN8-VGAMMAN16)*(74R/160R) VGAMMAN13 20R VGAMMAN16+((VGAMMAN8-VGAMMAN16)*(54R/160R) VGAMMAN14 18R VGAMMAN16+((VGAMMAN8-VGAMMAN16)*(36R/160R) VGAMMAN15 18R VGAMMAN16+((VGAMMAN8-VGAMMAN16)*(18R/160R) VGAMMAN16 18R VGAMMAN52+(VGAMMAN8-VGAMMAN52)*((50R-1R*VN16[4:0])/51R) VGAMMAN17 12R VGAMMAN24+((VGAMMAN16-VGAMMAN24)*(84R/96R) VGAMMAN18 12R VGAMMAN24+((VGAMMAN16-VGAMMAN24)*(72R/96R) VGAMMAN19 12R VGAMMAN24+((VGAMMAN16-VGAMMAN24)*(60R/96R) VGAMMAN20 12R VGAMMAN24+((VGAMMAN16-VGAMMAN24)*(48R/96R) VGAMMAN21 12R VGAMMAN24+((VGAMMAN16-VGAMMAN24)*(36R/96R) VGAMMAN22 12R VGAMMAN24+((VGAMMAN16-VGAMMAN24)*(24R/96R) VGAMMAN23 12R VGAMMAN24+((VGAMMAN16-VGAMMAN24)*(12R/96R) VGAMMAN24 12R VGAMMAN52+(VGAMMAN8-VGAMMAN52)*((32R-1R*VN24[4:0])/51R) VGAMMAN25 12R VGAMMAN52+((VGAMMAN24-VGAMMAN52)*(268R/280R) VGAMMAN26 12R VGAMMAN52+((VGAMMAN24-VGAMMAN52)*(256R/280R) VGAMMAN27 12R VGAMMAN52+((VGAMMAN24-VGAMMAN52)*(244R/280R) VGAMMAN28 12R VGAMMAN52+((VGAMMAN24-VGAMMAN52)*(232R/280R) VGAMMAN29 12R VGAMMAN52+((VGAMMAN24-VGAMMAN52)*(220R/280R) VGAMMAN30 12R VGAMMAN52+((VGAMMAN24-VGAMMAN52)*(208R/280R) VGAMMAN31 12R VGAMMAN52+((VGAMMAN24-VGAMMAN52)*(196R/280R) VGAMMAN31 12R VGAMMAN52+((VGAMMAN24-VGAMMAN52)*(184R/280R) VGAMMAN33 10R VGAMMAN52+((VGAMMAN24-VGAMMAN52)*(174R/280R) VGAMMAN34 10R VGAMMAN52+((VGAMMAN24-VGAMMAN52)*(164R/280R)

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 301 of 328 VGAMMAN35 10R VGAMMAN52+((VGAMMAN24-VGAMMAN52)*(154R/280R) VGAMMAN36 10R VGAMMAN52+((VGAMMAN24-VGAMMAN52)*(144R/280R) VGAMMAN31 12R VGAMMAN52+((VGAMMAN24-VGAMMAN52)*(134R/280R) VGAMMAN38 10R VGAMMAN52+((VGAMMAN24-VGAMMAN52)*(124R/280R) VGAMMAN39 10R VGAMMAN52+((VGAMMAN24-VGAMMAN52)*(114R/280R) VGAMMAN40 10R VGAMMAN52+((VGAMMAN24-VGAMMAN52)*(104R/280R) VGAMMAN41 10R VGAMMAN52+((VGAMMAN24-VGAMMAN52)*(94R/280R) VGAMMAN42 10R VGAMMAN52+((VGAMMAN24-VGAMMAN52)*(84R/280R) VGAMMAN43 10R VGAMMAN52+((VGAMMAN24-VGAMMAN52)*(74R/280R) VGAMMAN44 10R VGAMMAN52+((VGAMMAN24-VGAMMAN52)*(64R/280R) VGAMMAN45 8R VGAMMAN52+((VGAMMAN24-VGAMMAN52)*(56R/280R) VGAMMAN46 8R VGAMMAN52+((VGAMMAN24-VGAMMAN52)*(48R/280R) VGAMMAN47 8R VGAMMAN52+((VGAMMAN24-VGAMMAN52)*(40R/280R) VGAMMAN48 8R VGAMMAN52+((VGAMMAN24-VGAMMAN52)*(32R/280R) VGAMMAN49 8R VGAMMAN52+((VGAMMAN24-VGAMMAN52)*(24R/280R) VGAMMAN50 8R VGAMMAN52+((VGAMMAN24-VGAMMAN52)*(16R/280R) VGAMMAN51 8R VGAMMAN52+((VGAMMAN24-VGAMMAN52)*(8R/280R) VGAMMAN52 8R VGAMMAN247+(VGAMMAN8-VGAMMAN247)*((77R-0R)/90R)) , VN52[4:0] =0(Dec) VGAMMAN247+(VGAMMAN8-VGAMMAN247)*((77R-2R)/90R)) , VN52[4:0] =1(Dec) VGAMMAN247+(VGAMMAN8-VGAMMAN247)*((77R-4R)/90R)) , VN52[4:0] =2(Dec) VGAMMAN247+(VGAMMAN8-VGAMMAN247)*((74R-1R*VN VGAMMAN53 4R VGAMMAN80+((VGAMMAN52-VGAMMAN80)*(81R/84R) VGAMMAN54 4R VGAMMAN80+((VGAMMAN52-VGAMMAN80)*(78R/84R) VGAMMAN55 4R VGAMMAN80+((VGAMMAN52-VGAMMAN80)*(75R/84R) VGAMMAN56 4R VGAMMAN80+((VGAMMAN52-VGAMMAN80)*(72R/84R) VGAMMAN57 4R VGAMMAN80+((VGAMMAN52-VGAMMAN80)*(69R/84R) VGAMMAN58 4R VGAMMAN80+((VGAMMAN52-VGAMMAN80)*(66R/84R) VGAMMAN59 4R VGAMMAN80+((VGAMMAN52-VGAMMAN80)*(63R/84R) VGAMMAN60 4R VGAMMAN80+((VGAMMAN52-VGAMMAN80)*(60R/84R) VGAMMAN61 4R VGAMMAN80+((VGAMMAN52-VGAMMAN80)*(57R/84R) VGAMMAN62 4R VGAMMAN80+((VGAMMAN52-VGAMMAN80)*(54R/84R) VGAMMAN63 4R VGAMMAN80+((VGAMMAN52-VGAMMAN80)*(51R/84R) VGAMMAN64 4R VGAMMAN80+((VGAMMAN52-VGAMMAN80)*(48R/84R) VGAMMAN65 4R VGAMMAN80+((VGAMMAN52-VGAMMAN80)*(45R/84R) VGAMMAN66 4R VGAMMAN80+((VGAMMAN52-VGAMMAN80)*(42R/84R) VGAMMAN67 4R VGAMMAN80+((VGAMMAN52-VGAMMAN80)*(39R/84R) VGAMMAN68 4R VGAMMAN80+((VGAMMAN52-VGAMMAN80)*(36R/84R)

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 302 of 328 VGAMMAN69 4R VGAMMAN80+((VGAMMAN52-VGAMMAN80)*(33R/84R) VGAMMAN70 4R VGAMMAN80+((VGAMMAN52-VGAMMAN80)*(30R/84R) VGAMMAN71 4R VGAMMAN80+((VGAMMAN52-VGAMMAN80)*(27R/84R) VGAMMAN72 4R VGAMMAN80+((VGAMMAN52-VGAMMAN80)*(24R/84R) VGAMMAN73 4R VGAMMAN80+((VGAMMAN52-VGAMMAN80)*(21R/84R) VGAMMAN74 4R VGAMMAN80+((VGAMMAN52-VGAMMAN80)*(18R/84R) VGAMMAN75 4R VGAMMAN80+((VGAMMAN52-VGAMMAN80)*(15R/84R) VGAMMAN76 4R VGAMMAN80+((VGAMMAN52-VGAMMAN80)*(12R/84R) VGAMMAN77 4R VGAMMAN80+((VGAMMAN52-VGAMMAN80)*(9R/84R) VGAMMAN78 4R VGAMMAN80+((VGAMMAN52-VGAMMAN80)*(6R/84R) VGAMMAN79 4R VGAMMAN80+((VGAMMAN52-VGAMMAN80)*(3R/84R) VGAMMAN80 4R VGAMMAN203+(VGAMMAN52-VGAMMAN203)*((68R-0R)/75R) , VN80[3:0] =0(Dec) VGAMMAN203+(VGAMMAN52-VGAMMAN203)*((68R-2R)/75R) , VN80[3:0] =1(Dec) VGAMMAN203+(VGAMMAN52-VGAMMAN203)*((68R-4R)/75R) , VN80[3:0] =2(Dec) VGAMMAN203+(VGAMMAN52-VGAMMAN203)*((65R-1R*VN80[ VGAMMAN81 4R VGAMMAN108+((VGAMMAN80-VGAMMAN108)*(81R+/84R) VGAMMAN82 4R VGAMMAN108+((VGAMMAN80-VGAMMAN108)*(78R/84R) VGAMMAN83 4R VGAMMAN108+((VGAMMAN80-VGAMMAN108)*(75R/84R) VGAMMAN84 4R VGAMMAN108+((VGAMMAN80-VGAMMAN108)*(72R/84R) VGAMMAN85 4R VGAMMAN108+((VGAMMAN80-VGAMMAN108)*(69R/84R) VGAMMAN86 4R VGAMMAN108+((VGAMMAN80-VGAMMAN108)*(66R/84R) VGAMMAN87 4R VGAMMAN108+((VGAMMAN80-VGAMMAN108)*(63R/84R) VGAMMAN88 4R VGAMMAN108+((VGAMMAN80-VGAMMAN108)*(60R/84R) VGAMMAN89 4R VGAMMAN108+((VGAMMAN80-VGAMMAN108)*(57R/84R) VGAMMAN90 4R VGAMMAN108+((VGAMMAN80-VGAMMAN108)*(54R/84R) VGAMMAN91 4R VGAMMAN108+((VGAMMAN80-VGAMMAN108)*(51R/84R) VGAMMAN92 4R VGAMMAN108+((VGAMMAN80-VGAMMAN108)*(48R/84R) VGAMMAN93 4R VGAMMAN108+((VGAMMAN80-VGAMMAN108)*(45R/84R) VGAMMAN94 4R VGAMMAN108+((VGAMMAN80-VGAMMAN108)*(42R/84R) VGAMMAN95 4R VGAMMAN108+((VGAMMAN80-VGAMMAN108)*(39R/84R) VGAMMAN96 4R VGAMMAN108+((VGAMMAN80-VGAMMAN108)*(36R/84R) VGAMMAN97 4R VGAMMAN108+((VGAMMAN80-VGAMMAN108)*(33R/84R) VGAMMAN98 4R VGAMMAN108+((VGAMMAN80-VGAMMAN108)*(30R/84R) VGAMMAN99 4R VGAMMAN108+((VGAMMAN80-VGAMMAN108)*(27R/84R) VGAMMAN100 4R VGAMMAN108+((VGAMMAN80-VGAMMAN108)*(24R/84R) VGAMMAN101 4R VGAMMAN108+((VGAMMAN80-VGAMMAN108)*(21R/84R) VGAMMAN102 4R VGAMMAN108+((VGAMMAN80-VGAMMAN108)*(18R/84R)

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 303 of 328 VGAMMAN103 4R VGAMMAN108+((VGAMMAN80-VGAMMAN108)*(15R/84R) VGAMMAN104 4R VGAMMAN108+((VGAMMAN80-VGAMMAN108)*(12R/84R) VGAMMAN105 4R VGAMMAN108+((VGAMMAN80-VGAMMAN108)*(9R/84R) VGAMMAN106 4R VGAMMAN108+((VGAMMAN80-VGAMMAN108)*(6R/84R) VGAMMAN107 4R VGAMMAN108+((VGAMMAN80-VGAMMAN108)*(3R/84R) VGAMMAN108 4R VGAMMAN203+(VGAMMAN52-VGAMMAN203)*((52R-0R/75R) , VN108[3:0] =0(Dec) VGAMMAN203+(VGAMMAN52-VGAMMAN203)*((52R-2R/75R) , VN108[3:0] =1(Dec) VGAMMAN203+(VGAMMAN52-VGAMMAN203)*((52R-4R/75R) , VN108[3:0] =2(Dec) VGAMMAN203+(VGAMMAN52-VGAMMAN203)*((49R-1R*VN108 VGAMMAN109 4R VGAMMAN147+((VGAMMAN108-VGAMMAN147)*(114R/117R) VGAMMAN110 4R VGAMMAN147+((VGAMMAN108-VGAMMAN147)*(111R/117R) VGAMMAN111 4R VGAMMAN147+((VGAMMAN108-VGAMMAN147)*(108R/117R) VGAMMAN112 4R VGAMMAN147+((VGAMMAN108-VGAMMAN147)*(105R/117R) VGAMMAN113 4R VGAMMAN147+((VGAMMAN108-VGAMMAN147)*(102R/117R) VGAMMAN114 4R VGAMMAN147+((VGAMMAN108-VGAMMAN147)*(99R/117R) VGAMMAN115 4R VGAMMAN147+((VGAMMAN108-VGAMMAN147)*(96R/117R) VGAMMAN116 4R VGAMMAN147+((VGAMMAN108-VGAMMAN147)*(93R/117R) VGAMMAN117 4R VGAMMAN147+((VGAMMAN108-VGAMMAN147)*(90R/117R) VGAMMAN118 4R VGAMMAN147+((VGAMMAN108-VGAMMAN147)*(87R/117R) VGAMMAN119 4R VGAMMAN147+((VGAMMAN108-VGAMMAN147)*(84R/117R) VGAMMAN120 4R VGAMMAN147+((VGAMMAN108-VGAMMAN147)*(81R/117R) VGAMMAN121 4R VGAMMAN147+((VGAMMAN108-VGAMMAN147)*(78R/117R) VGAMMAN122 4R VGAMMAN147+((VGAMMAN108-VGAMMAN147)*(75R/117R) VGAMMAN123 4R VGAMMAN147+((VGAMMAN108-VGAMMAN147)*(72R/117R) VGAMMAN124 4R VGAMMAN147+((VGAMMAN108-VGAMMAN147)*(69R/117R) VGAMMAN125 4R VGAMMAN147+((VGAMMAN108-VGAMMAN147)*(66R/117R) VGAMMAN126 4R VGAMMAN147+((VGAMMAN108-VGAMMAN147)*(63R/117R) VGAMMAN127 4R VGAMMAN147+((VGAMMAN108-VGAMMAN147)*(60R/117R) VGAMMAN128 4R VGAMMAN147+((VGAMMAN108-VGAMMAN147)*(57R/117R) VGAMMAN129 4R VGAMMAN147+((VGAMMAN108-VGAMMAN147)*(54R/117R) VGAMMAN130 4R VGAMMAN147+((VGAMMAN108-VGAMMAN147)*(51R/117R) VGAMMAN131 4R VGAMMAN147+((VGAMMAN108-VGAMMAN147)*(48R/117R) VGAMMAN132 4R VGAMMAN147+((VGAMMAN108-VGAMMAN147)*(45R/117R) VGAMMAN133 4R VGAMMAN147+((VGAMMAN108-VGAMMAN147)*(42R/117R) VGAMMAN134 4R VGAMMAN147+((VGAMMAN108-VGAMMAN147)*(39R/117R) VGAMMAN135 4R VGAMMAN147+((VGAMMAN108-VGAMMAN147)*(36R/117R) VGAMMAN136 4R VGAMMAN147+((VGAMMAN108-VGAMMAN147)*(33R/117R)

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 304 of 328 VGAMMAN137 4R VGAMMAN147+((VGAMMAN108-VGAMMAN147)*(30R/117R) VGAMMAN138 4R VGAMMAN147+((VGAMMAN108-VGAMMAN147)*(27R/117R) VGAMMAN139 4R VGAMMAN147+((VGAMMAN108-VGAMMAN147)*(24R/117R) VGAMMAN140 4R VGAMMAN147+((VGAMMAN108-VGAMMAN147)*(21R/117R) VGAMMAN141 4R VGAMMAN147+((VGAMMAN108-VGAMMAN147)*(18R/117R) VGAMMAN142 4R VGAMMAN147+((VGAMMAN108-VGAMMAN147)*(15R/117R) VGAMMAN143 4R VGAMMAN147+((VGAMMAN108-VGAMMAN147)*(12R/117R) VGAMMAN144 4R VGAMMAN147+((VGAMMAN108-VGAMMAN147)*(9R/117R) VGAMMAN145 4R VGAMMAN147+((VGAMMAN108-VGAMMAN147)*(6R/117R) VGAMMAN146 4R VGAMMAN147+((VGAMMAN108-VGAMMAN147)*(3R/117R) VGAMMAN147 4R VGAMMAN203+(VGAMMAN52-VGAMMAN203)*((17R+1R*VN147[3:0])/75R) , else VGAMMAN203+(VGAMMAN52-VGAMMAN203)*((17R+31R/75R) , VN147[3:0] =13(Dec) VGAMMAN203+(VGAMMAN52-VGAMMAN203)*((17R+33R/75R) , VN147[3:0] =14(Dec) VGAMMAN203+(VGAMMAN52-VGAMMAN203)*((17R+35R/75 VGAMMAN148 4R VGAMMAN175+((VGAMMAN147-VGAMMAN175)*(81R/84R) VGAMMAN149 4R VGAMMAN175+((VGAMMAN147-VGAMMAN175)*(78R/84R) VGAMMAN150 4R VGAMMAN175+((VGAMMAN147-VGAMMAN175)*(75R/84R) VGAMMAN151 4R VGAMMAN175+((VGAMMAN147-VGAMMAN175)*(72R/84R) VGAMMAN152 4R VGAMMAN175+((VGAMMAN147-VGAMMAN175)*(69R/84R) VGAMMAN153 4R VGAMMAN175+((VGAMMAN147-VGAMMAN175)*(66R/84R) VGAMMAN154 4R VGAMMAN175+((VGAMMAN147-VGAMMAN175)*(63R/84R) VGAMMAN155 4R VGAMMAN175+((VGAMMAN147-VGAMMAN175)*(60R/84R) VGAMMAN156 4R VGAMMAN175+((VGAMMAN147-VGAMMAN175)*(57R/84R) VGAMMAN157 4R VGAMMAN175+((VGAMMAN147-VGAMMAN175)*(54R/84R) VGAMMAN158 4R VGAMMAN175+((VGAMMAN147-VGAMMAN175)*(51R/84R) VGAMMAN159 4R VGAMMAN175+((VGAMMAN147-VGAMMAN175)*(48R/84R) VGAMMAN160 4R VGAMMAN175+((VGAMMAN147-VGAMMAN175)*(45R/84R) VGAMMAN161 4R VGAMMAN175+((VGAMMAN147-VGAMMAN175)*(42R/84R) VGAMMAN162 4R VGAMMAN175+((VGAMMAN147-VGAMMAN175)*(39R/84R) VGAMMAN163 4R VGAMMAN175+((VGAMMAN147-VGAMMAN175)*(36R/84R) VGAMMAN164 4R VGAMMAN175+((VGAMMAN147-VGAMMAN175)*(33R/84R) VGAMMAN165 4R VGAMMAN175+((VGAMMAN147-VGAMMAN175)*(30R/84R) VGAMMAN166 4R VGAMMAN175+((VGAMMAN147-VGAMMAN175)*(27R/84R) VGAMMAN167 4R VGAMMAN175+((VGAMMAN147-VGAMMAN175)*(24R/84R) VGAMMAN168 4R VGAMMAN175+((VGAMMAN147-VGAMMAN175)*(21R/84R) VGAMMAN169 4R VGAMMAN175+((VGAMMAN147-VGAMMAN175)*(18R/84R) VGAMMAN170 4R VGAMMAN175+((VGAMMAN147-VGAMMAN175)*(15R/84R)

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 305 of 328 VGAMMAN171 4R VGAMMAN175+((VGAMMAN147-VGAMMAN175)*(12R/84R) VGAMMAN172 4R VGAMMAN175+((VGAMMAN147-VGAMMAN175)*(9R/84R) VGAMMAN173 4R VGAMMAN175+((VGAMMAN147-VGAMMAN175)*(6R/84R) VGAMMAN174 4R VGAMMAN175+((VGAMMAN147-VGAMMAN175)*(3R/84R) VGAMMAN175 4R VGAMMAN203+(VGAMMAN52-VGAMMAN203)*((1R+1R*VN175[3:0])/75R) , else VGAMMAN203+(VGAMMAN52-VGAMMAN203)*((1R+15R/75R) , VN175[3:0] =13(Dec) VGAMMAN203+(VGAMMAN52-VGAMMAN203)*((1R+17R/75R) , VN175[3:0] =14(Dec) VGAMMAN203+(VGAMMAN52-VGAMMAN203)*((1R+19R/75R) , VGAMMAN176 4R VGAMMAN203+((VGAMMAN175-VGAMMAN203)*(81R/84R) VGAMMAN177 4R VGAMMAN203+((VGAMMAN175-VGAMMAN203)*(78R/84R) VGAMMAN178 4R VGAMMAN203+((VGAMMAN175-VGAMMAN203)*(75R/84R) VGAMMAN179 4R VGAMMAN203+((VGAMMAN175-VGAMMAN203)*(72R/84R) VGAMMAN180 4R VGAMMAN203+((VGAMMAN175-VGAMMAN203)*(69R/84R) VGAMMAN181 4R VGAMMAN203+((VGAMMAN175-VGAMMAN203)*(66R/84R) VGAMMAN182 4R VGAMMAN203+((VGAMMAN175-VGAMMAN203)*(63R/84R) VGAMMAN183 4R VGAMMAN203+((VGAMMAN175-VGAMMAN203)*(60R/84R) VGAMMAN184 4R VGAMMAN203+((VGAMMAN175-VGAMMAN203)*(57R/84R) VGAMMAN185 4R VGAMMAN203+((VGAMMAN175-VGAMMAN203)*(54R/84R) VGAMMAN186 4R VGAMMAN203+((VGAMMAN175-VGAMMAN203)*(51R/84R) VGAMMAN187 4R VGAMMAN203+((VGAMMAN175-VGAMMAN203)*(48R/84R) VGAMMAN188 4R VGAMMAN203+((VGAMMAN175-VGAMMAN203)*(45R/84R) VGAMMAN189 4R VGAMMAN203+((VGAMMAN175-VGAMMAN203)*(42R/84R) VGAMMAN190 4R VGAMMAN203+((VGAMMAN175-VGAMMAN203)*(39R/84R) VGAMMAN191 4R VGAMMAN203+((VGAMMAN175-VGAMMAN203)*(36R/84R) VGAMMAN192 4R VGAMMAN203+((VGAMMAN175-VGAMMAN203)*(33R/84R) VGAMMAN193 4R VGAMMAN203+((VGAMMAN175-VGAMMAN203)*(30R/84R) VGAMMAN194 4R VGAMMAN203+((VGAMMAN175-VGAMMAN203)*(27R/84R) VGAMMAN195 4R VGAMMAN203+((VGAMMAN175-VGAMMAN203)*(24R/84R) VGAMMAN196 4R VGAMMAN203+((VGAMMAN175-VGAMMAN203)*(21R/84R) VGAMMAN197 4R VGAMMAN203+((VGAMMAN175-VGAMMAN203)*(18R/84R) VGAMMAN198 4R VGAMMAN203+((VGAMMAN175-VGAMMAN203)*(15R/84R) VGAMMAN199 4R VGAMMAN203+((VGAMMAN175-VGAMMAN203)*(12R/84R) VGAMMAN200 4R VGAMMAN203+((VGAMMAN175-VGAMMAN203)*(9R/84R) VGAMMAN201 4R VGAMMAN203+((VGAMMAN175-VGAMMAN203)*(6R/84R) VGAMMAN202 4R VGAMMAN203+((VGAMMAN175-VGAMMAN203)*(3R/84R) VGAMMAN203 4R VGAMMAN247+(VGAMMAN8-VGAMMAN247)*((8R+1R*VN203[4:0])/90R)) , else VGAMMAN247+(VGAMMAN8-VGAMMAN247)*((8R+38R/90R)) , VN203[4:0] =29(Dec)

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 306 of 328 VGAMMAN247+(VGAMMAN8-VGAMMAN247)*((8R+40R/90R)) , VN203[4:0] =30(Dec) VGAMMAN247+(VGAMMAN8-VGAMMAN247)*((8R+42R/90R)) VGAMMAN204 4R VGAMMAN231+((VGAMMAN203-VGAMMAN231)*(136R/140R) VGAMMAN205 4R VGAMMAN231+((VGAMMAN203-VGAMMAN231)*(132R/140R) VGAMMAN206 4R VGAMMAN231+((VGAMMAN203-VGAMMAN231)*(128R/140R) VGAMMAN207 4R VGAMMAN231+((VGAMMAN203-VGAMMAN231)*(124R/140R) VGAMMAN208 4R VGAMMAN231+((VGAMMAN203-VGAMMAN231)*(120R/140R) VGAMMAN209 4R VGAMMAN231+((VGAMMAN203-VGAMMAN231)*(116R/140R) VGAMMAN210 4R VGAMMAN231+((VGAMMAN203-VGAMMAN231)*(112R/140R) VGAMMAN211 4R VGAMMAN231+((VGAMMAN203-VGAMMAN231)*(108R/140R) VGAMMAN212 5R VGAMMAN231+((VGAMMAN203-VGAMMAN231)*(103R/140R) VGAMMAN213 5R VGAMMAN231+((VGAMMAN203-VGAMMAN231)*(98R/140R) VGAMMAN214 5R VGAMMAN231+((VGAMMAN203-VGAMMAN231)*(93R/140R) VGAMMAN215 5R VGAMMAN231+((VGAMMAN203-VGAMMAN231)*(88R/140R) VGAMMAN216 5R VGAMMAN231+((VGAMMAN203-VGAMMAN231)*(83R/140R) VGAMMAN217 5R VGAMMAN231+((VGAMMAN203-VGAMMAN231)*(78R/140R) VGAMMAN218 5R VGAMMAN231+((VGAMMAN203-VGAMMAN231)*(73R/140R) VGAMMAN219 5R VGAMMAN231+((VGAMMAN203-VGAMMAN231)*(68R/140R) VGAMMAN220 5R VGAMMAN231+((VGAMMAN203-VGAMMAN231)*(63R/140R) VGAMMAN221 5R VGAMMAN231+((VGAMMAN203-VGAMMAN231)*(58R/140R) VGAMMAN222 5R VGAMMAN231+((VGAMMAN203-VGAMMAN231)*(53R/140R) VGAMMAN223 5R VGAMMAN231+((VGAMMAN203-VGAMMAN231)*(48R/140R) VGAMMAN224 6R VGAMMAN231+((VGAMMAN203-VGAMMAN231)*(42R/140R) VGAMMAN225 6R VGAMMAN231+((VGAMMAN203-VGAMMAN231)*(36R/140R) VGAMMAN226 6R VGAMMAN231+((VGAMMAN203-VGAMMAN231)*(30R/140R) VGAMMAN227 6R VGAMMAN231+((VGAMMAN203-VGAMMAN231)*(24R/140R) VGAMMAN228 6R VGAMMAN231+((VGAMMAN203-VGAMMAN231)*(18R/140R) VGAMMAN229 6R VGAMMAN231+((VGAMMAN203-VGAMMAN231)*(12R/140R) VGAMMAN230 6R VGAMMAN231+((VGAMMAN203-VGAMMAN231)*(6R/140R) VGAMMAN231 6R VGAMMAN247+(VGAMMAN203-VGAMMAN247)*((1R+1R*VN231[4:0])/51R) VGAMMAN232 6R VGAMMAN239+((VGAMMAN231-VGAMMAN239)*(42R/48R) VGAMMAN233 6R VGAMMAN239+((VGAMMAN231-VGAMMAN239)*(36R/48R) VGAMMAN234 6R VGAMMAN239+((VGAMMAN231-VGAMMAN239)*(30R/48R) VGAMMAN235 6R VGAMMAN239+((VGAMMAN231-VGAMMAN239)*(24R/48R) VGAMMAN236 6R VGAMMAN239+((VGAMMAN231-VGAMMAN239)*(18R/48R) VGAMMAN237 6R VGAMMAN239+((VGAMMAN231-VGAMMAN239)*(12R/48R) VGAMMAN238 6R VGAMMAN239+((VGAMMAN231-VGAMMAN239)*(6R/48R)

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 307 of 328 VGAMMAN239 15R VGAMMAN247+(VGAMMAN203-VGAMMAN247)*((1R+1R*VN239[4:0])/51R) VGAMMAN240 6R VGAMMAN247+((VGAMMAN239-VGAMMAN247)*(74R/80R) VGAMMAN241 7R VGAMMAN247+((VGAMMAN239-VGAMMAN247)*(67R/80R) VGAMMAN242 9R VGAMMAN247+((VGAMMAN239-VGAMMAN247)*(58R/80R) VGAMMAN243 8R VGAMMAN247+((VGAMMAN239-VGAMMAN247)*(50R/80R) VGAMMAN244 11R VGAMMAN247+((VGAMMAN239-VGAMMAN247)*(39R/80R) VGAMMAN245 12R VGAMMAN247+((VGAMMAN239-VGAMMAN247)*(27R/80R) VGAMMAN246 12R VGAMMAN247+((VGAMMAN239-VGAMMAN247)*(15R/80R) VGAMMAN247 15R AGND+ΔVDHN(3R*VN247[5:0])/322R , ΔVDHN=(VREG2OUT-AGND) VGAMMAN248 12R VGAMMAN251+((VGAMMAN247-VGAMMAN251)*(68R/80R) VGAMMAN249 16R VGAMMAN251+((VGAMMAN247-VGAMMAN251)*(52R/80R) VGAMMAN250 24R VGAMMAN251+((VGAMMAN247-VGAMMAN251)*(28R/80R) VGAMMAN251 28R AGND+ΔVDHN(3R*VN251[5:0])/322R , ΔVDHN=(VREG2OUT-AGND) VGAMMAN252 25R VGAMMAN255+(VGAMMN251-VGAMMAN255)*(105R/130R) VGAMMAN253 45R VGAMMAN255+(VGAMMN251-VGAMMAN255)*(60R/130R) VGAMMAN254 20R VGAMMAN255+(VGAMMN251-VGAMMAN255)*(40R/130R) VGAMMAN255 10R AGND+ΔVDHN(3R*VN255[5:0])/322R , ΔVDHN=(VREG2OUT-AGND)

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 308 of 328 12. Deep Standby Mode Setting Set Page1_R58h:DSTB = 1 Display Off Sequence Deep Standby Mode Enter Deep Standby mode Set CSX pin = Low, then Set CSX pin = High Set CSX pin = Low, then set CSX pin = High Set CSX pin = Low, then set CSX pin = High Set CSX pin = Low, then set CSX pin = High Set CSX pin = Low, then set CSX pin = High Set CSX pin = Low, then set CSX pin = High Registers set as default value ILI's register setting Release from Deep Standby mode Display On Sequence Set CSX pin low to high x6 12 56 34CSX > 100ns > 100ns > 80ms Wait >150ms > 200ms Set RESX pin low to high Set RESX pin = Low, then Set RESX pin = High (See Section 9.1.3 Reset Timing) Figure 108 Deep Standby Mode Entry / Exit

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 309 of 328 13. Synchronization Time The GPO[3:2] of ILI9806E can output the synchronization signals to touch sensing signal for touch panel controller. To use these signals, touch panel controller can receive touch sensing signal while avoiding display changing noise. These signals are consist of vertical synchronization signal: VSOUT and horizontal synchronization signal: HSOUT. The level of output voltage is IOVCC to GND. Each signal can adjust output timing for internal synchronization signal. The high level width of VSOUT is 1 line, and it is adjustable.VSOUT is outputted always, but HSOUT is outputted during displaying only. (1) VSOUT output Timing VSOUT output means internal VSYNC is starting point. VSOUT output timing can be adjusted by VSOD register. Unit is 1H. (2) HSOUT output Timing HSOUT output means internal source output timing is starting point. HSOUT output timing can be adjusted by HSOD register. And HSOUT high level width can be adjusted by HSOHW register.

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 310 of 328 14. Electrical Characteristics 14.1. Absolute Maximum Ratings The absolute maximum rating is listed on Table 42. When the ILI9806E is used out of the absolute maximum ratings, it may be permanently damaged. To use the ILI9806E within the following electrical characteristics limit is strongly recommended for normal operation. If these el ectrical characteristic conditions are exceeded during normal operation, the ILI9806E will malfunction and cause poor reliability. Table 43 Absolute Maximum Ratings Item Symbol Unit Value Supply voltage(Analog) VCI ~ AGND V -0.3 ~ +4.6 Supply voltage(Analog) VCIP ~ CGND V -0.3 ~ +4.6 Supply voltage(Analog) VCIR ~ VSSR1 V -0.3 ~ +4.6 Supply voltage (I/O) IOVCC ~ DGND V -0.3 ~ +4.6 OTP Supply voltage VPP ~ AGND V -0.3 ~ +6.6 Supply voltage DDVDH ~ AGND V -0.3 ~ +6.6 Supply voltage DDVDL ~ AGND V 0.3 ~ -6.6 Supply voltage VGH ~ AGND V -0.3 ~ +25 Supply voltage VGL ~ AGND V 0.3 ~ -16 Driver supply voltage DDVDH – DDVDL V ≦13.2V Driver supply voltage VGH – VGL V ≦ 3 2 . 0 V Input voltage V IN V - 0 . 3 ~ I O V C C + 0 . 3 HS Input voltage V HSIN V - 0 . 3 ~ + 2 Operating temperature Topr ℃ -30 ~ +70 Storage temperature Tstg ℃ -55 ~ +110 Note: Even if the one of the above param eters is exceeded momentarily, t he quality of the product may be degraded. Absolute maximum ratings, therefore, specify the exceeding values which the product may be physically damaged. Be sure to use the product within the range of the absolute maximum ratings.

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 311 of 328 14.2. DC Characteristics for Panel Driving Item Symbol Condition Min. Typ. Max. Unit Note Power & Operation Voltage Operating voltage VCI VCIP VCIR - 2.5 2.8 3.6 V Operating voltage IOVCC - 1.65 1.8 3.6 V Note1,2 OTP Supply voltage VPP - 5.0 V Note1 Logic High level input voltage V IH - 0 . 7 * I O V C C I O V C C V N o t e 1 Logic Low level input voltage V IL - -0.3 0.3*IOVCC V Note1 Logic High level output voltage TE, SDO (SDA) , LEDPWM VOH I O H = - 1 . 0 m A 0 . 8 * I O V C C I O V C C V N o t e 1 Logic Low level output voltage TE, SDO (SDA) , LEDPWM VOL I O L = + 1 . 0 m A 0 0 . 2 * I O V C C V N o t e 1 Gate Driver High Voltage VGH - 10.0 - 20 V Gate Driver Low Voltage VGL - -15.0 - -6.0 V Driver Supply Voltage - |VGH-VGL| 16 - 32 V VCOM Operation DC VCOM Amplitude Voltage VCOM - -4.0 - 0 V Note3 Source Driver Source Output Range V SOUT - VREG2OUT +0.1 - VREG1OUT -0.1 V Note4 Positive Gamma Reference Voltage VREG1OUT - 3.0 - 6.1875 V Note5 Negative Gamma Reference Voltage VREG2OUT - -6.1875 - -3.0 V Note5 Source Output Setting Time Tr Below with 99% precision - 15 20 us Note3.4 Output Deviation Voltage (Source Output channel) Vdev Sout>=4.2V Sout<=0.8V - - 30 mV Note3 4.2V>Sout>0.8V - - 20 mV - Output Offset Voltage V OFFSET - - - 3 5 m V N o t e 3 Booster Operation Booster Voltage DDVDH - 6.5 V Booster Voltage DDVDL - -6.5 V Booster Drop Voltage DDVDH drop loading=1mA - - 5 % Gate Driver High Voltage VGH - 10.0 - 20 V Gate Driver Low Voltage VGL - -15.0 - -6.0 V Standby mode current consumption Sleep In mode I(IOVCC SLP IN) Ta = 25 °C VCI=2.8V IOVCC=1.8V 0 - 10 uA I(VCI SLP IN for DPI+SPI I/F) 5 - 60 uA I(VCI SLP IN for MIPI DSI I/F) 5 - 60 uA Deep Standby mode I(IOVCC DSTB) 0 - 1 uA I(VCI DSTB) 0 - 1 u A Note: 2. Supply digital IOVCC voltage equal or less than analog VCIP voltage. 3. Source channel loading = 10pF/channel 4. The Max. Value is between with Note 3 measure point and Gamma setting value 5. VREG1OUT≦DDVDH-0.3V and VREG2OUT≧DDVDL+0.3V.

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 312 of 328 14.3. DSI DC Characteristics DSI is using different state codes which are depending on DC voltage levels of the clock and data lanes. The meaning of the state codes is defined on the following table. State Code Line DC Voltage Levels CLOCK_P or DATA_P CLOCK_N or DATA_N HS-0 Low (HS) High (HS) HS-1 High (HS) Low (HS) LP-00 Low (LP) Low (LP) LP-01 Low (LP) High (LP) LP-10 High (LP) Low (LP) LP-11 High (LP) High (LP) Note: Ta=-30℃ t o 7 0℃ ( t o + 8 5℃ n o d a m a g e ) 14.3.1. DC characterist ics for Power Lines Parameter Symbol Condition Specification Unit Min. Typ. Max. Analog power supply voltage VCI Operating voltage 2.5 2.8 3.6 V Digital power supply voltage IOVCC I/O supply voltage 1.65 1.8 3.6 V Analog power supply voltage noise VVCI_NOISE Noise Range, 0 to 100MHz, Sinusoidal Wave (peak-to-peak) - - 100 mV Noise Range, 0 to 30kHz, Pulse Wave with Duty Cycle (50%/50%) - - 500 mV I/O power supply voltage noise V IOVCC_NOISE Noise Range, 0 to 100MHz, Sinusoidal Wave (peak-to-peak) - - 100 mV Note: 1. Ta=-30℃ t o 7 0℃ ( t o + 8 5℃ n o d a m a g e ) 2. These values are not symmetric amplitude, which centersm3g points are IOVCC or VCI. See examples as reference purposes, when VVCI_NOISE and VIOVCC_NOISE are maximums, below. Figure 109 Noise on Power Supply Lines

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 313 of 328 14.3.2. DC characterist ics for DSI LP mode DC levels of the LP-00, LP-01, LP -10 and LP-11 are defined on table bel ow: DC Characteristics for DSI LP mode when LP-RX, LP-CD or LP-TX is mentioned on the c ondition column. Other logical levels of the table are for MPU interface. Parameter Symbol Condition Specification Unit Min. Typ. Max. Logic High level output voltage V OH I OUT=-1mA, Note 2 0.8 V VCI - V VCI V Logic Low level output voltage V OL I OUT=1mA, Note 2 0.0 - 0.2V VCI V Logic High level input voltage V IHLPCD L P - C D , N o t e 3 4 5 0 - 1 3 5 0 m V Logic Low level input voltage V ILLPCD L P - C D , N o t e 3 0 . 0 - 2 0 0 m V Logic High level input voltage V IHLPRX L P - R X ( C L K , D 0 , D 1 ) , N o t e 3 8 8 0 - 1 3 5 0 m V Logic Low level input voltage V ILLPRX L P - R X ( C L K , D 0 , D 1 ) , N o t e 3 0 . 0 - 5 5 0 m V Logic Low level input voltage V ILLPRXULP L P - R X ( C L K U L P m o d e ) , N o t e 3 0 . 0 - 3 0 0 m V Logic high level output voltage V OHLPTX L P - T X ( D 0 ) , N o t e 3 1 . 1 - 1 . 3 V Logic Low level output voltage V OLLPTX LP-TX (D0), Note 3 -50 - 50 mV Logic High level input current I IH L P - C D , L P - R X , N o t e 3 - - 1 0 u A Logic Low level input current I IL L P - C D , L P - R X , N o t e 3 - 1 0 - - u A Note: 1. Ta=-30℃ t o 7 0℃ ( t o + 8 5℃ n o d a m a g e ) 2. LEDPWM 3. DSI High Speed mode is off 14.3.3. Spike / Glitch Rejection Figure 110 Spike / Glitch Rejection Note: 1. Peak Interference Amplitude max. 200mV and Interference Frequency min. 450MHz. 2. n = 0 and 1. Table 44 Spike / Glitch Rejection Spike / Glitch Rejection – DSI Signal Symbol Parameter Min Max Unit DSI-CLK+/-, DSI-Dn+/- SGD Input pulse rejection for DSI - 300 Vps

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 314 of 328 14.3.4. DC Characteristics for DSI HS mode Parameter Symbol Condition Specification Unit Input Common Mode Voltage for Clock V CMCLK DSI-CLK+/- Note 2, Note 3 70 - 330 mV Input Common Mode Voltage for Data V CMDATA DSI-Dn+/- Note 2, Note 3, Note 5 70 - 330 mV Common Mode Ripple for Clock Equal or Less than 450MHz VCMRCLKL450 DSI-CLK+/- Note 4 -50 - 50 mV Common Mode Ripple for Data Equal or Less than 450MHz VCMRDATAL450 DSI-Dn+/- Note 4, Note 5 -50 - 50 mV Common Mode Ripple for Clock More than 450MHz (peak sine wave) VCMRCLKM450 DSI-CLK+/- - - 100 mV Common Mode Ripple for Data More than 450MHz (peak sine wave) VCMRDATAM450 DSI-Dn+/- Note 5 - - 100 mV Differential Input Low Level Threshold Voltage for Clock VTHLCLK- D S I - C L K + / - - 7 0 - - m V Differential Input Low Level Threshold Voltage for Data VTHLDATA- DSI-Dn+/- Note 5 -70 - - mV Differential Input High Level Threshold Voltage for Clock VTHHCLK+ DSI-CLK+/- - - 70 mV Differential Input High Level Threshold Voltage for Data VTHHDATA+ DSI-Dn+/- Note 5 - - 70 mV Single-ended Input Low Voltage V ILHS DSI-CLK+/-, DSI-Dn+/- Note 3, Note 5 -40 - - mV Single-ended Input High Voltage V IHHS DSI-CLK+/-, DSI-Dn+/- Note 3, Note 5 - - 460 mV Differential Termination Resistor R TERM DSI-CLK+/-, DSI-Dn+/- Note 5 80 100 125 Ω Single-ended Threshold Voltage for Termination Enable VTERM-EN DSI-CLK+/-, DSI-Dn+/- Note 5 - - 450 mV Termination Capacitor C TERM DSI-CLK+/-, DSI-Dn+/- Note 5, Note 6 - - 60 pF Note: 1. Ta = -30℃ t o 7 0℃ ( t o + 8 5℃ n o d a m a g e ) , I O V C C = 1 . 6 5 t o 1 . 9 5 V . 2. Includes 50mV (-50mV to 50mV) ground difference. 3. Without VCMRCLKM450/VCMRDATAM450. 4. Without 50mV (-50mV to 50mV) ground difference. 5. n = 0 and 1. 6. For higher bit rates a 14pF capacitor will be needed to meet the common-mode return loss specification.

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 316 of 328 Figure 113 Differential Pair Termination Resistor on the Receiver Side

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 317 of 328 14.4. AC Characteristics 14.4.1. Display Serial In terface Timing Characteristics (3-line SPI system) Signal Symbol Parameter min max Unit Description CSX tcss Chip select time (Write) 15 - ns tcsh Chip select hold time (Read) 15 - ns tCHW C S “ H ” p u l s e w i d t h 4 0 - ns SCL twc Serial clock cycle (Write) 30 - ns twrh SCL “H” pulse width (Write) 10 - ns twrl SCL “L” pulse width (Write) 10 - ns trc Serial clock cycle (Read) 150 - ns trdh SCL “H” pulse width (Read) 60 - ns trdl SCL “L” pulse width (Read) 60 - ns SDA/SDO (Output) tacc Access time (Read) 10 100 ns For maximum CL=30pF For minimum CL=8pF toh Output disable time (Read) 15 100 ns SDA/SDI (Input) tds Data setup time (Write) 10 - ns tdh Data hold time (Write) 10 - ns Note: 2. Does not include signal rise and fall times.

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 318 of 328 14.4.2. Parallel 24/18/16-bit RGB Interface Timing Characteristics Signal Symbol Parameter min max Unit Description VS/ HS tSYNCS V S / H S s e t u p t i m e 5 - n s 24/18/16-bit bus RGB interface mode tSYNCH V S / H S h o l d t i m e 5 - ns DE tENS D E s e t u p t i m e 5 - n s tENH D E h o l d t i m e 5 - ns DB[23:0] tPOS D a t a s e t u p t i m e 5 - n s tPDH D a t a h o l d t i m e 5 - ns PCLK PWDH PCLK high-level period 13 - ns PWDL PCLK low-level period 13 - ns tCYCD P C L K c y c l e t i m e 2 8 - ns trgbr , trgbf P C L K , H S , V S r i s e / f a l l t i m e - 1 5 n s Note: Ta = -30 to 70 °C, IOVCC=1.65V to 3.6V, VCI=2.5V to 3.6V, DGND=0V

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 320 of 328 14.4.6. High Speed Mode – Rise and Fall Timings Figure 116 Rise and Fall Timings on Clock and Data Channels Table 47 Rise and Fall Timings on Clock and Data Channels Parameter Symbol Condition Specification Min Typ Max Unit Differential Rise Time for Clock t DRTCLK DSI-CLK+/- - - 150 (Note ) ps Differential Rise Time for Data t DRTDATA DSI-Dn+/- n=0 and 1 - - 150 (Note ) ps Differential Fall Time for Clock t DFTCLK DSI-CLK+/- - - 150 (Note ) ps Differential Fall Time for Data t DFTDATA DSI-Dn+/- n=0 and 1 - - 150 (Note ) ps Note:The display module has to meet timing requirements, what are defined for the transmitter (MPU) on MIPI D-Phy standard

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 322 of 328 14.4.8. Data Lanes from Low Po wer Mode to High Speed Mode Figure 119 Data Lanes – Low Power Mode to High Speed Mode Timings Table 50 Data Lanes – Low Power Mode to High Speed Mode Timings Signal Symbol Description Min Max Unit DSI-Dn+/-, n=0 and 1 T LPX L e n g t h o f a n y L o w P o w e r S t a t e P e r i o d 50 - ns DSI-Dn+/-, n=0 and 1 T HS-PREPARE T i m e t o d r i v e L P - 0 0 t o p r e p a r e f o r H S T r a n s m i s s i o n 40+4xUI 85+6xUI ns DSI-Dn+/-, n=0 and 1 T HS-TERM-EN Time to enable Data Lane Receiver line termination measured from when Dn crosses VILMAX - 35+4xUI ns

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 323 of 328 14.4.9. Data Lanes from High Speed Mode to Low Power Mode Figure 120 Data Lanes – High Speed Mode to Low Power Mode Timings Table 51 Data Lanes – High Speed Mode to Low Power Mode Timings Signal Symbol Description Min Max Unit DSI-Dn+/-, n=0 and 1 T HS-SKIP Time-Out at Display Module (ILI9806E) to ignore transition period of EoT 40 55+4xUI ns DSI-Dn+/-, n=0 and 1 T HS-EXIT T i m e t o d r i v e r L P - 1 1 a f t e r H S b u r s t 100 - ns

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 324 of 328 14.4.10. DSI Clock Burst – High Speed Mode to/from Low Power Mode Figure 121 Clock Lanes – High Speed Mode to/from Low Power Mode Timings Table 52 Clock Lanes – High Speed Mode to/from Low Power Mode Timings Signal Symbol Description Min Max Unit DSI-CLK+/- T CLK-POST Time that the MPU shall continue sending HS clock after the last associated Data Lanes has transitioned to LP mode 60+52xUI - ns DSI-CLK+/- T CLK-TRAIL Time to drive HS differential state after last payload clock bit of a HS transmission burst 60 - ns DSI-CLK+/- T HS-EXIT T i m e t o d r i v e L P - 1 1 a f t e r H S b u r s t 100 - ns DSI-CLK+/- T CLK-PREPARE T i m e t o d r i v e L P - 0 0 t o p r e p a r e f o r H S t r a n s m i s s i o n 38 95 ns DSI-CLK+/- T CLK-TERM-EN T i m e - o u t a t C l o c k L a n e t o e n a b l e H S t e r m i n a t i o n - 38 ns DSI-CLK+/- T CLK-PREPARE M i n i m u m l e a d H S - 0 d r i v e period before starting Clock 300 - ns DSI-CLK+/- T CLK-PRE Time that the HS clock shall be driven prior to any associated Data Lane beginning the transition from LP to HS mode 8xUI - ns

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 325 of 328 15. Application Circuit 15.1. Reference Circuit

1 DM Y _VSS

2 DM Y _VSS

3 DM Y _VSS

4 PAD A1

5 PAD B1

11 CO N TACT1A

12 CO N TACT1B

20 VG LO

21 VG LO

22 VG L_REG

23 VG L_REG

50 TE STD I N [ 0 ]

51 TE STD I N [ 1 ]

52 TE STD I N [ 2 ]

53 TE STD I N [ 3 ]

54 DM Y

55 TE STD I N [ 4 ]

56 TE STD I N [ 5 ]

57 DM Y

58 DM Y

59 DM Y

60 VREG 2O U T

61 VREG 2O U T

62 VREG 1O U T

81 IO V CC

82 LA N SE L

84 PSW AP

86 TE STD I N [ 6 ]

87 NB W S E L

92 IO V CC

93 TE STD I N [ 7 ]

94 TE STD O U T[ 0 ]

95 IM [3]

96 IM [2]

97 IM [1]

98 IM [0]

99 GP O [ 3 ]

100 GP O[ 2 ]

101 GP O[ 1 ]

102 GP O[ 0 ]

103 TEST DO U T[ 1]

105 TEST DO U T[ 2]

106 SDO

107 SDI

108 TEST DO U T[ 3]

110 TEST D_EN

111 CS X

112 RE SX

116 IO VC C

117 IO VC C

118 IO VC C

119 DB [2 3]

120 DB [2 2]

121 DB [2 1]

122 DB [2 0]

123 DB [1 9]

124 DB [1 8]

125 DB [1 7]

126 DB [1 6]

127 DB [1 5]

128 DB [1 4]

129 DB [1 3]

130 DB [1 2]

131 DB [1 1]

132 DB [1 0]

133 DB [9 ]

134 DB [8 ]

135 DB [7 ]

136 DB [6 ]

137 DB [5 ]

138 DB [4 ]

139 DB [3 ]

140 DB [2 ]

141 DB [1 ]

142 DB [0 ]

144 PCLK

148 LED O N

149 DM Y

151 IO VC C

152 IO VC C

153 IO VC C

170 VC I

171 VC I

172 VC I

173 VC I

178 VC O RE

179 VC O RE

180 VC O RE

181 VC O RE

217 V1 2_ M IP I

218 V1 2_ M IP I

219 V1 2_ M IP I

220 VC O RE _ M IPI

221 VC O RE _ M IPI

222 VC O RE _ M IPI

223 VC I

224 VC I

225 VC I

226 VC I

227 VC I

228 VC I

229 VC I

230 VC I

231 DM Y

233 VS SR [2 ]

234 VS SR [2 ]

235 VS SR [2 ]

236 VS SR [2 ]

237 DM Y

238 DM Y

239 VG H _ RE G

240 VG H _ RE G

243 DM Y

244 DM Y

247 DM Y

248 DM Y

249 VC IP

250 VC IP

251 VC IP

252 VC IP

253 VC IP

254 VC IP

261 C1 1P

262 C1 1P

263 C1 1P

264 C1 1N

265 C1 1N

266 C1 1N

267 C1 2P

268 C1 2P

269 C1 2P

270 C1 2N

271 C1 2N

272 C1 2N

273 C1 3P

274 C1 3P

275 C1 3P

276 C1 3N

277 C1 3N

278 C1 3N

279 C1 4P

280 C1 4P

281 C1 4P

282 C1 4N

283 C1 4N

284 C1 4N

300 C2 1P

301 C2 1P

302 C2 1P

303 C2 1N

304 C2 1N

305 C2 1N

306 C2 2P

307 C2 2P

308 C2 2P

309 C2 2N

310 C2 2N

311 C2 2N

312 C2 3P

313 C2 3P

314 C2 3P

315 C2 3N

316 C2 3N

317 C2 3N

318 C2 4P

319 C2 4P

320 C2 4P

321 C2 4N

322 C2 4N

323 C2 4N

324 VC IP

325 VC IP

326 VC IP

327 VC IP

328 VC IP

329 VC L

330 VC L

331 VC L

332 VC L

333 VC L

334 VC L

335 VC L

336 VS SR [3 ]

337 VS SR [3 ]

338 VS SR [3 ]

343 C3 1P

344 C3 1P

345 C3 1P

346 C3 1N

347 C3 1N

348 C3 1N

349 C3 2P

350 C3 2P

351 C3 2P

352 C3 2N

353 C3 2N

354 C3 2N

355 VC O RE

356 VC O RE

357 VC O RE

361 C4 1P

362 C4 1P

363 C4 1N

364 C4 1N

369 VG H _ RE G

370 VG H _ RE G

371 C5 1P

372 C5 1P

373 C5 1N

374 C5 1N

375 VG L _R E G

376 VG L _R E G

383 DM Y

384 DM Y

385 DM Y

386 DM Y

387 CO N T ACT 2A

388 CO N T ACT 2B

389 VC O M

390 VC O M

391 VC O M

392 VC O M

393 VC O M

396 DM Y _V S S

397 DM Y _V S S

398 DM Y _V S S

399 DM Y _VSS

400 DM Y_VS S 401 DM Y _VSS402 PA DA 3 403 PAD B3404 GOUT _ V GHO 405 GOUT _ V GHO406 GOUT _ V GHO 407 GOUT _ V GL O408 GOUT _ V GL O 409 GOUT _ V GL O410 GOUT [ 1 ] 411 GOUT [ 1 ]412 GOUT [ 2 ] 413 GOUT [ 2 ]414 LV G L 415 LV G L416 LV G L 417 VG H _REG418 VG H _REG 419 VG H _REG420 GOUT _ V GL O 421 GOUT _ V GL O422 GOUT _ V GL O 423 GOUT [ 3 ]424 GOUT [ 3 ] 425 GOUT [ 4 ]426 GOUT [ 4 ] 427 GOUT [ 5 ]428 GOUT [ 5 ] 429 GOUT [ 6 ]430 GOUT [ 6 ] 431 GOUT [ 7 ]432 GOUT [ 7 ] 433 GOUT [ 8 ]434 GOUT [ 8 ] 435 GOUT [ 9 ]436 GOUT [ 9 ] 437 GOUT [ 1 0 ]438 GOUT [ 1 0 ] 439 GOUT [ 1 1 ]440 GOUT [ 1 1 ] 441 GOUT [ 1 2 ]442 GOUT [ 1 2 ] 443 GOUT [ 1 3 ]444 GOUT [ 1 3 ] 445 GOUT [ 1 4 ]446 GOUT [ 1 4 ] 447 GOUT [ 1 5 ]448 GOUT [ 1 5 ] 449 GOUT [ 1 6 ]450 GOUT [ 1 6 ] 451 GOUT _ V GHO452 GOUT _ V GHO 453 GOUT _ V GHO454 GOUT _ V GHO 455 GOUT _ V GHO456 GOUT _ V GHO 457 DM Y _VG H458 DM Y_VG H 459 GOUT _ V GL O460 GOUT _ V GL O 461 GOUT _ V GL O462 GOUT _ V GL O 463 GOUT _ V GL O464 GOUT _ V GL O 465 DM Y _VSS466 DM Y_VS S 467 S[ 0]468 S[ 1] 469 S[ 2]470 S[ 3] 471 S[ 4]472 S[ 5] 473 S[ 6]474 S[ 7] 475 S[ 8]476 S[ 9] 477 S[ 10]478 S[ 11 ] 479 S[ 12]480 S[ 13 ] 481 S[ 14]482 S[ 15 ] 483 S[ 16]484 S[ 17 ] 485 S[ 18]486 S[ 19 ] 487 S[ 20]488 S[ 21 ] 489 S[ 22]490 S[ 23 ] 491 S[ 24]492 S[ 25 ] 493 S[ 26]494 S[ 27 ] 495 S[ 28]496 S[ 29 ] 497 S[ 30]498 S[ 31 ] 499 S[ 32]500 S[ 33 ] 501 S[ 34]502 S[ 35 ] 503 S[ 36]504 S[ 37 ] 505 S[ 38]506 S[ 39 ] 507 S[ 40]508 S[ 41 ] 509 S[ 42]510 S[ 43 ] 511 S[ 44]512 S[ 45 ] 513 S[ 46]514 S[ 47 ] 515 S[ 48]516 S[ 49 ] 517 S[ 50]518 S[ 51 ] 519 S[ 52]520 S[ 53 ] 521 S[ 54]522 S[ 55 ] 523 S[ 56]524 S[ 57 ] 525 S[ 58]526 S[ 59 ] 527 S[ 60]528 S[ 61 ] 529 S[ 62]530 S[ 63 ] 531 S[ 64]532 S[ 65 ] 533 S[ 66]534 S[ 67 ] 535 S[ 68]536 S[ 69 ] 537 S[ 70]538 S[ 71 ] 539 S[ 72]540 S[ 73 ] 541 S[ 74]542 S[ 75 ] 543 S[ 76]544 S[ 77 ] 545 S[ 78]546 S[ 79 ] 547 S[ 80]548 S[ 81 ] 549 S[ 82]550 S[ 83 ] 551 S[ 84]552 S[ 85 ] 553 S[ 86]554 S[ 87 ] 555 S[ 88]556 S[ 89 ] 557 S[ 90]558 S[ 91 ] 559 S[ 92]560 S[ 93 ] 561 S[ 94]562 S[ 95 ] 563 S[ 96]564 S[ 97 ] 565 S[ 98]566 S[ 99 ] 567 S[ 100 ]568 S[ 10 1] 569 S[ 102 ]570 S[ 10 3] 571 S[ 104 ]572 S[ 10 5] 573 S[ 106 ]574 S[ 10 7] 575 S[ 108 ]576 S[ 10 9] 577 S[ 110 ]578 S[ 11 1] 579 S[ 112 ]580 S[ 11 3] 581 S[ 114 ]582 S[ 11 5] 583 S[ 116 ]584 S[ 11 7] 585 S[ 118 ]586 S[ 11 9] 587 S[ 120 ]588 S[ 12 1] 589 S[ 122 ]590 S[ 12 3] 591 S[ 124 ]592 S[ 12 5] 593 S[ 126 ]594 S[ 12 7] 595 S[ 128 ]596 S[ 12 9] 597 S[ 130 ]598 S[ 13 1] 599 S[ 132 ]600 S[ 13 3] 601 S[ 134 ]602 S[ 13 5] 603 S[ 136 ]604 S[ 13 7] 605 S[ 138 ]606 S[ 13 9] 607 S[ 140 ]608 S[ 14 1] 609 S[ 142 ]610 S[ 14 3] 611 S[ 144 ]612 S[ 14 5] 613 S[ 146 ]614 S[ 14 7] 615 S[ 148 ]616 S[ 14 9] 617 S[ 150 ]618 S[ 15 1] 619 S[ 152 ]620 S[ 15 3] 621 S[ 154 ]622 S[ 15 5] 623 S[ 156 ]624 S[ 15 7] 625 S[ 158 ]626 S[ 15 9] 627 S[ 160 ]628 S[ 16 1] 629 S[ 162 ]630 S[ 16 3] 631 S[ 164 ]632 S[ 16 5] 633 S[ 166 ]634 S[ 16 7] 635 S[ 168 ]636 S[ 16 9] 637 S[ 170 ]638 S[ 17 1] 639 S[ 172 ]640 S[ 17 3] 641 S[ 174 ]642 S[ 17 5] 643 S[ 176 ]644 S[ 17 7] 645 S[ 178 ]646 S[ 17 9] 647 S[ 180 ]648 S[ 18 1] 649 S[ 182 ]650 S[ 18 3] 651 S[ 184 ]652 S[ 18 5] 653 S[ 186 ]654 S[ 18 7] 655 S[ 188 ]656 S[ 18 9] 657 S[ 190 ]658 S[ 19 1] 659 S[ 192 ]660 S[ 19 3] 661 S[ 194 ]662 S[ 19 5] 663 S[ 196 ]664 S[ 19 7] 665 S[ 198 ]666 S[ 19 9] 667 S[ 200 ]668 S[ 20 1] 669 S[ 202 ]670 S[ 20 3] 671 S[ 204 ]672 S[ 20 5] 673 S[ 206 ]674 S[ 20 7] 675 S[ 208 ]676 S[ 20 9] 677 S[ 210 ]678 S[ 21 1] 679 S[ 212 ]680 S[ 21 3] 681 S[ 214 ]682 S[ 21 5] 683 S[ 216 ]684 S[ 21 7] 685 S[ 218 ]686 S[ 21 9] 687 S[ 220 ]688 S[ 22 1] 689 S[ 222 ]690 S[ 22 3] 691 S[ 224 ]692 S[ 22 5] 693 S[ 226 ]694 S[ 22 7] 695 S[ 228 ]696 S[ 22 9] 697 S[ 230 ]698 S[ 23 1] 699 S[ 232 ]700 S[ 23 3] 701 S[ 234 ]702 S[ 23 5] 703 S[ 236 ]704 S[ 23 7] 705 S[ 238 ]706 S[ 23 9] 707 S[ 240 ]708 S[ 24 1] 709 S[ 242 ]710 S[ 24 3] 711 S[ 244 ]712 S[ 24 5] 713 S[ 246 ]714 S[ 24 7] 715 S[ 248 ]716 S[ 24 9] 717 S[ 250 ]718 S[ 25 1] 719 S[ 252 ]720 S[ 25 3] 721 S[ 254 ]722 S[ 25 5] 723 S[ 256 ]724 S[ 25 7] 725 S[ 258 ]726 S[ 25 9] 727 S[ 260 ]728 S[ 26 1] 729 S[ 262 ]730 S[ 26 3] 731 S[ 264 ]732 S[ 26 5] 733 S[ 266 ]734 S[ 26 7] 735 S[ 268 ]736 S[ 26 9] 737 S[ 270 ]738 S[ 27 1] 739 S[ 272 ]740 S[ 27 3] 741 S[ 274 ]742 S[ 27 5] 743 S[ 276 ]744 S[ 27 7] 745 S[ 278 ]746 S[ 27 9] 747 S[ 280 ]748 S[ 28 1] 749 S[ 282 ]750 S[ 28 3] 751 S[ 284 ]752 S[ 28 5] 753 S[ 286 ]754 S[ 28 7] 755 S[ 288 ]756 S[ 28 9] 757 S[ 290 ]758 S[ 29 1] 759 S[ 292 ]760 S[ 29 3] 761 S[ 294 ]762 S[ 29 5] 763 S[ 296 ]764 S[ 29 7] 765 S[ 298 ]766 S[ 29 9] 767 S[ 300 ]768 S[ 30 1] 769 S[ 302 ]770 S[ 30 3] 771 S[ 304 ]772 S[ 30 5] 773 S[ 306 ]774 S[ 30 7] 775 S[ 308 ]776 S[ 30 9] 777 S[ 310 ]778 S[ 31 1] 779 S[ 312 ]780 S[ 31 3] 781 S[ 314 ]782 S[ 31 5] 783 S[ 316 ]784 S[ 31 7] 785 S[ 318 ]786 S[ 31 9] 787 S[ 320 ]788 S[ 32 1] 789 S[ 322 ]790 S[ 32 3] 791 S[ 324 ]792 S[ 32 5] 793 S[ 326 ]794 S[ 32 7] 795 S[ 328 ]796 S[ 32 9] 797 S[ 330 ]798 S[ 33 1] 799 S[ 332 ]800 S[ 33 3] 801 S[ 334 ]802 S[ 33 5] 803 S[ 336 ]804 S[ 33 7] 805 S[ 338 ]806 S[ 33 9] 807 S[ 340 ]808 S[ 34 1] 809 S[ 342 ]810 S[ 34 3] 811 S[ 344 ]812 S[ 34 5] 813 S[ 346 ]814 S[ 34 7] 815 S[ 348 ]816 S[ 34 9] 817 S[ 350 ]818 S[ 35 1] 819 S[ 352 ]820 S[ 35 3] 821 S[ 354 ]822 S[ 35 5] 823 S[ 356 ]824 S[ 35 7] 825 S[ 358 ]826 S[ 35 9] 827 S[ 360 ]828 S[ 36 1] 829 S[ 362 ]830 S[ 36 3] 831 S[ 364 ]832 S[ 36 5] 833 S[ 366 ]834 S[ 36 7] 835 S[ 368 ]836 S[ 36 9] 837 S[ 370 ]838 S[ 37 1] 839 S[ 372 ]840 S[ 37 3] 841 S[ 374 ]842 S[ 37 5] 843 S[ 376 ]844 S[ 37 7] 845 S[ 378 ]846 S[ 37 9] 847 S[ 380 ]848 S[ 38 1] 849 S[ 382 ]850 S[ 38 3] 851 S[ 384 ]852 S[ 38 5] 853 S[ 386 ]854 S[ 38 7] 855 S[ 388 ]856 S[ 38 9] 857 S[ 390 ]858 S[ 39 1] 859 S[ 392 ]860 S[ 39 3] 861 S[ 394 ]862 S[ 39 5] 863 S[ 396 ]864 S[ 39 7] 865 S[ 398 ]866 S[ 39 9] 867 S[ 400 ]868 S[ 40 1] 869 S[ 402 ]870 S[ 40 3] 871 S[ 404 ]872 S[ 40 5] 873 S[ 406 ]874 S[ 40 7] 875 S[ 408 ]876 S[ 40 9] 877 S[ 410 ]878 S[ 41 1] 879 S[ 412 ]880 S[ 41 3] 881 S[ 414 ]882 S[ 41 5] 883 S[ 416 ]884 S[ 41 7] 885 S[ 418 ]886 S[ 41 9] 887 S[ 420 ]888 S[ 42 1] 889 S[ 422 ]890 S[ 42 3] 891 S[ 424 ]892 S[ 42 5] 893 S[ 426 ]894 S[ 42 7] 895 S[ 428 ]896 S[ 42 9] 897 S[ 430 ]898 S[ 43 1] 899 S[ 432 ]900 S[ 43 3] 901 S[ 434 ]902 S[ 43 5] 903 S[ 436 ]904 S[ 43 7] 905 S[ 438 ]906 S[ 43 9] 907 S[ 440 ]908 S[ 44 1] 909 S[ 442 ]910 S[ 44 3] 911 S[ 444 ]912 S[ 44 5] 913 S[ 446 ]914 S[ 44 7] 915 S[ 448 ]916 S[ 44 9] 917 S[ 450 ]918 S[ 45 1] 919 S[ 452 ]920 S[ 45 3] 921 S[ 454 ]922 S[ 45 5] 923 S[ 456 ]924 S[ 45 7] 925 S[ 458 ]926 S[ 45 9] 927 S[ 460 ]928 S[ 46 1] 929 S[ 462 ]930 S[ 46 3] 931 S[ 464 ]932 S[ 46 5] 933 S[ 466 ]934 S[ 46 7] 935 S[ 468 ]936 S[ 46 9] 937 S[ 470 ]938 S[ 47 1] 939 S[ 472 ]940 S[ 47 3] 941 S[ 474 ]942 S[ 47 5] 943 S[ 476 ]944 S[ 47 7] 945 S[ 478 ]946 S[ 47 9] 947 S[ 480 ]948 S[ 48 1] 949 S[ 482 ]950 S[ 48 3] 951 S[ 484 ]952 S[ 48 5] 953 S[ 486 ]954 S[ 48 7] 955 S[ 488 ]956 S[ 48 9] 957 S[ 490 ]958 S[ 49 1] 959 S[ 492 ]960 S[ 49 3] 961 S[ 494 ]962 S[ 49 5] 963 S[ 496 ]964 S[ 49 7] 965 S[ 498 ]966 S[ 49 9] 967 S[ 500 ]968 S[ 50 1] 969 S[ 502 ]970 S[ 50 3] 971 S[ 504 ]972 S[ 50 5] 973 S[ 506 ]974 S[ 50 7] 975 S[ 508 ]976 S[ 50 9] 977 S[ 510 ]978 S[ 51 1] 979 S[ 512 ]980 S[ 51 3] 981 S[ 514 ]982 S[ 51 5] 983 S[ 516 ]984 S[ 51 7] 985 S[ 518 ]986 S[ 51 9] 987 S[ 520 ]988 S[ 52 1] 989 S[ 522 ]990 S[ 52 3] 991 S[ 524 ]992 S[ 52 5] 993 S[ 526 ]994 S[ 52 7] 995 S[ 528 ]996 S[ 52 9] 997 S[ 530 ]998 S[ 53 1] 999 S[ 532 ]1000 S[533] 1001 S[ 53 4]1002 S[535] 1003 S[ 53 6]1004 S[537] 1005 S[ 53 8]1006 S[539] 1007 S[ 54 0]1008 S[541] 1009 S[ 54 2]1010 S[543] 1011 S[ 54 4]1012 S[545] 1013 S[ 54 6]1014 S[547] 1015 S[ 54 8]1016 S[549] 1017 S[ 55 0]1018 S[551] 1019 S[ 55 2]1020 S[553] 1021 S[ 55 4]1022 S[555] 1023 S[ 55 6]1024 S[557] 1025 S[ 55 8]1026 S[559] 1027 S[ 56 0]1028 S[561] 1029 S[ 56 2]1030 S[563] 1031 S[ 56 4]1032 S[565] 1033 S[ 56 6]1034 S[567] 1035 S[ 56 8]1036 S[569] 1037 S[ 57 0]1038 S[571] 1039 S[ 57 2]1040 S[573] 1041 S[ 57 4]1042 S[575] 1043 S[ 57 6]1044 S[577] 1045 S[ 57 8]1046 S[579] 1047 S[ 58 0]1048 S[581] 1049 S[ 58 2]1050 S[583] 1051 S[ 58 4]1052 S[585] 1053 S[ 58 6]1054 S[587] 1055 S[ 58 8]1056 S[589] 1057 S[ 59 0]1058 S[591] 1059 S[ 59 2]1060 S[593] 1061 S[ 59 4]1062 S[595] 1063 S[ 59 6]1064 S[597] 1065 S[ 59 8]1066 S[599] 1067 S[ 60 0]1068 S[601] 1069 S[ 60 2]1070 S[603] 1071 S[ 60 4]1072 S[605] 1073 S[ 60 6]1074 S[607] 1075 S[ 60 8]1076 S[609] 1077 S[ 61 0]1078 S[611] 1079 S[ 61 2]1080 S[613] 1081 S[ 61 4]1082 S[615] 1083 S[ 61 6]1084 S[617] 1085 S[ 61 8]1086 S[619] 1087 S[ 62 0]1088 S[621] 1089 S[ 62 2]1090 S[623] 1091 S[ 62 4]1092 S[625] 1093 S[ 62 6]1094 S[627] 1095 S[ 62 8]1096 S[629] 1097 S[ 63 0]1098 S[631] 1099 S[ 63 2]1100 S[633] 1101 S[ 63 4]1102 S[635] 1103 S[ 63 6]1104 S[637] 1105 S[ 63 8]1106 S[639] 1107 S[ 64 0]1108 S[641] 1109 S[ 64 2]1110 S[643] 1111 S[ 64 4]1112 S[645] 1113 S[ 64 6]1114 S[647] 1115 S[ 64 8]1116 S[649] 1117 S[ 65 0]1118 S[651] 1119 S[ 65 2]1120 S[653] 1121 S[ 65 4]1122 S[655] 1123 S[ 65 6]1124 S[657] 1125 S[ 65 8]1126 S[659] 1127 S[ 66 0]1128 S[661] 1129 S[ 66 2]1130 S[663] 1131 S[ 66 4]1132 S[665] 1133 S[ 66 6]1134 S[667] 1135 S[ 66 8]1136 S[669] 1137 S[ 67 0]1138 S[671] 1139 S[ 67 2]1140 S[673] 1141 S[ 67 4]1142 S[675] 1143 S[ 67 6]1144 S[677] 1145 S[ 67 8]1146 S[679] 1147 S[ 68 0]1148 S[681] 1149 S[ 68 2]1150 S[683] 1151 S[ 68 4]1152 S[685] 1153 S[ 68 6]1154 S[687] 1155 S[ 68 8]1156 S[689] 1157 S[ 69 0]1158 S[691] 1159 S[ 69 2]1160 S[693] 1161 S[ 69 4]1162 S[695] 1163 S[ 69 6]1164 S[697] 1165 S[ 69 8]1166 S[699] 1167 S[ 70 0]1168 S[701] 1169 S[ 70 2]1170 S[703] 1171 S[ 70 4]1172 S[705] 1173 S[ 70 6]1174 S[707] 1175 S[ 70 8]1176 S[709] 1177 S[ 71 0]1178 S[711] 1179 S[ 71 2]1180 S[713] 1181 S[ 71 4]1182 S[715] 1183 S[ 71 6]1184 S[717] 1185 S[ 71 8]1186 S[719] 1187 S[ 72 0]1188 DM Y _V S S 1189 DM Y_VS S1190 DM Y 1191 DM Y1192 DM Y 1193 DM Y1194 DM Y 1195 DM Y1196 DM Y 1197 DM Y1198 DM Y 1199 DM Y1200 DM Y 1201 DM Y1202 DM Y 1203 DM Y1204 DM Y 1205 DM Y1206 DM Y 1207 DM Y1208 DM Y 1209 DM Y1210 DM Y 1211 DM Y1212 DM Y 1213 DM Y1214 DM Y 1215 DM Y1216 DM Y 1217 DM Y1218 DM Y 1219 DM Y1220 DM Y 1221 DM Y1222 DM Y 1223 DM Y1224 DM Y 1225 DM Y1226 DM Y 1227 DM Y1228 DM Y 1229 DM Y1230 DM Y 1231 DM Y1232 DM Y 1233 DM Y1234 DM Y 1235 DM Y_VS S1236 DM Y _V S S 1237 S[ 72 1]1238 S[722] 1239 S[ 72 3]1240 S[724] 1241 S[ 72 5]1242 S[726] 1243 S[ 72 7]1244 S[728] 1245 S[ 72 9]1246 S[730] 1247 S[ 73 1]1248 S[732] 1249 S[ 73 3]1250 S[734] 1251 S[ 73 5]1252 S[736] 1253 S[ 73 7]1254 S[738] 1255 S[ 73 9]1256 S[740] 1257 S[ 74 1]1258 S[742] 1259 S[ 74 3]1260 S[744] 1261 S[ 74 5]1262 S[746] 1263 S[ 74 7]1264 S[748] 1265 S[ 74 9]1266 S[750] 1267 S[ 75 1]1268 S[752] 1269 S[ 75 3]1270 S[754] 1271 S[ 75 5]1272 S[756] 1273 S[ 75 7]1274 S[758] 1275 S[ 75 9]1276 S[760] 1277 S[ 76 1]1278 S[762] 1279 S[ 76 3]1280 S[764] 1281 S[ 76 5]1282 S[766] 1283 S[ 76 7]1284 S[768] 1285 S[ 76 9]1286 S[770] 1287 S[ 77 1]1288 S[772] 1289 S[ 77 3]1290 S[774] 1291 S[ 77 5]1292 S[776] 1293 S[ 77 7]1294 S[778] 1295 S[ 77 9]1296 S[780] 1297 S[ 78 1]1298 S[782] 1299 S[ 78 3]1300 S[784] 1301 S[ 78 5]1302 S[786] 1303 S[ 78 7]1304 S[788] 1305 S[ 78 9]1306 S[790] 1307 S[ 79 1]1308 S[792] 1309 S[ 79 3]1310 S[794] 1311 S[ 79 5]1312 S[796] 1313 S[ 79 7]1314 S[798] 1315 S[ 79 9]1316 S[800] 1317 S[ 80 1]1318 S[802] 1319 S[ 80 3]1320 S[804] 1321 S[ 80 5]1322 S[806] 1323 S[ 80 7]1324 S[808] 1325 S[ 80 9]1326 S[810] 1327 S[ 81 1]1328 S[812] 1329 S[ 81 3]1330 S[814] 1331 S[ 81 5]1332 S[816] 1333 S[ 81 7]1334 S[818] 1335 S[ 81 9]1336 S[820] 1337 S[ 82 1]1338 S[822] 1339 S[ 82 3]1340 S[824] 1341 S[ 82 5]1342 S[826] 1343 S[ 82 7]1344 S[828] 1345 S[ 82 9]1346 S[830] 1347 S[ 83 1]1348 S[832] 1349 S[ 83 3]1350 S[834] 1351 S[ 83 5]1352 S[836] 1353 S[ 83 7]1354 S[838] 1355 S[ 83 9]1356 S[840] 1357 S[ 84 1]1358 S[842] 1359 S[ 84 3]1360 S[844] 1361 S[ 84 5]1362 S[846] 1363 S[ 84 7]1364 S[848] 1365 S[ 84 9]1366 S[850] 1367 S[ 85 1]1368 S[852] 1369 S[ 85 3]1370 S[854] 1371 S[ 85 5]1372 S[856] 1373 S[ 85 7]1374 S[858] 1375 S[ 85 9]1376 S[860] 1377 S[ 86 1]1378 S[862] 1379 S[ 86 3]1380 S[864] 1381 S[ 86 5]1382 S[866] 1383 S[ 86 7]1384 S[868] 1385 S[ 86 9]1386 S[870] 1387 S[ 87 1]1388 S[872] 1389 S[ 87 3]1390 S[874] 1391 S[ 87 5]1392 S[876] 1393 S[ 87 7]1394 S[878] 1395 S[ 87 9]1396 S[880] 1397 S[ 88 1]1398 S[882] 1399 S[ 88 3]1400 S[884] 1401 S[ 88 5]1402 S[886] 1403 S[ 88 7]1404 S[888] 1405 S[ 88 9]1406 S[890] 1407 S[ 89 1]1408 S[892] 1409 S[ 89 3]1410 S[894] 1411 S[ 89 5]1412 S[896] 1413 S[ 89 7]1414 S[898] 1415 S[ 89 9]1416 S[900] 1417 S[ 90 1]1418 S[902] 1419 S[ 90 3]1420 S[904] 1421 S[ 90 5]1422 S[906] 1423 S[ 90 7]1424 S[908] 1425 S[ 90 9]1426 S[910] 1427 S[ 91 1]1428 S[912] 1429 S[ 91 3]1430 S[914] 1431 S[ 91 5]1432 S[916] 1433 S[ 91 7]1434 S[918] 1435 S[ 91 9]1436 S[920] 1437 S[ 92 1]1438 S[922] 1439 S[ 92 3]1440 S[924] 1441 S[ 92 5]1442 S[926] 1443 S[ 92 7]1444 S[928] 1445 S[ 92 9]1446 S[930] 1447 S[ 93 1]1448 S[932] 1449 S[ 93 3]1450 S[934] 1451 S[ 93 5]1452 S[936] 1453 S[ 93 7]1454 S[938] 1455 S[ 93 9]1456 S[940] 1457 S[ 94 1]1458 S[942] 1459 S[ 94 3]1460 S[944] 1461 S[ 94 5]1462 S[946] 1463 S[ 94 7]1464 S[948] 1465 S[ 94 9]1466 S[950] 1467 S[ 95 1]1468 S[952] 1469 S[ 95 3]1470 S[954] 1471 S[ 95 5]1472 S[956] 1473 S[ 95 7]1474 S[958] 1475 S[ 95 9]1476 S[960] 1477 S[ 96 1]1478 S[962] 1479 S[ 96 3]1480 S[964] 1481 S[ 96 5]1482 S[966] 1483 S[ 96 7]1484 S[968] 1485 S[ 96 9]1486 S[970] 1487 S[ 97 1]1488 S[972] 1489 S[ 97 3]1490 S[974] 1491 S[ 97 5]1492 S[976] 1493 S[ 97 7]1494 S[978] 1495 S[ 97 9]1496 S[980] 1497 S[ 98 1]1498 S[982] 1499 S[ 98 3]1500 S[984] 1501 S[ 98 5]1502 S[986] 1503 S[ 98 7]1504 S[988] 1505 S[ 98 9]1506 S[990] 1507 S[ 99 1]1508 S[992] 1509 S[ 99 3]1510 S[994] 1511 S[ 99 5]1512 S[996] 1513 S[ 99 7]1514 S[998] 1515 S[ 99 9]1516 S[1000] 1517 S[ 10 01 ]1518 S[1002] 1519 S[ 10 03 ]1520 S[1004] 1521 S[ 10 05 ]1522 S[1006] 1523 S[ 10 07 ]1524 S[1008] 1525 S[ 10 09 ]1526 S[1010] 1527 S[ 10 11 ]1528 S[1012] 1529 S[ 10 13 ]1530 S[1014] 1531 S[ 10 15 ]1532 S[1016] 1533 S[ 10 17 ]1534 S[1018] 1535 S[ 10 19 ]1536 S[1020] 1537 S[ 10 21 ]1538 S[1022] 1539 S[ 10 23 ]1540 S[1024] 1541 S[ 10 25 ]1542 S[1026] 1543 S[ 10 27 ]1544 S[1028] 1545 S[ 10 29 ]1546 S[1030] 1547 S[ 10 31 ]1548 S[1032] 1549 S[ 10 33 ]1550 S[1034] 1551 S[ 10 35 ]1552 S[1036] 1553 S[ 10 37 ]1554 S[1038] 1555 S[ 10 39 ]1556 S[1040] 1557 S[ 10 41 ]1558 S[1042] 1559 S[ 10 43 ]1560 S[1044] 1561 S[ 10 45 ]1562 S[1046] 1563 S[ 10 47 ]1564 S[1048] 1565 S[ 10 49 ]1566 S[1050] 1567 S[ 10 51 ]1568 S[1052] 1569 S[ 10 53 ]1570 S[1054] 1571 S[ 10 55 ]1572 S[1056] 1573 S[ 10 57 ]1574 S[1058] 1575 S[ 10 59 ]1576 S[1060] 1577 S[ 10 61 ]1578 S[1062] 1579 S[ 10 63 ]1580 S[1064] 1581 S[ 10 65 ]1582 S[1066] 1583 S[ 10 67 ]1584 S[1068] 1585 S[ 10 69 ]1586 S[1070] 1587 S[ 10 71 ]1588 S[1072] 1589 S[ 10 73 ]1590 S[1074] 1591 S[ 10 75 ]1592 S[1076] 1593 S[ 10 77 ]1594 S[1078] 1595 S[ 10 79 ]1596 S[1080] 1597 S[ 10 81 ]1598 S[1082] 1599 S[ 10 83 ]1600 S[1084] 1601 S[ 10 85 ]1602 S[1086] 1603 S[ 10 87 ]1604 S[1088] 1605 S[ 10 89 ]1606 S[1090] 1607 S[ 10 91 ]1608 S[1092] 1609 S[ 10 93 ]1610 S[1094] 1611 S[ 10 95 ]1612 S[1096] 1613 S[ 10 97 ]1614 S[1098] 1615 S[ 10 99 ]1616 S[1100] 1617 S[ 11 01 ]1618 S[1102] 1619 S[ 11 03 ]1620 S[1104] 1621 S[ 11 05 ]1622 S[1106] 1623 S[ 11 07 ]1624 S[1108] 1625 S[ 11 09 ]1626 S[1110] 1627 S[ 11 11 ]1628 S[1112] 1629 S[ 11 13 ]1630 S[1114] 1631 S[ 11 15 ]1632 S[1116] 1633 S[ 11 17 ]1634 S[1118] 1635 S[ 11 19 ]1636 S[1120] 1637 S[ 11 21 ]1638 S[1122] 1639 S[ 11 23 ]1640 S[1124] 1641 S[ 11 25 ]1642 S[1126] 1643 S[ 11 27 ]1644 S[1128] 1645 S[ 11 29 ]1646 S[1130] 1647 S[ 11 31 ]1648 S[1132] 1649 S[ 11 33 ]1650 S[1134] 1651 S[ 11 35 ]1652 S[1136] 1653 S[ 11 37 ]1654 S[1138] 1655 S[ 11 39 ]1656 S[1140] 1657 S[ 11 41 ]1658 S[1142] 1659 S[ 11 43 ]1660 S[1144] 1661 S[ 11 45 ]1662 S[1146] 1663 S[ 11 47 ]1664 S[1148] 1665 S[ 11 49 ]1666 S[1150] 1667 S[ 11 51 ]1668 S[1152] 1669 S[ 11 53 ]1670 S[1154] 1671 S[ 11 55 ]1672 S[1156] 1673 S[ 11 57 ]1674 S[1158] 1675 S[ 11 59 ]1676 S[1160] 1677 S[ 11 61 ]1678 S[1162] 1679 S[ 11 63 ]1680 S[1164] 1681 S[ 11 65 ]1682 S[1166] 1683 S[ 11 67 ]1684 S[1168] 1685 S[ 11 69 ]1686 S[1170] 1687 S[ 11 71 ]1688 S[1172] 1689 S[ 11 73 ]1690 S[1174] 1691 S[ 11 75 ]1692 S[1176] 1693 S[ 11 77 ]1694 S[1178] 1695 S[ 11 79 ]1696 S[1180] 1697 S[ 11 81 ]1698 S[1182] 1699 S[ 11 83 ]1700 S[1184] 1701 S[ 11 85 ]1702 S[1186] 1703 S[ 11 87 ]1704 S[1188] 1705 S[ 11 89 ]1706 S[1190] 1707 S[ 11 91 ]1708 S[1192] 1709 S[ 11 93 ]1710 S[1194] 1711 S[ 11 95 ]1712 S[1196] 1713 S[ 11 97 ]1714 S[1198] 1715 S[ 11 99 ]1716 S[1200] 1717 S[ 12 01 ]1718 S[1202] 1719 S[ 12 03 ]1720 S[1204] 1721 S[ 12 05 ]1722 S[1206] 1723 S[ 12 07 ]1724 S[1208] 1725 S[ 12 09 ]1726 S[1210] 1727 S[ 12 11 ]1728 S[1212] 1729 S[ 12 13 ]1730 S[1214] 1731 S[ 12 15 ]1732 S[1216] 1733 S[ 12 17 ]1734 S[1218] 1735 S[ 12 19 ]1736 S[1220] 1737 S[ 12 21 ]1738 S[1222] 1739 S[ 12 23 ]1740 S[1224] 1741 S[ 12 25 ]1742 S[1226] 1743 S[ 12 27 ]1744 S[1228] 1745 S[ 12 29 ]1746 S[1230] 1747 S[ 12 31 ]1748 S[1232] 1749 S[ 12 33 ]1750 S[1234] 1751 S[ 12 35 ]1752 S[1236] 1753 S[ 12 37 ]1754 S[1238] 1755 S[ 12 39 ]1756 S[1240] 1757 S[ 12 41 ]1758 S[1242] 1759 S[ 12 43 ]1760 S[1244] 1761 S[ 12 45 ]1762 S[1246] 1763 S[ 12 47 ]1764 S[1248] 1765 S[ 12 49 ]1766 S[1250] 1767 S[ 12 51 ]1768 S[1252] 1769 S[ 12 53 ]1770 S[1254] 1771 S[ 12 55 ]1772 S[1256] 1773 S[ 12 57 ]1774 S[1258] 1775 S[ 12 59 ]1776 S[1260] 1777 S[ 12 61 ]1778 S[1262] 1779 S[ 12 63 ]1780 S[1264] 1781 S[ 12 65 ]1782 S[1266] 1783 S[ 12 67 ]1784 S[1268] 1785 S[ 12 69 ]1786 S[1270] 1787 S[ 12 71 ]1788 S[1272] 1789 S[ 12 73 ]1790 S[1274] 1791 S[ 12 75 ]1792 S[1276] 1793 S[ 12 77 ]1794 S[1278] 1795 S[ 12 79 ]1796 S[1280] 1797 S[ 12 81 ]1798 S[1282] 1799 S[ 12 83 ]1800 S[1284] 1801 S[ 12 85 ]1802 S[1286] 1803 S[ 12 87 ]1804 S[1288] 1805 S[ 12 89 ]1806 S[1290] 1807 S[ 12 91 ]1808 S[1292] 1809 S[ 12 93 ]1810 S[1294] 1811 S[ 12 95 ]1812 S[1296] 1813 S[ 12 97 ]1814 S[1298] 1815 S[ 12 99 ]1816 S[1300] 1817 S[ 13 01 ]1818 S[1302] 1819 S[ 13 03 ]1820 S[1304] 1821 S[ 13 05 ]1822 S[1306] 1823 S[ 13 07 ]1824 S[1308] 1825 S[ 13 09 ]1826 S[1310] 1827 S[ 13 11 ]1828 S[1312] 1829 S[ 13 13 ]1830 S[1314] 1831 S[ 13 15 ]1832 S[1316] 1833 S[ 13 17 ]1834 S[1318] 1835 S[ 13 19 ]1836 S[1320] 1837 S[ 13 21 ]1838 S[1322] 1839 S[ 13 23 ]1840 S[1324] 1841 S[ 13 25 ]1842 S[1326] 1843 S[ 13 27 ]1844 S[1328] 1845 S[ 13 29 ]1846 S[1330] 1847 S[ 13 31 ]1848 S[1332] 1849 S[ 13 33 ]1850 S[1334] 1851 S[ 13 35 ]1852 S[1336] 1853 S[ 13 37 ]1854 S[1338] 1855 S[ 13 39 ]1856 S[1340] 1857 S[ 13 41 ]1858 S[1342] 1859 S[ 13 43 ]1860 S[1344] 1861 S[ 13 45 ]1862 S[1346] 1863 S[ 13 47 ]1864 S[1348] 1865 S[ 13 49 ]1866 S[1350] 1867 S[ 13 51 ]1868 S[1352] 1869 S[ 13 53 ]1870 S[1354] 1871 S[ 13 55 ]1872 S[1356] 1873 S[ 13 57 ]1874 S[1358] 1875 S[ 13 59 ]1876 S[1360] 1877 S[ 13 61 ]1878 S[1362] 1879 S[ 13 63 ]1880 S[1364] 1881 S[ 13 65 ]1882 S[1366] 1883 S[ 13 67 ]1884 S[1368] 1885 S[ 13 69 ]1886 S[1370] 1887 S[ 13 71 ]1888 S[1372] 1889 S[ 13 73 ]1890 S[1374] 1891 S[ 13 75 ]1892 S[1376] 1893 S[ 13 77 ]1894 S[1378] 1895 S[ 13 79 ]1896 S[1380] 1897 S[ 13 81 ]1898 S[1382] 1899 S[ 13 83 ]1900 S[1384] 1901 S[ 13 85 ]1902 S[1386] 1903 S[ 13 87 ]1904 S[1388] 1905 S[ 13 89 ]1906 S[1390] 1907 S[ 13 91 ]1908 S[1392] 1909 S[ 13 93 ]1910 S[1394] 1911 S[ 13 95 ]1912 S[1396] 1913 S[ 13 97 ]1914 S[1398] 1915 S[ 13 99 ]1916 S[1400] 1917 S[ 14 01 ]1918 S[1402] 1919 S[ 14 03 ]1920 S[1404] 1921 S[ 14 05 ]1922 S[1406] 1923 S[ 14 07 ]1924 S[1408] 1925 S[ 14 09 ]1926 S[1410] 1927 S[ 14 11 ]1928 S[1412] 1929 S[ 14 13 ]1930 S[1414] 1931 S[ 14 15 ]1932 S[1416] 1933 S[ 14 17 ]1934 S[1418] 1935 S[ 14 19 ]1936 S[1420] 1937 S[ 14 21 ]1938 S[1422] 1939 S[ 14 23 ]1940 S[1424] 1941 S[ 14 25 ]1942 S[1426] 1943 S[ 14 27 ]1944 S[1428] 1945 S[ 14 29 ]1946 S[1430] 1947 S[ 14 31 ]1948 S[1432] 1949 S[ 14 33 ]1950 S[1434] 1951 S[ 14 35 ]1952 S[1436] 1953 S[ 14 37 ]1954 S[1438] 1955 S[ 14 39 ]1956 S[1440] 1957 S[ 14 41 ]1958 DM Y _V S S 1959 DM Y_VS S 1960 GO UT _ V GL O 1961 GOUT _ V GL O1962 GO UT _ V GL O 1963 GOUT _ V GL O1964 GO UT _ V GL O 1965 GOUT _ V GL O1966 DM Y _V G H 1967 DM Y_VG H1968 GO UT _ V GHO 1969 GOUT _ V GHO1970 GO UT _ V GHO 1971 GOUT _ V GHO1972 GO UT _ V GHO 1973 GOUT _ V GHO1974 DM Y _V S S 1975 DM Y_VS S1976 DM Y 1977 DM Y1978 DM Y 1979 DM Y1980 DM Y 1981 DM Y1982 DM Y 1983 DM Y1984 DM Y 1985 DM Y1986 DM Y 1987 DM Y1988 DM Y 1989 DM Y1990 DM Y 1991 DM Y1992 DM Y 1993 DM Y1994 DM Y 1995 DM Y1996 DM Y 1997 DM Y1998 DM Y 1999 DM Y2000 DM Y 2001 DM Y2002 DM Y 2003 DM Y2004 DM Y 2005 DM Y2006 DM Y 2007 DM Y2008 DM Y 2009 DM Y2010 DM Y 2011 DM Y2012 DM Y 2013 DM Y2014 DM Y 2015 DM Y2016 DM Y _V S S 2017 DM Y_VS S2018 GO UT [ 1 7 ] 2019 GOUT [ 1 7 ]2020 GO UT [ 1 8 ] 2021 GOUT [ 1 8 ]2022 GO UT [ 1 9 ] 2023 GOUT [ 1 9 ]2024 GO UT [ 2 0 ] 2025 GOUT [ 2 0 ]2026 GO UT [ 2 1 ] 2027 GOUT [ 2 1 ]2028 GO UT [ 2 2 ] 2029 GOUT [ 2 2 ]2030 GO UT [ 2 3 ] 2031 GOUT [ 2 3 ]2032 GO UT [ 2 4 ] 2033 GOUT [ 2 4 ]2034 GO UT [ 2 5 ] 2035 GOUT [ 2 5 ]2036 GO UT [ 2 6 ] 2037 GOUT [ 2 6 ]2038 GO UT [ 2 7 ] 2039 GOUT [ 2 7 ]2040 GO UT [ 2 8 ] 2041 GOUT [ 2 8 ]2042 GO UT [ 2 9 ] 2043 GOUT [ 2 9 ]2044 GO UT [ 3 0 ] 2045 GOUT [ 3 0 ]2046 GO UT _ V GL O 2047 GOUT _ V GL O2048 GO UT _ V GL O 2049 VG H _REG2050 VG H _ RE G 2051 VG H _REG2052 LVG L 2053 LV G L2054 LVG L 2055 GOUT [ 3 1 ]2056 GO UT [ 3 1 ] 2057 GOUT [ 3 2 ]2058 GO UT [ 3 2 ] 2059 GOUT _ V GL O2060 GO UT _ V GL O 2061 GOUT _ V GL O2062 GO UT _ V GHO 2063 GOUT _ V GHO2064 GO UT _ V GHO 2065 PA DA 42066 PADB4 2067 DM Y_VS S2068 DM Y _V S S

2069 DM Y_VS S

-320 -220 -120 -20 180 280 380 -12000 -11000 -10000 -9000 -8000 -7000 -6000 -5000 -4000 -3000 -2000 -100001 0 0 0 2 0 0 0 3 0 0 0 4 0 0 0 5 0 0 0 6 0 0 0 7 0 0 0 8 0 0 0 9 0 0 0 1 0 0 0 0 1 1 0 0 0 1 2 0 0 0 Figure 122 Reference Circuit

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 326 of 328 15.2. ILI4002/ILI4003 Application Circuit Figure 123 ILI4002/ILI4003 Reference Circuit Table 52 ILI4002/ILI4003 External Component Cap. Value CL1 1uF (Min 10V) CL2 1uF (Min 10V) C1 1uF (Min 10V) C2 1uF (Min 10V) C3 1uF (Min 10V)

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 327 of 328 15.3. External Component The Table 53 shows specifications of external elements connected to the power supply circuit of ILI9806E. Table 53 External Component table Pad Name Connection Typical Value IOVCC Stable Capacitor to GND 1.0 µF (Min 4.0V) VCI, VCIP, VCIR Stable Capacitor to GND 1.0 µF (Min 6.3V) VCORE Stable Capacitor to GND 2.2 µF (Min 4.0V) VCORE_MIPI Stable Capacitor to GND 1.0 µF (Min 4.0V) V12_MIPI Stable Capacitor to GND 1.0 µF (Min 4.0V) C11P, C11N Flying Capacitor 1.0 µF (Min 6.3V) C12P, C12N Flying Capacitor 1.0 µF (Min 6.3V) C13P, C13N Flying Capacitor 1.0 µF (Min 6.3V) C14P, C14N Flying Capacitor 1.0 µF (Min 6.3V) C21P, C21N Flying Capacitor 1.0 µF (Min 6.3V) C22P, C22N Flying Capacitor 1.0 µF (Min 6.3V) C23P, C23N Flying Capacitor 1.0 µF (Min 6.3V) C24P, C24N Flying Capacitor 1.0 µF (Min 6.3V) C31P, C31N Flying Capacitor 1.0 µF (Min 6.3V) C32P, C32N Flying Capacitor 1.0 µF (Min 6.3V) C41P, C41N Flying Capacitor 1.0 µF (Min 16V) C51P, C51N Flying Capacitor 1.0 µF (Min 16V) DDVDH Stable Capacitor to GND 2.2 µF (Min 10V) DDVDL Stable Capacitor to GND 2.2 µF (Min 10V) VCL Stable Capacitor to GND 2.2 µF (Min 6.3V) VGH Stable Capacitor to GND 1.0 µF (Min 25V) VGL Stable Capacitor to GND, VGLX=VGL 1.0 µF (Min 25V) Schottky Diode to GND VF < 0.52V @ 1A, VR > 40V (Option) VGL_REG Stable Capacitor to GND 1.0 µF (Min 25V) VGH_REG Stable Capacitor to GND 1.0 µF (Min 25V) VCOM Stable Capacitor to GND 2.2 µF (Min 4.0V) VREF15 Stable Capacitor to GND 1.0 µF (Min 4.0V)

a-Si TFT LCD Single Chip Driver 480(RGB)x864 Resolution and 16.7M-color ILI9806E The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 328 of 328 16. Revision History Version No. Date Page Description V090 2013/06/28 All New created. V091 2013/07/09 221 Modify the TOUCH_OPT[1:0] Table

310 Remove the Diode option of DDVDH

177 Modify the description of P0_RFEh register

184 Modify the default value (P1_R21h=01h)

199 Modify the default value (P1_R41h=22h)

219 Modify the default value (P1_R57h=20h)

220 Modify the default value (P1_R58h=90h)

259 Add the restriction of LABC_SRE_THR function

137 & 260 Add the SRE Control register 137 & 261 Add the ALS function register 138~139 & 264~265 Add the GIP Setting register 139 & 266 Add the GOUT_VGLO control register 139 & 267 Add the GOUT_VGHO control register 140 & 268 Add the VCL control register 140 & 269 Add the VGL_REG enable register 140 & 270 Add the VREG1OUT and VREG2OUT enable register

271 Modify the Figure 95

284 Add the description of internal programming in Note2

V093 2013/08/26 17 & 193 Remove the 1/3/4 dot Inversion function V094 2013/09/12 1. Modify description “Fix to IOVCC or DGND level when not in use” for the CSX & SCL & SDI(SDA) input pin 2. Modify description “Fix to IOVCC , DGND or Floating level when not in use” for the DB[23:0] input pin 29 Modify the Output PAD of 2.5. Bump Arrangement

50 Table 10, CLOCK_P modify to Control mode, CLOCK_N modify to Escape

141~176 Add the description at Restriction

219 Modify the values of VDET set

257 Modify the value of DIM_MOV/STILL[2:0] table

258 Modify the value of DIM_UI[2:0] table

264 Add the description of F_TIME_OPT function

267 Add the register of P6_R52h

268 Modify the register name

270 Add the register of P7_R02h

280 Remove the 8.2. Gamma Default Values(for NW type LC)

309 Modify the SLP-IN current for DPI+SPI I/F, and add the SLP-IN current for MIPI

310 Modify the table of Line DC Voltage Levels

48 1. Modify the Max. value of DCLK , 41.7MHz modify to 35.7MHz 2. Modify the ”Note1. HLW+HBP+HFP >= 4.5us”

274 Add the TIME CONTROL(Page7_RE1h) register

324 Modify the Figure 122 and add the ITO resistance of input pad

V096 2014/01/15 231 Modify the Program / Read address table V097 2014/03/24 311 Modify the Max. & Min. current for Sleep-In & Deep Standby