ILI9325

ILI9325 ETC2 | Alldatasheet

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a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color Datasheet Version: V0.43 Document No.: ILI9325DS_V0.43.pdf ILI TECHNOLOGY CORP. 4F, No. 2, Tech. 5th Rd., Hsinchu Science Park, Taiwan 300, R.O.C. Tel.886-3-5670095; Fax.886-3-5670096 http://www.ilitek.com

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9325 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 2 of 107 Version: 0.43 Table of Contents S e c t i o n P a g e

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9325 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 3 of 107 Version: 0.43

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9325 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 4 of 107 Version: 0.43

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9325 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 7 of 107 Version: 0.43 1. Introduction ILI9325 is a 262,144-color one-chip SoC driver for a-TFT liquid crystal display with resolution of 240RGBx320 dots, comprising a 720-channel source driver, a 320-channel gate driver, 172,800 bytes RAM for graphic data of 240RGBx320 dots, and power supply circuit. ILI9325 has four kinds of system interfaces which are i80-system MPU interface (8-/9-/16-/18-bit bus width), VSYNC interface (system interface + VSYNC, internal clock, DB[17:0]), serial data transfer interface (SPI) and RGB 6-/16-/18-bit interface (DOTCLK, VSYNC, HSYNC, ENABLE, DB[17:0]). In RGB interface and VSYNC interface mode, the combined use of high-speed RAM write function and widow address function enables to display a moving picture at a position specified by a user and still pictures in other areas on the screen simultaneously, which makes it possible to transfer display the refresh data only to minimize data transfers and power consumption. ILI9325 can operate with 1.65V I/O interface voltage, and an incorporated voltage follower circuit to generate voltage levels for driving an LCD. The ILI9325 also supports a function to display in 8 colors and a sleep mode, allowing for precise power control by software and these features make the ILI9325 an ideal LCD driver for medium or small size portable products such as digital cellular phones, smart phone, PDA and PMP where long battery life is a major concern. 2. Features ‹ Single chip solution for a liquid crystal QVGA TFT LCD display ‹ 240RGBx320-dot resolution capable with real 262,144 display color ‹ Support MVA (Multi-domain Vertical Alignment) wide view display ‹ Incorporate 720-channel source driver and 320-channel gate driver ‹ Internal 172,800 bytes graphic RAM ‹ High-speed RAM burst write function ‹ System interfaces ¾ i80 system interface with 8-/ 9-/16-/18-bit bus width ¾ Serial Peripheral Interface (SPI) ¾ RGB interface with 6-/16-/18-bit bus width (VSYNC, HSYNC, DOTCLK, ENABLE, DB[17:0]) ¾ VSYNC interface (System interface + VSYNC) ‹ Internal oscillator and hardware reset ‹ Resizing function (×1/2, ×1/4) ‹ Reversible source/gate driver shift direction ‹ Window address function to specify a rectangular area for internal GRAM access ‹ Abundant functions for color display control ¾ γ-correction function enabling display in 262,144 colors ¾ Line-unit vertical scrolling function

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9325 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 8 of 107 Version: 0.43 ‹ Partial drive function, enabling partially driving an LCD panel at positions specified by user ‹ Incorporate step-up circuits for stepping up a liquid crystal drive voltage level up to 6 times (x6) ‹ Power saving functions ¾ 8-color mode ¾ standby mode ¾ sleep mode ‹ Low -power consumption architecture ¾ Low operating power supplies: ƒ IOVcc = 1.65V ~ 3.3 V (interface I/O) ƒ Vci = 2.5V ~ 3.3 V (analog) ‹ LCD Voltage drive: ¾ Source/VCOM power supply voltage ƒ DDVDH - GND = 4.5V ~ 6.0 ƒ VCL – GND = -2.0V ~ -3.0V ƒ VCI – VCL ≦ 6.0V ¾ Gate driver output voltage ƒ VGH - GND = 10V ~ 20V ƒ VGL – GND = -5V ~ -15V ƒ VGH – VGL ≦ 32V ¾ VCOM driver output voltage ƒ VCOMH = 3.0V ~ (DDVDH-0.2)V ƒ VCOML = (VCL+0.5)V ~ 0V ƒ VCOMH-VCOML ≦ 6.0V ‹ a-TFT LCD storage capacitor: Cst only

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9325 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 9 of 107 Version: 0.43 3. Block Diagram MPU I/F 18-bit 16-bit 9-bit 8-bit SPI I/F RGB I/F 18-bit 16-bit 6-bit VSYNC I/F nCS nWR/SCL nRD RS DB[17:0] SDI SDO VSYNC HSYNC TEST1 DOTCLK nRESET IM[3:0] TEST2 TS[8:0] IOVCC Regulator VCC GND RC-OSC. Timing Controller Charge-pump Power Circuit VREG1OUT C11+ VCI C11- DDVDH C12+ C12- VCL C22+ C22- VGH VGL VCOM Generator VCOM VCOMH VCOML Index Register (IR) Control Register (CR) Graphics Operation Read Latch Write Latch Graphics RAM (GRAM) 7272 Address Counter (AC) LCD Source Driver Grayscale Reference Voltage V63 ~ 0 S[720:1] LCD Gate Driver G[320:1] VGS VCI1 GND VDDD C13+ C13- C21+ C21- ENABLE TEST3 DUMMY1~15 DUMMY20~27

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9325 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 10 of 107 Version: 0.43 4. Pin Descriptions Pin Name I/O Type Descriptions Input Interface IM3, IM2, IM1, IM0/ID I IOVcc Select the MPU system interface mode IM3 IM2 IM1 IM0 MPU-Interface Mode DB Pin in use 0 0 0 0 Setting invalid 0 0 0 1 Setting invalid 0 0 1 0 i80-system 16-bit interface DB[17:10], DB[8:1] 0 0 1 1 i80-system 8-bit interface DB[17:10] 0 1 0 ID Serial Peripheral Interface (SPI) SDI, SDO 0 1 1 * Setting invalid 1 0 0 0 Setting invalid 1 0 0 1 Setting invalid 1 0 1 0 i80-system 18-bit interface DB[17:0] 1 0 1 1 i80-system 9-bit interface DB[17:9] 1 1 * * Setting invalid When the serial peripheral interface is selected, IM0 pin is used for the device code ID setting. nCS I MPU IOVcc A chip select signal. Low: the ILI9325 is selected and accessible High: the ILI9325 is not selected and not accessible Fix to the GND level when not in use. RS I MPU IOVcc A register select signal. Low: select an index or status register High: select a control register Fix to either IOVcc or GND level when not in use. nWR/SCL I MPU IOVcc A write strobe signal and enables an operation to write data when the signal is low. Fix to either IOVcc or GND level when not in use. SPI Mode: Synchronizing clock signal in SPI mode. nRD I MPU IOVcc A read strobe signal and enables an operation to read out data when the signal is low. Fix to either IOVcc or GND level when not in use. nRESET I MPU IOVcc A reset pin. Initializes the ILI9325 with a low input. Be sure to execute a power-on reset after supplying power. SDI I MPU IOVcc SPI interface input pin. The data is latched on the rising edge of the SCL signal. SDO O MPU IOVcc SPI interface output pin. The data is outputted on the falling edge of the SCL signal. Let SDO as floating when not used. DB[17:0] I/O MPU IOVcc An 18-bit parallel bi-directional data bus for MPU system interface mode 8-bit I/F: DB[17:10] is used. 9-bit I/F: DB[17:9] is used. 16-bit I/F: DB[17:10] and DB[8:1] is used. 18-bit I/F: DB[17:0] is used. 18-bit parallel bi-directional data bus for RGB interface operation 6-bit RGB I/F: DB[17:12] are used.

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9325 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 11 of 107 Version: 0.43 Pin Name I/O Type Descriptions 16-bit RGB I/F: DB[17:13] and DB[11:1] are used. 18-bit RGB I/F: DB[17:0] are used. Unused pins must be fixed to GND level. ENABLE I MPU IOVcc Data ENEABLE signal for RGB interface operation. Low: Select (access enabled) High: Not select (access inhibited) The EPL bit inverts the polarity of the ENABLE signal. Fix to either IOVcc or GND level when not in use. DOTCLK I MPU IOVcc Dot clock signal for RGB interface operation. DPL = “0”: Input data on the rising edge of DOTCLK DPL = “1”: Input data on the falling edge of DOTCLK Fix to the GND level when not in use VSYNC I MPU IOVcc Frame synchronizing signal for RGB interface operation. VSPL = “0”: Active low. VSPL = “1”: Active high. Fix to the GND level when not in use. HSYNC I MPU IOVcc Line synchronizing signal for RGB interface operation. HSPL = “0”: Active low. HSPL = “1”: Active high. Fix to the GND level when not in use FMARK O MPU IOVcc Output a frame head pulse signal. The FMARK signal is used when writing RAM data in synchronization with frame. Leave the pin open when not in use. LCD Driving signals S720~S1 O LCD Source output voltage signals applied to liquid crystal. To change the shift direction of signal outputs, use the SS bit. SS = “0”, the data in the RAM address “h00000” is output from S1. SS = “1”, the data in the RAM address “h00000” is output from S720. S1, S4, S7, … display red (R), S2, S5, S8, ... display green (G), and S3, S6, S9, ... display blue (B) (SS = 0). G320~G1 O LCD Gate line output signals. VGH: the level selecting gate lines VGL: the level not selecting gate lines VCOM O TFT common electrode A supply voltage to the common electrode of TFT panel. VCOM is AC voltage alternating signal between the VCOMH and VCOML levels. VCOMH O Stabilizing capacitor The high level of VCOM AC voltage. Connect to a stabilizing capacitor. VCOML O Stabilizing capacitor The low level of VCOM AC voltage. Adjust the VCOML level with the VDV bits. Connect to a stabilizing capacitor. VGS I GND or external resistor Reference level for the grayscale voltage generating circuit. The VGS level can be changed by connecting to an external resistor. Charge-pump and Regulator Circuit Vci I Power supply A supply voltage to the analog circuit. Connect to an external power supply of 2.5 ~ 3.3V. GND I Power supply GND for the analog side: GND = 0V. In case of COG, connect to GND on the FPC to prevent noise. Vci1 O Stabilizing capacitor An internal reference voltage for the step-up circuit1. The amplitude between Vci and GND is determined by the VC[2:0] bits. Make sure to set the Vci1 voltage so that the DDVDH, VGH and VGL voltages are set within the respective specification. DDVDH O Stabilizing Power supply for the source driver and Vcom drive.

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9325 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 12 of 107 Version: 0.43 Pin Name I/O Type Descriptions capacitor VGH O Stabilizing capacitor Power supply for the gate driver. VGL O Stabilizing capacitor Power supply for the gate driver. VCL O Stabilizing capacitor VcomL driver power supply. VCL = 0.5 ~ –VCI . Place a stabilizing capacitor between GND C11+, C11- C12+, C12- I/O Step-up capacitor Capacitor connection pins for the step-up circuit 1. C13+, C13- C21+, C21- C22+, C22- I/O Step-up capacitor Capacitor connection pins for the step-up circuit 2. VREG1OUT I/O Stabilizing capacitor Output voltage generated from the reference voltage. The voltage level is set with the VRH bits. VREG1OUT is (1) a source driver grayscale reference voltage, (2) VcomH level reference voltage, and (3) Vcom amplitude reference voltage. Connect to a stabilizing capacitor. VREG1OUT = 3.0 ~ (DDVDH – 0.2)V. Power Pads IOVcc I Power supply A supply voltage to the interface pins: IM[3:0], nRESET, nCS, nWR, nRD, RS, DB[17:0], VSYNC, HSYNC, DOTCLK, ENABLE, SCL, SDI, SDO. IOVcc = 1.65 ~ 3.3V and Vcc ≧ IOVcc. In case of COG, connect to Vcc on the FPC if IOVcc=Vcc, to prevent noise. VDDD O Power Digital circuit power pad. Connect these pins with the 1uF capacitor. GND I Power supply GND = 0V. Test Pads DUMMY1~ 15 DUMMY20 ~ 27 - - Dummy pad. Leave these pins as open. IOGNDDUM O GND GND pin. TESTO1~16 O Open Test pins. Leave them open. TEST1, 2, 3 I IOGND Test pins (internal pull low). Connect to GND or leave these pins as open. TS0~8 I OPEN Test pins (internal pull low). Leave them open. Liquid crystal power supply specifications Table 1 No. Item Description

1 TFT Source Driver 720 pins (240 x RGB)

2 TFT Gate Driver 320 pins

3 TFT Display’s Capacitor Structure Cst structure only (Common VCOM)

S1 ~ S720 V0 ~ V63 grayscales G1 ~ G320 VGH - VGL 4 Liquid Crystal Drive Output VCOM VCOMH - VCOML: Amplitude = electronic volumes IOVcc 1.65 ~ 3.30V 5 Input Voltage Vci 2.50 ~ 3.30V

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9325 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 13 of 107 Version: 0.43 DDVDH 4.5V ~ 6.0V VGH 10V ~ 20V VGL -5V ~ -15V VCL -2.0V ~ -3.0V VGH - VGL Max. 32V

6 Liquid Crystal Drive

Vci - VCL Max. 6.0V DDVDH Vci1 x2 VGH Vci1 x4, x5, x6 VGL Vci1 x-3, x-4, x-5 7 Internal Step-up Circuits VCL Vci1 x-1

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9325 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 14 of 107 Version: 0.43 4.1. Pad Arrangement and Coordination 15 20 15 152015 Alignment Marks Chip Size: 17820um x 870um Chip thickness : 280um or 400um (typ.) Pad Location: Pad Center. Coordinate Origin: Chip center Au bump height: 15um (typ.) Au Bump Size: 1. 16um x 98um Gate: G1 ~ G320 Source: S1 ~ S720 2. 50um x 80um I nput Pads Pad 1 to 243. Bump View Alignment Mark: A1 15 20 15 152015 Alignment Mark: A2 Face Up (Bump View) DUMMY23 S361 S362 S363 S364 S365 S366 S367 S368 S369 x y S353 S354 S355 S356 S357 S358 S359 S360 DUMMY24 G304 G306 G308 G310 G312 G314 G316 G318 G320 DUMMY20 DUMMY21 G10 G12 G14 G16 G18 S712 S713 S714 S715 S716 S717 S718 S719 S720 DUMMY22 ………… DUMMY27 G319 G317 G315 G313 G311 G309 G307 G305 G303 G17 G15 G13 G11 DUMMY26 DUMMY25 DUMMY1 TEST1 IOGNDDUM TESTO1 TESTO2 TESTO3 IM0/ID IM1 IM2 IM3 TEST2 TESTO4 TESTO5 TESTO6 TESTO7 TESTO8 TESTO9 TESTO10 nRESET nRESET VSYNC HSYNC DOTCLK ENABLE DB17 DB16 DB15 DB14 DB13 TESTO11 DB12 DB11 DB10 DB9 DB8 TEST3 TESTO12 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 TESTO13 SDO SDI nRD nWR/SCL RS nCS TESTO14 TESTO15 FMARK TESTO16 TS8 TS7 TS6 TS5 TS4 TS3 TS2 TS1 TS0 DUMMY 2 IOVCC IOVCC IOVCC IOVCC IOVCC IOVCC VDD D VDD D VDD D VDD D VDD D VDD D VDD D VDD D VDD D VDD D VDD D DUMMY 3 GND GND GND GND GND GND GND GND VGS VGS GND GND GND GND GND GND GND GND GND GND DUMMY 4 DUMMY 5 DUMMY 6 VCOM VCOM VCOM VCOM VCOM VCOM VCOM VCOMH VCOMH VCOMH VCOMH VCOMH VCOMH VCOML VCOML VCOML VCOML VREG1OUT VREG1OUT VREG1OUT DUMMY 7 DUMMY 8 DUMMY 9 VCL VCL VCL VCL VCL DDVDH DDVDH DDVDH DDVDH DDVDH DDVDH VCI1 VCI1 VCI1 VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI DUMMY1 0 DUMMY1 1 C12 - C12 - C12 - C12 - C12 - C12 + C12 + C12 + C12 + C12 + C11 - C11 - C11 - C11 - C11 - C11 + C11 + C11 + C11 + C11 + VGL VGL VGL VGL VGL VGL VGL VGL VGL VGL GND GND GND VGH VGH VGH VGH VGH VGH DUMMY1 2 DUMMY1 3 C13 - C13 - C13 - C13 - C13 + C22 - C22 - C22 - C22 - C22 + C22 + C22 + C22 + C22 + C22 + C13 + C13 + C13 + C21 - C21 - C21 - C21 - C21 - C21 - C21 - C21 + C21 + C21 + C21 + C21 + C21 + C21 + C22 - C22 - C22 - C22 + DUMMY1 4 DUMMY1 5

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9325 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 15 of 107 Version: 0.43

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9325 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 16 of 107 Version: 0.43

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9325 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 17 of 107 Version: 0.43

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9325 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 18 of 107 Version: 0.43

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9325 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 19 of 107 Version: 0.43 No. Name X Y No. Name X Y 1201 G141 -7219 202.5 1261 G261 -8179 202.5 1202 G143 -7235 319.5 1262 G263 -8195 319.5 1203 G145 -7251 202.5 1263 G265 -8211 202.5 1204 G147 -7267 319.5 1264 G267 -8227 319.5 1205 G149 -7283 202.5 1265 G269 -8243 202.5 1206 G151 -7299 319.5 1266 G271 -8259 319.5 1207 G153 -7315 202.5 1267 G273 -8275 202.5 1208 G155 -7331 319.5 1268 G275 -8291 319.5 1209 G157 -7347 202.5 1269 G277 -8307 202.5 1210 G159 -7363 319.5 1270 G279 -8323 319.5 1211 G161 -7379 202.5 1271 G281 -8339 202.5 1212 G163 -7395 319.5 1272 G283 -8355 319.5 1213 G165 -7411 202.5 1273 G285 -8371 202.5 1214 G167 -7427 319.5 1274 G287 -8387 319.5 1215 G169 -7443 202.5 1275 G289 -8403 202.5 1216 G171 -7459 319.5 1276 G291 -8419 319.5 1217 G173 -7475 202.5 1277 G293 -8435 202.5 1218 G175 -7491 319.5 1278 G295 -8451 319.5 1219 G177 -7507 202.5 1279 G297 -8467 202.5 1220 G179 -7523 319.5 1280 G299 -8483 319.5 1221 G181 -7539 202.5 1281 G301 -8499 202.5 1222 G183 -7555 319.5 1282 G303 -8515 319.5 1223 G185 -7571 202.5 1283 G305 -8531 202.5 1224 G187 -7587 319.5 1284 G307 -8547 319.5 1225 G189 -7603 202.5 1285 G309 -8563 202.5 1226 G191 -7619 319.5 1286 G311 -8579 319.5 1227 G193 -7635 202.5 1287 G313 -8595 202.5 1228 G195 -7651 319.5 1288 G315 -8611 319.5 1229 G197 -7667 202.5 1289 G317 -8627 202.5 1230 G199 -7683 319.5 1290 G319 -8643 319.5 1231 G201 -7699 202.5 1291 DUMMY27 -8659 202.5 1232 G203 -7715 319.5 Alignment mark X Y 1233 G205 -7731 202.5 1-a -8751 269 1234 G207 -7747 319.5 1-b 8751 269 1235 G209 -7763 202.5 1236 G211 -7779 319.5 1237 G213 -7795 202.5 1238 G215 -7811 319.5 1239 G217 -7827 202.5 1240 G219 -7843 319.5 1241 G221 -7859 202.5 1242 G223 -7875 319.5 1243 G225 -7891 202.5 1244 G227 -7907 319.5 1245 G229 -7923 202.5 1246 G231 -7939 319.5 1247 G233 -7955 202.5 1248 G235 -7971 319.5 1249 G237 -7987 202.5 1250 G239 -8003 319.5 1251 G241 -8019 202.5 1252 G243 -8035 319.5 1253 G245 -8051 202.5 1254 G247 -8067 319.5 1255 G249 -8083 202.5 1256 G251 -8099 319.5 1257 G253 -8115 202.5 1258 G255 -8131 319.5 1259 G257 -8147 202.5 1260 G259 -8163 319.5

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9325 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 20 of 107 Version: 0.43 S1 ~ S720 G1 ~ G320 DUMMY20~27 (No. 244 ~ 1291) 16 16 981998 Unit: um I/O Pads (No. 1 ~ 243) Pad Pump 50 x Pad Pump y X=20, 30, 35 Y=70, 80, 85 Unit: um

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9325 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 21 of 107 Version: 0.43 5. Block Description MPU System Interface ILI9325 supports three system high-speed interfaces: i80-system high-speed interfaces to 8-, 9-, 16-, 18-bit parallel ports and serial peripheral interface (SPI). The interface mode is selected by setting the IM[3:0] pins. ILI9325 has a 16-bit index register (IR), an 18-bit write-data register (WDR), and an 18-bit read-data register (RDR). The IR is the register to store index information from control registers and the internal GRAM. The WDR is the register to temporarily store data to be written to control registers and the internal GRAM. The RDR is the register to temporarily store data read from the GRAM. Data from the MPU to be written to the internal GRAM are first written to the WDR and then automatically written to the internal GRAM in internal operation. Data are read via the RDR from the internal GRAM. Therefore, invalid data are read out to the data bus when the ILI9325 read the first data from the internal GRAM. Valid data are read out after the ILI9325 performs the second read operation. Registers are written consecutively as the register execution time. Registers selection by system interface (8-/9-/16-/18-bit bus width) I80 Function RS nWR nRD Write an index to IR register 0 0 1 Read an internal status 0 1 0 Write to control registers or the internal GRAM by WDR register. 1 0 1 Read from the internal GRAM by RDR register. 1 1 0 Registers selection by the SPI system interface Function R/W RS Write an index to IR register 0 0 Read an internal status 1 0 Write to control registers or the internal GRAM by WDR register. 0 1 Read from the internal GRAM by RDR register. 1 1 Parallel RGB Interface ILI9325 supports the RGB interface and the VSYNC interface as the external interface for displaying a moving picture. When the RGB interface is selected, display operations are synchronized with externally supplied signals, VSYNC, HSYNC, and DOTCLK. In RGB interface mode, data (DB17-0) are written in synchronization with these signals according to the polarity of enable signal (ENABLE) to prevent flicker on display while updating display data. In VSYNC interface mode, the display operation is synchronized with the internal clock except frame synchronization, where the operation is synchronized with the VSYNC signal. Display data are written to the internal GRAM via the system interface. In this case, there are constraints in speed and method in writing data to the internal RAM. For details, see the “External Display Interface” section. The ILI9325 allows for switching between the external display interface and the system interface by instruction so that the optimum interface is selected for the kind of picture to be displayed on the screen (still and/or moving picture(s)). The RGB

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9325 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 22 of 107 Version: 0.43 interface, by writing all display data to the internal RAM, allows for transferring data only when updating the frames of a moving picture, contributing to low power requirement for moving picture display. Address Counter (AC) The address counter (AC) gives an address to the internal GRAM. When the index of the register for setting a RAM address in the AC is written to the IR, the address information is sent from the IR to the AC. As writing data to the internal GRAM, the address in the AC is automatically updated plus or minus 1. The window address function enables writing data only in the rectangular area arbitrarily set by users on the GRAM. Graphics RAM (GRAM) GRAM is graphics RAM storing bit-pattern data of 172,820 (240 x 320x 18/8) bytes with 18 bits per pixel. Grayscale Voltage Generating Circuit The grayscale voltage generating circuit generates a liquid crystal drive voltage according to grayscale data set in the γ-correction register to display in 262,144 colors. For details, see the “ γ-Correction Register” section. Timing Controller The timing generator generates a timing signal for operation of internal circuits such as the internal GRAM. The timing for the display operation such as RAM read operation and the timing for the internal operation such as access from the MPU are generated in the way not to interfere each other. Oscillator (OSC) ILI9325 generates RC oscillation with an internal oscillation resistor. The frame rate is adjusted by the register setting. LCD Driver Circuit The LCD driver circuit of ILI9325 consists of a 720-output source driver (S1 ~ S720) and a 320-output gate driver (G1~G320). Display pattern data are latched when the 720 th bit data are input. The latched data control the source driver and generate a drive waveform. The gate driver for scanning gate lines outputs either VGH or VGL level. The shift direction of 720 source outputs from the source driver is set with the SS bit and the shift direction of gate outputs from the gate driver is set with the GS bit. The scan mode by the gate driver is set with the SM bit. These bits allow setting an appropriate scan method for an LCD module. LCD Driver Power Supply Circuit The LCD drive power supply circuit generates the voltage levels VREG1OUT, VGH, VGL and Vcom for driving an LCD.

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9325 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 23 of 107 Version: 0.43 6. System Interface 6.1. Interface Specifications ILI9325 has the system interface to read/write the control registers and display graphics memory (GRAM), and the RGB Input Interface for displaying a moving picture. User can select an optimum interface to display the moving or still picture with efficient data transfer. All display data are stored in the GRAM to reduce the data transfer efforts and only the updating data is necessary to be transferred. User can only update a sub-range of GRAM by using the window address function. ILI9325 also has the RGB interface and VSYNC interface to transfer the display data without flicker the moving picture on the screen. In RGB interface mode, the display data is written into the GRAM through the control signals of ENABLE, VSYNC, HSYNC, DOTCLK and data bus DB[17:0]. In VSYNC interface mode, the internal display timing is synchronized with the frame synchronization signal (VSYNC). The VSYNC interface mode enables to display the moving picture display through the system interface. In this case, there are some constraints of speed and method to write data to the internal RAM. ILI9325 operates in one of the following 4 modes. The display mode can be switched by the control register. When switching from one mode to another, refer to the sequences mentioned in the sections of RGB and VSYNC interfaces. Operation Mode RAM Access Setting (RM) Display Operation Mode (DM[1:0]) Internal operating clock only (Displaying still pictures) System interface (RM = 0) Internal operating clock (DM[1:0] = 00) RGB interface (1) (Displaying moving pictures) RGB interface (RM = 1) RGB interface (DM[1:0] = 01) RGB interface (2) (Rewriting still pictures while displaying moving pictures) System interface (RM = 0) RGB interface (DM[1:0] = 01) VSYNC interface (Displaying moving pictures) System interface (RM = 0) VSYNC interface (DM[1:0] = 01) Note 1) Registers are set only via the system interface. Note 2) The RGB-I/F and the VSYNC-I/F are not available simultaneously.

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9325 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 24 of 107 Version: 0.43 System Interface RGB Interface ILI9325 nCS RS nWR nRD DB[17:0] ENABLE VSYNC HSYNC DOTCLK 18/16/6 System Figure1 System Interface and RGB Interface connection 6.2. Input Interfaces The following are the system interfaces available with the ILI9325. The interface is selected by setting the IM[3:0] pins. The system interface is used for setting registers and GRAM access. IM3 IM2 IM1 IM0/ID Interface Mode DB Pin 0 0 0 0 Setting invalid 0 0 0 1 Setting invalid 0 0 1 0 i80-system 16-bit interface DB[17:10], DB[8:1] 0 0 1 1 i80-system 8-bi t interface DB[17:10] 0 1 0 ID Serial Peripheral Interface (SPI) SDI, SDO 0 1 1 * Setting invalid 1 0 0 0 Setting invalid 1 0 0 1 Setting invalid 1 0 1 0 i80-system18-bi t interface DB[17:0] 1 0 1 1 i80-system 9-bi t interface DB[17:9] 1 1 * * Setting invalid

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9325 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 25 of 107 Version: 0.43 6.2.1. i80/18-bit System Interface The i80/18-bit system interface is selected by setting the IM[3:0] as “1010” levels. DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB 18-bit System Interf ace (262K colors) TRI=0, DFM[1:0]=00 Input Data Write Data Regi ster R5 R4 R3 R2 R1 R0 G5 G4 G2 G1 G0 B5 B4 B3 B2 B1G3GRAM Data & RGB Mapping B0 WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD nCS RS nWR nRD DB[17:0]18 System nCS nWR nRD D[31:0] Figure2 18-bit System Interface Data Format

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9325 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 26 of 107 Version: 0.43 6.2.2. i80/16-bit System Interface The i80/16-bit system interface is selected by setting the IM[3:0] as “0010” levels. The 262K or 65K color can be display through the 16-bit MPU interface. When the 262K color is displayed, two transfers (1st transfer: 2 bits, 2nd transfer: 16 bits or 1st transfer: 16 bits, 2nd transfer: 2 bits) are necessary for the 16-bit CPU interface. TRI DFM 16-bit MPU System Interface Data Format R4R5 R2R3 R0R1 G4G5 G2G3 G0G1 B4B5 B2B3 B0B1 0 * system 16-bit interface (1 transfers/pixel) 65,536 colors R4R5 R2R3 R0R1 G4G5 G2G3 G0G1 B4B5 B2B3 B0B1 1 0 80-system 16-bit interface (2 transfers/pixel) 262,144 colors R4R5 R2R3 R0R1 G4G5 G2G3 G0G1 B4B5 B2B3 B0B1 1 1 80-system 16-bit interface (2 transfers/pixel) 262,144 colors DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB 1st Transfer DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB 1st Transf er DB DB 2nd Transf er DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB 2nd Transfer1st Transfer DB DB Figure3 16-bit System Interface Data Format

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9325 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 27 of 107 Version: 0.43 6.2.3. i80/9-bit System Interface The i80/9-bit system interface is selected by setting the IM[3:0] as “1011” and the DB17~DB9 pins are used to transfer the data. When writing the 16-bit register, the data is divided into upper byte (8 bits and LSB is not used) lower byte and the upper byte is transferred first. The display data is also divided in upper byte (9 bits) and lower byte, and the upper byte is transferred first. The unused DB[8:0] pins must be tied to GND. nCS RS nWR nRD DB[17:9]9 System nCS nWR nRD D[8:0] 1st Transfer (Upper bi ts) DB DB DB DB DB DB DB DB DB 9-bit System I nterface (262K colors) TRI =0, DFM[ 1:0]=00 Input Data Write Data Regi ster R5 R4 R3 R2 R1 R0 G5 G4 G2 G1 G0 B5 B4 B3 B2 B1G3GRA M Data & RGB Mapping B0 WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD DB DB DB DB DB DB DB DB DB 2nd Transf er (Lower bits) Figure4 9-bit System Interface Data Format 6.2.4. i80/8-bit System Interface The i80/8-bit system interface is selected by setting the IM[3:0] as “0011” and the DB17~DB10 pins are used to transfer the data. When writing the 16-bit register, the data is divided into upper byte (8 bits and LSB is not used) lower byte and the upper byte is transferred first. The display data is also divided in upper byte (8 bits) and lower byte, and the upper byte is transferred first. The written data is expanded into 18 bits internally (see the figure below) and then written into GRAM. The unused DB[9:0] pins must be tied to GND.

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9325 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 28 of 107 Version: 0.43 TRI DFM 8-bi t M PU System I nterf ace Data Format DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB R4R5 R2R3 R0R1 G4G5 G2G3 G0G1 B4B5 B2B3 B0B1 1st Transf er 2nd Transfer 0 * system 8-bit interface (2 transfers/pixel) 65,536 colors DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB R4R5 R2R3 R0R1 G4G5 G2G3 G0G1 B4B5 B2B3 B0B1 2nd Transf er 3rd Transfer 1 0 80-system 8-bit interface (3 transfers/pixel) 262,144 colors DB DB 1st Transf er R4R5 R2R3 R0R1 G4G5 G2G3 G0G1 B4B5 B2B3 B0B1 1 1 80-system 8-bit interface (3 transfers/pixel) 262,144 colors DB DB DB DB DB DB DB DB DB DB DB DB 2nd Transfer 3rd Transf er1st Transf er DB DB DB DB DB DB Figure5 8-bit System Interface Data Format Data transfer synchronization in 8/9-bit bus interface mode ILI9325 supports a data transfer synchronization function to reset upper and lower counters which count the transfers numbers of upper and lower byte in 8/9-bit interface mode. If a mismatch arises in the numbers of transfers between the upper and lower byte counters due to noise and so on, the “00”h register is written 4 times consecutively to reset the upper and lower counters so that data tran sfer will restart wi th a transfer of upper byte. This synchronization function can effectively prevent display error if the upper/lower counters are periodically reset. “00＂hUpper/ Lowe r “00＂h“ 00＂h“ 00＂hU p p e r Lowe rDB[ 17:9] RS RD nWR 8-/9-bit transfe r synchroni zati on Figure6 Data Transfer Synchronization in 8/9-bit System Interface 6.3. Serial Peripheral Interface (SPI) The Serial Peripheral Interface (SPI) is selected by setting the IM[3:0] pins as “010x” level. The chip select pin

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9325 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 29 of 107 Version: 0.43 (nCS), the serial transfer clock pin (SCL), the serial data input pin (SDI) and the serial data output pin (SDO) are used in SPI mode. The ID pin sets the least significant bit of the identification code. The DB[17:0] pins, which are not used, must be tied to GND. The SPI interface operation enables from the falling edge of nCS and ends of data transfer on the rising edge of nCS. The start byte is transferred to start the SPI interface and the read/write operation and RS information are also included in the start byte. When the start byte is matched, the subsequent data is received by ILI9325. The seventh bit of start byte is RS bit. When RS = “0”, either index write operation or status read operation is executed. When RS = “1”, either register write operation or RAM read/write operation is executed. The eighth bit of the start byte is used to select either read or write operation (R/W bit). Data is written when the R/W bit is “0” and read back when the R/W bit is “1”. After receiving the start byte, ILI9325 starts to transfer or receive the data in unit of byte and the data transfer starts from the MSB bit. All the registers of the ILI9325 are 16-bit format and receive the first and the second byte datat as the upper and the lower eight bits of the 16-bit register respectively. In SPI mode, 5 bytes dummy read is necessary and the valid data starts from 6 th byte of read back data. Start Byte Format Transferred bits S 1 2 3 4 5 6 7 8 Start byte format Transfer start Device ID code RS R/W 0 1 1 1 0 ID 1/0 1/0 Note: ID bit is selected by setting the IM0/ID pin. RS and R/W Bit Function RS R/W Function 0 0 Set an index register 0 1 Read a status 1 0 Write a register or GRAM data 1 1 Read a register or GRAM data

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9325 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 30 of 107 Version: 0.43 WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD Seri al Peri pheral I nterf ace 65K col ors Input Data GRAM Data RGB mapping R5 R4 R3 R2 R1 R0 G5 G4 G2 G1 G0 B5 B4 B3 B2 B1G3 B0 D D D D D D D D D D D D D D D D Wri te Data Regi ster Seri al Peri pheral I nterf ace f or r egi ster access SP I Input Data D D D D D D D D D D D D D D Regi ster Data IB IB IB IB IB IB IB IB IB IB IB IB IB IB D IB D IB Figure 7 Data Format of SPI Interface

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9325 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 31 of 107 Version: 0.43 1234567891 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 24

01110 ID RS RW D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Start Byte Index register, registers setting, and GRAM write D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Status, registers read and GRAM read Start SCL (Input) SDI (Input) SDO (Output) (a) Basic data transmission through SPI End nCS (Input) 18 16 24 329 17 25 Start nCS (Input) (b) Consecutive data transmission through SPI Start Byte Register 1 upper eight bits Register 1 lower eight bits Register 2 upper eight bits SDI (Input) SCL (Input) Register 1 execution time Note: The first byte after the start byte is always the upper eight bits . Start End nCS (Input) (c) GRAM data read transmission SDI (Input) SCL (Input) Dummy read 1 Dummy read 2 Dummy read 3 Dummy read 4 Dummy read 5 RAM read upper byte RAM read lower byte SDO (Output) Note: Five bytes of invalid dummy data read after the start byte . Start End nCS (Input) (d) Status/registers read transmission Start ByteSDI (Input) SCL (Input) SDO (Output) Note: One byte of invalid dummy data read after the start byte . Start Byte RS=1, RW=1 18 16 249 17 Register 1 upper eight bits Register 1 lower eight bits Register 2 lower eight bits Figure8 Data transmission through serial peripheral interface (SPI)

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9325 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 32 of 107 Version: 0.43 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Start Byte GRAM data write GRAM data read Start SCL (Input) SDI (Input) SDO (Output) (e) Basic data transmission through SPI End nCS (Input) Start End nCS (Input) (f) GRAM data write transmission SDI (Input) SCL (Input) SDO (Output) Note: Five bytes of invalid dummy data read after the start byte. Start Byte 25 26 27 28 29 30 31 32 D16D17D18D19D120D21D22D23 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0D16D17D18D19D120D21D22D23 Start End nCS (Input) (g) GRAM data read transmission SDI (Input) SCL (Input) Dummy read 1 Dummy read 2 Dummy read 3 Dummy read 4 Dummy read 5 RAM read 1st byte RAM read 2nd byte SDO (Output) Note: Five bytes of invalid dummy data read after the start byte. Start Byte RS=1, RW=1 RAM data 1 1st transfer RAM data 1 2nd transfer RAM data 1 3rd transfer RAM data 2 1st transfer RAM data 2 2nd transfer RAM data 2 3rd transfer RAM read 3rd byte RAM data transfer in SPI mode when TRI=1 and DFM[1:0]=10. GRAM Data (1) execution time GRAM Data (2) execution time Figure9 Data transmission through serial peripheral interface (SPI), TRI=”1” and DFM=”10”)

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9325 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 33 of 107 Version: 0.43 6.4. VSYNC Interface ILI9325 supports the VSYNC interface in synchronization with the frame-synchronizing signal VSYNC to display the moving picture with the i80 system interface. When the VSYNC interface is selected to display a moving picture, the minimum GRAM update speed is limited and the VSYNC interface is enabled by setting DM[1:0] = “10” and RM = “0”. MPU VSYNC nCS RS DB[17:0] nWR Figure10 Data transmission through VSYNC interface) In the VSYNC mode, the display operation is synchronized with the internal clock and VSYNC input and the frame rate is determined by the pulse rate of VSYNC signal. All display data are stored in GRAM to minimize total data transfer required for moving picture display. Rewriting screen data Rewriting screen data VSYNC Write data to RAM through system interface Display operation synchronized with internal clocks Figure11 Moving picture data transmission through VSYNC interface

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9325 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 34 of 107 Version: 0.43 Display (320 lines) Back porch (14 lines) Front porch (2 lines) Black period VSYNC RAM Write Display operation Figure12 Operation through VSYNC Interface The VSYNC interface has the minimum speed limitation of writing data to the internal GRAM via the system interface, which are calculated from the following formula. Internal clock frequency (fosc.) [Hz] = FrameFrequency x (DisplayLine (NL) + FrontPorch (FP) + BackPorch (BP)) x ClockCyclePerLines (RTN) x FrequencyFluctuation. Note: When the RAM write operation does not start from the falling edge of VSYNC, the time from the falling edge of VSYNC until the start of RAM write operation must also be taken into account. An example of minimum GRAM writing speed and internal clock frequency in VSYNC interface mode is as below. [Example] Display size: 240 RGB × 320 lines Lines: 320 lines (NL = 100111) Back porch: 14 lines (BP = 1110) Front porch: 2 lines (FP = 0010) Frame frequency: 60 Hz Frequency fluctuation: 10% Minimum RAM write speed (HZ 240 x DisplayLines (NL ) [( BackPorch(BP)+DisplayLines(NL) - margins ] x 16 ( clocks ) x 1/fosc

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9325 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 35 of 107 Version: 0.43 Internal oscillator clock (fosc.) [Hz] = 60 x [320+ 2 + 14] x 16 clocks x (1.1/0.9) ≒ 394KHz When calculate the internal clock frequency, the oscillator variation is needed to be taken into consideration. In the above example, the calculated internal clock frequency with ±10% margin variation is considered and ensures to complete the display operation within one VS YNC cycle. The causes of frequency variation come from fabrication process of LSI, room temperature, external resistors and VCI voltage variation. Minimum speed for RAM writing [Hz] > 240 x 320 x 394K / [ (14 + 320 – 2)lines x 16clocks] ≒ 5.7 MHz The above theoretical value is calculated based on the premise that the ILI9325 starts to write data into the internal GRAM on the falling edge of VSYNC. There must at least be a margin of 2 lines between the physical display line and the GRAM line address where data writing operation is performed. The GRAM write speed of 5.7MHz or more will guarantee the completion of GRAM write operation before the ILI9325 starts to display the GRAM data on the screen and enable to rewrite the entire screen without flicker. Notes in using the VSYNC interface 1. The minimum GRAM write speed must be satisfied and the frequency variation must be taken into consideration. 2. The display frame rate is determined by the VSYNC signal and the period of VSYNC must be longer than the scan period of an entire display. 3. When switching from the internal clock operation mode (DM[1:0] = “00”) to the VSYNC interface mode or inversely, the switching starts from the next VSYNC cycle, i.e. after completing the display of the frame. 4. The partial display, vertical scroll, and interlaced scan functions are not available in VSYNC interface mode and set the AM bit to “0” to transfer display data.

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9325 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 36 of 107 Version: 0.43 Figure13 Transition flow between VSYNC and internal clock operation modes Set AM=0 Set GRAM Address Set DM [ 1 : 0]=10, RM= 0 for VSYNC interface mode Set index register to R 22h Write data to GRAM through VSYNC interface Wait more than 1 frame System Interface Mode to VSYNC interface mode System Interface Opeartion through VSYNC interface Display operation in synchronization with internal clocks DM [ 1:0], RM become enable after completion of displaying 1 frame Display operation in synchronization with VSYNC Set DM[1:0]=00, RM=0 for system interface mode Wait more than 1 frame VSYNC interface mode to System Interface Mode System Interface Opeartion through VSYNC interface Display operation in synchronization with internal clocks Display operation in synchronization with VSYNC DM [ 1 : 0], RM become enable after completion of displaying 1 frame Note: input VSYNC for more than 1 frame period after setting the DM , RM register .

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9325 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 37 of 107 Version: 0.43 6.5. RGB Input Interface The RGB Interface mode is available for ILI9325 and the interface is selected by setting the RIM[1:0] bits as following table. RIM1 RIM0 RGB Interface DB pins 0 0 18-bit RGB Interface DB[17:0] 0 1 16-bit RGB Interface DB[17:13], DB[11:1] 1 0 6-bit RGB Interface DB[17:12] 1 1 Setting prohibited 18-bit RGB Interface (262K colors) Input Data Write Data Regi ster R5 R4 R3 R2 R1 R0 G5 G4 G2 G1 G0 B5 B4 B3 B2 B1G3GRA M Data & RGB Mapping B0 WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD DB DB DB DB DB DB 6-bi t RGB I nterf ace (262K col ors) Input Data Write Data Regi ster R5 R4 R3 R2 R1 R0 G5 G4 G2 G1 G0 B5 B4 B3 B2 B1G3GRA M Data & RGB Mapping B0 WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD DB DB DB DB DB DB 1st Transf er 2nd Transf er DB DB DB DB DB DB 3rd Transfer DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB 16-bit RGB Interface (65K colors) Input Data Write Data Regi ster R5 R4 R3 R2 R1 R0 G5 G4 G2 G1 G0 B5 B4 B3 B2 B1G3GRA M Data & RGB Mapping B0 WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB Figure14 RGB Interface Data Format

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9325 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 38 of 107 Version: 0.43 6.5.1. RGB Interface The display operation via the RGB interface is synchronized with the VSYNC, HSYNC, and DOTCLK signals. The RGB interface transfers the updated data to GRAM with the high-speed write function and the update area is defined by the window address function. The back porch and front porch are used to set the RGB interface timing. VSYNC HSYNC DOTCLK Moving picture display area ENABLE RAM data display area Back porch period (BP[3:0]) Display period (NL[4:0] Front porch period (FP[3:0]) DB[17:0] Note 1: Front porch period continues until the next input of VSYNC. Note 2: Input DOTCLK throughout the operation. Note 3: Supply the VSYNC, HSYNC and DOTCLK with frequency that can meet the resolution requirement of panel. Figure15 GRAM Access Area by RGB Interface

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9325 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 39 of 107 Version: 0.43 6.5.2. RGB Interface Timing The timing chart of 18-/16-bit RGB interface mode is shown as follows. Figure16 Timing Chart of Signals in 18-/16-bit RGB Interface Mode HSYNC VSYNC DOTCLK ENABLE DB[17:0] Back porch Front porch 1 frame VLW >= 1H HLW >= 3 DOTCLK HSYNC DOTCLK ENABLE DB[17:0] DTST >= HLW Valid data VLW: VSYNC low period HLW: HSYNC low period DTST: data transfer startup time

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9325 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 40 of 107 Version: 0.43 The timing chart of 6-bit RGB interface mode is shown as follows. Figure17 Timing chart of signals in 6-bit RGB interface mode HSYNC VSYNC DOTCLK ENABLE DB[17:12] Back porch Front porch 1 frame VLW >= 1H HLW >= 3 DOTCLK HSYNC DOTCLK ENABLE DB[17:12] DTST >= HLW Valid data VLW: VSYNC low period HLW: HSYNC low period DTST: data transfer startup time . Note 1) In 6-bit RGB interface mode, each dot of one pixel (R, G and B) is transferred in synchronization with DOTCLKs. Note 2) In 6-bit RGB interface mode, set the cycles of VSYNC, HSYNC and ENABLE to 3 multiples of DOTCLKs. R G B R G B BR G B//

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9325 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 41 of 107 Version: 0.43 6.5.3. Moving Picture Mode ILI9325 has the RGB interface to display moving picture and incorporates GRAM to store display data, which has following merits in displaying a moving picture.

• The window address function defined the update area of GRAM.
• Only the moving picture area of GRAM is updated.
• When display the moving picture in RGB interface mode, the DB[17:0] can be switched as system interface to update still picture area and registers, such as icons. RAM access via a system interface in RGB-I/F mode ILI9325 allows GRAM access via the system interface in RGB interface mode. In RGB interface mode, data are written to the internal GRAM in synchronization with DOTCLK and ENABLE signals. When write data to the internal GRAM by the system interface, set ENABLE to terminate the RGB interface and switch to the system interface to update the registers (RM = “0”) and the still picture of GRAM. When restart RAM access in RGB interface mode, wait one read/write cycle and then set RM = “1” and the index register to R22h to start accessing RAM via the RGB interface. If RAM accesses via two interfaces conflicts, there is no guarantee that data are written to the internal GRAM. The following figure illustrates the operation of the IL I9325 when displaying a mo ving picture via the RGB interface and rewriting the still picture RAM area via the system interface. Moving Picture Area Still Picture Area VSYNC ENABLE DOTCLK DB[17:0] Update a frame Set IR to R22h Update moving picture area Set RM=0 Set AD[15:0] Set IR to R22h Update display data in other than the moving picture area Set AD[15:0] Set RM=1 Set IR to R22h Update a frame Update moving picture area Figure18 Example of update the still and moving picture

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9325 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 42 of 107 Version: 0.43 6.5.4. 6-bit RGB Interface The 6-bit RGB interface is selected by setting the RIM[1:0] bits to “10”. The display operation is synchronized with VSYNC, HSYNC, and DOTCLK signals. Display data are transferred to the internal GRAM in synchronization with the display operation via 6-bit RGB data bus (DB[17:12]) according to the data enable signal (ENABLE). Unused pins (DB[11:0]) must be fixed at GND level. Registers can be set by the system interface (i80/SPI). In p u t Da ta RGB Assi gnment RGB i nterf ace wi th 6-bi t data bus DB DB DB DB DB DB R5 R4 R3 R2 R1 R0 G5 G4 G2 G1 G0 B5 B4 B3 B2 B1G3 B0 1st Transfer 2nd Transfer DB DB DB DB DB DB DB DB DB DB DB DB 3rd Transfer Data transfer synchronization in 6-bit RGB interface mode ILI9325 has data transfer counters to count the first, second, third data transfers in 6-bit RGB interface mode. The transfer counter is always reset to the state of first data transfer on the falling edge of VSYNC. If a mismatch arises in the number of each data transfer, the counter is reset to the state of first data transfer at the start of the frame (i.e. on the falling edge of VSYNC) to restart data transfer in the correct order from the next frame. This function is expedient for moving picture display, which requires consecutive data transfer in light of minimizing effects from failed data transfer and enabling the system to return to a normal state. Note that internal display operation is performed in units of pixels (RGB: taking 3 inputs of DOTCLK). Accordingly, the number of DOTCLK inputs in one frame period must be a multiple of 3 to complete data transfer correctly. Otherwise it will affect the display of that frame as well as the next frame. HSYNC ENABLE DOTCLK DB[17:12] 1st 2nd 3rd 1st 2nd 3rd 1st 2nd 3rd 1st 2nd 3rd Transf er synchroni zati on

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9325 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 43 of 107 Version: 0.43 6.5.5. 16-bit RGB Interface The 16-bit RGB interface is selected by setting the RIM[1:0] bits to “01”. The display operation is synchronized with VSYNC, HSYNC, and DOTCLK signals. Display data are transferred to the internal RAM in synchronization with the display operation via 16-bit RGB data bus (DB17-13, DB11-1) according to the data enable signal (ENABLE). Registers are set only via the system interface. 16-bit RGB Interf ace (65K colors) Input Data Write Data Regi ster R5 R4 R3 R2 R1 R0 G5 G4 G2 G1 G0 B5 B4 B3 B2 B1G3GRA M Data & RGB Mapping B0 WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB 6.5.6. 18-bit RGB Interface The 18-bit RGB interface is selected by setting the RIM[1:0] bits to “00”. The display operation is synchronized with VSYNC, HSYNC, and DOTCLK signals. Display data are transferred to the internal RAM in synchronization with the display operation via 18-bit RGB data bus (DB[17:0]) according to the data enable signal (ENABLE). Registers are set only via the system interface. DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB RGB Assi gnment R5 R4 R3 R2 R1 R0 G5 G4 G2 G1 G0 B5 B4 B3 B2 B1G3 B0 RGB interface with 18-bit data bus Input Data Notes in using the RGB Input Interface 1. The following are the functions not available in RGB Input Interface mode. Function RGB interface I80 system interface Partial display Not available Available Scroll function Not available Available Interlaced scan Not available Available 2. VSYNC, HSYNC, and DOTCLK signals must be supplied throughout a display operation period. 3. The periods set with the NO[1:0] bits (gate output non-overlap period), STD[1:0] bits (source output delay period) and EQ[1:0] bits (equalization period) are not based on the internal clock but based on DOTCLK in

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9325 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 44 of 107 Version: 0.43 RGB interface mode. 4. In 6-bit RGB interface mode, each of RGB dots is transferred in synchronization with a DOTCLK input. In other words, it takes 3 DOTCLK inputs to transfer one pixel. Be sure to complete data transfer in units of 3 DOTCLK inputs in 6-bit RGB interface mode. 5. In 6-bit RGB interface mode, data of one pixel, which consists of RGB dots, are transferred in units of 3 DOTCLK. Accordingly, set the cycle of each signal in 6-bit interface mode (VSYNC, HSYNC, ENABLE, DB[17:0]) to contain DOTCLK inputs of a multiple of 3 to complete data transfer in units of pixels. 6. When switching from the internal operation mode to the RGB Input Interface mode, or the other way around, follow the sequence below. 7. In RGB interface mode, the front porch period continues until the next VSYNC input is detected after drawing one frame. 8. In RGB interface mode, a RAM address (AD[15:0]) is set in the address counter every frame on the falling edge of VSYNC. Figure19 Internal clock operation/RGB interface mode switching AM=0 Set AD[15:0] Set RGB Interface mode DM[1:0]=01 and RM=1 Set IR to R22h (GRAM data write) Wait for more than 1 frame Write data through RGB I/F Internal clock operation to RGB I/F Internal clock operation * DM[1:0] and RM become enable after completion of display 1 frame RGB Interface Operation RGB Interface (Display operation in synchronization with VSYNC, HSYNC, DOTCLK) * SPI interface can be used to set the registers and data RGB I/F to Internal clock operation * DM[1:0] and RM become enable after completion of display 1 frame Internal clock operation RGB Interface Operation Set Internal Clock Operation mode DM[1:0]=00 and RM=0 Wait for more than 1 frame Internal clock operation RGB Interface (Display operation in synchronization with VSYNC, HSYNC, DOTCLK) Display operation in synchronization with internal clock Note Note: Input RGB Interface signals (VSYNC, HSYNC, DOTCLK) before setting DM[1;0] and RM to the RGB interface mode

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9325 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 45 of 107 Version: 0.43 Set D M = 1, RM =0 wi th RGB interface mode S et AD[15;0] Set I R t o R22 h (G RAM data write) Write data through RGB interface to write da ta through syste m interface RGB Interf ace operati on Write data to GRAM through syste m interface Wri t e data t hr ough syst em i n t er f ace t o w r i t e d at a t h ro u gh RGB i nterface Write data to GRAM t hrough system i nt erf ace Set AD [15;0] Set D M =1 , R M= 1 wi th RGB i nt erf ace mode Set IR to R22h (GRA M data w ri t e) RGB Interface operati on Syste m Interf a ce operation System Interface operati on Figure20 GRAM access between system interface and RGB interface

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9325 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 46 of 107 Version: 0.43 6.6. Interface Timing The following are diagrams of interfacing timing with LCD panel control signals in internal operation and RGB interface modes. 1 2345 3 2 0 319318 1 2 FLM G320 ….. 1 2345 3 2 0 319318 S[720:1] VCOM DB[17:0] ENABLE DOTCLK HSYNC VS YNC Figure21 Relationship between RGB I/F signals and LCD Driving Signals for Panel

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9325 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 47 of 107 Version: 0.43 7. Register Descriptions 7.1. Registers Access ILI9325 adopts 18-bit bus interface architecture for high-performance microprocessor. All the functional blocks of ILI9325 starts to work after receiving the correct instruction from the external microprocessor by the 18-, 16-, 9-, 8-bit interface. The index register (IR) stores the register address to which the instructions and display data will be written. The register selection signal (RS), the read/write signals (nRD/nWR) and data bus D17-0 are used to read/write the instructions and data of ILI9325. The registers of the ILI9325 are categorized into the following groups. 1. Specify the index of register (IR) 2. Read a status 3. Display control 4. Power management Control 5. Graphics data processing 6. Set internal GRAM address (AC) 7. Transfer data to/from the internal GRAM (R22) 8. Internal grayscale γ-correction (R30 ~ R39) Normally, the display data (GRAM) is most often updated, and in order since the ILI9325 can update internal GRAM address automatically as it writes data to the inte rnal GRAM and minimize data transfer by using the window address function, there are fewer loads on the program in the microprocessor. As the following figure shows, the way of assigning data to the 16 register bits (D[15:0]) varies for each interface. Send registers in accordance with the following data transfer format. S erial P eripheral Interface for register access SPI Input Data D D D D D D D D D D D D D D Regi ster Data D D D D D D D D D D D D D D D D D D Figure22 Register Setting with Serial Peripheral Interface (SPI)

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9325 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 48 of 107 Version: 0.43 DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB i 80/M68 system 18-bit data bus i nterface Data Bus (DB[17:0]) Regi ster Bi t (D[15:0]) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB i 80/M68 system 16-bit data bus i nterface Data Bus (DB[17:10]), (DB[8:1]) Regi ster Bi t (D[15:0]) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DB DB DB DB DB DB DB DB DB i 80/M68 system 9-bit data bus i nterface Data Bus (DB[17:9]) Regi ster Bi t (D[15:0]) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1st Transfer DB DB DB DB DB DB DB DB DB 2nd Transfer DB DB DB DB DB DB DB DB i 80/M68 system 8-bit data bus i nterface/Seri al peri pheral i nterface (2/3 transmi ssi on) Data Bus (DB[17:10]) Regi ster Bi t (D[15:0]) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1st Tra nsfe r DB DB DB DB DB DB DB DB 2nd Tra nsfe r Figure23 Register setting with i80 System Interface

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9325 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 49 of 107 Version: 0.43 i 80 18-/16-bi t System Bus Interface Ti mi ng Wri te regi ster “in de x＂ Write re g is te r “data＂ nWR DB[ 17:0] nRD RS nCS (a) Write to register Wri t e regi st er “ind e x＂ R e a d re g is te r “data＂ nWR DB[ 17:0] nRD RS nCS (b) Read from register i 80 9-/8-bi t System Bus I nterface Ti mi ng “00h＂ Wri te regi ster “ in de x＂ nWR DB[ 17:10] nRD RS nCS (a) Write to register (b) Read from register Wri te regi ster “hi gh byte data＂ Write register “low byte d a ta ＂ “00h＂ Wri te regi ster “ in de x＂ nWR DB[ 17:10] nRD RS nCS Read regi ster “hi gh byte data＂ Read regi ster “lo w b yte da ta ＂ Figure 24 Register Read/Write Timing of i80 System Interface

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9325 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 50 of 107 Version: 0.43 7.2. Instruction Descriptions No. Registers Name R/W RS D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 IR Index Register W 0 - - - - - - - - ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 00h Driver Code Read RO 1 1 0 0 1 0 0 1 1 0 0 1 0 0 1 0 1 01h Driver Output Control 1 W 1 0 0 0 0 0 SM 0 SS 0 0 0 0 0 0 0 0 02h LCD Driving Control W 1 0 0 0 0 0 0 BC0 EOR 0 0 0 0 0 0 0 0 03h Entry Mode W 1 TRI DFM 0 BGR 0 0 0 0 ORG 0 I/D1 I/D0 AM 0 0 0 04h Resize Control W 1 0 0 0 0 0 0 RCV1 RCV0 0 0 RCH1 RCH0 0 0 RSZ1 RSZ0 07h Display Control 1 W 1 0 0 PTDE1 PTDE0 0 0 0 BASEE 0 0 GON DTE CL 0 D1 D0 08h Display Control 2 W 1 0 0 0 0 FP3 FP2 FP1 FP0 0 0 0 0 BP3 BP2 BP1 BP0 09h Display Control 3 W 1 0 0 0 0 0 PTS2 PTS1 PTS0 0 0 PTG1 PTG0 ISC3 ISC2 ISC1 ISC0 0Ah Display Control 4 W 1 0 0 0 0 0 0 0 0 0 0 0 0 FMARKOE FMI2 FMI1 FMI0 0Ch RGB Display Interface Control 1 W 1 0 ENC2 ENC1 ENC0 0 0 0 RM 0 0 DM1 DM0 0 0 RIM1 RIM0 0Dh Frame Maker Position W 1 0 0 0 0 0 0 0 FMP8 FMP7 FMP6 FMP5 FMP4 FMP3 FMP2 FMP1 FMP0 0Fh RGB Display Interface Control 2 W 1 0 0 0 0 0 0 0 0 0 0 0 VSPL HSPL 0 DPL EPL 10h Power Control 1 W 1 0 0 0 SAP 0 BT2 BT1 BT0 APE AP2 AP1 AP0 0 0 SLP STB 11h Power Control 2 W 1 0 0 0 0 0 DC12 DC11 DC10 0 DC02 DC01 DC00 0 VC2 VC1 VC0 12h Power Control 3 W 1 0 0 0 0 0 0 0 0 VCIRE 0 0 PON VRH3 VRH2 VRH1 VRH0 13h Power Control 4 W 1 0 0 0 VDV4 VDV3 VDV2 VDV1 VDV0 0 0 0 0 0 0 0 0 20h Horizontal GRAM Address Set W 1 0 0 0 0 0 0 0 0 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 21h Vertical GRAM Address Set W 1 0 0 0 0 0 0 0 AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 22h Write Data to GRAM W 1 RAM write data (WD17-0) / read data (RD17-0) bits are transferred via different data bus lines according to the selected interfaces. 29h Power Control 7 W 1 0 0 0 0 0 0 0 0 0 0 VCM5 VCM4 VCM3 VCM2 VCM1 VCM0 2Bh Frame Rate and Color Control W 1 0 0 0 0 0 0 0 0 0 0 0 0 FRS[3] FRS[2] FRS[1] FRS[0] 30h Gamma Control 1 W 1 0 0 0 0 0 KP1[2] KP1[1] KP1[0] 0 0 0 0 0 KP0[2] KP0[1] KP0[0] 31h Gamma Control 2 W 1 0 0 0 0 0 KP3[2] KP3[1] KP3[0] 0 0 0 0 0 KP2[2] KP2[1] KP2[0] 32h Gamma Control 3 W 1 0 0 0 0 0 KP5[2] KP5[1] KP5[0] 0 0 0 0 0 KP4[2] KP4[1] KP4[0] 35h Gamma Control 4 W 1 0 0 0 0 0 RP1[2] RP1[1] RP1[0] 0 0 0 0 0 RP0[2] RP0[1] RP0[0] 36h Gamma Control 5 W 1 0 0 0 VRP1[4] VRP1[3] VRP1[2] VRP1[1] VRP1[0] 0 0 0 0 VRP0[3] VRP0[2] VRP0[1] VRP0[0] 37h Gamma Control 6 W 1 0 0 0 0 0 KN1[2] KN1[1] KN1[0] 0 0 0 0 0 KN0[2] KN0[1] KN0[0] 38h Gamma Control 7 W 1 0 0 0 0 0 KN3[2] KN3[1] KN3[0] 0 0 0 0 0 KN2[2] KN2[1] KN2[0] 39h Gamma Control 8 W 1 0 0 0 0 0 KN5[2] KN5[1] KN5[0] 0 0 0 0 0 KN4[2] KN4[1] KN4[0] 3Ch Gamma Control 9 W 1 0 0 0 0 0 RN1[2] RN1[1] RN1[0] 0 0 0 0 0 RN0[2] RN0[1] RN0[0] 3Dh Gamma Control 10 W 1 0 0 0 VRN1[4] VRN1[3] VRN1[2] VRN1[1] VRN1[0] 0 0 0 0 VRN0[3] VRN0[2] VRN0[1] VRN0[0] 50h Horizontal Address Start W 1 0 0 0 0 0 0 0 0 HSA7 HSA6 HSA5 HSA4 HSA3 HSA2 HSA1 HSA0

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9325 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 51 of 107 Version: 0.43 No. Registers Name R/W RS D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Position 51h Horizontal Address End Position W 1 0 0 0 0 0 0 0 0 HEA7 HEA6 HEA5 HEA4 HEA3 HEA2 HEA1 HEA0 52h Vertical Address Start Position W 1 0 0 0 0 0 0 0 VSA8 VSA7 VSA6 VSA5 VSA4 VSA3 VSA2 VSA1 VSA0 53h Vertical Address End Position W 1 0 0 0 0 0 0 0 VEA8 VEA7 VEA6 VEA5 VEA4 VEA3 VEA2 VEA1 VEA0 60h Driver Output Control 2 W 1 GS 0 NL5 NL4 NL3 NL2 NL1 NL0 0 0 SCN5 SCN4 SCN3 SCN2 SCN1 SCN0 61h Base Image Display Control W 1 0 0 0 0 0 0 0 0 0 0 0 0 0 NDL VLE REV 6Ah Vertical Scroll Control W 1 0 0 0 0 0 0 0 VL8 VL7 VL6 VL5 VL4 VL3 VL2 VL1 VL0 80h Partial Image 1 Display Position W 1 0 0 0 0 0 0 0 PT DP08 PTDP07 PTDP06 PTDP05 PTDP04 PTDP03 PTDP02 PTDP01 PTDP00 81h Partial Image 1 Area (Start Line) W 1 0 0 0 0 0 0 0 PT SA08 PTSA07 PTSA06 PTSA05 PTSA0 4 PTSA03 PTSA02 PTSA01 PTSA00 82h Partial Image 1 Area (End Line) W 1 0 0 0 0 0 0 0 PTEA0 8 PTEA07 PTEA06 PTEA05 PTEA04 P TEA03 PTEA02 PTEA01 PTEA00 83h Partial Image 2 Display Position W 1 0 0 0 0 0 0 0 PT DP18 PTDP17 PTDP16 PTDP15 PTDP14 PTDP13 PTDP12 PTDP11 PTDP10 84h Partial Image 2 Area (Start Line) W 1 0 0 0 0 0 0 0 PT SA18 PTSA17 PTSA16 PTSA15 PTSA1 4 PTSA13 PTSA12 PTSA11 PTSA10 85h Partial Image 2 Area (End Line) W 1 0 0 0 0 0 0 0 PTEA1 8 PTEA17 PTEA16 PTEA15 PTEA14 P TEA13 PTEA12 PTEA11 PTEA10 90h Panel Interface Control 1 W 1 0 0 0 0 0 0 DIVI1 DIVI00 0 0 0 0 RTNI3 RTNI2 RTNI1 RTNI0 92h Panel Interface Control 2 W 1 0 0 0 0 0 NOWI2 NOWI1 NOWI0 0 0 0 0 0 0 0 0 95h Panel Interface Control 4 W 1 0 0 0 0 0 0 DIVE1 DIVE0 0 0 RTNE5 RTNE4 RTNE3 RTNE2 RTNE1 RTNE0 A1h OTP VCM Programming Control W 1 0 0 0 0 OTP_ PGM_EN 0 0 0 0 0 VCM_ OTP5 VCM_ OTP4 VCM_ OTP3 VCM_ OTP2 VCM_ OTP1 VCM_ OTP0 A2h OTP VCM Status and Enable W 1 PGM_ CNT1 PGM_ CNT0 VCM_ VCM_ VCM_ VCM_ VCM_ VCM_ D0 0 0 0 0 0 0 0 VCM_ EN A5h OTP Programming ID Key W 1 KEY KEY KEY KEY KEY KEY KEY KEY KEY KEY KEY KEY KEY KEY KEY KEY

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9325 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 52 of 107 Version: 0.43 7.2.1. Index (IR) R/W RS D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 W 0 - - - - - - - - ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 The index register specifies the address of register (R00h ~ RFFh) or RAM which will be accessed. 7.2.2. ID code (R00h) R/W RS D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 RO 1 1 0 0 1 0 0 1 1 0 0 1 0 0 1 0 1 The device code “9325”h is read out when read this register. 7.2.3. Driver Output Control (R01h) R/W RS D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 W 1 0 0 0 0 0 SM 0 SS 0 0 0 0 0 0 0 0 SS: Select the shift direction of outputs from the source driver. When SS = 0, the shift direction of outputs is from S1 to S720 When SS = 1, the shift direction of outputs is from S720 to S1. In addition to the shift direction, the settings for both SS and BGR bits are required to change the assignment of R, G, B dots to the source driver pins. To assign R, G, B dots to the source driver pins from S1 to S720, set SS = 0. To assign R, G, B dots to the source driver pins from S720 to S1, set SS = 1. When changing SS or BGR bits, RAM data must be rewritten. SM: Sets the gate driver pin arrangement in combination with the GS bit (R60h) to select the optimal scan mode for the module.

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9325 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 53 of 107 Version: 0.43 SM GS Scan Direction Gate Output Sequence 0 0 G317 G319 G318 G320 ILI9325 Odd-numberEven-number G1 to G319 TFT Panel G2 to G320 G317, G318, G319, G320 0 1 G2 to G320 G317 G319 ILI9325 Odd-numberEven-number TFT Panel G1 to G319 G318 G320 G320, G319, G318, …, G6, G5, G4, G3, G2, G1 1 0 G319 G320 ILI9325 Odd-number Even-number TFT Panel G1 to G319 G2 to G320 G313, G315, G317, G319 G314, G316, G318, G320

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9325 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 54 of 107 Version: 0.43 1 1 G320 ILI9325 Odd-number Even-number G319 TFT Panel G2 to G320 G1 to G319 G320, G318, G316, …, G10, G8, G6, G4, G2 G319, G317, G315, …, G9, G78, G5, G3, G1 7.2.4. LCD Driving Wave Control (R02h) R/W RS D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 W 1 0 0 0 0 0 1 B/C EOR 0 0 0 0 0 0 0 0 .B/C 0 : Frame/Field inversion 1 : Line inversion EOR: EOR = 1 and B/C=1 to set the line inversion. 7.2.5. Entry Mode (R03h) R/W RS D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 W 1 TRI DFM 0 BGR 0 0 0 0 ORG 0 I/D1 I/D0 AM 0 0 0 AM Control the GRAM update direction. When AM = “0”, the address is updated in horizontal writing direction. When AM = “1”, the address is updated in vertical writing direction. When a window area is set by registers R50h ~R53h, only the addressed GRAM area is updated based on I/D[1:0] and AM bits setting. I/D[1:0] Control the address counter (AC) to automatically increase or decrease by 1 when update one pixel display data. Refer to the following figure for the details.

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9325 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 55 of 107 Version: 0.43 I/D[1:0] = 00 Horizontal : decrement Ve rtica l : de cre me nt I /D[ 1:0] = 01 Hori zontal : i ncrement Ve rtica l : de cre me nt I /D[ 1:0] = 10 Hori zontal : decrement Ve rtica l : incre me nt I /D[ 1:0] = 11 Hori zontal : i ncrement Ve rtica l : incre me nt AM = 0 Horizontal AM = 1 Ve rtica l B E B E B E B E B E B EB E B E Figure25 GRAM Access Direction Setting ORG Moves the origin address according to the ID setting when a window address area is made. This function is enabled when writing data with the window address area using high-speed RAM write. ORG = “0”: The origin address is not moved. In this case, specify the address to start write operation according to the GRAM address map within the window address area. ORG = “1”: The original address “00000h” moves according to the I/D[1:0] setting. Notes: 1. When ORG=1, only t he origin address address”00000h” can be set in the RAM address set registers R20h, and R21h. 2. In RAM read operation, make sure to set ORG=0. BGR Swap the R and B order of written data. BGR=”0”: Follow the RGB order to write the pixel data. BGR=”1”: Swap the RGB data to BGR in writing into GRAM. TRI When TRI = “1”, data are transferred to the internal RAM in 8-bit x 3 transfers mode via the 8-bit interface. It is also possible to send data via the 16-bit interface or SPI in the transfer mode that realizes display in 262k colors in combination with DFM bits. When not using these interface modes, be sure to set TRI = “0”. DFM Set the mode of transferring data to the internal RAM when TRI = “1”. See the following figures for details.

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9325 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 56 of 107 Version: 0.43 TRI DFM 16-bit MPU System Interface Data Format R4R5 R2R3 R0R1 G4G5 G2G3 G0G1 B4B5 B2B3 B0B1 0 * system 16-bit interface (1 transfers/pixel) 65,536 colors R4R5 R2R3 R0R1 G4G5 G2G3 G0G1 B4B5 B2B3 B0B1 1 0 80-system 16-bit interface (2 transfers/pixel) 262,144 colors R4R5 R2R3 R0R1 G4G5 G2G3 G0G1 B4B5 B2B3 B0B1 1 1 80-system 16-bit interface (2 transfers/pixel) 262,144 colors DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB 1st Transfer DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB 1st Transf er DB DB 2nd Transf er DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB 2nd Transfer1st Transfer DB DB Figure26 16-bit MPU System Interface Data Format TRI DFM 8-bi t M PU System I nterf ace Data Format DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB R4R5 R2R3 R0R1 G4G5 G2G3 G0G1 B4B5 B2B3 B0B1 1st Transf er 2nd Transfer 0 * system 8-bit interface (2 transfers/pixel) 65,536 colors DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB R4R5 R2R3 R0R1 G4G5 G2G3 G0G1 B4B5 B2B3 B0B1 2nd Transf er 3rd Transfer 1 0 80-system 8-bit interface (3 transfers/pixel) 262,144 colors DB DB 1st Transf er R4R5 R2R3 R0R1 G4G5 G2G3 G0G1 B4B5 B2B3 B0B1 1 1 80-system 8-bit interface (3 transfers/pixel) 262,144 colors DB DB DB DB DB DB DB DB DB DB DB DB 2nd Transfer 3rd Transf er1st Transf er DB DB DB DB DB DB Figure27 8-bit MPU System Interface Data Format 7.2.6. Resizing Control Register (R04h) R/W RS D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 W 1 0 0 0 0 0 0 RCV1 RCV0 0 0 RCH1 RCH0 0 0 RSZ1 RSZ0 RSZ[1:0] Sets the resizing factor. When the RSZ bits are set for resizing, the ILI9325 writes the data according to the resizing factor so that the original image is displayed in horizontal and vertical dimensions, which are contracted

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9325 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 57 of 107 Version: 0.43 according to the factor respectively. See “Resizing function”. RCH[1:0] Sets the number of remainder pixels in horizontal direction when resizing a picture. By specifying the number of remainder pixels by RCH bits, the data can be transferred without taking the reminder pixels into consideration. Make sure that RCH = 2’h0 when not using the resizing function (RSZ = 2’h0) or there are no remainder pixels. RCV[1:0] Sets the number of remainder pixels in vertical direction when resizing a picture. By specifying the number of remainder pixels by RCV bits, the data can be transferred without taking the reminder pixels into consideration. Make sure that RCV = 2’h0 when not using the resizing function (RSZ = 2’h0) or there are no remainder pixels. RSZ[1:0] Resizing factor

00 No resizing (x1)

10 Setting prohibited

RCH[1:0] Number of remainder Pixels in Horizontal Direction 00 0 pixel* 01 1 pixel 10 2 pixel 11 3 pixel RCV[1:0] Number of remainder Pixels in Vertical Direction 00 0 pixel* 01 1 pixel 10 2 pixel 11 3 pixel *1 pixel = 1RGB 7.2.7. Display Control 1 (R07h) R/W RS D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 W 1 0 0 PTDE1 PTDE0 0 0 0 BASEE 0 0 GON DTE CL 0 D1 D0 D[1:0] Set D[1:0]=”11” to turn on the display panel, and D[1:0]=”00” to turn off the display panel. A graphics display is turned on the panel when writing D1 = “1”, and is turned off when writing D1 = “0”. When writing D1 = “0”, the graphics display data is retained in the internal GRAM and the ILI9325 displays the data when writing D1 = “1”. When D1 = “0”, i.e. while no display is shown on the panel, all source outputs becomes the GND level to reduce charging/discharging current, which is generated within the LCD while driving liquid crystal with AC voltage. When the display is turned off by setting D[1:0] = “01”, the ILI9325 continues internal display operation. When the display is turned off by setting D[1:0] = “00”, the ILI9325 internal display operation is halted completely. In combination with the GON, DTE setting, the D[1:0] setting controls display ON/OFF.

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9325 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 58 of 107 Version: 0.43 D1 D0 BASEE Source, VCOM Outp ut ILI9325 internal operation 0 0 0 GND Halt 0 1 1 GND Operate 1 0 0 Non-lit display Operate 1 1 0 Non-lit display Operate 1 1 1 Base image display Operate Note: 1. data write operation from the microcontroller is performed irrespective of the setting of D[1:0] bits. 2. The D[1:0] setting is valid on both 1st and 2nd displays. 3. The non-lit display level from the source output pins is determined by instruction (PTS). CL When CL = “1”, the 8-color display mode is selected. CL Colors 0 262,144 1 8 GON and DTE Set the output level of gate driver G1 ~ G320 as follows GON DTE G1 ~G320 Gate Output 0 0 VGH 0 1 VGH 1 0 VGL 1 1 Normal Display BASEE Base image display enable bit. When BASEE = “0”, no base image is displayed. The ILI9325 drives liquid crystal at non-lit display level or displays only partial images. When BASEE = “1”, the base image is displayed. The D[1:0] setting has higher priority over the BASEE setting. PTDE[1:0] Partial image 2 and Partial image 1 enable bits PTDE1/0 = 0: turns off partial image. Only base image is displayed. PTDE1/0 = 1: turns on partial image. Set the base image display enable bit to 0 (BASEE = 0). 7.2.8. Display Control 2 (R08h) R/W RS D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 W 1 0 0 0 0 FP3 FP2 FP1 FP0 0 0 0 0 BP3 BP2 BP1 BP0 FP[3:0]/BP[3:0] The FP[3:0] and BP[3:0] bits specify the line number of front and back porch periods respectively. When setting the FP[3:0] and BP[3:0] value, the following conditions shall be met: BP + FP ≤ 16 lines FP ≥ 2 lines BP ≥ 2 lines

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9325 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 59 of 107 Version: 0.43 Set the BP[3:0] and FP[3:0] bits as below for each operation modes Operation Mode BP FP BP+FP I80 System Interface Operation Mode BP ≥ 2 lines FP ≥ 2 lines FP +BP ≤ 16 lines RGB interface Operation BP ≥ 2 lines FP ≥ 2 lines FP +BP ≤ 16 lines VSYNC interface Operation BP ≥ 2 lines FP ≥ 2 lines FP +BP = 16 lines FP[3:0] Number of lines for Front Porch BP[3:0] Number of lines for Back Porch

0000 Setting Prohibited

0001 Setting Prohibited

1111 Setting Prohibited

Note: The output timing to the LCD is delayed by 2 lines period from the input of synchronizing signal. 7.2.9. Display Control 3 (R09h) R/W RS D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 W 1 0 0 0 0 0 PTS2 PTS1 PTS0 0 0 PTG1 PTG0 ISC3 ISC2 ISC1 ISC0 ISC[3:0]: Specify the scan cycle interval of gate driver in non-display area when PTG[1:0]=”10” to select interval scan. Then scan cycle is set as odd number from 0~29 frame periods. The polarity is inverted every scan cycle. ISC3 ISC3 ISC3 ISC3 Scan Cycle f FLM=60 Hz 0 0 0 0 0 frame - 0 0 0 1 1 frame 17ms 0 0 1 0 3 frame 50ms 0 0 1 1 5 frame 84ms 0 1 0 0 7 frame 117ms 0 1 0 1 9 frame 150ms 0 1 1 0 11 frame 184ms 0 1 1 1 13 frame 217ms 1 0 0 0 15 frame 251ms 1 0 0 1 17 frame 284ms 1 0 1 0 19 frame 317ms 1 0 1 1 21 frame 351ms 1 1 0 0 23 frame 384ms 1 1 0 1 25 frame 418ms 1 1 1 0 27 frame 451ms 1 1 1 1 29 frame 484ms

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9325 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 60 of 107 Version: 0.43 PTG[1:0] Set the scan mode in non-display area. PTG1 PTG0 Gate outputs in non-display area Source outputs in non-display area Vcom output 0 0 Normal scan Set with the PTS[2:0] bits VcomH/VcomL 0 1 Setting Prohibited - - 1 0 Interval scan Set with the PTS[2:0] bits VcomH/VcomL 1 1 Setting Prohibited - - PTS[2:0] Set the source output level in non-display area drive period (front/back porch period and blank area between partial displays). When PTS[2] = 1, the operation of amplifiers which generates the grayscales other than V0 and V63 are halted and the step-up clock frequency becomes half the normal frequency in non-display drive period in order to reduce power consumption. Source output level PTS[2:0] Positive polarity Negative polarity Grayscale amplifier in operation Step-up clock frequency

000 V63 V0 V63 to V0 Register Setting (DC1, DC0)

001 Setting Prohibited Setting Prohibited - -

010 GND GND V63 to V0 Register Setting (DC1, DC0)

011 Hi-Z Hi-Z V63 to V0 Register Setting (DC1, DC0)

100 V63 V0 V63 and V0 frequency setting by DC1, DC0

101 Setting Prohibited Setting Prohibited - -

110 GND GND V63 and V0 frequency setting by DC1, DC0

111 Hi-Z Hi-Z V63 and V0 frequency setting by DC1, DC0

Notes: 1. The power efficiency can be improved by halting grayscale amplifiers and slowing down the step-up clock frequency only in non-display drive period. 2. The gate output level in non-lit display area drive period is determined by PTG[1:0]. 7.2.10. Display C ontrol 4 (R0Ah) R/W RS D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 W 1 0 0 0 0 0 0 0 0 0 0 0 0 FMARKOE FMI2 FMI1 FMI0 FMI[2:0] Set the output interval of FMARK signal according to the display data rewrite cycle and data transfer rate. FMARKOE When FMARKOE=1, ILI9325 starts to output FMARK signal in the output interval set by FMI[2:0] bits. FMI[2:0] Output Interval 000 1 frame 001 2 frame 011 4 frame 101 6 frame Others Setting disabled

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9325 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 61 of 107 Version: 0.43 7.2.11. RGB Display Inte rface Control 1 (R0Ch) R/W RS D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 W 1 0 ENC2 ENC1 ENC0 0 0 0 RM 0 0 DM1 DM0 0 0 RIM1 RIM0 RIM[1:0] Select the RGB interface data width. RIM1 RIM0 RGB Interface Mode 0 0 18-bit RGB interface (1 transfer/pixel), DB[17:0] 0 1 16-bit RGB interface (1 transfe r/pixel), DB[17:13] and DB[11:1] 1 0 6-bit RGB interface (3 transfers/pixel), DB[17:12] 1 1 Setting disabled Note1: Registers are set only by the system interface. Note2: Be sure that one pixel (3 dots) data transfer finished when interface switch. DM[1:0] Select the display operation mode. DM1 DM0 Display Interface 0 0 Internal system clock 0 1 RGB interface 1 0 VSYNC interface 1 1 Setting disabled The DM[1:0] setting allows switching between internal clock operation mode and external display interface operation mode. However, switching between the RGB interface operation mode and the VSYNC interface operation mode is prohibited. RM Select the interface to access the GRAM. Set RM to “1” when writing display data by the RGB interface. RM Interface for RAM Access

0 System interface/VSYNC interface

1 RGB interface

Display State Operation Mode RAM Access (RM) Display Operation Mode (DM[1:0] Still pictures Internal clock operation System interface (RM = 0) Internal clock operation (DM[1:0] = 00) Moving pictures RGB interface (1) RGB interface (RM = 1) RGB interface (DM[1:0] = 01) Rewrite still picture area while RGB interface Displaying moving pictures. System interface (RM = 0) RGB interface (DM[1:0] = 01) Moving pictures VSYNC interface System interface (RM = 0) VSYNC interface (DM[1:0] = 10) Note 1: Registers are set only via the system interface or SPI interface. Note 2: Refer to the flowcharts of “RGB Input Interface” section for the mode switch. ENC[2:0] Set the GRAM write cycle through the RGB interface ENC[2:0] GRAM Write Cycle (Frame periods) 000 1 Frame 001 2 Frames 010 3 Frames 011 4 Frames

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9325 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 62 of 107 Version: 0.43 100 5 Frames 101 6 Frames 110 7 Frames 111 8 Frames 7.2.12. Frame Marker Position (R0Dh) R/W RS D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 W 1 0 0 0 0 0 0 0 FMP8 FMP7 FMP6 FMP5 FMP4 FMP3 FMP2 FMP1 FMP0 FMP[8:0] Sets the output position of frame cycle (frame marker). When FMP[8:0]=0, a high-active pulse FMARK is output at the start of back porch period for one display line period (1H). Make sure the 9’h000 ≦ F M P ≦ B P + N L + F P FMP[8:0] FMARK Output Position 9’h000 0 th line 9’h001 1 st line 9’h002 2 nd line 9’h003 3 rd line 9’h175 373 rd line 9’h176 374 th line 9’h177 375 th line 7.2.13. RGB Display Inte rface Control 2 (R0Fh) R/W RS D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 W 1 0 0 0 0 0 0 0 0 0 0 0 VSPL HSPL 0 EPL DPL DPL: Sets the signal polarity of the DOTCLK pin. DPL = “0” The data is input on the rising edge of DOTCLK DPL = “1” The data is input on the falling edge of DOTCLK EPL: Sets the signal polarity of the ENABLE pin. EPL = “0” The data DB17-0 is written when ENABLE = “0”. Disable data write operation when ENABLE = “1”. EPL = “1” The data DB17-0 is written when ENABLE = “1”. Disable data write operation when ENABLE = “0”. HSPL: Sets the signal polarity of the HSYNC pin. HSPL = “0” Low active HSPL = “1” High active VSPL: Sets the signal polarity of the VSYNC pin. VSPL = “0” Low active VSPL = “1” High active

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9325 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 63 of 107 Version: 0.43 7.2.14. Power Control 1 (R10h) R/W RS D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 W 1 0 0 0 SAP 0 BT2 BT1 BT0 APE AP2 AP1 AP0 0 0 SLP STB SLP: When SLP = 1, ILI9325 enters the sleep mode and the display operation stops except the RC oscillator to reduce the power consumption. In the sleep mode, the GRAM data and instructions cannot be updated except the following two instructions. a. Exit sleep mode (SLP = “0”) b. Start oscillation STB: When STB = 1, ILI9325 enters the standby mode and the display operation stops except the GRAM power supply to reduce the power consumption. In the STB mode, the GRAM data and instructions cannot be updated except the following two instructions. a. Exit standby mode (STB = “0”) b. Start oscillation AP[2:0]: Adjusts the constant current in the operational amplifier circuit in the LCD power supply circuit. The larger constant current enhances the drivab ility of the LCD, but it al so increases the current consumption. Adjust the constant current taking the trade-off into account between the display quality and the current consumption. In no-display period, set AP[2:0] = “000” to halt the operational amplifier circuits and the step-up circuits to reduce current consumption. AP[2:0] Gamma driver amplifiers Source driver amplifiers

000 Halt Halt

001 1.00 1.00 010 1.00 0.75 011 1.00 0.50 100 0.75 1.00 101 0.75 0.75 110 0.75 0.50 111 0.50 0.50 SAP: Source Driver output control SAP=0, Source driver is disabled. SAP=1, Source driver is enabled. When starting the charge-pump of LCD in the Power ON stage, make sure that SAP=0, and set the SAP=1, after starting up the LCD power supply circuit. APE: Power supply enable bit. Set APE = “1” to start the generation of power supply according to the power supply startup sequence. BT[3:0]: Sets the factor used in the step-up circuits. Select the optimal step-up factor for the operating voltage. To reduce power consumption, set a smaller factor.

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9325 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 64 of 107 Version: 0.43 BT[2:0] DDVDH VCL VGH VGL 3’h0 Vci1 x 2 - Vci1 - Vci1 x 5 3’h1 - Vci1 x 4 3’h2 Vci1 x 2 - Vci1 Vci1 x 6 - Vci1 x 3 3’h3 - Vci1 x 5 3’h4 - Vci1 x 4 3’h5 Vci1 x 2 - Vci1 Vci1 x 5 - Vci1 x 3 3’h6 - Vci1 x 4 3’h7 Vci1 x 2 - Vci1 Vci1 x 4 - Vci1 x 3 Notes: 1. Connect capacitors to the capacitor connection pins when generating DDVDH, VGH, VGL and VCL levels. 7.2.15. Power Control 2 (R11h) R/W RS D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 W 1 0 0 0 0 0 DC12 DC11 DC10 0 DC02 DC01 DC00 0 VC2 VC1 VC0 VC[2:0] Sets the ratio factor of Vci to generate the reference voltages Vci1. VC2 VC1 VC0 Vci1 voltage 0 0 0 0.95 x Vci 0 0 1 0.90 x Vci 0 1 0 0.85 x Vci 0 1 1 0.80 x Vci 1 0 0 0.75 x Vci 1 0 1 0.70 x Vci 1 1 0 Disabled 1 1 1 1.0 x Vci DC0[2:0]: Selects the operating frequency of the step-up circuit 1. The higher step-up operating frequency enhances the drivability of the step-up circuit and the quality of display but increases the current consumption. Adjust the frequency taking the trade-off between the display quality and the current consumption into account. DC1[2:0]: Selects the operating frequency of the step-up circuit 2. The higher step-up operating frequency enhances the drivability of the step-up circuit and the quality of display but increases the current consumption. Adjust the frequency taking the trade-off between the display quality and the current consumption into account. DC02 DC01 DC00 Step-up circuit1 step-up frequency (fDCDC1) DC12 DC11 DC10 Step-up circuit2 step-up frequency (fDCDC2) 0 0 0 Fosc 0 0 0 Fosc / 4 0 0 1 Fosc / 2 0 0 1 Fosc / 8 0 1 0 Fosc / 4 0 1 0 Fosc / 16 0 1 1 Fosc / 8 0 1 1 Fosc / 32 1 0 0 Fosc / 16 1 0 0 Fosc / 64 1 0 1 Fosc / 32 1 0 1 Fosc / 128 1 1 0 Fosc / 64 1 1 0 Fosc / 256 1 1 1 Halt step-up circuit 1 1 1 1 Halt step-up circuit 2

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9325 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 65 of 107 Version: 0.43 Note: Be sure fDCDC1≥fDCDC2 when setting DC0[2:0] and DC1[2:0]. 7.2.16. Power Control 3 (R12h) R/W RS D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 W 1 0 0 0 0 0 0 0 0 VCIRE 0 0 PON VRH3 VRH2 VRH1 VRH0 VRH[3:0] Set the amplifying rate (1.6 ~ 1.9) of Vci applied to output the VREG1OUT level, which is a reference level for the VCOM level and the grayscale voltage level. VCIRE: Select the external reference voltage Vci or internal reference voltage VCIR. VCIRE=0 External reference voltage Vci ( default) VCIRE =1 Internal reference voltage 2.5V VCIRE =0 VCIRE =1 VRH3 VRH2 VRH1 VRH0 VREG1OUT VRH3 VRH2 VRH1 VRH0 VREG1OUT 0 0 0 0 Halt 0 0 0 0 Halt 0 0 0 1 Vci x 2.00 0 0 0 1 2.5V x 2.00 = 5.000V 0 0 1 0 Vci x 2.05 0 0 1 0 2.5V x 2.05 = 5.125V 0 0 1 1 Vci x 2.10 0 0 1 1 2.5V x 2.10 = 5.250V 0 1 0 0 Vci x 2.20 0 1 0 0 2.5V x 2.20 = 5.500V 0 1 0 1 Vci x 2.30 0 1 0 1 2.5V x 2.30 = 5.750V 0 1 1 0 Vci x 2.40 0 1 1 0 2.5V x 2.40 = 6.000V 0 1 1 1 Vci x 2.40 0 1 1 1 2.5V x 2.40 = 6.000V 1 0 0 0 Vci x 1.60 1 0 0 0 2.5V x 1.60 = 4.000V 1 0 0 1 Vci x 1.65 1 0 0 1 2.5V x 1.65 = 4.125V 1 0 1 0 Vci x 1.70 1 0 1 0 2.5V x 1.70 = 4.250V 1 0 1 1 Vci x 1.75 1 0 1 1 2.5V x 1.75 = 4.375V 1 1 0 0 Vci x 1.80 1 1 0 0 2.5V x 1.80 = 4.500V 1 1 0 1 Vci x 1.85 1 1 0 1 2.5V x 1.85 = 4.625V 1 1 1 0 Vci x 1.90 1 1 1 0 2.5V x 1.90 = 4.750V 1 1 1 1 Vci x 1.95 1 1 1 1 2.5V x 1.95 = 4.875V When VCI<2.5V, Internal reference voltage will be same as VCI. Make sure that VC and VRH setting restriction: VREG1OUT ≦ (DDVDH - 0.2)V. PON: Control ON/OFF of circuit3 (VGL) output. PON=0 VGL output is disable PON=1 VGL output is enable 7.2.17. Power Control 4 (R13h) R/W RS D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 W 1 0 0 0 VDV4 VDV3 VDV2 VDV1 VDV0 0 0 0 0 0 0 0 0 VDV[4:0] Select the factor of VREG1OUT to set the amplitude of Vcom alternating voltage from 0.70 to 1.24 x VREG1OUT . VDV4 VDV3 VDV2 VDV1 VDV0 VCOM amplit ude VDV4 VDV3 VDV2 VDV1 VDV0 VCOM amplitude 0 0 0 0 0 VREG1OUT x 0.70 1 0 0 0 0 VREG1OUT x 0.94 0 0 0 0 1 VREG1OUT x 0.72 1 0 0 0 1 VREG1OUT x 0.96

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9325 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 66 of 107 Version: 0.43 0 0 0 1 0 VREG1OUT x 0.74 1 0 0 1 0 VREG1OUT x 0.98 0 0 0 1 1 VREG1OUT x 0.76 1 0 0 1 1 VREG1OUT x 1.00 0 0 1 0 0 VREG1OUT x 0.78 1 0 1 0 0 VREG1OUT x 1.02 0 0 1 0 1 VREG1OUT x 0.80 1 0 1 0 1 VREG1OUT x 1.04 0 0 1 1 0 VREG1OUT x 0.82 1 0 1 1 0 VREG1OUT x 1.06 0 0 1 1 1 VREG1OUT x 0.84 1 0 1 1 1 VREG1OUT x 1.08 0 1 0 0 0 VREG1OUT x 0.86 1 1 0 0 0 VREG1OUT x 1.10 0 1 0 0 1 VREG1OUT x 0.88 1 1 0 0 1 VREG1OUT x 1.12 0 1 0 1 0 VREG1OUT x 0.90 1 1 0 1 0 VREG1OUT x 1.14 0 1 0 1 1 VREG1OUT x 0.92 1 1 0 1 1 VREG1OUT x 1.16 0 1 1 0 0 VREG1OUT x 0.94 1 1 1 0 0 VREG1OUT x 1.18 0 1 1 0 1 VREG1OUT x 0.96 1 1 1 0 1 VREG1OUT x 1.20 0 1 1 1 0 VREG1OUT x 0.98 1 1 1 1 0 VREG1OUT x 1.22 0 1 1 1 1 VREG1OUT x 1.00 1 1 1 1 1 VREG1OUT x 1.24 Set VDV[4:0] to let Vcom amplitude less than 6V. 7.2.18. GRAM Horizontal/Ver tical Address Set (R20h, R21h) R/W RS D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 W 1 0 0 0 0 0 0 0 0 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 W 1 0 0 0 0 0 0 0 AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD[16:0] Set the initial value of address counter (AC). The address counter (AC) is automatically updated in accordance to the setting of the AM, I/D bits as data is written to the internal GRAM. The address counter is not automatically updated when read data from the internal GRAM. AD[16:0] GRAM Data Map 17’h00000 ~ 17’h000EF 1 st line GRAM Data 17’h00100 ~ 17’h001EF 2 nd line GRAM Data 17’h00200 ~ 17’h002EF 3 rd line GRAM Data 17’h00300 ~ 17’h003EF 4 th line GRAM Data 17’h13D00 ~ 17’ h13DEF 318 th line GRAM Data 17’h13E00 ~ 17’ h13EEF 319 th line GRAM Data 17’h13F00 ~ 17’h13FEF 320 th line GRAM Data Note1: When the RGB interface is se lected (RM = “1”), the address AD[16:0] is set to the address counter every frame on the falling edge of VSYNC. Note2: When the internal clock o peration or the VSYNC interface mode is selected (RM = “0”), the address AD[16:0] is set to address counter when update register R21. 7.2.19. Write Data to GRAM (R22h) R/W RS D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 W 1 RAM write data (WD[17:0], the DB[17:0] pin assignment differs for each interface. This register is the GRAM access port. When update the display data through this register, the address counter (AC) is increased/decreased automatically. 7.2.20. Read Data from GRAM (R22h) R/W RS D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9325 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 67 of 107 Version: 0.43 R 1 RAM Read Data (RD[17:0], the DB[17:0] pin assignment differs for each interface. RD[17:0] Read 18-bit data from GRAM through the read data register (RDR). DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB 18-bi t System I nterface Output Data Write Data Regi ster R5 R4 R3 R2 R1 R0 G5 G4 G2 G1 G0 B5 B4 B3 B2 B1G3GRAM Data & RGB Mappi ng B0 RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB 16-bi t System I nterface Output Data Write Data Regi ster R5 R4 R3 R2 R1 R0 G5 G4 G2 G1 G0 B5 B4 B3 B2 B1G3GRAM Data & RGB Mappi ng B0 RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD DB DB DB DB DB DB DB DB DB 9-bi t System I nterface Output Data Write Data Regi ster R5 R4 R3 R2 R1 R0 G5 G4 G2 G1 G0 B5 B4 B3 B2 B1G3GRAM Data & RGB Mappi ng B0 RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB 8-bi t System I nterface / Seri al Data Transfer Interf ace Output Data Write Data Regi ster R5 R4 R3 R2 R1 R0 G5 G4 G2 G1 G0 B5 B4 B3 B2 B1G3GRAM Data & RGB Mappi ng B0 RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD DB DB DB DB DB DB DB DB 1st Transfer 2nd Transfer 1st Transf er 2nd Transf er Figure 28 Data Read from GRAM through Read Data Register in 18-/16-/9-/8-bit Interface Mode

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9325 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 68 of 107 Version: 0.43 Set I / D A M , HA S/HEA , V SA /V EA Set address M Dummy read (i nval i d dat a) GRA M -> Read data l atch Read Output (data of address M) Read dat al at ch - > DB[ 17: 0] Set address N Dummy read (i nval i d dat a) GRA M -> Read data l atch Read Output (data of address N) Read dat al at ch - > DB[ 17: 0] Read Output (data of address M+1) Read dat al at ch - > DB[ 17: 0] Figure 29 GRAM Data Read Back Flow Chart 7.2.21. Power Control 7 (R29h) R/W RS D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 W 1 0 0 0 0 0 0 0 0 0 0 VCM5 VCM4 VCM3 VCM2 VCM1 VCM0 VCM[5:0] Set the internal VcomH voltage. VCM5 VCM4 VCM3 VCM2 VCM1 VCM0 VCOM H VCM5 VCM4 VCM3 VCM2 VCM1 VCM0 VCOMH 0 0 0 0 0 0 VREG1OUT x 0.685 1 0 0 0 0 0 VREG1OUT x 0.845 0 0 0 0 0 1 VREG1OUT x 0.690 1 0 0 0 0 1 VREG1OUT x 0.850 0 0 0 0 1 0 VREG1OUT x 0.695 1 0 0 0 1 0 VREG1OUT x 0.855 0 0 0 0 1 1 VREG1OUT x 0.700 1 0 0 0 1 1 VREG1OUT x 0.860 0 0 0 1 0 0 VREG1OUT x 1 0 0 1 0 0 VREG1OUT x

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9325 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 69 of 107 Version: 0.43 0.705 0.865 0 0 0 1 0 1 VREG1OUT x 0.710 1 0 0 1 0 1 VREG1OUT x 0.870 0 0 0 1 1 0 VREG1OUT x 0.715 1 0 0 1 1 0 VREG1OUT x 0.875 0 0 0 1 1 1 VREG1OUT x 0.720 1 0 0 1 1 1 VREG1OUT x 0.880 0 0 1 0 0 0 VREG1OUT x 0.725 1 0 1 0 0 0 VREG1OUT x 0.885 0 0 1 0 0 1 VREG1OUT x 0.730 1 0 1 0 0 1 VREG1OUT x 0.890 0 0 1 0 1 0 VREG1OUT x 0.735 1 0 1 0 1 0 VREG1OUT x 0.895 0 0 1 0 1 1 VREG1OUT x 0.740 1 0 1 0 1 1 VREG1OUT x 0.900 0 0 1 1 0 0 VREG1OUT x 0.745 1 0 1 1 0 0 VREG1OUT x 0.905 0 0 1 1 0 1 VREG1OUT x 0.750 1 0 1 1 0 1 VREG1OUT x 0.910 0 0 1 1 1 0 VREG1OUT x 0.755 1 0 1 1 1 0 VREG1OUT x 0.915 0 0 1 1 1 1 VREG1OUT x 0.760 1 0 1 1 1 1 VREG1OUT x 0.920 0 1 0 0 0 0 VREG1OUT x 0.765 1 1 0 0 0 0 VREG1OUT x 0.925 0 1 0 0 0 1 VREG1OUT x 0.770 1 1 0 0 0 1 VREG1OUT x 0.930 0 1 0 0 1 0 VREG1OUT x 0.775 1 1 0 0 1 0 VREG1OUT x 0.935 0 1 0 0 1 1 VREG1OUT x 0.780 1 1 0 0 1 1 VREG1OUT x 0.940 0 1 0 1 0 0 VREG1OUT x 0.785 1 1 0 1 0 0 VREG1OUT x 0.945 0 1 0 1 0 1 VREG1OUT x 0.790 1 1 0 1 0 1 VREG1OUT x 0.950 0 1 0 1 1 0 VREG1OUT x 0.795 1 1 0 1 1 0 VREG1OUT x 0.955 0 1 0 1 1 1 VREG1OUT x 0.800 1 1 0 1 1 1 VREG1OUT x 0.960 0 1 1 0 0 0 VREG1OUT x 0.805 1 1 1 0 0 0 VREG1OUT x 0.965 0 1 1 0 0 1 VREG1OUT x 0.810 1 1 1 0 0 1 VREG1OUT x 0.970 0 1 1 0 1 0 VREG1OUT x 0.815 1 1 1 0 1 0 VREG1OUT x 0.975 0 1 1 0 1 1 VREG1OUT x 0.820 1 1 1 0 1 1 VREG1OUT x 0.980 0 1 1 1 0 0 VREG1OUT x 0.825 1 1 1 1 0 0 VREG1OUT x 0.985 0 1 1 1 0 1 VREG1OUT x 0.830 1 1 1 1 0 1 VREG1OUT x 0.990 0 1 1 1 1 0 VREG1OUT x 0.835 1 1 1 1 1 0 VREG1OUT x 0.995 0 1 1 1 1 1 VREG1OUT x 0.840 1 1 1 1 1 1 VREG1OUT x 1.000 7.2.22. Frame Rate and Color Control (R2Bh) R/W RS D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 W 1 0 0 0 0 0 0 0 0 0 0 0 0 FRS3 FRS2 FRS1 FRS0 FRS[4:0] Set the frame rate when the internal resistor is used for oscillator circuit. FRS[3:0] FRS[3:0] Frame Rate 0000 4’h0 30

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9325 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 70 of 107 Version: 0.43 0001 4’h1 31 0010 4’h2 33 0011 4’h3 35 0100 4’h4 38 0101 4’h5 40 0110 4’h6 43 0111 4’h7 47 1000 4’h8 51 1001 4’h9 56 1010 4’hA 62 1011 4’hB 70 1100 4’hC 80 1101 4’hD 93 1110 4’hE 112 1111 4’hF Setting Prohibited 7.2.23. Gamma Control (R30h ~ R3Dh) R/W RS D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 R30h W 1 0 0 0 0 0 KP1[2] KP1[1] KP1[0] 0 0 0 0 0 KP0[2] KP0[1] KP0[0] R31h W 1 0 0 0 0 0 KP3[2] KP3[1] KP3[0] 0 0 0 0 0 KP2[2] KP2[1] KP2[0] R32h W 1 0 0 0 0 0 KP5[2] KP5[1] KP5[0] 0 0 0 0 0 KP4[2] KP4[1] KP4[0] R35h W 1 0 0 0 0 0 RP1[2] RP1[1] RP1[0] 0 0 0 0 0 RP0[2] RP0[1] RP0[0] R36h W 1 0 0 0 VRP1[4] VRP1[3] VRP1[2] VRP1[1] VRP1[0] 0 0 0 0 VRP0[3] VRP0[2] VRP0[1] VRP0[0] R37h W 1 0 0 0 0 0 KN1[2] KN1[1] KN1[0] 0 0 0 0 0 KN0[2] KN0[1] KN0[0] R38h W 1 0 0 0 0 0 KN3[2] KN3[1] KN3[0] 0 0 0 0 0 KN2[2] KN2[1] KN2[0] R39h W 1 0 0 0 0 0 KN5[2] KN5[1] KN5[0] 0 0 0 0 0 KN4[2] KN4[1] KN4[0] R3Ch W 1 0 0 0 0 0 RN1[2] RN1[1] RN1[0] 0 0 0 0 0 RN0[2] RN0[1] RN0[0] R3Dh W 1 0 0 0 VRN1[4] VRN1[3] VRN1[2] VRN1[1] VRN1[0] 0 0 0 0 VRN0[3] VRN0[2] VRN0[1] VRN0[0] KP5-0[2:0] : γfine adjustment register for positive polarity RP1-0[2:0] : γgradient adjustment register for positive polarity VRP1-0[4:0] : γamplitude adjustment register for positive polarity KN5-0[2:0] : γfine adjustment register for negative polarity RN1-0[2:0] : γgradient adjustment register for negative polarity VRN1-0[4:0] : γamplitude adjustment register for negative polarity For details “γ-Correction Function” section. 7.2.24. Horizontal and Ve rtical RAM Address Position (R50h, R51h, R52h, R53h) R/W RS D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 R50h W 1 0 0 0 0 0 0 0 0 HSA7 HSA6 HSA5 HSA4 HSA3 HSA2 HSA1 HSA0 R51h W 1 0 0 0 0 0 0 0 0 HEA7 HEA6 HEA5 HEA4 HEA3 HEA2 HEA1 HEA0 R52h W 1 0 0 0 0 0 0 0 VSA8 VSA7 VSA6 VSA5 VSA4 VSA3 VSA2 VSA1 VSA0 R53h W 1 0 0 0 0 0 0 0 VEA8 VEA7 VEA6 VEA5 VEA4 VEA3 VEA2 VEA1 VEA0

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9325 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 71 of 107 Version: 0.43 HSA[7:0]/HEA[7:0] HSA[7:0] and HEA[7:0] represent the respective addresses at the start and end of the window address area in horizontal direction. By setting HSA and HEA bits, it is possible to limit the area on the GRAM horizontally for writing data. The HSA and HEA bits must be set before starting RAM write operation. In setting these bits, be sure “00”h ≤ HSA[7:0]< HEA[7:0] ≤ “EF”h. and “04”h≦HEA-HAS. VSA[8:0]/VEA[8:0] VSA[8:0] and VEA[8:0] represent the respective addresses at the start and end of the window address area in vertical direction. By setting VSA and VEA bits, it is possible to limit the area on the GRAM vertically for writing data. T he VSA and VEA bits must be set before starting RAM write operation. In setting, be sure “000”h ≤ VSA[8:0]< VEA[8:0] ≤ “13F”h. Window Address Are a HSA HEA VS A VEA 0000h 13FEFh GRAM Addre s s Are a Figure 30 GRAM Access Range Configuration Note1. The window address range must be within the GRAM address space. Note2. Data are written to GRAM in four-words when operating in high speed mode, the dummy write operations should be inserted depending on the window address area. For details, see the High-Speed RAM Write Function section. 7.2.25. Gate Scan Control (R60h, R61h, R6Ah) R/W RS D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 R60h W 1 GS 0 NL5 NL4 NL3 NL2 NL1 NL0 0 0 SCN5 SCN4 SCN3 SCN2 SCN1 SCN0 R61h W 1 0 0 0 0 0 0 0 0 0 0 0 0 0 NDL VLE REV R6Ah W 1 0 0 0 0 0 0 0 VL8 VL7 VL6 VL5 VL4 VL3 VL2 VL1 VL0

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9325 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 72 of 107 Version: 0.43 SCN[5:0] The ILI9325 allows to specify the gate line from which the gate driver starts to scan by setting the SCN[5:0] bits. Scanning Start Position SM=0 SM=1 SCN[5:0] GS=0 GS=1 GS=0 GS=1 00h G1 G320 G1 G320 01h G9 G312 G17 G304 02h G17 G304 G33 G288 03h G25 G296 G49 G272 04h G33 G288 G65 G256 05h G41 G280 G81 G240 06h G49 G272 G97 G224 07h G57 G264 G113 G208 08h G65 G256 G129 G192 09h G73 G248 G145 G176 0Ah G81 G240 G161 G160 0Bh G89 G232 G177 G144 0Ch G97 G224 G193 G128 0Dh G105 G216 G209 G112 0Eh G113 G208 G2 G96 0Fh G121 G200 G18 G80 10h G129 G192 G34 G64 11h G137 G184 G50 G48 12h G145 G176 G66 G32 13h G153 G168 G82 G16 14h G161 G160 G98 G319 15h G169 G152 G114 G303 16h G177 G144 G130 G287 17h G185 G136 G146 G271 18h G193 G128 G162 G255 19h G201 G120 G178 G239 1Ah G209 G112 G194 G223 1Bh G217 G104 G114 G207 1Ch G225 G96 G130 G191 1Dh G233 G88 G146 G175 1Eh G241 G80 G162 G159 1Fh G249 G72 G178 G143 20h G257 G64 G194 G127 21h G265 G56 G210 G111 22h G273 G48 G226 G95 23h G281 G40 G242 G79 24h G289 G32 G258 G63 25h G297 G24 G274 G47 26h G305 G16 G290 G31 27h G313 G8 G306 G15 28h ~ 3Fh Setting disabled Setting disabled Setting disabled Setting disabled NL[5:0]: Sets the number of lines to drive the LCD at an interval of 8 lines. The GRAM address mapping is not affected by the number of lines set by NL[5:0]. The number of lines must be the same or more than the number of lines necessary for the size of the liquid crystal panel.

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9325 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 73 of 107 Version: 0.43 NL[5:0] LCD Drive Line 6’h00 8 lines 6’h01 16 lines 6’h02 24lines … … 6’h1D 240 lines 6’h1E 248 lines 6’h1F 256 lines 6’h20 264 lines 6’h21 272 lines 6’h22 280 lines 6’h23 288 lines 6’h24 296 lines 6’h25 304 lines 6’h26 312 line 6’h27 320 line Others Setting inhibited NDL: Sets the source driver output level in the non-display area. Non-Display Area NDL Positive Polarity Negative Polarity

0 V63 V0

1 V0 V63

GS: Sets the direction of scan by the gate driver in the range determined by SCN[4:0] and NL[4:0]. The scan direction determined by GS = 0 can be reversed by setting GS = 1. When GS = 0, the scan direction is from G1 to G320. When GS = 1, the scan direction is from G320 to G1 REV: Enables the grayscale inversion of the image by setting REV=1. Source Output in Display Area REV GRAM Data Positive polarity negative polarity 18’h00000 18’h3FFFF V63 V63 18’h00000 18’h3FFFF V63 V63 VLE: Vertical scroll display enable bit. When VLE = 1, the ILI9325 starts displaying the base image from the line (of the physical display) determined by VL[8:0] bits. VL[8:0] sets the amount of scrolling, which is the number of lines to shift the start line of the display from the first line of the physical display. Note that the partial image display position is not affected by the base image scrolling. The vertical scrolling is not available in external display interface operation. In this case, make sure to

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9325 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 74 of 107 Version: 0.43 set VLE = “0”. VLE Base Image Display

0 Fixed

1 Enable Scrolling

VL[8:0]: Sets the scrolling amount of base image. The base image is scrolled in vertical direction and displayed from the line determined by VL[8:0]. Make sure that VL[8:0] ≦320. 7.2.26. Partial Image 1 Display Position (R80h) R/W RS D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 W 1 0 0 0 0 0 0 0 PTD P0[8] PTD P0[7] PTD P0[6] PTD P0[5] PTD P0[4] PTD P0[3] PTD P0[2] PTD P0[1] PTD P0[0] PTDP0[8:0]: Sets the display start position of partial image 1. The display areas of the partial images 1 and 2 must not overlap each another. 7.2.27. Partial Image 1 RAM St art/End Address (R81h, R82h) R/W RS D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 W 1 0 0 0 0 0 0 0 PTS A0[8] PTS A0[7] PTS A0[6] PTS A0[5] PTS A0[4] PTS A0[3] PTS A0[2] PTS A0[1] PTS A0[0] W 1 0 0 0 0 0 0 0 PTE A0[8] PTE A0[7] PTE A0[6] PTE A0[5] PTE A0[4] PTE A0[3] PTE A0[2] PTE A0[1] PTE A0[0] PTSA0[8:0] PTEA0[8:0]: Sets the start line address and the end line address of the RAM area storing the data of partial image 1. Make sure PTSA0[8:0] ≤ PTEA0[8:0]. 7.2.28. Partial Image 2 Display Position (R83h) R/W RS D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 W 1 0 0 0 0 0 0 0 PTD P1[8] PTD P1[7] PTD P1[6] PTD P1[5] PTD P1[4] PTD P1[3] PTD P1[2] PTD P1[1] PTD P1[0] PTDP1[8:0]: Sets the display start position of partial image 2 The display areas of the partial images 1 and 2 must not overlap each another. 7.2.29. Partial Image 2 RAM St art/End Address (R84h, R85h) R/W RS D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 W 1 0 0 0 0 0 0 0 PTS A1[8] PTS A1[7] PTS A1[6] PTS A1[5] PTS A1[4] PTS A1[3] PTS A1[2] PTS A1[1] PTS A1[0] W 1 0 0 0 0 0 0 0 PTE A1[8] PTE A1[7] PTE A1[6] PTE A1[5] PTE A1[4] PTE A1[3] PTE A1[2] PTE A1[1] PTE A1[0] PTSA1[8:0] PTEA1[8:0]: Sets the start line address and the end line address of the RAM area storing the data of partial image 2 Make sure PTSA1[8:0] ≤ PTEA1[8:0].

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9325 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 75 of 107 Version: 0.43 7.2.30. Panel Interface Control 1 (R90h) R/W RS D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 W 1 0 0 0 0 0 0 DIVI1 DIVI0 0 0 0 RTNI4 RTNI3 RTNI2 RTNI1 RTNI0 RTNI[4:0]: Sets 1H (line) clock number of internal clock operating mode. In this mode, ILI9325 display operation is synchronized with internal clock signal. RTNI[4:0] Clocks/Line RTNI[4:0] Clocks/Line 00000~01111 Setting Disabled 11000 24 clocks 10000 16 clocks 11001 25 clocks 10001 17 clocks 11010 26 clocks 10010 18 clocks 11011 27 clocks 10011 19 clocks 11100 28 clocks 10100 20 clocks 11101 29 clocks 10101 21 clocks 11110 30 clocks 10110 22 clocks 11111 31 clocks 10111 23 clocks DIVI[1:0]: Sets the division ratio of internal clock frequency. DIVI1 DIVI0 Division Ratio Internal Operation Clock Frequency 0 0 1 fosc / 1 0 1 2 fosc / 2 1 0 4 fosc / 4 1 1 8 fosc / 8 7.2.31. Panel Interface Control 2 (R92h) R/W RS D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 W 1 0 0 0 0 0 NOWI[2] NOWI[1] NOWI[0] 0 0 0 0 0 0 0 0 NOWI[2:0]: Sets the gate output non-overlap period when ILI9325 display operation is synchronized with internal clock signal. NOWI[2:0] Gate Non-overlap Period 000 0 clocks 001 1 clocks 010 2 clocks 011 3 clocks 100 4 clocks 101 5 clocks 110 6 clocks 111 7 clocks Note: The gate output non-overlap period is defined by the number of frequency-divided internal clocks, the frequency of which is determined by instruction (DIVI), from the reference point. 7.2.32. Panel Interface Control 4 (R95h) R/W RS D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 W 1 0 0 0 0 0 0 DIVE1 DIVE0 0 0 RTNE5 RTNE4 RTNE3 RTNE2 RTNE1 RTNE0 RTNE[5:0]: Sets 1H (line) clock number of RGB interface mode. In this mode, ILI9325 display operation is

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9325 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 76 of 107 Version: 0.43 synchronized with RGB interface signals. DIVE (division ratio) x RTNE (DOTCLKs) ≤ DOTCLKs in 1H period. RTNE[5:0] Clocks per line period (1H) RTNE[5:0] Clocks per line period (1H) RTNE[5:0] Clocks per line period (1H) RTNE[5:0] Clocks per line period (1H) 00h Setting Prohibited 10h 16 clocks 20h 32 clocks 30h 48 clocks 01h Setting Prohibited 11h 17 clocks 21h 33 clocks 31h 49 clocks 02h Setting Prohibited 12h 18 clocks 22h 34 clocks 32h 50 clocks 03h Setting Prohibited 13h 19 clocks 23h 35 clocks 33h 51 clocks 04h Setting Prohibited 14h 20 clocks 24h 36 clocks 34h 52 clocks 05h Setting Prohibited 15h 21 clocks 25h 37 clocks 35h 53 clocks 06h Setting Prohibited 16h 22 clocks 26h 38 clocks 36h 54 clocks 07h Setting Prohibited 17h 23 clocks 27h 39 clocks 37h 55 clocks 08h Setting Prohibited 18h 24 clocks 28h 40 clocks 38h 56 clocks 09h Setting Prohibited 19h 25 clocks 29h 41 clocks 39h 57 clocks 0ah Setting Prohibited 1ah 26 clocks 2ah 42 clocks 3ah 58 clocks 0bh Setting Prohibited 1bh 27 clocks 2bh 43 clocks 3bh 59 clocks 0ch Setting Prohibited 1ch 28 clocks 2ch 44 clocks 3ch 60 clocks 0dh Setting Prohibited 1dh 29 clocks 2dh 45 clocks 3dh 61 clocks 0eh Setting Prohibited 1eh 30 clocks 2eh 46 clocks 3eh 62 clocks 0fh Setting Prohibited 1fh 31 clocks 2fh 47 clocks 3fh 63 clocks DIVE[1:0]: Sets the division ratio of DOTCLK when ILI9325 display operation is synchronized with RGB interface signals. DIVE[1:0] Division Ratio 18/16-bit RGB Interface DOTCLK=5MHz 6-bit x 3 Transfers RGB Interface DOTCLK=5MHz

00 Setting Prohibited Setting Prohi bited - Setting Prohibited -

01 1/4 4 DOTCLKS 0.8 μs 12 DOTCLKS 0.8 μs 10 1/8 8 DOTCLKS 1.6 μs 24 DOTCLKS 1.6 μs 11 1/16 16 DOTCLKS 3.2 μs 48 DOTCLKS 3.2 μs 7.2.33. Panel Interface Control 5 (R97h) R/W RS D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 W 1 0 0 0 0 NOWE3 NOWE2 NOWE1 NOWE0 0 0 0 0 0 0 0 0 NOWE[2:0]: Sets the gate output non-overlap period when the ILI9320 display operation is synchronized with RGB interface signals. NOWE[3:0] Gate Non-overlap Period NOWE[3:0] Gate Non-overlap Period 0000 0 clocks 1000 8 clocks 0001 1 clocks 1001 9 clocks 0010 2 clocks 1010 10 clocks 0011 3 clocks 1011 11 clocks 0100 4 clocks 1100 12 clocks 0101 5 clocks 1101 13 clocks 0110 6 clocks 1110 14 clocks 0111 7 clocks 1111 15 clocks Note: 1 clock = (number of data transfer/pixel) x DIVE (division ratio) [DOTCLK] 7.2.34. OTP VCM Programming Control (RA1h) R/W RS D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 W 1 0 0 0 0 OTP_ PGM_EN 0 0000 VCM_ OTP5 VCM_ OTP4 VCM_ OTP3 VCM_ OTP2 VCM_ OTP1 VCM_ OTP0 OTP_PGM_EN: OTP programming enable. When program OTP, must set this bit. OTP data can be

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9325 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 77 of 107 Version: 0.43 programmed 3 times. VCM_OTP[5:0]: OTP programming data for VCOMH voltage, the voltage refer to VCM[5:0] value. 7.2.35. OTP VCM Status and Enable (RA2h) R/W RS D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 W 1 PGM_ CNT1 PGM_ CNT0 VCM_ VCM_ VCM_ VCM_ VCM_ VCM_ D0 0 0 0 0 0 0 0 VCM_ EN PGM_CNT[1:0]: OTP programmed record. These bits are read only. OTP_PGM_CNT[1:0] Description

00 OTP clean

01 OTP programmed 1 time

10 OTP programmed 2 times

11 OTP programmed 3 times

VCM_D[5:0]: OTP VCM data read value. These bits are read only. VCM_EN: OTP VCM data enable. ’1’: Set this bit to enable OTP VCM data to replace R29h VCM value. ’0’: Default value, use R29h VCM value. 7.2.36. OTP Programming ID Key (RA5h) R/W RS D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 W 1 KEY KEY KEY KEY KEY KEY KEY KEY KEY KEY KEY KEY KEY KEY KEY KEY KEY[15:0]: OTP Programming ID key protection. Before writing OTP programming data RA1h, it must write RA5h with 0xAA55 value first to make OTP programming successfully. If RA5h is not written with 0xAA55, OTP programming will be fail. See OTP Programming flow.

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9325 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 78 of 107 Version: 0.43 8. OTP Programming Flow N Start Power On ILI9325 Check OTP_PGM_CNT=11? Supply External 7.0V to DDVDH Wait 10ms Set ID Key RA5h=0xAA55 Program OTP VCM Data RA1h=0x08xx (xx=6 bit VCM value) Wait 10ms Cut Off External 7.0V Power Reset End Y

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9325 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 79 of 107 Version: 0.43 9. GRAM Address Map & Read/Write ILI9325 has an internal graphics RAM (GRAM) of 87,120 bytes to store the display data and one pixel is constructed of 18 bits. The GRAM can be accessed through the i80 system, SPI and RGB interfaces. i 80 18-/16-bi t System Bus Interface Ti mi ng Write “0022h＂ to index register Write GRAM “data＂ Nth pixel nWR DB[ 17:0] nRD RS nCS (a) Write to GRAM nWR DB[ 17:0] nRD RS nCS (b) Re a d from GRAM i80 9-/8-bit S ystem Bus Interface Timing (a) Write to GRAM (b) Re a d from GRAM Write GRAM “data＂ (N+1)th pixel Write GRAM “data＂ (N+2)th pixel Write GRAM “data＂ (N+3)th pixel Write “0022h＂ to index register 1st Read “data＂ Nth pi xel Dummy Read 2nd Read “ data＂ (N+1)th pixel 3rd Read “data＂ (N+2)th pixel “00h＂ Nth pixel nWR DB[ 17:9] nRD RS nCS “22h＂ 1st write high byte 1st wri te lo w byte (N+1)th pixel 2nd write high byte 2nd write low byte (N+2)th pixel 3rd wri te high byte 3rd wri te low byte “00h＂ Nth pixel nWR DB[ 17:9] nRD RS nCS “22h＂ Dummy Read 1 Dummy Read 2 (N+1)th pixel 1st read high byte 1st read low byte 2nd read high byte 2nd read low byte Figure31 GRAM Read/Write Timing of i80-System Interface

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9325 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 80 of 107 Version: 0.43 GRAM address map table of SS=0, BGR=0 SS=0, BGR=0 S1…S3 S4…S6 S7…S9 S10…S12 … S517…S519 S520…S522 S523…S525 S526…S720 GS=0 GS=1 DB17…0 DB17…0 DB17…0 DB17…0 … DB17…0 DB17…0 DB17…0 DB17…0

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9325 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 81 of 107 Version: 0.43 DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB i80/M68 system 16-bit data bus interf ace GRAM Data RGB A ssi gnment R5 R4 R3 R2 R1 R0 G5 G4 G2 G1 G0 B5 B4 B3 B2 B1G3 S (3n+1)Source Output Pin S (3n+2) S (3n+3) N=0 to 175 DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB i80/M68 system 18-bit data bus interf ace GRAM Data RGB A ssi gnment R5 R4 R3 R2 R1 R0 G5 G4 G2 G1 G0 B5 B4 B3 B2 B1G3 S (3n+1)Source Output Pin S (3n+2) S (3n+3) N=0 to 175 DB DB DB DB DB DB DB DB DB i80/M68 system 9-bit data bus interf ace GRAM Data RGB A ssi gnment R5 R4 R3 R2 R1 R0 G5 G4 G2 G1 G0 B5 B4 B3 B2 B1G3 S (3n+1)Source Output Pin S (3n+2) S (3n+3) N=0 to 175 DB DB DB DB DB DB DB DB DB 1st Transfer 2nd Transfer GRAM Data and display data of 18-/16-/9-bit system interface (S S=＂0", BGR=＂0") Figure32 i80-System Interface with 18-/16-/9-bit Data Bus (SS=”0”, BGR=”0”)

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9325 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 82 of 107 Version: 0.43 i 80/M68 system 8-bi t i nterface / SPI Interf ace (2 transf ers/pi xel ) DB DB DB DB DB DB DB DB 10GRAM Data RGB Assignment R5 R4 R3 R2 R1 R0 G5 G4 G2 G1 G0 B5 B4 B3 B2 B1G3 S (3n+1)Source Output Pin S (3n+2) S (3n+3) N=0 to 175 GRAM Data RGB Assignment Source Output Pin i 80/M68 system 8-bi t i nterf ace (SS=＂0", BGR=＂0") DB DB DB DB DB DB DB DB i 80/M68 system 8-bi t i nterface (3 transf ers/pixel , TRI=＂1", DFM[1:0]=＂00") GRAM Data RGB Assignment R5 R4 R3 R2 R1 R0 G5 G4 G2 G1 G0 B5 B4 B3 B2 B1G3 S (3n+1)Source Output Pin S (3n+2) S (3n+3) N=0 to 175 1st Transfer 2nd Transfer 3rd Transfer i 80/M 68 system 8-bi t i nterf ace (3 transf ers/pi xel , TRI =＂1", DFM[ 1:0] =＂10) DB DB DB DB DB DB R5 R4 R3 R2 R1 R0 G5 G4 G2 G1 G0 B5 B4 B3 B2 B1G3 N=0 to 175 1st Transfer 2nd Transfer DB DB DB DB DB DB DB DB DB DB DB DB 3rd Transfer 1s t tra ns fe r 2nd transfer DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB Figure33 i80-System Interface with 8-bit Data Bus (SS=”0”, BGR=”0”)

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9325 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 83 of 107 Version: 0.43 GRAM address map table of SS=1, BGR=1 SS=1, BGR=1 S720…S718 S717…S715 S714…S712 S711…S709 … S12…S10 S9…S7 S6…S4 S3…S1 GS=0 GS=1 DB17…0 DB17…0 DB17…0 DB17…0 … DB17…0 DB17…0 DB17…0 DB17…0

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9325 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 84 of 107 Version: 0.43 DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB i 80/M68 system 18-bi t data bus i nterface GRAM Data RGB Assignment R5 R4 R3 R2 R1 R0 G5 G4 G2 G1 G0 B5 B4 B3 B2 B1G3 S (528-3n)Source Output Pi n S (527-3n) S (526-3n) N=0 to 175 DB DB DB DB DB DB DB DB DB i 80/M68 system 9-bi t data bus i nterface GRAM Data RGB Assignment R5 R4 R3 R2 R1 R0 G5 G4 G2 G1 G0 B5 B4 B3 B2 B1G3 Source Output Pi n N=0 to 175 DB DB DB DB DB DB DB DB DB 1st Transfer 2nd Transfer GRAM Data and display data of 18-/9-bit system interf ace (SS=＂ 1", BGR=＂1") Figure 34 i80-System Interface with 18-/9-bit Data Bus (SS=”1”, BGR=”1”)

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9325 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 85 of 107 Version: 0.43 10. Window Address Function The window address function enables writing display data consecutively in a rectangular area (a window address area) made on the internal RAM. The window address area is made by setting the horizontal address register (start: HSA[7:0], end: HEA[7:0] bits) and the vertical address register (start: VSA[8:0], end: VEA[8:0] bits). The AM bit sets the transition direction of RAM address (either increment or decrement). These bits enable the ILI9325 to write data including image data consecutively not taking data wrap positions into account. The window address area must be made within the GRAM address map area. Also, the GRAM address bits (RAM address set register) must be an address within the window address area. [Window address setting area] (Horizontal direction) 00H ≤ HSA[7:0] ≤ HEA[7:0] ≤ “EF”H (Vertical direction) 00H ≤ VSA[8:0] ≤ VEA[8:0]≤ “13F”H [RAM address, AD (an address within a window address area)]] (RAM address) HSA[7:0] ≤ AD[7:0] ≤ HEA[7:0] VSA[8:0] ≤ AD[15:8] ≤ VEA[8:0] “00000＂h “000EF＂h “13FEF＂h“13F00＂h 2010h 203Fh 4F3Fh4F10h 2110h 213Fh Window Address Area Window address setting area HSA[7:0] = 10h, HSA[ 7:0] = 3Fh, I/D = 1 (increment) VSA[8:0] = 20h, VSA[ 8:0] = 4Fh, AM = 0 (horizontal writing ) GRA M A ddress M ap Figure 35 GRAM Access Window Map

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9325 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 86 of 107 Version: 0.43 11. Gamma Correction ILI9325 incorporates the γ-correction function to display 262,144 colors for the LCD panel. The γ-correction is performed with 3 groups of registers determining eight reference grayscale levels, which are gradient adjustment, amplitude adjustment and fine-adjustment regi sters for positive and negative polarities, to make ILI9325 available with liquid crystal panels of various characteristics. 8 to 1 s e le ction 8 to 1 sel ecti on 8 to 1 s e le ction 8 to 1 s e le ctio n 8 to 1 sel ecti on 8 to 1 sel ect i on PRP/ N0 Gradi ent Adjus tme nt Regi ster PRP/N1 VRP /N0 Ampl itude Adjus tme nt Regi ster VRP /N1PK P/N5 Fine Adjus tme nt Re giste rs (6 x 3 bits ) VgP 0/VgN0 VgP 1/VgN1 VgP 8/VgN8 VgP 20/VgN20 VgP 43/VgN43 VgP 55/VgN55 VgP 62/VgN62 VgP 63/VgN63 …... V20 V43 V55 V62 …... V63 V61 V56 VREG1OUT VGS PK P/ N4 PK P/ N3 PK P/ N2 PK P/N1 PK P/N0 Figure 36 Grayscale Voltage Generation

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9325 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 87 of 107 Version: 0.43 VgP 0 VP 1 VP 2 VP 3 VP 4 VP 5 VP 6 VP 7 VP 8 RP1 RP2 RP3 RP4 RP5 RP6 RP7 RP15 VP 25 VP 26 VP 27 VP 28 VP 29 VP 30 VP 31 VP 32 RP24 RP25 RP26 RP27 RP28 RP29 RP30 RP23 VP 33 VP 34 VP 35 VP 36 VP 37 VP 38 VP 39 VP 40 RP31 RP46 RP47 8 to 1 Sel ect i on 8 to 1 S e le ction VP 9 VP 10 VP 11 VP 12 VP 13 VP 14 VP 15 VP 16 RP8 RP9 RP10 RP11 RP12 RP13 RP14 VgP 1 VgP 8 VP 17 VP 18 VP 19 VP 20 VP 21 VP 22 VP 23 VP 24 RP16 RP17 RP18 RP19 RP20 RP21 RP22 VROP 0 0 ~ 30R PK P0[ 2:0] PK P1[ 2:0] 8 to 1 S e le ctio n VgP 20 PK P2[ 2:0] 8 to 1 Sel ect i on VgP 43 PK P3[ 2:0] VRCP0 0 ~ 28R 5R5R VRP 0[4:0] PRP0[ 2:0] PRP1[ 2: 0] VRP 1[4:0] RP33 RP34 RP35 RP36 RP37 RP38 RP32 8 to 1 Sel ect i on VgP 55 PK P4[ 2:0] VP 41 VP 42 VP 43 VP 44 VP 45 VP 46 VP 47 VP 48 RP40 RP41 RP42 RP43 RP44 RP45 RP39 8 to 1 S e le ctio n VgP 62 PK P5[ 2:0] VgP 63VP 495R VROP 1 0 ~ 31R VgN0 VN1 VN2 VN3 VN4 VN5 VN6 VN7 VN8 RN1 RN2 RN3 RN4 RN5 RN6 RN7 RN15 VN25 VN26 VN27 VN28 VN29 VN30 VN31 VN32 RN24 RN25 RN26 RN27 RN28 RN29 RN30 RN23 VN33 VN34 VN35 VN36 VN37 VN38 VN39 VN40 RN31 RN46 RN47 8 to 1 Sel ect i on 8 to 1 S e le ction VN9 VN10 VN11 VN12 VN13 VN14 VN15 VN16 RN8 RN9 RN10 RN11 RN12 RN13 RN14 VgN1 VgN8 VN17 VN18 VN19 VN20 VN21 VN22 VN23 VN24 RN16 RN17 RN18 RN19 RN20 RN21 RN22 VR ON0 0 ~ 30R PK N0[ 2: 0] PK N1[ 2: 0] 8 to 1 S e le ctio n VgN20 PK N2[ 2: 0] 8 to 1 Sel ect i on VgN43 PK N3[ 2: 0] VRCP0 0 ~ 28R 5R5R VRN0[4:0] PRN0[ 2:0] PRN1[ 2: 0] VRN1[4:0] RN33 RN34 RN35 RN36 RN37 RN38 RN32 8 to 1 Sel ect i on VgN55 PK N4[ 2: 0] VN41 VN42 VN43 VN44 VN45 VN46 VN47 VN48 RN40 RN41 RN42 RN43 RN44 RN45 RN39 8 to 1 S e le ctio n VgN62 PK N5[ 2: 0] VgN63VN495R VR ON1 0 ~ 31R VREG1OUT VGS RN0RP0 VRCP1 0 ~ 28R VR CN1 0 ~ 28R 1uF/10V Figure 37 Grayscale Voltage Adjustment

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9325 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 88 of 107 Version: 0.43 1. Gradient adjustment registers The gradient adjustment registers are used to adjust the gradient of the curve representing the relationship between the grayscale and the grayscale reference voltage level. To adjust the gradient, the resistance values of variable resistors in the middle of the ladder resistor are adjusted by registers PRP0[2:0]/PRN0[2:0], PRP1[2:0]/PRN1[2:0]. The regist ers consist of positive and negative polarity registers, allowing asymmetric drive. 2. Amplitude adjustment registers The amplitude adjustment registers, VRP0[3:0]/VRN0[3:0], VRP1[4:0]/VRN1[4:0], are used to adjust the amplitude of grayscale voltages. To adjust the amplitude, the resistance values of variable resistors at the top and bottom of the ladder resistor are adjusted. Same as the gradient registers, the amplitude adjustment registers consist of positive and negative polarity registers. 3. Fine adjustment registers The fine adjustment registers are used to fine-adjust grayscale voltage levels. To fine-adjust grayscale voltage levels, fine adjustment registers adjust the reference voltage levels, 8 levels for each register generated from the ladder resistor, in respective 8-to -1 selectors. Same with other registers, the fine adjustment registers consist of positive and negative polarity registers. Gradient adj ustment Grayscal e vol t age Ampl itude adjustment Grayscal e vol tage Fine adjustment Grayscal e vol tage Figure 38 Gamma Curve Adjustment Register Groups Positive Polarity Negative Polarity Description PRP0 [2:0] PRN0 [2 :0] Variable resistor VRCP0, VRCN0 Gradient adjustment PRP1 [2:0] PRN1 [2 :0] Variable resistor VRCP1, VRCN1 VRP0 [3:0] VRN0 [3 :0] Variable resi stor VROP0, VRON0 Amplitude adjustment VRP1 [4:0] VRN1 [4 :0] Variable resi stor VROP1, VRON1 KP0 [2:0] KN0 [2:0] 8- to-1 selector (voltage level of grayscale 1) KP1 [2:0] KN1 [2:0] 8- to-1 selector (voltage level of grayscale 8) KP2 [2:0] KN2 [2:0] 8- to-1 selector (voltage level of grayscale 20) KP3 [2:0] KN3 [2:0] 8- to-1 selector (voltage level of grayscale 43) KP4 [2:0] KN4 [2:0] 8- to-1 selector (voltage level of grayscale 55) Fine adjustment KP5 [2:0] KN5 [2:0] 8- to-1 selector (voltage level of grayscale 62)

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9325 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 89 of 107 Version: 0.43 Ladder resistors and 8-to-1 selector Block configuration The reference voltage generating block consists of two ladder resistor units including variable resistors and 8-to-1 selectors. Each 8-to-1 selector selects one of the 8 voltage levels generated from the ladder resistor unit to output as a grayscale reference voltage. Both variable resistors and 8-to-1 selectors are controlled according to the γ-correction registers. This unit has pins to connect a volume resistor externally to compensate differences in various characteristics of panels. Variable resistors ILI9325 uses variable resistors of the following three purposes: gradient adjustment (VRCP(N)0/VRCP(N)1); amplitude adjustment (1) (VROP(N)0); and the amplitude adjustment (2) (VROP(N)1). The resistance values of these variable resistors are set by gradient adjustment registers and amplitude adjustment registers as follows. Gradient adjustment Amplitude adju stment (1) Amplitude adjustment (2) PRP(N)0/1[2:0] Register VRCP(N)0 Resistance VRP(N)0[3:0] Register VROP(N)0 Resistance VRP(N)1[4:0] Register VROP(N)1 Resistance 000 0R 0000 0R 00000 0R 001 4R 0001 2R 00001 1R 010 8R 0010 4R 00010 2R 011 12R : : : : 100 16R : : : : 101 20R 1101 26R 11101 29R 110 24R 1111 28R 11110 30R 111 28R 1111 30R 11111 31R 8-to-1 selectors The 8-to-1 selector selects one of eight voltage levels generated from the ladder resistor unit according to the fine adjustment register and output the selected voltage level as a reference grayscale voltage (VgP(N)1~6). The table below shows the setting in the fine adjustment register and the selected voltage levels for respective reference grayscale voltages. Fine adjustment registers and selected voltage Register Selected Voltage KP(N)[2:0] VgP(N)1 VgP(N)8 VgP(N)20 VgP(N)43 VgP(N)55 VgP(N)62

000 VP(N)1 VP(N)9 VP(N)17 VP(N)25 VP(N)33 VP(N)41

001 VP(N)2 VP(N)10 VP(N)18 VP(N)26 VP(N)34 VP(N)42

010 VP(N)3 VP(N)11 VP(N)19 VP(N)27 VP(N)35 VP(N)43

011 VP(N)4 VP(N)12 VP(N)20 VP(N)28 VP(N)36 VP(N)44

100 VP(N)5 VP(N)13 VP(N)21 VP(N)29 VP(N)37 VP(N)45

101 VP(N)6 VP(N)14 VP(N)22 VP(N)30 VP(N)38 VP(N)46

110 VP(N)7 VP(N)15 VP(N)23 VP(N)31 VP(N)39 VP(N)47

111 VP(N)8 VP(N)16 VP(N)24 VP(N)32 VP(N)40 VP(N)48

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9325 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 91 of 107 Version: 0.43 12. Application 12.1. Configuration of Power Supply Circuit < 100 ohm< 100 ohm < 100 ohm Fmark nCS RS nWR nRDSDI SDO DB0 DB1DB2 DB3DB4 DB5DB6 DB7 DB8 DB9DB10 DB11DB12 DB13 DB14 DB15DB16 DB17ENABLE DOTCLKHSYNC VS YNC nRESET IM3 IM2IM1 IM0 < 15 ohm < 15 ohm < 15 ohm < 15 ohm < 15 ohm < 15 ohm < 15 ohm < 5 ohm < 20 ohm < 10 ohm < 5 ohm < 5 ohm < 100 ohm < 100 ohm < 100 ohm< 100 ohm < 100 ohm < 100 ohm < 100 ohm < 100 ohm< 100 ohm < 100 ohm < 100 ohm < 100 ohm< 100 ohm < 100 ohm < 100 ohm < 100 ohm < 100 ohm 1uF/10V 1uF/25V 1uF/25V IOVC C VCI X Face Up (Bump Vi ew) DUMMY23 S361 S362 S363 S364 S365 S366 S367 S368 S369 x y S353 S354 S355 S356 S357 S358 S359 S360 DUMMY24 G304 G306 G308 G310 G312 G314 G316 G318 G320 DUMMY20 DUMMY21 G10 G12 G14 G16 G18 S712 S713 S714 S715 S716 S717 S718 S719 S720 DUMMY22 ………… DUMMY27 G319 G317 G315 G313 G311 G309 G307 G305 G303 G17 G15 G13 G11 DUMMY26 DUMMY25 DUMMY1 TEST1 IOGNDDUM TESTO1 TESTO2 TESTO3 IM0 /ID IM1 IM2 IM3 TEST2 TESTO4 TESTO5 TESTO6 TESTO7 TESTO8 TESTO9 TESTO10 nRESET nRESET VSYNC HSYNC DOTCLK ENABLE DB17 DB16 DB15 DB14 DB13 TESTO11 DB12 DB11 DB10 DB9 DB8 TEST3 TESTO12 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 TESTO13 S DO SDI nRD nWR/SCL RS nCS TESTO14 TESTO15 FMARK TESTO16 TS8 TS7 TS6 TS5 TS4 TS3 TS2 TS1 TS0 DUMMY2 IO VCC IO VCC IO VCC IO VCC IOVCC IOVCC VDDD VDDD VDDD VDDD VDDD VDDD VDDD VDDD VDDD VDDD VDDD DUMMY3 GND GND GND GND GND GND GND GND VG S VG S GND GND GND GND GND GND GND GND GND GND DUMMY4 DUMMY5 DUMMY6 VCOM VCOM VCOM VCOM VCOM VCOM VCOM VCOMH VCOMH VCOMH VCOMH VCOMH VCOMH VCOML VCOML VCOML VCOML VREG1OUT VREG1OUT VREG1OUT DUMMY7 DUMMY8 DUMMY9 VCL VCL VCL VCL VCL DDVDH DDVDH DDVDH DDVDH DDVDH DDVDH VCI1 VCI1 VCI1 VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI DUMMY10 DUMMY11 C12- C12- C12- C12- C12- C12+ C12+ C12+ C12+ C12+ C11- C11- C11- C11- C11- C11+ C11+ C11+ C11+ C11+ VG L VG L VG L VG L VG L VG L VG L VG L VG L VG L GND GND GND VGH VGH VGH VG H VG H VG H DUMMY12 DUMMY13 C13- C13- C13- C13- C13+ C22- C22- C22- C22- C22+ C22+ C22+ C22+ C22+ C22+ C13+ C13+ C13+ C21- C21- C21- C21- C21- C21- C21- C21+ C21+ C21+ C21+ C21+ C21+ C21+ C22- C22- C22- C22+ DUMMY14 DUMMY15 < 100 ohm < 100 ohm < 100 ohm 1uF/10V 1uF/6.3V < 40 ohm 1uF/6.3V 1uF/6.3V 1uF/6.3V 1uF/10V 1uF/6.3V 1uF/6.3V 1uF/6.3V 1uF/6.3V 1uF/6.3V < 50 ohm < 15 ohm < 100 ohm< 100 ohm < 100 ohm < 100 ohm < 100 ohm< 100 ohm< 100 ohm < 100 ohm< 100 ohm < 100 ohm< 100 ohm < 100 ohm< 100 ohm< 100 ohm < 100 ohm < 100 ohm < 10 ohm < 20 ohm < 20 ohm < 20 ohm < 15 ohm < 15 ohm < 10 ohm < 10 ohm < 10 ohm < 10 ohm < 15 ohm To Panel To Panel VCL VCL DDVDH Figure 41 Power Supply Circuit Block

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9325 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 92 of 107 Version: 0.43 The following table shows specifications of external elements connected to the ILI9325’s power supply circuit. Items Recommended Specification Pin connection 6.3V VREG1OUT, VCI1, VDDD, VCL, VCOMH, VCOML, C11+/-, C12+/-, C13+/-, 10V DDVDH, C21+/-, C22+/- Capacity 1 µF (B characteristics) 25V VGH, VGL Schottky diode VF<0.4V/20mA at 25°C, VR ≥30V (Recommended diode: HSC226) (VCL – VGL), (DDVDH – VGH), (Vci – DDVDH)

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9325 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 93 of 107 Version: 0.43 12.2. Display ON/OFF Sequence Figure 42 Display On/Off Register Setting Sequence

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9325 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 94 of 107 Version: 0.43 12.3. Standby and Sleep Mode Set Standby (STB = 1) Display Off Sequence Release from Standby (STB = 0) R10 ← 0190h Display On Sequence Standby Set Sleep (SLP = 1) Display Off Sequence Release from Sleep (SLP = 0) R10 ← 0190h Display On Sequence Sleep Release from standby Release from Sleep 80ms or more Stabilizing time 80ms or more Stabilizing time Figure 43 Standby/Sleep Mode Register Setting Sequence

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9325 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 95 of 107 Version: 0.43 12.4. Power Supply Configuration When supplying and cutting off power, follow the sequence below. The setting time for step-up circuits and operational amplifiers depends on external resistance and capacitance. Power Supply ON (VCC, VCI, IOVCC) VCI IOV CC GND VCI IOVCC or VCI, IOVCC Simultaneously Power On Reset and Display OFF Registers setting before power supply startup Display OFF Setting DTE = 0 D[1:0] = 00 GON = 0 PON = 0 50ms or more Stabilizing time LCD Power Supply ON Sequence Power supply initial setting Set VC[2:0], VRH[3:0], VCM[5;0], VDV[5:0], PON=0,BT[2:0] = 000 Registers setting for power supply startup 80ms or more Step-up circuit stabilizing time Power supply operation setting Set BT[2:0],PON = 1, Set AP[2:0],APE=1, Set DC1[2:0], DC0[2:0] Set the other registers Display ON Sequence Display ON Operational Amplifier stabilizing time Set SAP=1 DTE=1 D[1:0]=11 GON=1 Normal Display Display OFF Sequence Display OFF Power Supply Halt Setting Display ON Setting DTE=1 D[1:0]=11 GON=1 SAP=0 AP[2:0] = 000 PON = 0 Power Supply OFF (VCC, VCI, IOVCC) VCIIOVCC GND IOVCC VCI Or IOVCC, VCI Simultaneously Figure 44 Power Supply ON/OFF Sequence

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9325 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 96 of 107 Version: 0.43 12.5. Voltage Generation The pattern diagram for setting the voltages and the waveforms of the voltages of the ILI9325 are as follows. Vci (2.5 ~ 3.3V) VGH (+9 ~ 16.5V) VLCD (4.5 ~ 5.5V) VREG1OUT (3.0 ~ (VLCD-0.2)V ) VCOMH (3.0 ~ (VLCD-0.2)V ) VCOML (VCL+0.5) ~ -1V ) VCL (0 ~ -3.3V) Figure 45 Voltage Configuration Diagram Note: The DDVDH, VGH, VGL, and VCL output voltage le vels are lower than their theoretical levels (ideal voltage levels) due to current consumption at respective outputs. The voltage levels in the following relationships (DDVDH – VREG1OUT ) > 0.2V and (VCOML – VCL) > 0.5V are the actual voltage levels. When the alternating cycles of VCOM are set high (e.g. the polarity inverts every line cycle), current consumption is large. In this case, check the voltage before use.

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9325 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 97 of 107 Version: 0.43 12.6. Applied Voltage to the TFT panel Source outputVCOM Gate Output VGH VGL Figure 46 Voltage Output to TFT LCD Panel 12.7. Partial Display Function The ILI9325 allows selectively driving two partial images on the screen at arbitrary positions set in the screen drive position registers. The following example shows the setting for partial display function: Base Image Display Setting BASEE 0 NL[5:0] 6’h27 Partial Image 1 Display Setting PTDE0 1 PTSA0[8:0] 9’h000 PTEA0[8:0] 9’h00F PTDP0[8:0] 9’h080 Partial Image 2 Display Setting PTDE1 1 PTSA1[8:0] 9’h020 PTEA1[8:0] 9’h02F PTDP1[8:0] 9’h0C0

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9325 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 98 of 107 Version: 0.43 0 (1st line) 1 (2nd line) 2 (3rd line) Parti al I mage 1 Display Area Par ti al I mage 1 GRAM Area Par ti al I mage 2 GRAM Area Parti al I mage 1 Display Area 319 (320th line) GRAM MAP LCD Panel PTSA0=9'h000 PTEA0=9'h00F PTSA1=9'h020 PTEA1=9'h02F PTDP0=9'h080 PTDP1=9'h0C0 Figure 47 Partial Display Example 12.8. Resizing Function ILI9325 supports resizing function (x1/2, x1/4), which is performed when writing image data to GRAM. The resizing function is enabled by setting a window addre ss area and the RSZ bit which represents the resizing factor (x1/2, x1/4) of image. The resizing function allows the system to transfer the original-size image data into the GRAM with resized image data.

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9325 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 100 of 107 Version: 0.43 X Y Original Image Size (X0, Y0) (X0+dx-1, Y0+dy-1) dx dy dx= (X-H)/N, H=X mod N dy= (Y-V)/N, V=Y mod N GRAM Address Original image data number in horizontal direction X Original image data number in Vertical direction Y Resizing Ration 1/N Resizing Setting RSZ N-1 Remainder pixels in horizontal direction RCH H Remainder pixels in vertical direction RCV V GRAM writing start address AD (x0, y0) HSA x0 HEA x0+dx-1 VSA y0 GRAM window setting VEA y0+dy-1

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9325 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 101 of 107 Version: 0.43 13. Electrical Characteristics 13.1. Absolute Maximum Ratings The absolute maximum rating is listed on following table. When ILI9325 is used out of the absolute maximum ratings, the ILI9325 may be permanently damaged. To use the ILI9325 within the following electrical characteristics limit is strongly recommended for normal operation. If these electrical characteristic conditions are exceeded during normal operation, the ILI9325 will malfunction and cause poor reliability. Item Symbol Unit Value Note Power supply voltage (1) IOVCC V -0.3 ~ + 4.6 1, 2 Power supply voltage (1) VCI - GND V -0.3 ~ + 4.6 1, 4 Power supply voltage (1) DDVDH - GND V -0.3 ~ + 6.0 1, 4 Power supply voltage (1) GND -VCL V -0.3 ~ + 4.6 1 Power supply voltage (1) DDVDH - VCL V -0.3 ~ + 9.0 1, 5 Power supply voltage (1) VGH - GND V -0.3 ~ + 18.5 1, 5 Power supply voltage (1) GND - VGL V -0.3 ~ + 18.5 1, 6 Input voltage Vt V -0.3 ~ VCC+ 0.3 1 Operating temperature Topr °C -40 ~ + 85 8, 9 Storage temperature Tstg °C -55 ~ + 110 8, 9 Notes: 1. GND must be maintained 2. (High) (VCC = VCC) ≥ GND (Low), (High) IOVCC ≥ GND (Low). 3. Make sure (High) VCI ≥ GND (Low). 4. Make sure (High) DDVDH ≥ GND (Low). 5. Make sure (High) DDVDH ≥ VCL (Low). 6. Make sure (High) VGH ≥ GND (Low). 7. Make sure (High) GND ≥ VGL (Low). 8. For die and wafer products, specified up to 85°C. 9. This temperature specifications apply to the TCP package

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9325 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 102 of 107 Version: 0.43 13.2. DC Characteristics (VCC = VCI=2.40 ~ 3.0V, IOVCC = 1.65 ~ 3.30V, Ta= -40 ~ 85 °C) Item Symbol Unit Test Condition Min. Typ. Max. Note Input high voltage V IH V IOVCC= 1.8 ~ 3.3V 0.8*IOV CC - IOVCC - Input low voltage V IL V IOVCC= 1.8 ~ 3.3V -0.3 - 0.2*IOVCC - Output high voltage(1) ( DB0-17 Pins) VOH1 V IOH = -0.1 mA 0.8*IOV CC - - - Output low voltage ( DB0-17 Pins) VOL1 V IOVCC=1.65~3.3V - - 0.2*IOVCC - I/O leakage current I LI µA Vin = 0 ~ VCC -0.1 - 0.1 - Current consumption during normal operation CC – GND ) IOP µA VCC=2.8V , Ta=25°C , fOSC = 512KHz ( Line) GRAM data = 0000h - 100 (VCC) - - Current consumption during standby mode CC – GND ) IST µA VCI=2.8V , Ta=25 °C - 30 50 - LCD Drive Power Supply Current ( DDVDH-GND ) ILCD mA VCI=2.8V , VREG1OUT =4.8V DDVDH=5.2V , Frame Rate: 70Hz, line-inversion, Ta=25 °C, GRAM data = 0000h, - 5.5 - - LCD Driving Voltage ( DDVDH-GND ) DDVDH V - 4.5 - 6 - Output deviation voltage VDEV mV - - - 20 - Output offset voltage VOFFSET mV Note1 - - 35 - Note1: The Max. value is between with measure point and Gamma setting value. 13.3. Reset Timing Characteristics Reset Timing Characteristics (IOVCC = 1.65 ~ 3.3 V) Item Symbol Unit Min. Typ. Max. Reset low-level width t RES_L ms 1 - - Reset rise time t rRES µs - - 10 Reset high-level width t RES_H ms 50 - - 13.4. AC Characteristics 13.4.1. i80-System Inte rface Timing Characteristics Normal Write Mode (IOVCC = 1.65~3.3V) Item Symbol Unit Min. Typ. Max. Test Condition Bus cycle time Write tCYCW ns 100 - - -

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9325 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 103 of 107 Version: 0.43 Read tCYCR ns 300 - - - Write low-level pulse width PWLW ns 50 - - - Write high-level pulse width PWHW ns 50 - - - Read low-level pulse width PWLR ns 150 - - - Read high-level pulse width PWHR ns 150 - - Write / Read rise / fall time tWRr/tWRf ns - - 25 Write ( RS to nCS, E/nWR ) 10 - - Setup time Read ( RS to nCS, RW/nRD ) tAS ns 5 - - Address hold time tAH ns 5 - - Write data set up time tDSW ns 10 - - Write data hold time tH ns 15 - - Read data delay time tDDR ns - - 100 Read data hold time tDHR ns 5 - - VIH VIL VIH VIL VIL tAS tWRf VIL VIH tAH tWRr VIH tCYCW , tCYCR VIH VIL VIH VIL VIH VOH VOL VOH VOL tDDR tDHR tDSW tH PW LW, PW LR PW HW, PW HR RS nCS nWR, nRD Write Data DB[17:0] Read Data DB[17:0] Va lid Da ta Va lid Da ta Figure 50 i80-System Bus Timing 13.4.2. Serial Data Transfer Interface Timing Characteristics (IOVCC= 1.65 ~ 3.3V) Item Symbol Unit Min. Typ. Max. Test Condition Write ( received ) tSCYC ns 100 - - Serial clock cycle time Read ( transmitted ) tSCYC ns 200 - - Write ( received ) tSCH ns 40 - - Serial clock high – level pulse width Read ( transmitted ) tSCH ns 100 - - Write ( received ) tSCL ns 40 - - Serial clock low – level pulse width Read ( transmitted ) tSCL ns 100 - - Serial clock rise / fall time tSCr, tSCf ns - - 5

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9325 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 104 of 107 Version: 0.43 Item Symbol Unit Min. Typ. Max. Test Condition Chip select set up time tCSU ns 10 - - Chip select hold time tCH ns 50 - - Serial input data set up time tSISU ns 20 - - Serial input data hold time tSIH ns 20 - - Serial output data set up time tSOD ns - - 100 Serial output data hold time tSOH ns 5 - - VIL tCSU VIH VIL VIH VIL VIH VIL VIH VIL tSI SU VIH VIL VIH VIL tSI H tSCr tSCf tSCH tSCL tSCY C tCH VIH Input Data Input Data VOH VOL Output Data Output Data tSOD VOH VOL VOH VOL nCS SCL SDI SDO Figure 51 SPI System Bus Timing 13.4.3. RGB Interface Timing Characteristics 18/16-bit Bus RGB Interface Mode (IOVCC = 1.65 ~ 3.3V) Item Symbol Unit Min. Typ. Max. Test Condition VSYNC/HSYNC setup time tSYNCS ns 0 - - - ENABLE setup time tENS ns 10 - - - ENABLE hold time tENH ns 10 - - - PD Data setup time tPDS ns 10 - - - PD Data hold time tPDH ns 40 - - - DOTCLK high-level pulse width PWDH ns 40 - - - DOTCLK low-level pulse width PWDL ns 40 - - - DOTCLK cycle time tCYCD ns 100 - - - DOTCLK, VSYNC, HSYNC, rise/fall time trghr, trghf ns - - 25 - 6-bit Bus RGB Interface Mode (IOVCC = 1.65 ~ 3.3V) Item Symbol Unit Min. Typ. Max. Test Condition VSYNC/HSYNC setup time tSYNCS ns 0 - - - ENABLE setup time tENS ns 10 - - - ENABLE hold time tENH ns 10 - - - PD Data setup time tPDS ns 10 - - - PD Data hold time tPDH ns 30 - - - DOTCLK high-level pulse width PWDH ns 30 - - - DOTCLK low-level pulse width PWDL ns 30 - - - DOTCLK cycle time tCYCD ns 80 - - -

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9325 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 105 of 107 Version: 0.43 DOTCLK, VSYNC, HSYNC, rise/fall time trghr, trghf ns - - 25 - VIH VIL tASE VIH VIL VIH VIL VIH VIL VIH VIL trgbf trgbr VIH tSYNCS VILVIL VIH tENS PWDLtrgbf trgbr PWDH tENH tPDS tPDH tCYCD VIH Write Data Figure52 RGB Interface Timing

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9325 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 106 of 107 Version: 0.43 14. Revision History Version No. Date Page Description V0.28 2007/07/05 96 Modify the FPC circuit V0.29 2007/07/12 15 Modify the alignment mark pattern V0.30 2007/09/07 55 Modify the frame rate setting of R2Bh register V0.31 2007/10/29 57 Add the high speed write function V0.32 2007/11/02 71、72 Modify Frame rate value by register setting V0.33 2007/11/08 105 Modify Output Voltage deviation item V0.34 2007/11/27 96 Modify the pin recommend resistance V0.35 2007/11/30 96 Remove the TEST1 and TEST2 output to FPC. V0.36 2008/01/10 98 51, 64 105 Modify Display OFF register setting 1. Remove the deep standby mode function (DSTB) 2. Modify the NL[5:0] setting of R60h 3. Modify the source output deviation and offset 4. Modify the diode connection description (VCL – VGL), (DDVDH – VGH), (Vci – DDVDH) V0.37 2008/01/15 99 1. Modify the DDVDH – VREG1OUT > 0.3Volt. V0.38 2008/01/18 99 1. Modify the DDVDH – VREG1OUT > 0.2Volt. 2. Remove the register R00h. V0.39 2008/01/21 78 105 Add Reg. 97h. Modify Fig.45 STB mode register setting sequence. Modify the Fig. 53 power supply ON/OFF sequence. Modify the reset timing characteristics. V0.4 2008/01/24 53 Modify the register R00h. V0.41 2008/02/05 67 Modify the register R12h statement DDVDH – VREG1OUT > 0.2Volt. V0.42 2008/03/17 22 Delete Bit Operation function V0.43 2008/09/10 36,39,40, 44,45,50, 54,55 Remove R03h HWM bit and its statement.

a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9325 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 107 of 107 Version: 0.43